Membrane-based microelectromechanical system (MEMS) devices and methods of making

Abstract

The application relates to the technical field of micro electro mechanical system (MEMS), and discloses a MEMS device and a preparation method thereof. The preparation method of the MEMS device comprises the following steps: providing a MEMS structure layer, forming a first dielectric passivation layer on the MEMS structure layer, synchronously forming a multi-layer structure re-wiring layer on the first dielectric passivation layer, and forming at least one temperature sensing structure in the re-wiring layer, the re-wiring layer is used for planning the layout of input / output ports on the MEMS structure layer, and the temperature sensing structure is used for measuring the temperature of the MEMS device; forming a second dielectric passivation layer on the re-wiring layer, and the second dielectric passivation layer has an opening to expose the pads of the re-wiring layer, so as to be electrically connected with external devices. The application improves the accuracy of temperature compensation of the MEMS device and improves the comprehensive performance of the MEMS device.

Description

Technical Field

[0001] This application relates to the field of microelectromechanical systems (MEMS) technology, specifically to a MEMS device and its fabrication method. Background Technology

[0002] Micro-Electro-Mechanical Systems (MEMS) devices (such as MEMS oscillators, gyroscopes, accelerometers, and pressure sensors) are highly sensitive to changes in ambient temperature during operation. Temperature fluctuations can cause changes in the material parameters of MEMS structural layers (such as elastic modulus and residual stress), thereby affecting key performance indicators such as resonant frequency, sensitivity, and zero-point output. Therefore, temperature compensation for MEMS devices is essential for achieving high-precision and high-stability output. Existing temperature compensation methods mostly employ active compensation strategies, which involve acquiring the real-time temperature of the MEMS device and using compensation circuits or algorithms to correct measurement errors caused by temperature. To achieve accurate temperature acquisition, a temperature sensor is typically integrated near or inside the MEMS device.

[0003] Currently, there are two main methods for integrating temperature sensors: one method is to place the temperature sensor inside a control chip (ASIC) that is electrically connected to the MEMS device. However, the control chip and the MEMS device chip are physically separate, and there is a significant thermal gradient between them. Especially when the device experiences rapid power changes or the ambient temperature changes rapidly, the temperature difference between the control chip and the MEMS chip is difficult to ignore. This causes the temperature measured by the temperature sensor to fail to accurately reflect the actual operating temperature of the MEMS structure layer, thus reducing the accuracy of temperature compensation.

[0004] Another approach is to fabricate the temperature sensor directly on the surface of the MEMS device's structural layer. The MEMS structural layer is the core functional layer enabling mechanical movement or deformation. While directly forming a thermistor as a temperature sensor on this layer can shorten the thermal path and improve measurement accuracy, the thickness, doping concentration, stress, and other parameters of the MEMS structural layer are optimized based on the device's mechanical properties, not designed specifically for the thermistor's performance. If polysilicon resistors are used, their sheet resistance is typically high, but the temperature coefficient and linearity are difficult to optimize simultaneously. If traditional metal materials (such as aluminum or copper) are used to form the thermistor, their sheet resistance is extremely low (typically less than 0.1 Ω / sq). To obtain a high resistance value in the kiloohm range to match high-precision temperature measurement circuits (such as Wheatstone bridges and resistance-to-frequency conversion circuits), extremely long metal traces (several centimeters) are required, resulting in the thermistor occupying an excessively large chip area (typically exceeding mm²). 2 (Level), while the area of ​​the MEMS structure layer itself is very limited and difficult to accommodate. Summary of the Invention

[0005] In view of this, this application provides a MEMS device and a method for fabricating the same, in order to solve the aforementioned technical problems.

[0006] In a first aspect, embodiments of this application disclose a method for fabricating a MEMS device, including: A MEMS structure layer is provided, and a first dielectric passivation layer is formed on the MEMS structure layer; A multi-layer redistribution layer is simultaneously formed on the first dielectric passivation layer, and at least one temperature sensing structure is formed in the redistribution layer. The redistribution layer is used to plan the layout of input / output ports on the MEMS structure layer, and the temperature sensing structure is used to measure the temperature of the MEMS device. A second dielectric passivation layer is formed on the redistribution layer, the second dielectric passivation layer having openings to expose the pads of the redistribution layer for electrical connection with external devices.

[0007] In one possible example, the synchronous formation of a multilayer redistribution layer on the first dielectric passivation layer, and the formation of at least one temperature sensing structure in the redistribution layer, includes: A first seed layer is formed on the first dielectric passivation layer, and the first seed layer is sequentially photolithographically lithographically, electroplated, and etched to form a first metal layer; A first dielectric insulating layer is formed on the first metal layer, and a high-resistivity alloy thin film layer is formed on the first dielectric insulating layer; The high-resistivity alloy thin film layer is photolithographically etched and etched to form at least one temperature sensing structure; A second dielectric insulating layer is formed on the temperature sensing structure, and a second metal layer is formed on the second dielectric insulating layer.

[0008] In one possible example, the first dielectric insulating layer has an exposed portion of the first metal layer and a conductive via at the end of the temperature sensing structure opposite to the second dielectric insulating layer. And forming the second metal layer on the second dielectric insulating layer, including: A second seed layer is formed on the second dielectric insulating layer, and the second seed layer is sequentially photolithographically lithographically, electroplated, and etched to form a second metal layer that fills the conductive vias and serves as the pads of the redistribution layer.

[0009] In one possible example, the material used to prepare the high-resistivity alloy thin film layer includes any one of nickel-chromium alloy, tantalum nitride, titanium nitride, chromium silicide, or silicon carbide.

[0010] In one possible example, the high-resistivity alloy thin film layer is a nickel-chromium alloy film layer with a nickel-chromium mass ratio of 80:20, a film thickness of 200 nm, and a sheet resistance of 100 Ω / sq. Alternatively, the high-resistivity alloy thin film layer is a tantalum nitride film layer with a thickness of 100 nm and a sheet resistance of 200 Ω / sq.

[0011] In one possible example, the temperature sensing structure is arranged in a linear, serpentine, spiral, or grid-like structure.

[0012] In one possible example, the temperature sensing structure, arranged in a serpentine pattern, has a line width of 2µm to 20µm, a spacing of 2µm to 20µm between adjacent lines, and a ratio of the total length of the temperature sensing structure to the straight-line distance between its two ends of ≥1.2:1.

[0013] In one possible example, the temperature sensing structure forms a heat conduction path with the MEMS device through a thermally conductive via, the thermally conductive via penetrating the material layer between the MEMS device and the temperature sensing structure, and the thermally conductive via is provided with thermally conductive material.

[0014] In one possible example, after forming the second dielectric passivation layer on the redistribution layer, the method further includes: A control chip is provided, and the MEMS device is flip-chip bonded to the control chip via the pads of the redistribution layer.

[0015] Secondly, this application discloses a MEMS device, which is fabricated by the MEMS device fabrication method described in any of the above embodiments.

[0016] In summary, compared with the prior art, this application discloses a MEMS device and its fabrication method. After forming a first dielectric passivation layer on the MEMS structure layer, a multi-layer redistribution layer is simultaneously formed on the first dielectric passivation layer. At least one temperature sensing structure for measuring the temperature of the MEMS device is directly formed in this redistribution layer. Subsequently, a second dielectric passivation layer with pad openings is covered. This solves the problem of inaccurate temperature measurement caused by long distance and thermal gradients when placing the temperature sensor inside the control chip. In other words, this application integrates the temperature sensing structure into the redistribution layer closely attached to the MEMS structure layer, resulting in a very short thermal path and good thermal coupling. This allows the temperature sensing structure to accurately reflect the actual operating temperature of the MEMS structure layer, fundamentally eliminating the thermal gradient problem. On the one hand, the measurement error caused by temperature is limited by the stringent constraints of the MEMS front-end process, which restricts the fabrication of temperature sensors directly on the MEMS structure layer. On the other hand, this application transfers the formation of the temperature sensing structure from the MEMS structure layer to an independent back-end packaging redistribution layer. The redistribution layer itself has a high degree of design freedom with a multi-layer structure, and can realize temperature sensing structures such as high-resistance thermistors in a small area. Moreover, the temperature sensing structure is formed synchronously with the redistribution layer, which neither occupies the effective area of ​​the MEMS structure layer nor is it limited by the process parameters of the MEMS structure layer. Thus, accurate, small-area, and high-performance on-chip temperature measurement is achieved in a low-cost and highly integrated manner, improving the accuracy of temperature compensation of MEMS devices and improving the overall performance of MEMS devices. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of the MEMS device fabrication method according to an embodiment of this application; Figure 2 This is a sub-flowchart of the MEMS device fabrication method according to an embodiment of this application; Figure 3 This is a schematic diagram of the structure of the first MEMS device according to the embodiments of this application; Figure 4 This is a schematic diagram of the structure of the second type of MEMS device according to the embodiments of this application; Figure 5 This is a schematic diagram of the redistribution layer structure according to an embodiment of this application; Figure 6 This is a schematic diagram of the temperature sensing structure according to an embodiment of this application. Detailed Implementation

[0019] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the claims.

[0020] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0021] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0022] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0023] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0024] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.

[0025] Please refer to Figure 1 This application discloses a method for fabricating a MEMS device, which includes: S101 provides a MEMS structure layer, on which a first dielectric passivation layer 2 is formed.

[0026] S102, a multi-layer redistribution layer is simultaneously formed on the first dielectric passivation layer, and at least one temperature sensing structure is formed in the redistribution layer. The redistribution layer is used to plan the layout of input / output ports on the MEMS structure layer, and the temperature sensing structure is used to measure the temperature of the MEMS device.

[0027] S103, a second dielectric passivation layer is formed on the redistribution layer, the second dielectric passivation layer having openings to expose the pads of the redistribution layer for electrical connection with external devices.

[0028] That is, after forming a first dielectric passivation layer on the MEMS structure layer, a multi-layer redistribution layer is simultaneously formed on the first dielectric passivation layer, and at least one temperature sensing structure for measuring the temperature of the MEMS device is directly formed in the redistribution layer. Then, a second dielectric passivation layer with pad openings is covered. This solves the problem of inaccurate temperature measurement caused by long distance and thermal gradients when the temperature sensor is placed inside the control chip. In this embodiment, the temperature sensing structure is integrated into the redistribution layer closely attached to the MEMS structure layer, resulting in a very short thermal path and good thermal coupling. This allows the temperature sensing structure to accurately reflect the actual operating temperature of the MEMS structure layer, fundamentally eliminating measurement errors caused by thermal gradients. On the other hand, regarding… Existing methods for directly fabricating temperature sensors on the MEMS structure layer are limited by the stringent constraints of MEMS front-end processes. This embodiment transfers the formation of the temperature sensing structure from the MEMS structure layer to a separate back-end packaging redistribution layer. The redistribution layer itself has a high degree of design freedom with a multi-layer structure, and can realize temperature sensing structures such as high-resistance thermistors in a small area. Moreover, the temperature sensing structure is formed synchronously with the redistribution layer, which neither occupies the effective area of ​​the MEMS structure layer nor is it limited by the process parameters of the MEMS structure layer. Thus, it achieves accurate, small-area, and high-performance on-chip temperature measurement in a low-cost and highly integrated manner, improves the accuracy of temperature compensation of MEMS devices, and enhances the overall performance of MEMS devices.

[0029] The following will continue to combine Figures 2 to 6 This paper provides a detailed description of each step in the MEMS device fabrication method of this application.

[0030] Continue to refer to Figure 3 and Figure 5 A MEMS structure layer 1 is provided, and a first dielectric passivation layer 2 is formed on the MEMS structure layer 1.

[0031] In this context, MEMS structure layer 1 refers to a wafer or die that has completed MEMS front-end processing, and has a MEMS functional structure formed inside it. Depending on the type of MEMS device, MEMS structure layer 1 can be a MEMS resonator structure, a vibrating mass block of a MEMS gyroscope, a cantilever beam and sensing capacitor of a MEMS accelerometer, or a sensitive membrane of a MEMS pressure sensor, etc., and this application embodiment does not limit this.

[0032] The material of MEMS structure layer 1 is typically monocrystalline silicon, polycrystalline silicon, or silicon-on-insulator (SOI), and its surface has electrodes or pads (not shown in the figure) that need to be electrically connected to external circuits.

[0033] The first dielectric passivation layer 2 is formed on the upper surface of the MEMS structure layer 1. On the one hand, it serves as an electrical insulating layer, isolating the subsequently formed redistribution layer 3 (RDL) from the movable structures and signal lines in the MEMS structure layer 1, and forming electrical connections only at the designed via locations. On the other hand, it provides a flat deposition substrate for the subsequent redistribution layer 3.

[0034] The material of the first dielectric passivation layer 2 can be selected from one or more combinations of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or other organic or inorganic insulating media.

[0035] Preferably, in order to balance insulation performance and process compatibility, the first dielectric passivation layer 2 is made of silicon dioxide or silicon nitride, with a thickness of 1µm to 5µm, preferably 3µm.

[0036] In one example, the first dielectric passivation layer 2 can be deposited, spin-coated, or laminated onto the surface of the MEMS structure layer 1. After forming a complete first dielectric passivation layer 2, contact holes can be opened at the corresponding electrode positions of the MEMS structure layer 1 through photolithography and etching processes to expose the underlying metal pads or silicon vias, preparing for the subsequent electrical connection between the redistribution layer 3 and the MEMS structure layer 1.

[0037] Specifically, photoresist can be coated on the first dielectric passivation layer 2, and the pattern of the contact hole can be exposed and developed using a mask. Then, dry etching (such as reactive ion etching, RIE) or wet etching can be used to remove the dielectric material in the contact hole area until the electrodes on the MEMS structure layer 1 are exposed. The etching gas can be a CF4 / CHF3-based gas.

[0038] To enhance the adhesion between the first dielectric passivation layer 2 and the MEMS structure layer 1 and the subsequent redistribution layer 3, the surface of the MEMS structure layer 1 can be plasma cleaned or coated with a thin adhesion promoter (such as hexamethyldisilazane, HMDS) before depositing the first dielectric passivation layer 2.

[0039] The first dielectric passivation layer 2 can be a single-layer structure or a multilayer composite structure composed of two or more insulating materials. For example, a thin silicon nitride layer can be deposited first as a stress buffer layer and ion barrier layer, followed by a thicker silicon dioxide layer as the main insulating layer. The multilayer structure can better regulate stress, improve insulation performance, and prevent metal ions from diffusing into the MEMS structure layer 1.

[0040] Continue to refer to Figure 3 and Figure 5 After the first dielectric passivation layer 2 is fabricated, a multi-layer redistribution layer 3 is simultaneously formed on the first dielectric passivation layer 2, and at least one temperature sensing structure 4 is formed in the redistribution layer 3. The redistribution layer 3 is used to plan the layout of the input / output ports on the MEMS structure layer 1, and the temperature sensing structure 4 is used to measure the temperature of the MEMS device.

[0041] In this step, "synchronization" means that the formation process of the temperature sensing structure 4 and the formation process of at least one metal layer or insulating layer in the redistribution layer 3 are completed sequentially or simultaneously in the same process sequence, without the need to introduce additional independent photolithography layers or equipment for the temperature sensing structure 4.

[0042] As a specific implementation, the redistribution layer 3 is constructed using a fan-out wafer-level packaging process, including a first metal layer 31, a second metal layer 34, and a high-resistivity alloy thin film layer located between the first metal layer 31 and the second metal layer 34. The high-resistivity alloy thin film layer, after patterning, forms a temperature sensing structure 4. The first metal layer 31 is used to lead out the electrodes on the MEMS structure layer 1, and the second metal layer 34 is used to form external pads and interlayer interconnections. The temperature sensing structure 4 formed by the high-resistivity alloy thin film layer is electrically connected to the first metal layer 31 and / or the second metal layer 34 through conductive vias, and finally its two ends are led to the pads on the second metal layer 34 for connection to an external temperature measurement circuit.

[0043] As another implementation, the temperature sensing structure 4 can also be formed on the same plane as a metal layer in the redistribution layer 3. For example, both the high-resistivity alloy thin film layer and the first metal layer 31 are arranged on the upper surface of the first dielectric passivation layer 2. Specifically, after the first dielectric passivation layer 2 is fabricated, a single photolithography process is used to form the patterns of the first metal layer 31 and the high-resistivity alloy thin film layer in designated areas, respectively. The two are located on the same horizontal plane and are electrically isolated from each other. The first metal layer 31 is used for signal output, and the high-resistivity alloy thin film layer is patterned to form the temperature sensing structure 4. Then, an interlayer insulating layer is deposited together on top of the two layers to cover and protect the temperature sensing structure 4. Subsequently, vias are opened at both ends of the first metal layer 31 and the temperature sensing structure 4 in the interlayer insulating layer, and then a second metal layer 34 is deposited. The vias enable electrical connection with the first metal layer 31 and lead the two ends of the temperature sensing structure 4 to the upper pads.

[0044] Alternatively, the high-resistivity alloy thin film layer is directly deposited on the first dielectric passivation layer 2, while the first metal layer 31 and the second metal layer 34 are sequentially formed on top of the high-resistivity alloy thin film layer. Specifically: a high-resistivity alloy thin film layer is deposited on the surface of the first dielectric passivation layer 2 by magnetron sputtering, and the temperature sensing structure 4 is patterned by photolithography. Then, a thin insulating layer is deposited on the entire surface, and vias are opened at the locations where electrical connections are required at both ends of the temperature sensing structure 4. Next, a seed layer is deposited and electroplated to form the first metal layer 31. The first metal layer 31 is used for signal redistribution and also contacts both ends of the temperature sensing structure 4 through the vias to lead out the resistance signal. Subsequently, an interlayer insulating layer and the second metal layer 34 are formed. In this structure, the temperature sensing structure 4 is located at the bottom of the redistribution layer 3, closer to the MEMS structure layer 1, which helps to shorten the heat conduction path and improve the temperature sensing response speed. At the same time, both the first metal layer 31 and the second metal layer 34 can be used to form pads and interconnects, providing high design flexibility.

[0045] In one example, continue to refer to Figure 2 Simultaneously, a multi-layer redistribution layer 3 is formed on the first dielectric passivation layer 2, and at least one temperature sensing structure 4 is formed in the redistribution layer 3, including: S1021, a first seed layer is formed on the first dielectric passivation layer 2, and the first seed layer is sequentially photolithographically lithographically, electroplated and etched to form a first metal layer 31.

[0046] In this step, a titanium layer and a copper layer are sequentially deposited on the surface of the first dielectric passivation layer 2 using physical vapor deposition (e.g., magnetron sputtering) as a first seed layer. The titanium layer serves as an adhesion layer, and the copper layer serves as a conductive layer. After deposition, photoresist is spin-coated onto the first seed layer, and the pattern to be formed into the first metal layer 31 is transferred onto the photoresist through exposure and development. Then, using the first seed layer as a cathode, the wafer is immersed in a copper sulfate electroplating solution for electrochemical deposition, growing a copper metal layer at the opening of the photoresist with a target thickness of 2µm to 5µm.

[0047] After electroplating, the remaining photoresist is stripped, and excess seed layers not covered by the copper metal layer are removed by wet etching or plasma etching, leaving only the desired first metal layer 31 pattern. The first metal layer 31 is electrically connected to the electrodes on the MEMS structure layer 1 via pre-drilled contact holes on the first dielectric passivation layer 2, for leading internal signals outward.

[0048] S1022, a first dielectric insulating layer 32 is formed on the first metal layer 31, and a high-resistivity alloy thin film layer is formed on the first dielectric insulating layer 32.

[0049] In this step, the first dielectric insulating layer 32 covers the first metal layer 31 to isolate the first metal layer 31 from the subsequent high-resistivity alloy thin film layer. Specifically, a dielectric material can be spin-coated onto the surface of the first metal layer 31 to cover it, and then heated and cured to form a dense first dielectric insulating layer 32. Then, a high-resistivity alloy thin film layer is deposited on the first dielectric insulating layer 32 using a magnetron sputtering process.

[0050] S1023, photolithography and etching of a high-resistivity alloy thin film layer to form at least one temperature sensing structure 4.

[0051] In this step, photoresist is spin-coated onto the deposited high-resistivity alloy thin film layer, and then exposed and developed using a mask to form the pattern of the temperature sensing structure 4. This pattern can be linear, serpentine, spiral, or grid-like. That is, the temperature sensing structure 4 is arranged in a linear, serpentine, spiral, or grid-like structure.

[0052] After development, dry etching is used to etch the exposed high-resistivity alloy thin film layer until the high-resistivity alloy outside the pattern area is completely removed, leaving the patterned temperature sensing structure 4.

[0053] After etching, the photoresist is removed and a rapid thermal annealing process is performed (e.g., annealing at 400°C for 1 minute in a nitrogen atmosphere) to stabilize the resistance value and temperature coefficient of the temperature sensing structure 4.

[0054] S1024, a second dielectric insulating layer 33 is formed on the temperature sensing structure 4, and a second metal layer 34 is formed on the second dielectric insulating layer 33.

[0055] In this step, a dielectric material is spin-coated again onto the patterned temperature sensing structure 4, and then heated and cured to form a second dielectric insulating layer 33. The material of this second dielectric insulating layer 33 can be the same as that of the first dielectric insulating layer 32. Then, a second metal layer 34 is formed on the second dielectric insulating layer 33.

[0056] Through steps S1021 to S1024 described above, the entire process of redistribution layer 3 of the multi-layer structure and the integration of temperature sensing structure 4 in redistribution layer 3 is completed simultaneously. This process flow is highly compatible with the RDL process in fan-out wafer-level packaging or 2.5D / 3D packaging, does not introduce additional photolithography layers, and has lower manufacturing costs and higher mass production feasibility.

[0057] It should be noted that the second metal layer 34 includes pads electrically connected to both ends of the temperature sensing structure 4, conductive channels interconnected with the first metal layer 31, and pads for external input / output, which are used to lead the signal of the temperature sensing structure 4 to the device surface and realize the electrical connection between multiple layers.

[0058] The first dielectric insulating layer 32 and the second dielectric insulating layer 33 have exposed portions at the ends of the first metal layer 31 and the temperature sensing structure 4, respectively, forming conductive vias. Specifically, after the deposition of the first dielectric insulating layer 32, a first set of conductive vias is formed in the first dielectric insulating layer 32 through photolithography and etching processes. These vias are located in areas of the first metal layer 31 that need to be interconnected upwards, exposing the surface of the underlying first metal layer 31. After the deposition of the second dielectric insulating layer 33, a second set of conductive vias is formed in the second dielectric insulating layer 33 through photolithography and etching processes. These vias are located in ends of the temperature sensing structure 4 (i.e., thermistor) that need to be connected to external circuits, exposing the surface of the underlying high-resistivity alloy thin film layer. Furthermore, for locations where direct access from the first metal layer 31 to the second metal layer 34 is required, the vias in the second dielectric insulating layer 33 are aligned vertically with the vias in the first dielectric insulating layer 32, forming composite conductive vias that penetrate both insulating layers, allowing the subsequently filled metal to simultaneously contact the first metal layer 31.

[0059] Preferably, a second metal layer 34 is formed on the second dielectric insulating layer 33, comprising: A second seed layer is formed on the second dielectric insulating layer 33. The second seed layer is then photolithographically lithographically, electroplated, and etched to form a second metal layer 34 that fills the conductive vias and serves as the pads of the redistribution layer 3.

[0060] Specifically, a titanium layer and a copper layer are sequentially deposited on the surface of the second dielectric insulating layer 33 using physical vapor deposition (e.g., magnetron sputtering) as a second seed layer. The titanium layer serves as an adhesion layer, and the copper layer serves as a conductive layer. After deposition, photoresist is spin-coated onto the second seed layer, and the area where the second metal layer 34 needs to be formed is exposed by exposure and development. This area includes the locations of the conductive vias to be filled and the locations of the pad patterns. After development, the wafer is immersed in a copper sulfate electroplating solution with the second seed layer as the cathode for electrochemical deposition to grow a copper metal layer with a target thickness of 2µm to 5µm. During the electroplating process, copper metal is simultaneously deposited inside the conductive vias and in the photoresist opening areas. After electroplating, the remaining photoresist is stripped off, and the excess seed layer not covered by the copper metal layer is removed by wet etching or plasma etching, leaving only the required second metal layer 34. The second metal layer 34 thus formed serves both as the pads 3a of the redistribution layer 3 and as a vertical interconnect structure connecting different layers.

[0061] The pad 3a is used for subsequent electrical connection with external devices (such as control chips and printed circuit boards), and it can be brought out by ball bonding or direct wire bonding. At the same time, the metal filling the conductive via reliably leads the end of the temperature sensing structure 4 and the nodes of the first metal layer 31 that need to be externally connected to the pad 3a, thereby realizing the output of temperature signals and the input and output of MEMS drive / detection signals.

[0062] Optionally, the high-resistivity alloy thin film layer can be prepared from any of a variety of high-resistivity alloys or metal compounds. For example, materials for the high-resistivity alloy thin film layer include, but are not limited to, nickel-chromium alloy (NiCr), tantalum nitride (TaN), titanium nitride (TiN), chromium silicide (CrSi), or silicon carbide (SiC). These materials all exhibit high sheet resistance, enabling the achievement of kiloohm-level resistance values ​​within a small area, while also possessing stable temperature coefficients and good process compatibility.

[0063] Preferably, the high-resistivity alloy thin film layer is a nickel-chromium alloy film layer, with a nickel-chromium mass ratio of 80:20. This ratio of nickel-chromium alloy exhibits high resistivity and a stable temperature coefficient of resistance, making it suitable as a sensitive material for temperature sensing structures in MEMS devices. In this embodiment, the nickel-chromium alloy film layer can be deposited using a magnetron sputtering process, with the film thickness controlled at 200 nm. Under this thickness condition, the sheet resistance is 100 Ω / sq.

[0064] Alternatively, as another preferred embodiment, the high-resistivity alloy thin film layer is a tantalum nitride film layer. Tantalum nitride also exhibits high sheet resistance and excellent long-term stability, and is well-compatible with standard semiconductor back-end processes. Furthermore, the tantalum nitride film layer can be deposited using a reactive sputtering process, with the film thickness controlled to 100 nm. Under this thickness condition, the sheet resistance is 200 Ω / sq.

[0065] Based on the foregoing embodiments, as a preferred implementation of this embodiment, the following will be further discussed... Figure 6 The temperature sensing structure 4 is preferably arranged in a serpentine structure. The serpentine structure can effectively increase the physical length of the resistive element within a limited planar area, thereby increasing the total resistance value, while maintaining good mechanical stability and thermal uniformity.

[0066] The temperature sensing structure 4, which is arranged in a serpentine structure, has multiple parallel lines connected sequentially by end bends. The width of each line is denoted as K, and the distance between two adjacent parallel lines is denoted as J. In order to achieve a balance between photolithography yield and resistance stability, the line width (K in the figure) of the temperature sensing structure 4 is 2um to 20um, and the distance between adjacent lines (J in the figure) is 2um to 20um.

[0067] Preferably, the line width is 5µm and the spacing between adjacent lines is 5µm. This combination is beneficial for obtaining a higher pattern density and can avoid photolithographic bridging defects or parasitic coupling caused by too small a spacing.

[0068] Furthermore, the ratio of the total length of the temperature sensing structure 4 (i.e., the total physical length measured along the serpentine path from one end of the structure to the other) to the straight-line distance between its two ends (marked as H in the figure, the straight-line span between the first and last pads or ends) is ≥1.2:1. By setting this ratio, a longer resistance path can be obtained without increasing the lateral projected area of ​​the device, thus complementing the high sheet resistance of the high-resistivity alloy thin film layer to achieve a resistance of 0.01mm. 2 Even in smaller areas, resistance values ​​in the kΩ range can be achieved.

[0069] As another feasible approach, the temperature sensing structure 4 can also adopt a spiral or grid layout, which also meets the requirements for line width, spacing, and length ratio. Regardless of the specific geometry used, as long as it is formed inside the redistribution layer 3 and meets the above-mentioned dimensional parameters, the technical effect of high resistance in a small area can be achieved.

[0070] Continue to refer to Figure 3 and Figure 5 A second dielectric passivation layer 5 is formed on the redistribution layer 3. The second dielectric passivation layer 5 has openings to expose the pads 3a of the redistribution layer 3 for electrical connection with external devices.

[0071] In this step, after the redistribution layer 3 and temperature sensing structure 4 are fabricated, a second dielectric passivation layer 5 is formed on the redistribution layer 3. The second dielectric passivation layer 5 serves as the outermost protective structure of the device, covering and protecting the metal wiring, interlayer insulation layer, and temperature sensing structure 4 in the redistribution layer 3, preventing external moisture, ionic contaminants, or mechanical damage from affecting the device. Simultaneously, selective openings expose the pads 3a, providing electrical access points for subsequent packaging interconnects.

[0072] Optionally, the formation process of the second dielectric passivation layer 5 is the same as that of the first dielectric passivation layer 2.

[0073] In one example, continue to refer to Figure 4 After forming the second dielectric passivation layer 5 on the redistribution layer 3, the method further includes: providing a control chip 6, wherein the MEMS device is flip-chip bonded to the control chip 6 through the pad 3a of the redistribution layer 3.

[0074] The control chip 6 can be an application-specific integrated circuit (ASIC) that integrates a temperature measurement circuit (such as a Wheatstone bridge, a resistance-to-frequency conversion circuit, or a multiplexer) to output a temperature signal based on the resistance change of the temperature sensing structure 4. The upper surface of the control chip 6 can be provided with connection pads corresponding to the positions of pads 3a, and its surface can be chemically plated with nickel-gold to enhance solderability.

[0075] Through flip-chip bonding, the end of the temperature sensing structure 4 can be electrically connected to the temperature measurement circuit inside the control chip 6 via the conductive vias and pads 3a of the redistribution layer 3. Simultaneously, the driving and sensing electrodes of the MEMS structure layer 1 are also connected to the corresponding functional modules of the control chip 6 via the redistribution layer 3 and pads 3a. This forms a highly integrated MEMS package with an extremely short internal thermal path. The temperature sensing structure 4 can accurately sense temperature changes in the MEMS structure layer 1 in real time, allowing the control chip 6 to perform precise temperature compensation and improve the output stability of the MEMS device across the entire temperature range.

[0076] It should be noted that the temperature sensing structure 4 forms a heat conduction path with the MEMS device through thermally conductive vias. These vias penetrate the material layer between the MEMS device and the temperature sensing structure 4, and contain thermally conductive material. Specifically, to shorten the response time of the temperature sensing structure 4 to temperature changes in the MEMS structure layer 1 and improve real-time temperature measurement, one or more thermally conductive vias are provided between the MEMS structure layer 1 and the temperature sensing structure 4. These vias can vertically penetrate the material layer between them, including the first dielectric passivation layer 2 and a portion of the interlayer insulation layer (e.g., the first dielectric insulation layer 32) in the redistribution layer 3. The vias are filled with a highly thermally conductive material, rapidly transferring heat from the MEMS structure layer 1 to the vicinity of the temperature sensing structure 4, achieving good thermal coupling between the two.

[0077] The thermal vias can be formed simultaneously with the conductive vias in the redistribution layer 3, without the need for additional photolithography layers. Alternatively, the thermal vias can also terminate within the first dielectric passivation layer 2 without directly contacting the MEMS structure layer 1, only needing to be close to the upper surface of the MEMS structure layer 1, in order to avoid electrical interference to the MEMS structure layer 1.

[0078] In one example, the temperature sensing structure 4 formed by the high-resistivity alloy thin film layer can be a thermistor. The sheet resistance of the high-resistivity alloy thin film is 50Ω / sq-3000Ω / sq, and can be less than 0.01mm. 2 High-resistance thermistors ranging from 100Ω to 10kΩ can be achieved within a small area. Specifically, by selecting a nickel-chromium alloy (NiCr, mass ratio 80:20) and controlling the film thickness to 200nm, a sheet resistance of 100Ω / sq can be obtained; or by selecting tantalum nitride (TaN) and controlling the film thickness to 100nm, a sheet resistance of 200Ω / sq can be obtained. Combined with compact layouts such as serpentine and spiral designs, the actual occupied area can be as low as 0.005mm². 2 Therefore, the MEMS device fabricated using the above method utilizes redistribution layer 3 to form a high-resistance thermistor within a very small area. This thermistor structure exhibits a temperature coefficient of +50ppm / ℃ within the operating temperature range of -40℃ to +85℃, with a resistance change linearity better than 0.1%, meaning the resistance value shows a highly linear relationship with temperature changes, without significant hysteresis or inflection points. The thermal response time constant is approximately 3ms, enabling it to rapidly follow temperature changes in MEMS structure layer 1.

[0079] This application also discloses a MEMS device, which is fabricated by the MEMS device fabrication method of any of the above embodiments. For other working principles and processes of the MEMS device in this embodiment, please refer to the foregoing description of the MEMS device fabrication method in this embodiment, which will not be repeated here.

[0080] The foregoing has provided a detailed description of the MEMS devices and their fabrication methods provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. It should be noted that the descriptions of each embodiment in this application have different focuses; parts not described in detail or in a particular embodiment can be referred to in the relevant descriptions of other embodiments.

[0081] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. The technical features of the technical solution of this application can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are also included within the patent protection scope of this application, as long as the combination of these technical features does not contradict each other.

[0082] The present application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only for the purpose of helping to understand the core ideas of the present application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present application. Therefore, the content of this specification should not be construed as a limitation of the present application.

Claims

1. A method of fabricating a MEMS device, the method comprising: include: A MEMS structure layer is provided, and a first dielectric passivation layer is formed on the MEMS structure layer; A multi-layer redistribution layer is simultaneously formed on the first dielectric passivation layer, and at least one temperature sensing structure is formed in the redistribution layer. The redistribution layer is used to plan the layout of input / output ports on the MEMS structure layer, and the temperature sensing structure is used to measure the temperature of the MEMS device. A second dielectric passivation layer is formed on the redistribution layer, the second dielectric passivation layer having openings to expose the pads of the redistribution layer for electrical connection with external devices.

2. The MEMS device fabrication method according to claim 1, characterized in that, The simultaneous formation of a multilayer redistribution layer on the first dielectric passivation layer, and the formation of at least one temperature sensing structure in the redistribution layer, includes: A first seed layer is formed on the first dielectric passivation layer, and the first seed layer is sequentially photolithographically lithographically, electroplated, and etched to form a first metal layer; A first dielectric insulating layer is formed on the first metal layer, and a high-resistivity alloy thin film layer is formed on the first dielectric insulating layer; The high-resistivity alloy thin film layer is photolithographically etched and etched to form at least one temperature sensing structure; A second dielectric insulating layer is formed on the temperature sensing structure, and a second metal layer is formed on the second dielectric insulating layer.

3. The MEMS device fabrication method as described in claim 2, characterized in that, The first dielectric insulating layer and the second dielectric insulating layer have exposed portions of the first metal layer and conductive vias at the ends of the temperature sensing structure; And forming the second metal layer on the second dielectric insulating layer, including: A second seed layer is formed on the second dielectric insulating layer, and the second seed layer is sequentially photolithographically lithographically, electroplated, and etched to form a second metal layer that fills the conductive vias and serves as the pads of the redistribution layer.

4. The MEMS device fabrication method as described in claim 2, characterized in that, The high-resistivity alloy thin film layer is prepared using any one of nickel-chromium alloy, tantalum nitride, titanium nitride, chromium silicide, or silicon carbide.

5. The MEMS device fabrication method according to claim 1, characterized in that, The high-resistivity alloy thin film layer is a nickel-chromium alloy film layer with a nickel-chromium mass ratio of 80:20, a film thickness of 200nm, and a sheet resistance of 100Ω / sq. Alternatively, the high-resistivity alloy thin film layer is a tantalum nitride film layer with a thickness of 100 nm and a sheet resistance of 200 Ω / sq.

6. The MEMS device fabrication method according to claim 1, characterized in that, The temperature sensing structure is arranged in a linear, serpentine, spiral, or grid-like structure.

7. The MEMS device fabrication method as described in claim 6, characterized in that, The temperature sensing structure, which is arranged in a serpentine pattern, has a line width of 2µm to 20µm, a spacing of 2µm to 20µm between adjacent lines, and a ratio of the total length of the temperature sensing structure to the straight-line distance between its two ends of ≥1.2:

1.

8. The MEMS device fabrication method according to claim 1, characterized in that, The temperature sensing structure forms a heat conduction path with the MEMS device through a thermally conductive via. The thermally conductive via extends through the material layer between the MEMS device and the temperature sensing structure, and a thermally conductive material is provided in the thermally conductive via.

9. The MEMS device fabrication method according to claim 1, characterized in that, After forming the second dielectric passivation layer on the redistribution layer, the method further includes: A control chip is provided, and the MEMS device is flip-chip bonded to the control chip via the pads of the redistribution layer.

10. A MEMS device, characterized in that, The MEMS device is fabricated by the MEMS device fabrication method according to any one of claims 1 to 9.

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