Fan control method and system

Abstract

The application relates to a fan control method and system, which comprises the following steps: when an alternating current power is connected, driving a fan with a first preset duty ratio during a first preset time; monitoring a timer signal and bus behavior from a baseboard management controller during the first preset time; judging whether the timer signal or the bus behavior is detected; after the timer signal or the bus behavior is not detected during the first preset time, driving the fan with a second preset duty ratio; when the timer signal or the bus behavior is detected, transferring the control right of the fan to the baseboard management controller; when the baseboard management controller is reset or firmware is upgraded, driving the fan with the first preset duty ratio during a second preset time; and judging the driving mode of the fan according to whether any one of the timer signal and the bus behavior is detected during the second preset time. According to the application, the system energy consumption can be effectively saved.

Description

Technical Field

[0001] This application relates to the field of computer hardware technology, and in particular to a fan control method and system. Background Technology

[0002] In traditional server thermal control architectures, the division of labor between the Baseboard Management Controller (BMC) and the Complex Programmable Logic Device (CPLD) mainly relies on the BMC as the primary decision-making unit for fan speed control. The BMC actively sends control commands to the CPLD to execute the corresponding Pulse Width Modulation (PWM) speed control switching.

[0003] In this architecture, the complex programmable logic device (CPL) acts only as a passive execution unit, lacking the mechanism to independently determine the operating status of the baseboard management controller (BMD). Furthermore, all fan speed adjustment logic must wait for instructions from the BMD before execution. In addition, when the BMD is in an abnormal operating state due to software errors, hardware failures, or firmware upgrades, the CPL cannot effectively respond, only passively switching the fan speed to a preset fixed high-speed mode to ensure the system does not overheat, resulting in unnecessary energy waste and hindering energy conservation. Summary of the Invention

[0004] In view of the above problems, this application provides a fan control system and method.

[0005] A fan control system according to an embodiment of this application includes a baseboard management controller, a fan, and a complex programmable logic device (CPLD), wherein the CPLD is connected to the baseboard management controller and the fan. The baseboard management controller outputs timer signals and bus behavior. The fan generates airflow for heat dissipation. The CPLD drives the fan for a first preset duty cycle for a first preset time when AC power is connected. When either a timer signal or a bus behavior is detected from the baseboard management controller, the control of the fan is transferred to the baseboard management controller. If no timer signal or bus behavior is detected within the first preset time, the fan is driven with a second preset duty cycle. When the baseboard management controller is reset or undergoes a firmware upgrade, the fan is driven with the first preset duty cycle for the second preset time, and the fan driving mode is determined based on whether either a timer signal or a bus behavior is detected within the second preset time.

[0006] A fan control method according to an embodiment of this application, executed by a complex programmable logic device, includes: when AC power is connected, driving a fan with a first preset duty cycle for a first preset time period; monitoring timer signals and bus behavior from a baseboard management controller during the first preset time period; determining whether a timer signal or bus behavior is detected; if no timer signal or bus behavior is detected during the first preset time period, driving the fan with a second preset duty cycle; if a timer signal or bus behavior is detected, transferring fan control authority to the baseboard management controller; when the baseboard management controller is reset or firmware is upgraded, driving the fan with the first preset duty cycle during a second preset time period; and determining the fan driving mode based on whether either a timer signal or bus behavior is detected during the second preset time period.

[0007] Through the above architecture, the fan control system and method disclosed in this application can be autonomously determined and distinguished by a complex programmable logic device when the baseboard management controller is in different states such as normal operation, firmware upgrade or system restart, and adjust the corresponding fan speed control strategy accordingly. This avoids the use of a single mode with a fixed high speed when the baseboard management controller is abnormal, thereby effectively saving system energy consumption and reducing unnecessary power waste.

[0008] The foregoing description of the contents of this application and the following description of the embodiments are intended to demonstrate and explain the spirit and principles of this application, and to provide further explanation of the scope of this patent application. Attached Figure Description

[0009] Figure 1 This is a functional block diagram of a fan control system drawn according to an embodiment of this application.

[0010] Figure 2 This is a flowchart illustrating a fan control method based on an embodiment of this application.

[0011] Figure 3 This is a flowchart illustrating a fan control method that continuously outputs a timer signal to a complex programmable logic device, based on an embodiment of this application.

[0012] Figure 4 This is a flowchart of a fan control method based on another embodiment of this application. Detailed Implementation

[0013] The specific features and advantages of this application are described in detail below in the embodiments. The content is sufficient to enable anyone skilled in the art to understand the technical content of this application and implement it accordingly. Furthermore, based on the content disclosed in this specification, the claims, and the drawings, anyone skilled in the art can easily understand the related objectives and advantages of this application. The following examples are used to further illustrate the viewpoints of this application, and are not intended to limit the scope of this application in any way.

[0014] Please see Figure 1 , Figure 1 This is a functional block diagram of a fan control system drawn according to an embodiment of this application. Figure 1 As shown, the fan control system 1 includes a baseboard management controller 11, a fan 12, a complex programmable logic device (FPGA) 13, and an identification button 14, wherein the identification button 14 is an optional component. The FPGA 13 is connected to the baseboard management controller 11, the fan 12, and / or the identification button 14 via wired or wireless means.

[0015] The board management controller 11 is used to output timer signals and bus behavior. For example, the board management controller 11 can be used to output a watchdog timer (WDT) signal to trigger a reset procedure or protection mechanism when the system malfunctions, the firmware fails, or no response is received within a predetermined time. Specifically, the bus behavior can be, for example, the access behavior of the inter-integrated circuit (I2C) bus, including but not limited to address transfer, data reading, data writing, signal commands, and / or clock synchronization control.

[0016] Fan 12 is used to generate airflow for heat dissipation. For example, fan 12 can be a DC fan, a pulse width modulation controlled fan, or other speed-adjustable fan, and the speed of fan 12 can be adjusted according to the input duty cycle signal to meet different heat dissipation requirements. Fan 12 can be located inside the chassis, around the power supply module, the motherboard, near the heat dissipation module or other heat-generating components, and its speed can be adjusted via the speed signal from the baseboard management controller 11 and / or the complex programmable logic device 13.

[0017] The complex programmable logic device 13 is used to drive the fan 12 at a first preset duty cycle for a first preset time when AC power is connected. When either a timer signal or bus behavior from the baseboard management controller 11 is detected, control of the fan 12 is transferred to the baseboard management controller 11. For example, the first preset time can be 120 seconds. When the system server is connected to AC power and starts up, the complex programmable logic device 13 can actively output a control signal corresponding to the first preset duty cycle before the baseboard management controller 11 completes power-on, so that the fan 12 maintains a preset speed during the first preset time. After no timer signal or bus behavior is detected during the first preset time, the complex programmable logic device 13 drives the fan 12 at a second preset duty cycle. For example, the first preset duty cycle can be a 50% duty cycle speed, and the second preset duty cycle can be a 75% duty cycle speed, with the second preset duty cycle being higher than the first preset duty cycle. During a reset or firmware upgrade of the baseboard management controller 11, the complex programmable logic device 13 drives the fan 12 with a first preset duty cycle during a second preset time period, and determines the driving mode of the fan 12 based on whether either a timer signal or bus behavior is detected during the second preset time period. For example, the second preset time period can be 60 seconds, and the reset of the baseboard management controller 11 can be a hard reset or a soft reset. The complex programmable logic device 13 can determine whether the baseboard management controller 11 is soft reset based on whether a timer signal or bus behavior is detected.

[0018] Specifically, the baseboard management controller 11 and the complex programmable logic device 13 can have an independent heartbeat signal monitoring mechanism. During normal operation, the baseboard management controller 11 can continuously send regular signals (e.g., periodic pulses) to the complex programmable logic device 13 through general-purpose input / output (GPIO) pins as an indication of normal operation. When the baseboard management controller 11 temporarily stops operating due to a firmware soft reset, the heartbeat signal output will be interrupted. The complex programmable logic device 13 can have timing logic inside to continuously monitor this heartbeat signal. If the expected signal transition is not detected within a preset allowable time, the complex programmable logic device 13 can determine that the baseboard management controller 11 is in a reset or unresponsive state, and accordingly start the backup cooling fan control driver.

[0019] In one embodiment, when the baseboard management controller 11 performs a firmware partition upgrade, the complex programmable logic device 13 can first determine whether the server is powered on for the first time via AC. If the server is powered on for the first time via AC, the firmware partition upgrade operation will not be performed, and the upgrade can only be performed in the power-off state. The complex programmable logic device 13 can infer the possible state of the baseboard management controller 11 based on this. When the firmware upgrade target is the firmware partition of the complex programmable logic device 13 itself, since the flash memory partition storage area of ​​the complex programmable logic device 13 is independent of the partition currently running in the static random access memory, the upgrade operation is only performed on the flash memory partition. Therefore, the complex programmable logic device 13 can determine whether the firmware partition is in the upgrade state by monitoring the edge signal of the I2C bus, and temporarily output a speed with a 50% duty cycle as the preset fan upgrade partition speed adjustment value. After the partition upgrade is completed, the complex programmable logic device 13 can determine the state of the watchdog timer signal or the I2C polling signal. If a signal exists, the baseboard management controller 11 is allowed to take over the fan speed adjustment logic; if no signal exists, a safe speed adjustment process with a 75% duty cycle is preset.

[0020] In one embodiment, when the firmware upgrade target is the baseboard management controller 11 or a partition of the basic input / output system, the complex programmable logic device 13 can make a comprehensive judgment based on the shutdown history and the current shutdown state. If the judgment confirms that it is a firmware partition upgrade operation, the complex programmable logic device 13 can set a preset fan speed value with a 50% duty cycle for 300 seconds to ensure the heat dissipation requirements of the device during the upgrade. If no watchdog timer signal or I2C polling signal is received within 300 seconds, the complex programmable logic device 13 can determine that the baseboard management controller 11 is in an abnormal operating state and switch the fan to a safe speed mode with a 75% duty cycle. After the baseboard management controller 11 resumes normal operation, the fan speed control authority is returned to the baseboard management controller 11.

[0021] The identification button 14 is used to receive the reset signal from the board management controller 11. For example, when the board management controller 11 is in normal operation, if the user presses and holds the identification button 14 to trigger a reset, the complex programmable logic device 13 will forcibly pull the external reset (EXTRST_N) signal of the board management controller 11 low to perform a hard reset on the board management controller 11. Specifically, the identification button 14 can be directly connected to the general purpose input / output pin of the complex programmable logic device 13. When the user presses the identification button 14, the complex programmable logic device 13 can immediately know that the user has triggered a hard reset by detecting the potential change of the general purpose input / output pin.

[0022] Please see Figure 2 , Figure 2This is a flowchart illustrating a fan control method according to an embodiment of this application. Figure 2 As shown, the fan control method includes the following steps: S101: When AC power is connected, drive the fan with a first preset duty cycle during a first preset time period; S103: Monitor the timer signal and bus behavior from the board management controller during the first preset time period; S105: Determine whether a timer signal or bus behavior is detected; S107: After no timer signal or bus behavior is detected during the first preset time period, drive the fan with a second preset duty cycle; S109: When a timer signal or bus behavior is detected, transfer the control of the fan to the board management controller; S111: When the board management controller is reset or firmware is upgraded, drive the fan with the first preset duty cycle during the second preset time period; and S113: Determine the fan driving mode based on whether either a timer signal or bus behavior is detected during the second preset time period. The fan control method is applicable to... Figure 1 The fan control system 1 shown, i.e., the fan control method, can be achieved through... Figure 1 The complex programmable logic device 13 shown is executed, as exemplified below. Figure 1 The fan control system 1 shown is used for illustration. Figure 2 The fan control method shown.

[0023] In step S101, when AC power is connected, the complex programmable logic device 13 drives the fan 12 with a first preset duty cycle during a first preset time period. Specifically, when the system is connected to AC power and starts up, the complex programmable logic device 13 can complete power-on initialization earlier than the baseboard management controller 11, and the first preset time parameter (e.g., 120 seconds) and the first preset duty cycle parameter (e.g., 50%) stored inside the complex programmable logic device 13 can be loaded into the pulse width modulation control logic. The complex programmable logic device 13 can generate a corresponding pulse width modulation signal according to the first preset duty cycle parameter, and output the signal through the general purpose input / output pin coupled to the fan 12 to drive the fan 12 to run.

[0024] In step S103, the complex programmable logic device 13 monitors timer signals and bus behavior from the substrate management controller 12 within a first preset time period. Specifically, the bus behavior includes polling of inter-integrated circuit registers and signal detection.

[0025] In step S105, the complex programmable logic device 13 determines whether a timer signal or bus behavior is detected. Specifically, the complex programmable logic device 13 can independently determine the operating status of the baseboard management controller 11 based on whether at least one of the aforementioned two signals is detected, and determine the duty cycle driving mode of the fan 12 accordingly. Therefore, the complex programmable logic device 13 can independently determine the status of the baseboard management controller 11 and switch the duty cycle of the fan 12 based on whether a timer signal or bus behavior is detected.

[0026] In step S107, after the complex programmable logic device 13 does not detect a timer signal or bus behavior during a first preset time period, the complex programmable logic device 13 drives the fan 12 at a second preset duty cycle. For example, the first preset duty cycle can be a 50% duty cycle speed, and the second preset duty cycle can be a 75% duty cycle speed. Specifically, the second preset duty cycle is higher than the first preset duty cycle.

[0027] In step S109, when the complex programmable logic device 13 detects a timer signal or bus behavior, it transfers control of the fan 12 to the baseboard management controller 11. For example, when the complex programmable logic device 13 receives a watchdog timer signal output by the baseboard management controller 11 within a first preset time period, or detects that the baseboard management controller 11 performs address access, data read / write, or other bus communication behavior through the I2C interface, it can determine that the baseboard management controller 11 has completed startup and has normal control functions, and transfers control of the fan 12 to the baseboard management controller 11.

[0028] In step S111, during a reset or firmware upgrade of the baseboard management controller 11, the complex programmable logic device 13 drives the fan 12 at a first preset duty cycle for a second preset time period. For example, a reset of the baseboard management controller 11 may include either a hard reset or a soft reset. The second preset time period may be 60 seconds when the baseboard management controller 11 is reset. Specifically, a firmware upgrade may include a firmware partition upgrade for one of the complex programmable logic device 13, the baseboard management controller 11, and the basic input / output system. In one embodiment, when a firmware partition upgrade is detected for the baseboard management controller 11 or the basic input / output system, the complex programmable logic device 13 may drive the fan 12 at the first preset duty cycle for a third preset time period. The third preset time may be, for example, 300 seconds.

[0029] In step S113, the complex programmable logic device 13 determines the driving mode of the fan 12 based on whether either a timer signal or bus behavior is detected during a second preset time period. Specifically, when the complex programmable logic device 13 detects that the baseboard management controller 11 resumes outputting at least one of the timer signal or bus behavior during the second preset time period, it can determine that the baseboard management controller 11 has completed a reset or firmware upgrade, and therefore the control of the fan 12 can be transferred back to the baseboard management controller 11; otherwise, if at least one of the above is not detected after the second preset time period expires, the complex programmable logic device 13 continues to drive the fan 12 with the second preset duty cycle.

[0030] Please see Figure 3 , Figure 3 This is a flowchart illustrating the continuous output of a timer signal to a complex programmable logic device in a fan control method according to an embodiment of this application. Figure 3 As shown, the fan control method, in addition to Figure 2 In addition to the steps shown, the system may also include step S110: determining the operating state of the baseboard management controller when the baseboard management controller continuously outputs a timer signal to the complex programmable logic device; and step S112: driving the fan according to the operating state of the baseboard management controller and the register speed adjustment command received in advance from the baseboard management controller. In this embodiment, steps S110 and S112 can be executed in... Figure 2 After step S109.

[0031] In step S110, when the baseboard management controller 11 continuously outputs timer signals to the complex programmable logic device 13, the complex programmable logic device 13 determines the operating state of the baseboard management controller 11. Specifically, when the baseboard management controller 11 manually stops the Intelligent Platform Management Interface (IPMI) tool, only the polling access behavior of the baseboard management controller 11 to the I2C register at the driver layer is suspended, without affecting the continuous output of the watchdog basic input / output function at the application layer. In this case, the complex programmable logic device 13 can determine that the baseboard management controller 11 is maintaining normal operation based on the continuously received timer signals.

[0032] In step S112, the complex programmable logic device 13 drives the fan 12 according to the operating status of the baseboard management controller 11 and the register speed adjustment command received in advance from the baseboard management controller 11. Specifically, since the complex programmable logic device 13 determines in step S110 that the baseboard management controller 11 still has normal control capability, the register speed adjustment command previously issued or manually issued by the baseboard management controller 11 is still valid. Therefore, the complex programmable logic device 13 can continuously drive the fan 12 to maintain the current set speed according to the register value corresponding to the register speed adjustment command, without having to switch to the abnormal protection mode due to the pause of I2C polling behavior. In this way, it can avoid misjudging the baseboard management controller 11 as abnormal due to the stop of a specific management tool and maintain the stability of fan 12 control.

[0033] Please see Figure 4 , Figure 4 This is a flowchart illustrating a fan control method according to another embodiment of this application. Figure 4 As shown, the fan control method may include steps S201 to S225. The fan control method is applicable to... Figure 1 The fan control system 1 shown below is exemplarily described below. Figure 1 The fan control system 1 shown is used for illustration. Figure 4 The fan control method shown.

[0034] In step S201, the AC power supply powers the system server. In step S203, the complex programmable logic device 13 executes the default pulse width modulation fan speed control during a first preset time period. Step S205 is executed in the same way as step S105, so it will not be described again. Steps S207 to S211 are executed in the same way as steps S109 to S113, so they will not be described again. In step S213, based on whether there is a record of a DC power supply change from ON to OFF, the complex programmable logic device 13 determines whether the system is currently powered on or whether to execute the default pulse width modulation safety speed control. Specifically, when the judgment result of step S213 is "yes", that is, there is a record of DC power-on to power-off change, the complex programmable logic device 13 system further executes step S215: determine whether the current state is powered on; when the judgment result of step S213 is "no", that is, there is no record of DC power-on to power-off change, step S217 is executed: the complex programmable logic device 13 defaults to pulse width modulation safe speed regulation, for example, using a second preset duty cycle of 75% to control the safe speed of fan 12.

[0035] In step S215, the complex programmable logic device 13 determines whether the system is currently powered on. If the result of step S215 is "yes," meaning there is a record of DC power-on to power-off and the system is currently powered on, step S217 is executed. If the result of step S215 is "no," meaning the system is not currently powered on, step S219 is executed: the complex programmable logic device 13 determines whether there is a bus behavior for firmware upgrades. If the result of step S219 is "yes," meaning the complex programmable logic device 13 determines that there is an edge change in the I2C connection for firmware upgrades, step S221 is executed: the complex programmable logic device 13 executes default pulse width modulation fan speed control until the upgrade is completed. If the result of step S219 is "no," meaning the complex programmable logic device 13 determines that there is an edge change in the I2C connection for no firmware upgrades, step S223 is executed: the complex programmable logic device 13 executes default pulse width modulation fan speed control for a third preset time period. Specifically, the third preset time period can be 300 seconds, and the default pulse width modulation fan speed can be the first preset duty cycle of 50%.

[0036] In step S225, the complex programmable logic device 13 determines whether it has read the timer signal or bus behavior of the baseboard management controller 11. If the determination result of step S225 is "yes," meaning the complex programmable logic device 13 has read the timer signal or bus behavior of the baseboard management controller 11, step S207 is executed: the complex programmable logic device 13 performs speed adjustment of the baseboard management controller 11. If the determination result of step S225 is "no," meaning the complex programmable logic device 13 has not read the timer signal or bus behavior of the baseboard management controller 11, step S217 is executed: the complex programmable logic device 13 performs default pulse width modulation safety speed adjustment. Step S225 can be executed during the third preset time period or after the firmware upgrade is completed.

[0037] Through the above architecture, the fan control system and method disclosed in this application can be autonomously detected and distinguished by complex programmable logic devices when the baseboard management controller is in different states such as normal operation, firmware upgrade or system restart, and adjust the corresponding fan speed control strategy accordingly. This avoids the use of a single mode with fixed high speed when the baseboard management controller is abnormal, thereby effectively saving system energy consumption and reducing unnecessary power waste.

[0038] While this application discloses the above embodiments, they are not intended to limit the scope of this application. Any modifications and refinements made without departing from the spirit and scope of this application are within the scope of patent protection of this application. Please refer to the appended claims for the defined scope of protection of this application.

Claims

1. A fan control method, characterized in that, Applications include: When AC power is connected, the fan is driven with a first preset duty cycle during a first preset time period; Monitor timer signals and bus behavior from the baseboard management controller within the first preset time period; determine whether the timer signal or the bus behavior is detected; After no timer signal or bus behavior is detected during the first preset time period, the fan is driven with a second preset duty cycle; Upon detecting the timer signal or the bus behavior, control of the fan is transferred to the baseboard management controller; During a reset or firmware upgrade of the baseboard management controller, the fan is driven with the first preset duty cycle during a second preset time period; and The fan's driving mode is determined based on whether either the timer signal or the bus behavior is detected during the second preset time period.

2. The fan control method according to claim 1, characterized in that, The bus behavior includes polling of inter-integrated circuit registers and signal detection.

3. The fan control method according to claim 2, characterized in that, The method further includes: When the baseboard management controller continuously outputs the timer signal to the complex programmable logic device, the operating state of the baseboard management controller is determined; and The fan is driven according to the operating status of the baseboard management controller and the register speed adjustment command received in advance from the baseboard management controller.

4. The fan control method according to claim 1, characterized in that, The second preset duty cycle is higher than the first preset duty cycle.

5. The fan control method according to claim 1, characterized in that, The reset of the baseboard management controller includes either a hard reset or a soft reset.

6. The fan control method according to claim 1, characterized in that, The firmware upgrade includes a firmware partition upgrade for one of the complex programmable logic devices, the substrate management controller, and the basic input / output system.

7. The fan control method according to claim 6, characterized in that, The method further includes: When the firmware partition is detected to be upgraded for the baseboard management controller or the basic input / output system, the fan is driven with the first preset duty cycle during a third preset time period.

8. The fan control method according to claim 1, characterized in that, The complex programmable logic device independently determines the status of the baseboard management controller and switches the duty cycle of the fan based on whether the timer signal or the bus behavior is detected.

9. A fan control system, characterized in that, The system includes: The baseboard management controller is used to output timer signals and control bus behavior. Fans are used to generate airflow for heat dissipation; and A complex programmable logic device (FPGA) is connected to the baseboard management controller and the fan. When AC power is connected, the FPGA drives the fan for a first preset duty cycle for a first preset time. When either a timer signal or a bus behavior is detected from the baseboard management controller, the FPGA transfers control of the fan to the baseboard management controller. After no timer signal or bus behavior is detected during the first preset time, the FPGA drives the fan for a second preset duty cycle. During a reset or firmware upgrade of the baseboard management controller, the FPGA drives the fan for the second preset time with the first preset duty cycle. The fan driving mode is determined based on whether either the timer signal or the bus behavior is detected during the second preset time.

10. The fan control system according to claim 9, characterized in that, The system also includes: An identification button, connected to the complex programmable logic device, is used to receive a reset signal from the baseboard management controller.

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