Probe card and method for reducing WAT parasitic resistance

Abstract

The application provides a probe card and a method for reducing WAT parasitic resistance. Each two Pin pairs correspond to a test Pad. Pins marked with odd numbers are Force Pins for applying voltage or current, and Pins marked with even numbers are Sense Pins for measuring voltage or current. The application effectively solves the problem of parasitic resistance that is difficult to fundamentally remove during WAT testing, and is particularly effective for testing small resistance and small impedance devices.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and specifically to a probe card and method for reducing WAT parasitic resistance. Background Technology

[0002] In the semiconductor integrated circuit industry, wafer accessible test (WAT) is usually a batch of automated tests used to monitor process, design, and device issues. It is also one of the standards for whether a wafer can be shipped. Therefore, the accuracy and data quality of wafer accessible test are extremely important.

[0003] The contact between the WAT testing equipment and the wafer under test is through probe cards. Test pads are areas specifically designed for testing the probes, formed by covering the device under test with aluminum of a certain thickness after it has been brought to the wafer surface through subsequent processes such as vias and metal layers. For example... Figure 1 As shown, a test key is formed by 12 pads arranged according to size requirements. During WAT automatic testing, the metal pins on the probe card contact the pads one by one, and the connection to the test machine is achieved through the PCB board and wiring on the probe card.

[0004] In actual wafer tack testing (WAT), the measured resistance value includes the true wafer resistance and the parasitic resistance of the test contacts. This includes the parasitic resistance of the probe card itself, the resistance of impurity particles on the test pins during testing, and the parasitic resistance from incompletely removed components such as test equipment wiring. The low-resistance parameters in WAT testing, or parameters that can be equivalent to low-impedance devices, are particularly sensitive to these parasitic resistances. Therefore, the removal of parasitic resistance during WAT testing is crucial. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a probe card and method for reducing WAT parasitic resistance, so as to solve the problem that it is difficult to effectively remove parasitic resistance in the WAT testing process in the prior art.

[0006] To achieve the above and other related objectives, this application provides a probe card for reducing WAT parasitic resistance. Each pair of pins on the probe card corresponds to a test pad, wherein pins with odd-numbered markings are Force Pins for applying voltage or current, and pins with even-numbered markings are Sense Pins for measuring voltage or current.

[0007] Preferably, the Force pin and Sense pin that contact each Pad are connected to different test units of the corresponding machine.

[0008] This application also provides a method for reducing the parasitic resistance of WAT, based on the above-mentioned probe card using a four-terminal method to separate current excitation and voltage sampling. Current excitation is provided through the pins of the probe card that are in contact with the two pads and have odd numbers, and voltage sampling is performed through the pins of the probe card that are in contact with the two pads and have even numbers.

[0009] This application also provides a method for reducing the parasitic resistance of WAT, which involves voltage compensation of the test device based on the aforementioned probe card.

[0010] Preferably, the step of voltage compensation for the test device includes: applying a voltage Vf1 to the Pad of the test device through the Force Pin, and then measuring the actual voltage of the Pad of the test device through the Sense Pin to obtain the measured voltage Vm1; determining whether the difference between the two meets the accuracy requirements; if not, the sum of Vf1 and the difference is used as the new applied voltage, and the above steps are repeated until the new difference meets the accuracy requirements.

[0011] As described above, the probe card and method for reducing WAT parasitic resistance provided in this application have the following beneficial effects: effectively solving the problem of parasitic resistance that is difficult to completely remove during WAT testing, and is particularly effective for testing devices with small resistance and low impedance. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0013] Figure 1 This diagram illustrates the correspondence between probe card pins and test pads in the prior art. Figure 2 The diagram shows the correspondence between the probe card pins and test pads for reducing WAT parasitic resistance according to an embodiment of this application. Figure 3 This diagram illustrates the correspondence between the probe card pins and the probe card interface connections for reducing WAT parasitic resistance according to an embodiment of this application. Figure 4 The diagram shows a four-terminal test method implemented based on the method for reducing WAT parasitic resistance provided in the embodiments of this application. Figure 5 The diagram shows a four-terminal testing method implemented based on existing technology. Figure 6The diagram shows a comparison of resistance data obtained by the method for reducing WAT parasitic resistance provided in the embodiments of this application and the prior art. Figure 7 The flowchart shown is a process for voltage compensation of a test device based on the method for reducing the parasitic resistance of WAT provided in the embodiments of this application. Figure 8 The chart shows a comparison of linear region drain current data obtained by the method for reducing WAT parasitic resistance provided in the embodiments of this application and the prior art. Detailed Implementation

[0014] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0015] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0016] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0017] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0018] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0019] Parasitic resistance during WAT testing originates from two main sources: contact resistance caused by the test pin and parasitic resistance generated by the test equipment's wiring, probe cards, etc. Ideally, contact resistance is relatively low, but if there is insufficient contact between the test pin and the test pad, or if other impurities adhere to the test pin, the contact resistance value may change. Parasitic resistance of the probe card is difficult to eliminate, but this value is generally constant and does not change significantly, and probe card manufacturers strive to minimize this value. During prolonged automated WAT testing, impurities inevitably accumulate on the probe tip. This is because the test pin continuously scrapes through the alumina layer on the pad and slides a distance to ensure the test pin is encased in aluminum pad, guaranteeing good contact. When the test pin is lifted off the pad, it may carry away the aluminum and alumina it was in contact with, adhering to the probe tip and forming impurities that increase parasitic resistance. The resistivity of alumina is known to be 10⁻⁶. 15 The resistivity of pure aluminum is 2.6548E-6 ohms / cm. Calculations show that the resistance of impurity particles is greatly affected by the material. If the impurity particles contain a certain proportion of aluminum oxide, they will generate a large parasitic resistance. Assuming a small resistance measurement value is 50 ohms, a 5-ohm parasitic resistance value will introduce a 10% data error. As mentioned earlier, if the impurity particles are oxides or other materials with high resistivity, parasitic resistance is easily generated. Therefore, the removal of parasitic resistance is particularly important during WAT testing.

[0020] For parasitic resistances unavoidable in test paths caused by wiring and materials, common methods include standardizing the resistance of the machine cables and eliminating this resistance in the machine system, or using a four-terminal Kelvin connection for the measuring instrument cables. However, both of these methods only remove the parasitic resistance of the testing instrument, not the parasitic resistance associated with the probe card.

[0021] Currently, impurity particles on test probe cards are primarily removed using online needle cleaning technology. The principle behind this technique is that the test pins are repeatedly pierced at a certain height onto cleaning paper, which has adhesive and shaping properties. The friction and adhesion between the test pins and the cleaning paper then adhere and remove the impurities. The cleaning paper has a certain thickness, exceeding the piercing height, thus ensuring that the probe tips are not damaged during cleaning. However, this method only improves the quantity of impurity particles and cannot completely eliminate the effects of impurity particles and parasitic resistance. This is because the cleaning effect is related to the lifespan of the cleaning paper, the size and material of the impurity particles, and the duration of the test, making it difficult to completely remove impurity particles in practical applications.

[0022] To address the problem of effectively removing parasitic resistance during the WAT testing process in existing technologies, this application provides a probe card for reducing WAT parasitic resistance. Each pair of pins on the probe card corresponds to a test pad. Pins with odd-numbered markings are Force Pins used to apply voltage or current, while pins with even-numbered markings are Sense Pins used to measure voltage or current.

[0023] Please see Figure 2 The test key consists of 12 pads arranged according to size requirements. During WAT automatic testing, a pair of pins on the probe card contacts a pad in a one-to-one correspondence. Each pair of pins contains a Force Pin and a Sense Pin. Pins with odd-numbered markings are Force Pins, and pins with even-numbered markings are Sense Pins. The Force Pin and Sense Pin that contact each pad are connected to different test units of the corresponding machine.

[0024] Please see Figure 3 The 24 small dots in the center are Pin 1-24 from left to right. The correspondence between the Pin number and the probe card interface number is shown in Table 1.

[0025] Table 1. Correspondence between Pin Serial Number and Probe Card Interface Serial Number 1 18 2 31 3 17 4 32 5 16 6 33 7 15 8 34 9 14 10 35 11 13 12 36 13 12 14 37 15 11 16 38 17 10 18 39 19 9 20 40 21 8 22 41 23 7 24 42 This application also provides a method for reducing the parasitic resistance of WAT, such as Figure 4 As shown, a four-terminal method (Kelvin connection) is used to separate current excitation and voltage sampling. Current excitation is provided to the pins with odd-numbered markings that contact the two pads on the probe card, while voltage sampling is performed on the pins with even-numbered markings that contact the two pads. This method is particularly suitable for testing small resistances. Even if parasitic resistance was not considered during layout design, this method can eliminate it, while also saving layout area compared to... Figure 5 The existing technology shown requires four pads to connect the device under test (DUT) during layout design (two pads for applying current (or voltage), and the other two pads for measuring potential difference), doubling the number of devices on a row of test keys and improving cost-effectiveness. For example... Figure 6 As shown, compared with the prior art, the parasitic resistance obtained by using the above method is reduced by 0.4%-1.5%.

[0026] This application also provides a method for reducing the parasitic resistance of WAT by performing voltage compensation on the test device using a probe card. For example... Figure 7As shown, after applying voltage Vf1 to the Pad of the test device through the Force Pin, the actual voltage of the Pad of the test device is measured through the Sense Pin to obtain the measured voltage Vm1. It is then determined whether the difference between the two meets the accuracy requirements. If not, the sum of Vf1 and the difference is used as the new applied voltage, and the above steps are repeated until the new difference meets the accuracy requirements. Figure 8 As shown, compared with the prior art, the linear region drain current Idlin obtained by using the above method increases by 0.4%-2.2%.

[0027] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0028] In summary, the probe card and method for reducing parasitic resistance in WAT testing provided in this application effectively solve the problem of parasitic resistance that is difficult to completely remove during WAT testing, and are particularly effective for testing devices with low resistance and low impedance. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0029] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A probe card for reducing WAT parasitic resistance, characterized in that, Each pair of pins on the probe card corresponds to a test pad. Pins with odd-numbered markings are Force Pins used to apply voltage or current, while Pins with even-numbered markings are Sense Pins used to measure voltage or current.

2. The probe card according to claim 1, characterized in that, The Force pin and Sense pin that contact each Pad are connected to different test units of the corresponding machine.

3. A method for reducing the parasitic resistance of a probe card, characterized in that, The probe card according to any one of claims 1-2 uses a four-terminal method to separate current excitation and voltage sampling. Current excitation is provided through the pins of the probe card that are in contact with two pads and have odd-numbered markings, and voltage sampling is performed through the pins of the probe card that are in contact with two pads and have even-numbered markings.

4. A method for reducing the parasitic resistance of a probe card, characterized in that, Voltage compensation for the test device is performed using the probe card according to any one of claims 1-2.

5. The method according to claim 4, characterized in that, The steps for voltage compensation of the test device include: applying a voltage Vf1 to the Pad of the test device through the Force Pin, measuring the actual voltage of the Pad of the test device through the Sense Pin to obtain a measured voltage Vm1; determining whether the difference between Vf1 and Vm1 meets the accuracy requirements; if not, the sum of Vf1 and the difference is used as the new applied voltage, and repeating the above steps until the new difference meets the accuracy requirements.

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