A high voltage charge pump overvoltage detection circuit
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2026-03-27
- Publication Date
- 2026-08-07
AI Technical Summary
对于升压型电荷泵输出所产生的电压，则需要一个过压检测电路，防止产生的电压值过高，造成芯片结构的损毁
[0021]本发明的有益效果为：采用一组共源共栅电流镜，将原本的输出采样电流复制，使得传统结构的高压管的源极可以接地，根据器件结构的特性，可以选用源漏耐压更大的功率管，使电路的应用范围更广。
Smart Images
Figure CN122525202A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power management technology, specifically relating to a high-voltage charge pump detection circuit. Background Technology
[0002] Overvoltage detection circuit for charge pumps is a crucial component of power management chips. The charge pump's core function is to boost, buck, or reverse the polarity of DC voltage without the need for inductors. For the output voltage of a boost-type charge pump, an overvoltage detection circuit is required to prevent excessively high voltage values from damaging the chip structure. For high-voltage charge pumps, the output voltage is typically compared to the input voltage before conversion. Therefore, the detection circuit must be a high-voltage structure. Traditional circuit structures, due to the voltage withstand characteristics of the components, cannot detect excessively high voltages. Summary of the Invention
[0003] To address the aforementioned problems, this invention provides a high-voltage charge pump overvoltage detection circuit, which, compared to traditional charge pump overvoltage detection circuits, has a wider voltage detection range in high-voltage detection.
[0004] The technical solution of this invention is to utilize current sampling to change the connection method of the high-voltage tube, thereby expanding the range of available devices.
[0005] To achieve the above-mentioned objectives, the present invention provides a high-voltage charge pump overvoltage detection circuit, including a bias circuit, a current mirror circuit, an error amplifier, a compensation capacitor, a negative feedback structure, a current sampling circuit, and a voltage output resistor;
[0006] Bias circuit: provides bias for the error amplifier;
[0007] Current mirror circuit: ensures that the currents in the two branches being detected are equal;
[0008] Error amplifier: Combined with a negative feedback structure, it achieves voltage clamping.
[0009] Compensation capacitor: Miller compensation is used to change the positions of the dominant and secondary poles and enhance the stability of the circuit;
[0010] Negative feedback structure: Combined with an error amplifier, it achieves voltage clamping.
[0011] Current sampling circuit: Changes the output position of the circuit;
[0012] Voltage output resistor: Used to convert current signals into voltage signals for output.
[0013] In a preferred embodiment, the bias circuit includes a first NMOS transistor MN1 and a second NMOS transistor MN2; the drain and gate of the first NMOS transistor MN1 are interconnected and connected to the source of the second NMOS transistor MN2; the source of the first NMOS transistor MN1 is connected to the ground rail; the drain and gate of the second NMOS transistor MN2 are interconnected and connected to the output of the reference current source.
[0014] In a preferred embodiment, the current mirror circuit includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6; the gate of the third NMOS transistor MN3 is connected to the gate and drain of the first NMOS transistor MN1 and the gate of the fifth NMOS transistor MN5; the source of the third NMOS transistor MN3 is connected to the ground rail; the drain of the third NMOS transistor MN3 is connected to the source of the fourth NMOS transistor MN4; the gate of the fourth NMOS transistor MN4 is connected to the drain and gate of the second NMOS transistor MN2 and the gate of the sixth NMOS transistor MN6; the source of the fifth NMOS transistor MN5 is grounded to the ground rail; the drain of the fifth NMOS transistor MN5 is connected to the source of the sixth NMOS transistor MN6; the drain of the sixth NMOS transistor MN6 is connected to the drain of the fourth PMOS transistor MP4, the positive terminal of the first capacitor C1, and the gate of the seventh NMOS transistor MN7.
[0015] In a preferred embodiment, the error amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP4; the drain and gate of the first PMOS transistor MP1 are interconnected and connected to the gate of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3; the source of the first PMOS transistor MP1 is connected to one end of a first resistor; the source of the second PMOS transistor MP2 is connected to one end of a second resistor R2; the drain of the second PMOS transistor MP2 is connected to the source of the fourth PMOS transistor MP4; the gate and drain of the third PMOS transistor MP3 are interconnected and connected to the gate of the fourth PMOS transistor MP4; the drain of the fourth PMOS transistor MP4 is connected to the drain of the sixth NMOS transistor MP6, the positive terminal of the first capacitor C1, and the gate of the seventh NMOS transistor MN7, serving as the output of the error amplifier.
[0016] As a preferred embodiment, the compensation capacitor is a first capacitor C1; the positive terminal of the first capacitor is connected to the gate of the seventh NMOS transistor MN7, the drain of the sixth NMOS transistor MN6, and the drain of the fourth PMOS transistor MP4; the negative terminal is connected to the ground rail.
[0017] In a preferred embodiment, the negative feedback structure includes a seventh NMOS transistor MN7, a fifth PMOS transistor MP5, and a seventh PMOS transistor MP7; the gate of the seventh NMOS transistor MP7 is connected to the positive terminal of the first capacitor, the drain of the sixth NMOS transistor MN6, and the drain of the fourth PMOS transistor MP4; the source of the seventh NMOS transistor MN7 is connected to the ground rail; the drain of the seventh NMOS transistor MN7 is connected to the drain and source of the seventh PMOS transistor MP7 and the gate of the eighth PMOS transistor MP8; the source of the fifth PMOS transistor MP5 is connected to the source of the second PMOS transistor MP2 and one end of the second resistor R2; the gate and drain of the fifth NMOS transistor MN5 are interconnected and connected to the gate of the sixth PMOS transistor MP6 and the source of the seventh PMOS transistor MP7; the gate and drain of the seventh PMOS transistor MP7 are interconnected and connected to the gate of the eighth PMOS transistor MP8 and the drain of the seventh NMOS transistor MN7.
[0018] In a preferred embodiment, the current sampling circuit includes a first resistor, a second resistor, a sixth PMOS transistor, and an eighth PMOS transistor; one end of the first resistor R1 is connected to the source of the first PMOS transistor MP1; the other end of the first resistor R1 is connected to the power supply voltage VDD; one end of the second resistor R2 is connected to the source of the second PMOS transistor MP2, the source of the fifth PMOS transistor MP5, and the source of the sixth PMOS transistor MP6; the other end of the second resistor R2 is connected to the charge pump output voltage VCP; the gate of the sixth PMOS transistor MP6 is connected to the drain and gate of the fifth PMOS transistor MP5 and the source of the seventh PMOS transistor MP7; the drain of the sixth PMOS transistor MP6 is connected to the source of the eighth PMOS transistor MP8; the gate of the eighth PMOS transistor MP8 is connected to the gate and drain of the seventh PMOS transistor MP7 and the drain of the seventh NMOS transistor MN7; and the drain of the eighth PMOS transistor MP8 is connected to one end of the third resistor R3.
[0019] As a preferred embodiment, the voltage output resistor is a third resistor R3; one end of the third resistor R3 is connected to the ground rail, and the other end is connected to the drain of the eighth PMOS transistor MP8, serving as the output of the entire circuit.
[0020] As a preferred embodiment, the channel width ratio of the first NMOS transistor MN1 and the third NMOS transistor MN3 is 1:1; the channel width ratio of the first NMOS transistor MN1 and the fifth NMOS transistor MN5 is 1:1; the channel width ratio of the second NMOS transistor MN2 and the fourth NMOS transistor MN4 is 1:1; the channel width ratio of the second NMOS transistor MN2 and the sixth NMOS transistor MN6 is 1:1; the channel width ratio of the first PMOS transistor MP1 and the second PMOS transistor MP2 is 1:1; the channel width ratio of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 is 1:1; the channel width ratio of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 is 1:1; and the channel width ratio of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 is 1:1.
[0021] The beneficial effects of this invention are as follows: by using a set of common source and common gate current mirrors, the original output sampling current is copied, so that the source of the high voltage tube in the traditional structure can be grounded. According to the characteristics of the device structure, a power tube with a higher source-drain withstand voltage can be selected, making the application range of the circuit wider. Attached Figure Description
[0022] Figure 1 This invention provides an overvoltage detection circuit for a high-voltage charge pump.
[0023] Figure 2 This is a traditional high-voltage charge pump overvoltage detection circuit without current mirror sampling.
[0024] Wherein, MN1 is the first NMOS transistor, MN2 is the second NMOS transistor, MN3 is the third NMOS transistor, MN4 is the fourth NMOS transistor, MN5 is the fifth NMOS transistor, MN6 is the sixth NMOS transistor, MN7 is the seventh NMOS transistor, MP1 is the first PMOS transistor, MP2 is the second PMOS transistor, MP3 is the third PMOS transistor, MP4 is the fourth PMOS transistor, MP5 is the fifth PMOS transistor, MP6 is the sixth PMOS transistor, MP7 is the seventh PMOS transistor, MP8 is the eighth PMOS transistor, C1 is the compensation capacitor, R1 is the first resistor, R2 is the second resistor, and R3 is the third resistor. Detailed Implementation
[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0026] like Figure 1As shown, the high-voltage charge pump detection circuit proposed in this invention includes a bias circuit, a current mirror circuit, an error amplifier, a compensation capacitor, a negative feedback structure, a current sampling circuit, and a voltage output resistor.
[0027] Bias circuit: Provides appropriate bias for the error amplifier;
[0028] Current mirror circuit: ensures that the currents in the two branches being detected are equal;
[0029] Error amplifier: Combined with a negative feedback structure, it achieves voltage clamping.
[0030] The above three modules constitute the basic structure of the voltage subtractor in the overvoltage detection circuit, which can convert the voltage difference into a current signal.
[0031] Compensation capacitor: Miller compensation is used to change the positions of the dominant and secondary poles and enhance the stability of the circuit;
[0032] Negative feedback structure: Combined with an error amplifier, it achieves voltage clamping.
[0033] Current sampling circuit: By changing the output position of the circuit, a wider range of high-voltage tube models can be selected;
[0034] Voltage output resistor: Used to convert current signals into voltage signals for output.
[0035] The current sampling circuit changes the circuit structure through a current mirror, allowing the source of the high-voltage NMOS to be grounded, enabling the selection of models with higher voltage withstand capability and achieving wider applications.
[0036] The bias circuit includes a first NMOS transistor and a second NMOS transistor;
[0037] The drain and gate of the first NMOS transistor MN1 are interconnected and connected to the source of the second NMOS transistor MN2; the source of the first NMOS transistor MN1 is connected to the ground rail; the drain and gate of the second NMOS transistor MN2 are interconnected and connected to the output of the reference current source.
[0038] Preferably, the current mirror circuit includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6;
[0039] The gate of the third NMOS transistor MN3 is connected to the gate and drain of the first NMOS transistor MN1 and the gate of the fifth NMOS transistor MN5; the source of the third NMOS transistor MN3 is connected to the ground rail; the drain of the third NMOS transistor MN3 is connected to the source of the fourth NMOS transistor MN4; the gate of the fourth NMOS transistor MN4, the drain and gate of the second NMOS transistor MN2, and the gate of the sixth NMOS transistor MN6 are connected; the source of the fifth NMOS transistor MN5 is grounded to the ground rail; the drain of the fifth NMOS transistor MN5 is connected to the source of the sixth NMOS transistor MN6; the drain of the sixth NMOS transistor MN6 is connected to the drain of the fourth PMOS transistor MP4, the positive terminal of the first capacitor C1, and the gate of the seventh NMOS transistor MN7.
[0040] Preferably, the error amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP4;
[0041] The drain and gate of the first PMOS transistor MP1 are interconnected and connected to the gate of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3. The source of the first PMOS transistor MP1 is connected to one end of the first resistor R1. The source of the second PMOS transistor MP2 is connected to one end of the second resistor R2. The drain of the second PMOS transistor MP2 is connected to the source of the fourth PMOS transistor MP4. The gate and drain of the third PMOS transistor MP3 are interconnected and connected to the gate of the fourth PMOS transistor MP4. The drain of the fourth PMOS transistor MP4 is connected to the drain of the sixth NMOS transistor MN6, the positive terminal of the first capacitor C1, and the gate of the seventh NMOS transistor MN7, serving as the output of the error amplifier.
[0042] Preferably, the compensation capacitor is a first capacitor C1;
[0043] The positive terminal of the first capacitor is connected to the gate of the seventh NMOS transistor MN7, the drain of the sixth NMOS transistor MN6, and the drain of the fourth PMOS transistor MP4; the negative terminal is connected to the ground rail.
[0044] Preferably, the negative feedback structure includes a seventh NMOS transistor MN7, a fifth PMOS transistor MP5, and a seventh PMOS transistor MP7;
[0045] The gate of the seventh NMOS transistor MN6 is connected to the positive terminal of the first capacitor, the drain of the sixth NMOS transistor MN6, and the drain of the fourth PMOS transistor MP4; the source of the seventh NMOS transistor MN7 is connected to the ground rail; the drain of the seventh NMOS transistor MN7 is connected to the drain and source of the seventh PMOS transistor MP7 and the gate of the eighth PMOS transistor MP8; the source of the fifth PMOS transistor MP5 is connected to the source of the second PMOS transistor MP2 and one end of the second resistor R2; the gate and drain of the fifth NMOS transistor MN5 are interconnected and connected to the gate of the sixth PMOS transistor MP6 and the source of the seventh PMOS transistor MP7; the gate and drain of the seventh PMOS transistor MP7 are interconnected and connected to the gate of the eighth PMOS transistor MP8 and the drain of the seventh NMOS transistor MN7.
[0046] Preferably, the current sampling circuit includes a first resistor R1, a second resistor RR2, a sixth PMOS transistor MP6, and an eighth PMOS transistor MP8;
[0047] One end of the first resistor R1 is connected to the source of the first PMOS transistor MP1; the other end of the first resistor R1 is connected to the power supply voltage VDD; one end of the second resistor R2 is connected to the source of the second PMOS transistor MP2, the source of the fifth PMOS transistor MP5, and the source of the sixth PMOS transistor MP6; the other end of the second resistor R2 is connected to the charge pump output voltage VCP; the gate of the sixth PMOS transistor MP6 is connected to the drain and gate of the fifth PMOS transistor MP5 and the source of the seventh PMOS transistor MP7; the drain of the sixth PMOS transistor MP6 is connected to the source of the eighth PMOS transistor MP8; the gate of the eighth PMOS transistor MP8 is connected to the gate and drain of the seventh PMOS transistor MP7 and the drain of the seventh NMOS transistor MN7; the drain of the eighth PMOS transistor MP8 is connected to one end of the third resistor R3.
[0048] Preferably, the voltage output resistor is a third resistor;
[0049] One end of the third resistor R3 is connected to the ground rail, and the other end is connected to the drain of the eighth PMOS transistor MP8, serving as the output of the entire circuit.
[0050] Preferably, the channel width ratio of the first NMOS transistor MN1 to the third NMOS transistor MN3 is 1:1; the channel width ratio of the first NMOS transistor MN1 to the fifth NMOS transistor MN5 is 1:1; the channel width ratio of the second NMOS transistor MN2 to the fourth NMOS transistor MN4 is 1:1; the channel width ratio of the second NMOS transistor MN2 to the sixth NMOS transistor MN6 is 1:1; the channel width ratio of the first PMOS transistor MP1 to the second PMOS transistor MP2 is 1:1; the channel width ratio of the third PMOS transistor MP3 to the fourth PMOS transistor MP4 is 1:1; the channel width ratio of the fifth PMOS transistor MP5 to the sixth PMOS transistor MP6 is 1:1; and the channel width ratio of the seventh PMOS transistor MP7 to the eighth PMOS transistor MP8 is 1:1.
[0051] Figure 2 As can be seen from the traditional overvoltage detection structure, the source of the high-voltage NMOS in this structure must be connected to a resistor, and the voltage rating of the selected device is lower than that of this invention.
[0052] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A high-voltage charge pump overvoltage detection circuit, characterized in that, Includes bias circuit, current mirror circuit, error amplifier, compensation capacitor, negative feedback structure, current sampling circuit, and voltage output resistor; Bias circuit: provides bias for the error amplifier; Current mirror circuit: ensures that the currents in the two branches being detected are equal; Error amplifier: Combined with a negative feedback structure, it achieves voltage clamping. Compensation capacitor: Miller compensation is used to change the positions of the dominant and secondary poles and enhance the stability of the circuit; Negative feedback structure: Combined with an error amplifier, it achieves voltage clamping. Current sampling circuit: Changes the output position of the circuit; Voltage output resistor: Used to convert current signals into voltage signals for output.
2. The high-voltage charge pump overvoltage detection circuit according to claim 1, characterized in that, The bias circuit includes a first NMOS transistor MN1 and a second NMOS transistor MN2; the drain and gate of the first NMOS transistor MN1 are interconnected and connected to the source of the second NMOS transistor MN2; the source of the first NMOS transistor MN1 is connected to the ground rail; the drain and gate of the second NMOS transistor MN2 are interconnected and connected to the output of the reference current source.
3. The high-voltage charge pump overvoltage detection circuit according to claim 1, characterized in that, The current mirror circuit includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6; The gate of the third NMOS transistor MN3 is connected to the gate and drain of the first NMOS transistor MN1 and the gate of the fifth NMOS transistor MN5; the source of the third NMOS transistor MN3 is connected to the ground rail; the drain of the third NMOS transistor MN3 is connected to the source of the fourth NMOS transistor MN4; the gate of the fourth NMOS transistor MN4, the drain and gate of the second NMOS transistor MN2, and the gate of the sixth NMOS transistor MN6 are connected; the source of the fifth NMOS transistor MN5 is grounded to the ground rail; the drain of the fifth NMOS transistor MN5 is connected to the source of the sixth NMOS transistor MN6; the drain of the sixth NMOS transistor MN6 is connected to the drain of the fourth PMOS transistor MP4, the positive terminal of the first capacitor C1, and the gate of the seventh NMOS transistor MN7.
4. The high-voltage charge pump overvoltage detection circuit according to claim 1, characterized in that, The error amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP4; The drain and gate of the first PMOS transistor MP1 are interconnected and connected to the gate of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3. The source of the first PMOS transistor MP1 is connected to one end of the first resistor. The source of the second PMOS transistor MP2 is connected to one end of the second resistor R2. The drain of the second PMOS transistor MP2 is connected to the source of the fourth PMOS transistor MP4. The gate and drain of the third PMOS transistor MP3 are interconnected and connected to the gate of the fourth PMOS transistor MP4. The drain of the fourth PMOS transistor MP4 is connected to the drain of the sixth NMOS transistor MP6, the positive terminal of the first capacitor C1, and the gate of the seventh NMOS transistor MN7, serving as the output of the error amplifier.
5. The high-voltage charge pump overvoltage detection circuit according to claim 1, characterized in that, The compensation capacitor is the first capacitor C1; the positive terminal of the first capacitor is connected to the gate of the seventh NMOS transistor MN7, the drain of the sixth NMOS transistor MN6, and the drain of the fourth PMOS transistor MP4; the negative terminal is connected to the ground rail.
6. The high-voltage charge pump overvoltage detection circuit according to claim 1, characterized in that, The negative feedback structure includes the seventh NMOS transistor MN7, the fifth PMOS transistor MP5, and the seventh PMOS transistor MP7; The gate of the seventh NMOS transistor MP7 is connected to the positive terminal of the first capacitor, the drain of the sixth NMOS transistor MN6, and the drain of the fourth PMOS transistor MP4; the source of the seventh NMOS transistor MN7 is connected to the ground rail; the drain of the seventh NMOS transistor MN7 is connected to the drain and source of the seventh PMOS transistor MP7 and the gate of the eighth PMOS transistor MP8; the source of the fifth PMOS transistor MP5 is connected to the source of the second PMOS transistor MP2 and one end of the second resistor R2; the gate and drain of the fifth NMOS transistor MN5 are interconnected and connected to the gate of the sixth PMOS transistor MP6 and the source of the seventh PMOS transistor MP7; the gate and drain of the seventh PMOS transistor MP7 are interconnected and connected to the gate of the eighth PMOS transistor MP8 and the drain of the seventh NMOS transistor MN7.
7. The high-voltage charge pump overvoltage detection circuit according to claim 1, characterized in that, The current sampling circuit includes a first resistor, a second resistor, a sixth PMOS transistor, and an eighth PMOS transistor; One end of the first resistor R1 is connected to the source of the first PMOS transistor MP1; the other end of the first resistor R1 is connected to the power supply voltage VDD; one end of the second resistor R2 is connected to the source of the second PMOS transistor MP2, the source of the fifth PMOS transistor MP5, and the source of the sixth PMOS transistor MP6; the other end of the second resistor R2 is connected to the charge pump output voltage VCP; the gate of the sixth PMOS transistor MP6 is connected to the drain and gate of the fifth PMOS transistor MP5 and the source of the seventh PMOS transistor MP7; the drain of the sixth PMOS transistor MP6 is connected to the source of the eighth PMOS transistor MP8; the gate of the eighth PMOS transistor MP8 is connected to the gate and drain of the seventh PMOS transistor MP7 and the drain of the seventh NMOS transistor MN7; the drain of the eighth PMOS transistor MP8 is connected to one end of the third resistor R3.
8. The high-voltage charge pump overvoltage detection circuit according to claim 1, characterized in that, The voltage output resistor is the third resistor R3; one end of the third resistor R3 is connected to the ground rail, and the other end is connected to the drain of the eighth PMOS transistor MP8, and serves as the output of the entire circuit.
9. The high-voltage charge pump overvoltage detection circuit according to claim 1, characterized in that, The channel width ratio of the first NMOS transistor MN1 and the third NMOS transistor MN3 is 1:1; the channel width ratio of the first NMOS transistor MN1 and the fifth NMOS transistor MN5 is 1:1; the channel width ratio of the second NMOS transistor MN2 and the fourth NMOS transistor MN4 is 1:1; the channel width ratio of the second NMOS transistor MN2 and the sixth NMOS transistor MN6 is 1:1; the channel width ratio of the first PMOS transistor MP1 and the second PMOS transistor MP2 is 1:1; the channel width ratio of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 is 1:1; the channel width ratio of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 is 1:1; the channel width ratio of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 is 1:1.