A phase closing control method based on cycle determination and neighborhood matching

Abstract

The present application relates to the technical field of initial phase controllable power supply, in particular to a phase closing control method based on cycle determination and neighborhood matching, which mainly covers the cycle part, the matching part and the delay compensation part. In the cycle part, with the help of cycle determination, the disturbance caused by the instantaneous response of the input instruction to the phase angle locking can be effectively filtered out, thereby ensuring the stability of the system before triggering. In the matching part, the matching mechanism is expanded from single-point matching to neighborhood matching, and the equality constraint is relaxed to interval constraint, so as to improve the operation efficiency of the system. In the delay compensation part, based on the quantitative analysis of the sampling offset and the hardware response time of the system, the output deviation is corrected by using the compensation function. Theoretical analysis and experiment are carried out on the existing initial phase adjustable power supply based on digital phase-locked loop, and the results show that the control method proposed in the present application can improve the output stability of the initial phase controllable power supply based on digital phase-locked loop, and control the output error within ±0.18°.

Description

Technical Field

[0001] This invention relates to the field of initial phase controllable power supply technology, and in particular to a phase closing control method based on cyclic determination and neighborhood matching. Background Technology

[0002] The initial phase controllable power supply experimental device is widely used in transformer inrush current testing, aerospace motor control and testing, and other fields. When a transformer is switched on under no-load conditions, the residual magnetism and the initial phase angle of the conduction voltage can easily lead to core saturation, generating an inrush current that can reach 6-8 times the rated current. The specific value depends on the phase at the moment of switching on. This current is similar to the short-circuit current and may cause misjudgment in the relay system and damage to equipment. With the widespread application of high-power transformers in power systems, accurate measurement of the maximum inrush current is crucial. Measuring transformer inrush current requires the use of an initial phase adjustable power supply.

[0003] Currently, the existing technical implementation path of adjustable initial phase power supplies based on digital phase-locked loops (PLLs) is as follows: An isolated voltage signal in phase with the mains power is acquired through a front-end sampling circuit; the phase information of the mains power is extracted in real time using a digital PLL algorithm built into the microprocessor; subsequently, the control program logically compares the real-time phase with the preset input target phase, and outputs a drive command to switching devices such as solid-state relays at the phase matching moment, thus conducting the AC power supply through a closed loop to obtain an output voltage waveform with a specific initial phase angle. However, initial phase control generally suffers from defects such as output oscillation, response delay, and insufficient stability. The underlying principles and adverse effects are mainly reflected in the following aspects:

[0004] 1. The Principle of Output Oscillation Caused by Transient Command Trigger: In a control system based on a digital phase-locked loop (PLL), the PLL tracks the input reference signal by continuously adjusting the frequency and phase of the controlled oscillator. When the user issues a momentary command such as "start triggering" or "change phase angle" via an external button or command interface, the microprocessor's interrupt response or the sudden adjustment of the main loop logic can introduce transient calculation interference to the running PLL algorithm. This transient disturbance causes a sudden change in the phase error function of the PLL, resulting in high-frequency oscillations or phase jumps in the output waveform at the moment of triggering. For precision experiments such as transformer excitation current testing, this unstable initial phase can cause the test data to lose its accuracy and may even induce a huge surge current that damages the experimental equipment.

[0005] 2. Phase Angle Acquisition Failure and Accuracy Loss Due to Discrete Sampling Traditional phase matching devices typically employ "single-point equality matching" logic, requiring the real-time phase to be precisely equal to the target phase. However, microcontroller systems perform discrete sampling based on a fixed frequency. Principle Analysis: Due to the sampling period, the phase angle increases in a stepwise manner in the digital sequence. When the sampling frequency is insufficient or the phase step is too large, the real-time phase often "skips" the target phase point. This causes the system to miss trigger points in the current cycle, forcing it to enter the next cycle or one more cycle to re-find a match, resulting in unpredictable response delays and severely impacting the system's real-time response speed and the reliability of phase acquisition.

[0006] 3. Output Shift Due to Physical Lag in Hardware Links: Existing devices often overlook the physical time elapsed between the issuance of a software instruction and its complete execution in the hardware. Analysis: A complete control link includes MCU instruction execution time, optocoupler isolation drive delay, and the turn-on time of relays or power semiconductor devices. The accumulated physical lag time formed by these components is an objective reality. In a power frequency environment, even with absolutely precise software matching, this physical delay of tens of microseconds or even milliseconds will cause a significant phase shift in the initial phase angle of the actual output voltage waveform. Summary of the Invention

[0007] The purpose of this invention is to provide a phase closing control method based on cyclic determination and neighborhood matching, so as to improve the problems existing in the prior art.

[0008] This invention is implemented as follows: a phase closing control method based on cyclic decision-making and neighborhood matching, comprising the following steps:

[0009] S1. Steady-state verification: Real-time monitoring of the mains phase angle output by the digital phase-locked loop, using multi-cycle continuous cyclic judgment to verify the stability of the phase angle for a preset number of N cycles. After satisfying the steady-state criterion N times consecutively, the system is determined to enter the triggerable state.

[0010] S2, Neighborhood Matching: Construct a neighborhood matching interval centered on the target closing phase angle, determine whether the real-time phase is included in the interval, and generate a closing preparation signal when the interval matching is satisfied.

[0011] S3, Delay Compensation: Quantifies the system's full-link error, calculates the compensation time based on the total error and performs advance correction to eliminate phase offset caused by hardware and software delays, and outputs the final closing signal.

[0012] More preferably, in step S1, the steady-state criterion is: the counter increments once whenever the phase angle reaches or crosses a preset target angle; if a disturbance occurs or the target is not met during the counting process, the counter is reset and counted again; the value of N is 50 ≤ N ≤ 150.

[0013] More preferably, the value of N is 100.

[0014] More preferably, the digital phase-locked loop extracts two orthogonal components of the mains voltage using a second-order generalized integrator SOGI. Among them, the in-phase component The transfer function is: Orthogonal components The transfer function is: ; For the Laplace operator, The fundamental angular frequency of the mains power supply. is the damping coefficient.

[0015] More preferably, in step S2, the neighborhood matching interval is determined by the sampling resolution. Determined, with the target phase angle X as the center, the interval is: .

[0016] More preferably, in step S3, the end-to-end error includes: phase-locked loop (PLL) operation instruction cycle. Hardware sampling phase difference ADC conversion module error and the physical time required for power devices to turn on. The function expression for the total compensation time is: , This refers to the power grid frequency, the mains power standard. =50Hz.

[0017] Compared with the prior art, the present invention has the following advantages: (1) The present invention, through theoretical analysis and experimental results of the existing digital phase-locked loop-based adjustable power supply, shows that the code of the loop part improves the output stability of the system, effectively eliminates and effectively filters out the random disturbances generated by the instantaneous response of the trigger command, greatly improves the stability of the system, and meets the requirements of precision control.

[0018] (2) The matching code in this invention solves the problem of "missed triggering" caused by the inability to strictly satisfy point-to-point precise matching in actual discrete sampling. This invention extends the matching mechanism from single-point matching to neighborhood matching and relaxes the equality constraint to interval constraint, which greatly improves the reliability of the system.

[0019] (3) The delay part of the present invention solves the phase sampling deviation introduced by the capacitive device in the sampling circuit of the original device, the error caused by the response time of the actuator, and the error caused by the software calculation. Combined with the original device, the error is reduced to ±0.18°, which greatly improves the phase control accuracy and meets the requirements of precision control. Attached Figure Description

[0020] Figure 1 The flowchart shows the loop judgment algorithm and delay compensation of this invention embodiment;

[0021] Figure 2 This is a diagram illustrating the overall system architecture in an embodiment of the present invention.

[0022] Figure 3 This is a simplified diagram of the sampling circuit structure in an embodiment of the present invention;

[0023] Figure 4 This is an AC analysis diagram of the sampling circuit in an embodiment of the present invention;

[0024] Figure 5 This is a simplified structural diagram of the ADC analog-to-digital conversion module in an embodiment of the present invention;

[0025] Figure 6 This is a response waveform diagram of the driving module in an embodiment of the present invention;

[0026] Figure 7 This is a response waveform diagram of the solid-state relay module in an embodiment of the present invention;

[0027] Figure 8 This is a code response time diagram in an embodiment of the present invention;

[0028] Figure 9 This is a waveform diagram of different initial phase angles in an embodiment of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0030] Example 1: This example provides a phase closing control method based on cyclic decision-making and neighborhood matching. The overall process is as follows: Figure 1 As shown, this method specifically includes the following three core stages:

[0031] S1: System steady-state verification based on cyclic decision-making;

[0032] The system first monitors the phase angle data output by the digital phase-locked loop (PLL) in real time. The PLL extracts the vertical component of the mains voltage through a second-order generalized integrator, providing the basic signal for phase tracking. Upon receiving a trigger command, the system initiates a stability determination program: by establishing a multi-cycle cyclic determination logic, it tracks the phase angle locking state in real time over a preset number of N (the value of N is preferably 50 ≤ N ≤ 150, typically 100, to ensure the PLL algorithm fully converges to a steady state while also considering the real-time nature of the command response) consecutive signal cycles. The stability determination criterion is: real-time monitoring of the phase angle output by the PLL; whenever the phase angle reaches or crosses a preset target angle, a logic counter increments; if a reset signal is detected before the counting is complete, the counter is cleared and counted again until N consecutive successful matchings of the target phase are achieved, at which point the system is considered to have reached a stable trigger state. During this process, the phase angle data of each cycle is verified to meet the preset stability determination criteria, filtering out random disturbances to the phase angle locking caused by the instantaneous response of the trigger command. After completing the above steady-state verification and determining that the system has reached a stable trigger state, the digital phase-locked loop will continuously output stable and reliable phase angle data, providing continuous and effective signal input for the subsequent target phase angle matching stage.

[0033] In some embodiments, the triggering condition for the reset signal is that the phase angle has not reached or crossed the preset target angle. The specific mechanism is that when the triggering condition of the reset signal is met, the counter will be cleared and the counting will start again until the target phase is successfully matched, and the system will be determined to have reached a stable triggering state. The reset signal can be divided into "power-on reset" and "hardware reset". The specific mechanism is that after the reset signal is triggered, the microcontroller's internal control register is forced to fall back to the hardware preset initial value.

[0034] The phase-locked loop extracts the vertical component of the mains voltage using a second-order generalized integrator. Its transfer function is: , Let be the transfer function of the second-order generalized integrator (SOGI). For the Laplace complex frequency operator, The fundamental resonant angular frequency of the mains power supply. This is the damping coefficient (bandwidth coefficient). The fundamental component, which is in phase with the input mains power, is directly taken from the SOGI direct-through branch;

[0035] In-phase component The complex frequency domain expression is In the formula, Input mains voltage signal Laplace transform, That is, the transfer function of the in-phase branch, which is the same as the one mentioned earlier. Consistent;

[0036] Orthogonal components Generated by SOGI orthogonal branches, its transfer function is similar to Sharing the same second-order denominator, only the numerators differ, the complex frequency domain expression is:

[0037] ;

[0038] right and By performing inverse Laplace transforms on each component, the in-phase components in the time domain can be obtained. and orthogonal components The two components share the resonant pole of the second-order generalized integrator, and achieve orthogonal outputs with a 90° phase difference through different numerator terms, providing the basic signal for subsequent phase-locked loop phase calculations.

[0039] S2: Neighborhood matching mechanism based on interval constraints;

[0040] To address the "lateral discretization" phenomenon in sampling systems along the time axis, this invention relaxes the traditional single-point equality matching logic into interval inclusion judgment logic. The "lateral discretization" referred to in this invention specifically refers to the quantization processing performed on continuous analog signals by the sampling control system along the time axis. Unlike amplitude quantization caused by ADC conversion, lateral discretization is determined by the system sampling frequency. The continuously changing mains phase trajectory is determined Forced to be divided into time intervals The discrete state sequence is expressed as follows: This discretization process introduces an inherent "sampling blind zone" in the phase domain, the width of which is equal to the single-step phase increment. Therefore, lateral discretization determines the theoretical limit of phase control accuracy and is the fundamental cause of steady-state phase tracking errors. In the execution architecture of the digital control algorithm, to ensure the uniformity and efficiency of trigonometric function operations, the system standardizes the mapping between the input angle (°) and the internal computational load (rad). The conversion relationship between the two is defined as follows: , Expresses angle values ​​in degrees (°). The angle value is expressed in radians (rad). The system control chip performs discrete sampling of the 50Hz mains signal at a sampling frequency of Z kHz (the sampling frequency can be selected according to different situations). This lateral discretization in the time domain maps the continuous analog phase trajectory into a series of discrete, stepped sampling points, with a sampling resolution of Z kHz. Let the initial phase angle at the start of sampling be... Then the first The degree of the interrupted sampling can be expressed as: And the specific formula for calculating the resolution is: ,in, To control the sampling frequency of the chip, This refers to the phase sampling resolution (the phase interval between two adjacent samples). For the first The actual phase angle output by the phase-locked loop during the next interrupt sampling. The initial phase angle is the time when sampling begins (the first sampling). This represents the number of sampling interruptions (sampling point number). express The value range is non-negative integers (0, 1, 2, 3...); if the initial phase angle of the target voltage set by the system is X, then due to the limitations of lateral discretization, the point-to-point precise matching condition... In actual discrete sampling, it is almost impossible to strictly meet the requirements. If precise matching is forced, it will lead to a serious "missed triggering" phenomenon.

[0041] After completing the system steady-state verification in step S1 and determining that the system has reached a stable triggering state, this invention proceeds to the phase angle matching determination stage. To address the problem of missed triggers in single-point matching under discrete sampling conditions, this invention extends the matching mechanism from single-point matching to neighborhood matching, and relaxes the equality constraint to an interval constraint. Considering the angular interval between adjacent sampling points is... The maximum theoretical deviation between the target initial phase angle X and the nearest sampling point does not exceed Convert it to radians: , The theoretical maximum phase angle error (in radians) is introduced to the neighborhood matching mechanism; based on this, a dynamic matching window centered on the target phase angle X is constructed: This ensures that all target phase angles can be reliably matched, even considering sampling and quantization errors. Based on the aforementioned analysis of discrete sampling and neighborhood matching mechanisms, this method, while improving the system's matching reliability, also introduces a theoretical maximum limit of... The steady-state phase angle error. In actual execution, when the current phase angle data output by the digital phase-locked loop falls within the above dynamic matching window, it is determined that the target phase angle is successfully matched, triggering the subsequent closing control logic.

[0042] S3. End-to-End Quantization Error and Delay Compensation: After completing the system steady-state verification in step S1 and the target phase neighborhood matching determination in step S2, the system has identified that the current phase falls into the target window. However, from the time the software determines a successful match to the actual closing of the power device, there are inherent delays and errors in multiple stages of the entire control link: including the time consumed by the phase-locked loop operation, hardware sampling phase deviation, ADC conversion delay, and power device conduction time. These factors will cause the actual closing time to lag behind the target phase, resulting in closing errors. Therefore, after completing the phase matching determination, this invention enters the end-to-end quantization error and delay compensation stage, actively compensating for the deviations caused by the aforementioned time-domain delays.

[0043] Error component identification: The total error includes the instruction cycles of the phase-locked loop (PLL) operation. Hardware sampling phase difference ADC conversion module error and the physical time required for power devices to turn on. The aforementioned error components can be pre-determined through factory calibration or online calibration, serving as the basis for compensation calculations. The functional expression for the total compensation time is: , This refers to the power grid frequency, the mains power standard. =50Hz.

[0044] Compensation Implementation: Based on the total compensation time converted into the corresponding phase offset, a delay compensation function is constructed. This mechanism, by pre-setting a correction amount on the time axis and issuing the closing command in advance, ensures that the end time of the total delay coincides exactly with the target phase of the mains waveform, thus ensuring that the final output error is controlled within the preset accuracy range; that is, ensuring the final output phase angle error... satisfy Accordingly, the system can issue a closing command at the compensated time within the target phase window to achieve precise closing under the target phase, and ultimately control the closing phase angle error within the preset accuracy range.

[0045] In summary, this embodiment effectively filters out random disturbances to phase angle locking caused by the instantaneous response of trigger commands through 50-150 cycles of cyclic verification. High-reliability capture accuracy: The neighborhood matching mechanism overcomes the sampling point loss caused by "lateral discretization," controlling the steady-state phase angle error within ±0.18°. Time-domain adaptive compensation: The end-to-end error calibration mechanism eliminates hardware execution lag, achieving precise alignment between the output waveform and the target phase.

[0046] Example 2: Based on Example 1, as follows Figure 2As shown, this embodiment provides a phase closing control system based on cyclic determination and neighborhood matching, used to implement the method in Embodiment 1, including an input module, a signal conditioning module, a flyback power supply, a main control chip, an algorithm processing module, a delay adjustment module, a drive module, an interactive control module, a relay module, a current transformer, a transformer, and an oscilloscope.

[0047] The input module's input terminal is connected to the mains power, and its output terminals are connected to the signal conditioning module and the main circuit, respectively, to provide power input, control input, and command input. A flyback power supply is connected to the input module to provide a stable operating power supply to all modules of the entire device (including the main control chip, algorithm processing module, etc.), ensuring the normal operation of each component. The mains power input is a 220V / 50Hz AC signal, directly taken from the industrial or residential power grid; control inputs include the target initial phase angle parameter (any value within the range of 0-360°) set by the user through the interactive control module and the voltage / current feedback signal collected in real time by the current transformer during system operation; command inputs are user operation commands, input through the physical buttons or rotary encoder of the interactive control module. A transformer is located in the main circuit, connected sequentially to the mains output terminal of the input module, the relay module, and the load side, to achieve electrical isolation and voltage adaptation, converting the mains voltage to an operating voltage suitable for the load, while suppressing common-mode interference in the power grid, ensuring the electrical safety of the device and the load. The signal output from the input module is filtered and amplified by the signal conditioning module before being transmitted to the main control chip. The main control chip serves as the control core of the entire device. The control algorithm processing module executes core algorithms such as loop judgment and neighborhood matching. The algorithm processing module transmits the calculation results to the delay adjustment module, which performs delay compensation based on the end-to-end error analysis results. The output signal of the delay adjustment module is sent to the drive module, which drives the relay module to perform the closing action. The oscilloscope is used to monitor and display the voltage, current waveforms, and phase changes of the entire system in real time, facilitating the observation of the closing effect and error.

[0048] 1) Error analysis of the sampling circuit

[0049] To achieve end-to-end delay compensation, the phase error of the signal sampling stage is first modeled and analyzed: The circuit diagram of the rectifier circuit is as follows... Figure 3 As shown, the circuit contains both AC and DC components. To analyze the phase error between the output and input, we perform an AC analysis by disconnecting the current source, resulting in the circuit diagram shown below. Figure 4 As shown.

[0050] First, analyze the impedance, substituting the capacitance... , , , We can obtain:

[0051] ;

[0052] ;

[0053] ;

[0054] in, The capacitor in the circuit. For resistance, The imaginary unit, The angular frequency of the AC signal. , , , capacitors in order , and resistance AC impedance, This is the equivalent impedance of R3 and C3 connected in parallel. This is the equivalent impedance after Z3 and C2 are connected in series.

[0055] To facilitate calculation, the admittance is transformed. The admittance is , The admittance is , The admittance is Admittances at both ends of AB for , and The sum is:

[0056] ;

[0057] ;

[0058] ;

[0059] ;

[0060] To simplify subsequent calculations, the decimal places are omitted, and further simplification yields: ;in The unit of admittance. The imaginary unit, Indicates parallel connection;

[0061] Therefore, it can be calculated that, for the entire system, the current leads the voltage. Finally, the phase shift of the hardware circuit can be calculated. .

[0062] 2) Error analysis of the ADC analog-to-digital conversion module

[0063] Next, we will continue to model and calculate the phase error introduced by the ADC conversion stage in the signal chain: Figure 5 This is a simplified circuit diagram from the signal source to the ADC analog-to-digital converter module. The parameters in this device are matched with those in the simplified diagram, specifically the sampling resistor. Sampling capacitor Decoupling capacitor The closed-loop output impedance of the operational amplifier The operational amplifier output voltage is .

[0064] Current flowing into node E The expression is: ;

[0065] The current flowing from point E into GND through the decoupling capacitor ,for: ;

[0066] The current flowing from point E into point F for: ;

[0067] According to the KCL of node E, we can obtain: ;

[0068] According to the KCL of node F, we can obtain: ;

[0069] Finally, we can obtain:

[0070] ;

[0071] ;

[0072] in, The current flowing from the operational amplifier to node E, This is the output voltage of the op-amp. Let the voltage at node E be the voltage. Let F be the voltage at node F. Let CQ be the current flowing from node E to GND. Let be the current flowing from node E to node F. For series resistance, For the op-amp output resistor, This is the decoupling capacitor from node E to ground. This is the DC blocking / filtering capacitor for node F to ground.

[0073] Substitute the parameters into the function expression for the total compensation time. Finally, the phase shift was obtained. .

[0074] 3) Drive equipment error analysis

[0075] Subsequently, the hardware response time of the switching execution stage was calibrated through actual measurement: We used an oscilloscope to test the response time of the driver module and the solid-state relay module, and obtained the results. Figure 6 and Figure 7 The figure shows that the total response time of the solid-state relay and the drive module is 372ns.

[0076] 4) Software error analysis

[0077] Besides hardware errors, the latency introduced by the algorithm processing itself is quantified: The following is the time required for a microcontroller to process data and perform loop judgments, measured using breakpoints in Debug mode within the Keil development environment. Specifically, breakpoints are set at the beginning and end of the critical data processing code segment, and the execution time of the instructions between the two breakpoints is recorded using a simulator, thus quantifying the required time. Figure 8 and Figure 9 These represent the time consumed by data processing and the time consumed by loop checks, respectively:

[0078] from Figure 8 The calculation time and loop judgment time of the phase-locked algorithm are 3.917μs and 1.204μs, respectively, which means that it takes 5.121μs from sampling the corresponding phase angle to the output model. Figure 9 Figures (a)-(f) show the experimental results of the closing waveform of the present invention under different target initial phase angles, which are used to verify the accurate phase control effect of the system under any initial phase angle in the range of 0°~300°.

[0079] Based on the error analysis results of the above hardware and software components, the total system delay is calculated and the final compensation scheme is determined: the lag angles of the sampling module and the ADC analog-to-digital conversion module are converted into time, which are 0.288755ms and 0.0000146ms respectively. The total delay time is obtained by adding up the various delay times, which is 0.2942626ms.

[0080] Based on the above measurement results, the formula for the compensation delay time required by the system can be derived as follows:

[0081] ;

[0082] The final result is 0.019710843179s. Since the STM32 standard library only provides microsecond-level integer delay functions, the decimal part is discarded and rounded to the nearest integer in the actual implementation. ;

[0083] The rounding operation introduces a delay deviation of 0.1569 μs, which corresponds to a phase angle error of approximately: (The original text appears to be incomplete and contains errors. A more accurate translation would require the full context.) ;

[0084] Introduced by combining neighborhood matching The maximum error of the system can be obtained. ,Right now .

[0085] The specific steps of the loop judgment algorithm are as follows:

[0086] 1. Initialization preparation: After the system is powered on, the SOGI digital phase-locked loop algorithm is automatically started. The main control chip captures the mains phase angle information in real time at a sampling frequency of ZkHz and updates it continuously. At the same time, it stores the target closing phase angle set by the user.

[0087] 2. Triggering the judgment process: After the user presses the button, the system enters the loop judgment phase and initializes the loop counter i=0;

[0088] 3. Phase angle comparison and judgment: The phase angle acquired in real time is compared with the set target phase angle to determine whether the real-time phase angle information falls within the neighborhood matching interval;

[0089] 4. Loop Counting and Termination Condition: If a single comparison meets the error requirement, counter i is incremented by 1; otherwise, the counter value remains unchanged, and the data acquisition and comparison process is repeated until counter i accumulates to 100 times. If a reset command is encountered during the accumulation phase, counter i is cleared to zero.

[0090] 5. Execute the delay instruction: When the counter reaches 100 times, it is determined that the phase angle has been stably matched, and the delay module executes the delay time calculated based on the error of each part;

[0091] 6. Perform closing action: After the delayed action is completed, a drive signal is output to the drive module;

[0092] 7. Process End: After the circuit is closed, the counter is reset to 0, and the algorithm exits the loop judgment stage.

[0093] This system is applicable to multiple fields such as high-precision control, real-time communication, new energy, and scientific research testing, and has broad prospects for industrial application.

[0094] Below are waveform diagrams showing six different closing angles selected within the range of 0-360°, with a step size of 60°. Figure 9 As shown, the waveforms at different closing angles are exported and analyzed in Matlab. The phase dimension is in degrees, and the error dimension is in millidegrees.

[0095] Table 1. Phase Error Table for Different Initial Phase Angles

[0096]

[0097] Based on the data in the table, the maximum error is 0.168789°, which is within the accuracy range of the theoretical derivation.

[0098] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A phase closing control method based on cyclic decision-making and neighborhood matching, characterized in that, Includes the following steps: S1. Steady-state verification: Real-time monitoring of the mains phase angle output by the digital phase-locked loop, using multi-cycle continuous cyclic judgment to verify the stability of the phase angle for a preset number of N cycles. After satisfying the steady-state criterion N times consecutively, the system is determined to enter the triggerable state. S2, Neighborhood Matching: Construct a neighborhood matching interval centered on the target closing phase angle, determine whether the real-time phase is included in the interval, and generate a closing preparation signal when the interval matching is satisfied. S3, Delay Compensation: Quantifies the system's full-link error, calculates the compensation time based on the total error and performs advance correction to eliminate phase offset caused by hardware and software delays, and outputs the final closing signal.

2. The method according to claim 1, characterized in that, In step S1, the steady-state criterion is as follows: the counter increments once whenever the phase angle reaches or crosses the preset target angle; if a disturbance occurs or the target is not met during the counting process, the counter is reset to zero and counted again; the value of N is 50 ≤ N ≤ 150.

3. The method according to claim 2, characterized in that, The preferred value for N is 100.

4. The method according to claim 3, characterized in that, The digital phase-locked loop extracts two orthogonal components of the mains voltage through a second-order generalized integrator SOGI. Among them, the in-phase component The transfer function is: Orthogonal components The transfer function is: ; For the Laplace operator, The fundamental angular frequency of the mains power supply. is the damping coefficient.

5. The method according to claim 4, characterized in that, In step S2, the neighborhood matching interval is determined by the sampling resolution. Determined, with the target phase angle X as the center, the interval is: .

6. The method according to claim 5, characterized in that, In step S3, the end-to-end error includes: phase-locked loop (PLL) operation instruction cycle. Hardware sampling phase difference ADC conversion module error and the physical time required for power devices to turn on. The function expression for the total compensation time is: , This refers to the power grid frequency, the mains power standard. =50Hz.

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