Dynamic gate stress test high-speed driving circuit and test method

Abstract

The application discloses a dynamic gate stress test high-speed driving circuit and a test method. The on driving module comprises an on unit and at least one on adjusting unit. The on unit comprises an on power supply and a first on switch with a positive pole of the on power supply connected to a drain. Each on adjusting unit comprises an on adjusting power supply and a second on switch. The negative pole of the on adjusting power supply is connected to the positive pole of the on power supply or the positive pole of the adjacent on adjusting power supply. The application solves the problem that the existing dynamic gate stress test relies on the driving circuit which has limited space for improving the gate peak current, resulting in a serious reduction in the actual applied transient voltage change rate voltage, and the problem that it is difficult to realize continuous regulation and stable output of the applied voltage by relying on resistance or capacitance discharge regulation to apply voltage.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device testing technology, and more specifically, relates to a high-speed driving circuit and testing method for dynamic gate stress testing. Background Technology

[0002] Dynamic gate stress testing is a reliability testing method for power semiconductor devices such as silicon carbide and gallium nitride. It primarily involves applying a high-rate-of-change voltage to the gate of the power semiconductor device using a driving circuit. This simulates the transient strong electric field experienced by the power semiconductor device during high-frequency switching, thereby accelerating the exposure of the gate oxide layer and interface defects to assess the long-term operational reliability of the power semiconductor device.

[0003] While existing driving circuits for dynamic gate stress testing can adjust the applied voltage through resistor or capacitor discharge to achieve high-frequency switching of power semiconductor devices, they still have the following application limitations: On the one hand, the parasitic inductance and parasitic resistance in the drive circuit limit the potential for increasing the peak gate current, resulting in a significant reduction in the actual applied high rate of change voltage, which fails to meet the gate stress test requirements. On the other hand, resistors have a narrow range of voltage adjustment and low control precision, while the voltage applied by capacitor discharge decays exponentially with charge loss, making it difficult to achieve continuous adjustment and stable voltage output.

[0004] Based on this, this application proposes a high-speed driving circuit and testing method for dynamic gate stress testing to overcome the above-mentioned defects. Summary of the Invention

[0005] The present invention aims to overcome the limitations of existing dynamic gate stress testing methods in terms of the driving circuit's ability to increase the peak gate current, which leads to a significant reduction in the actual applied instantaneous voltage change rate. It also addresses the problem that relying on resistors or capacitors to adjust the applied voltage makes it difficult to achieve continuous adjustment and stable output of the applied voltage.

[0006] To achieve the above objectives, the present invention provides a high-speed driving circuit and testing method for dynamic gate stress testing.

[0007] According to a first aspect of the present invention, a high-speed driving circuit for dynamic gate stress testing is provided, comprising: The control module is used to generate voltage output commands; A conduction drive module includes a conduction unit and at least one conduction adjustment unit. The conduction unit includes a conduction power supply and a first conduction switch whose drain is connected to the positive terminal of the conduction power supply. Each conduction adjustment unit includes a conduction adjustment power supply and a second conduction switch. The negative terminal of the conduction adjustment power supply is connected to the positive terminal of the conduction power supply or an adjacent positive terminal of the conduction adjustment power supply. The drain of the second conduction switch is connected to the positive terminal of the conduction adjustment power supply, and its source is short-circuited to the source of the first conduction switch. The short-circuit point forms a conduction voltage output terminal to output a conduction voltage according to the voltage output command. A shutdown drive module includes a shutdown unit and at least one shutdown adjustment unit. The shutdown unit includes a shutdown power supply and a first shutdown switch whose source is connected to the negative terminal of the shutdown power supply. Each shutdown adjustment unit includes a shutdown adjustment power supply and a second shutdown switch. The positive terminal of the shutdown adjustment power supply is connected to the negative terminal of the shutdown power supply or the negative terminal of an adjacent shutdown adjustment power supply. The source of the second shutdown switch is connected to the negative terminal of the shutdown adjustment power supply, and its drain is short-circuited to the drain of the first shutdown switch. The short-circuit point forms a shutdown voltage output terminal to output a shutdown voltage according to the voltage output command. An impedance adjustment module, the input terminal of which is connected to the on-voltage output terminal or the off-voltage output terminal; The gate of the device under test is connected to the output terminal of the impedance adjustment module.

[0008] Optionally, the conduction drive module further includes only a conduction unit, which includes a conduction power supply and a first conduction switch whose drain is connected to the positive terminal of the conduction power supply. The source of the first conduction switch forms a conduction voltage output terminal and is connected to a turn-off voltage output terminal.

[0009] Optionally, the shutdown drive module further includes a shutdown unit, which includes a shutdown power supply and a first shutdown switch whose source is connected to the negative terminal of the shutdown power supply. The drain of the first shutdown switch forms a shutdown voltage output terminal and is connected to a conduction voltage output terminal.

[0010] Optionally, the control module includes a controller with a high-speed digital I / O port, the controller being configured to output PWM signals to the gates of the first on switch, the second on switch, the first off switch, and the second off switch via the high-speed digital I / O port, and to communicate with a host computer.

[0011] Optionally, the conduction unit further includes a forward isolation diode, the anode of which is connected to the positive terminal of the conduction power supply, and the cathode of which is connected to the drain of the first conduction switch.

[0012] Optionally, the shutdown unit further includes a reverse isolation diode, the cathode of which is connected to the negative terminal of the shutdown power supply, and the anode of which is connected to the source terminal of the first turn-on switch.

[0013] Optionally, the impedance adjustment module includes a gate adjustment resistor, the input of which is connected to the on-voltage output or the off-voltage output, and the output is connected to the device under test.

[0014] According to a second aspect of the present invention, a test method for dynamic gate stress testing of a high-speed drive circuit based on any one of the above claims is also provided, comprising: Based on the response of the control module, a voltage output command is generated to output a high-level signal to the first and second conducting switches; Adjust the voltage value of the power supply according to the preset adjustment parameters; After a preset duration, a low-level signal is output to the second on switch; Based on the response of the control module, the voltage output command is generated to output a low-level signal to the first on switch and a high-level signal to the first off switch and the second off switch. Adjust the voltage value of the power supply to be turned off according to the preset adjustment parameters; After the preset duration, a low-level signal is output to the second off switch, and it is determined whether the current cycle count has reached the preset number. If so, then terminate the test. If not, then output a high-level signal to the first and second conduction switches again until the test is terminated.

[0015] Optionally, the step of outputting a low level to the second conducting switch after the preset duration specifically includes: After the preset duration, the controller outputs a low-level PWM signal to the second on switch, and the second on switch receives the low-level PWM signal and turns off.

[0016] Optionally, the step of responding to and generating the voltage output command based on the control module to output a low-level signal to the first on switch and a high-level signal to the first off switch and the second off switch specifically includes: The controller receives the reference voltage value, dead time, preset number of times and preset adjustment parameters output by the host computer, and outputs a low-level PWM signal to the first on switch to turn off the first on switch. After the dead time interval, the controller outputs a high-level signal to turn on the first shutdown switch and the second shutdown switch.

[0017] Compared with the prior art, the present invention has the following beneficial effects: The high-speed drive circuit for dynamic gate stress testing proposed in this invention achieves a significant increase in gate peak current by overcoming parasitic parameter limitations and ensuring the actual application effect of high-rate-of-change voltage through a structure in which the conduction drive module uses a series superposition of the conduction power supply and the conduction regulation power supply, and the turn-off drive module uses a series superposition of the turn-off power supply and the turn-off regulation power supply. Furthermore, the output voltage of the conduction regulation power supply and the turn-off regulation power supply can be independently adjusted by the voltage output command generated by the control module, so as to achieve continuous linear adjustment of the conduction and turn-off rates without changing the hardware. In addition, the design of maintaining steady state by the first conduction switch and the first turn-off switch achieves stable output of applied voltage under pure power supply architecture, avoiding the decay characteristics of capacitor discharge. Finally, the physical separation design of the conduction drive module and the turn-off drive module enables completely independent adjustment of the turn-on and turn-off rates, meeting the differentiated needs of different test scenarios.

[0018] The proposed test method based on a high-speed drive circuit for dynamic gate stress testing utilizes a control module to simultaneously turn on the first and second on switches. This outputs a superimposed potential of the on-state power supply and the on-state regulation power supply, increasing the gate voltage change rate and overcoming the transient drive force bottleneck. The on-state regulation power supply voltage is independently and linearly controlled to regulate the turn-on rate, overcoming the drawbacks of traditional speed regulation. After a preset time, the second on switch is turned off, allowing the on-state power supply to maintain steady-state conduction and eliminate voltage overshoot. Furthermore, by simultaneously turning on the first and second off switches, the outputs a superimposed potential of the off-state power supply and the off-state regulation power supply to achieve rapid turn-off. The off-state regulation power supply voltage is then independently and linearly controlled to regulate the turn-off rate. After a preset time, the first off switch is turned off, allowing the off-state power supply to maintain steady-state turn-off. Continuous testing is completed after a certain number of cycles, meeting the requirements for dynamic gate stress testing.

[0019] As can be seen from the above, the technical solution of the present invention can effectively solve the problems that the existing dynamic gate stress test relies on a driving circuit that has limited room for increasing the peak gate current, resulting in a serious reduction in the actual applied instantaneous voltage change rate, and that it is difficult to achieve continuous adjustment and stable output of the applied voltage by relying on the discharge adjustment of resistors or capacitors.

[0020] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0021] Figure 1 This is a topology diagram of a high-speed drive circuit for dynamic gate stress testing according to an embodiment of the present invention; Figure 2 This is a topology diagram of a high-speed drive circuit for dynamic gate stress testing in one embodiment of the present invention. Figure 3 This is a topology diagram of a high-speed drive circuit for dynamic gate stress testing in another embodiment of the present invention. Figure 4 This is a flowchart illustrating the dynamic gate stress testing method according to an embodiment of the present invention. Detailed Implementation

[0022] To enable those skilled in the art to more fully understand the technical solutions of the present invention, exemplary embodiments of the present invention will be described more comprehensively and in detail below with reference to the accompanying drawings. Obviously, the one or more embodiments of the present invention described below are merely one or more specific ways to implement the technical solutions of the present invention, and are not exhaustive. It should be understood that other ways belonging to a general inventive concept can be used to implement the technical solutions of the present invention, and should not be limited to the embodiments described exemplary. Based on one or more embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0023] Reference Figure 1-3 An embodiment of the present invention provides a high-speed driving circuit for dynamic gate stress testing, comprising: The control module is used to generate voltage output commands; A conduction drive module includes a conduction unit and at least one conduction adjustment unit. The conduction unit includes a conduction power supply VCC1 and a first conduction switch Q1 whose drain is connected to the positive terminal of the conduction power supply VCC1. Each conduction adjustment unit includes a conduction adjustment power supply VCC2 and a second conduction switch Q2. The negative terminal of the conduction adjustment power supply VCC2 is connected to the positive terminal of the conduction power supply VCC1 or the positive terminal of an adjacent conduction adjustment power supply VCC2. The drain of the second conduction switch Q2 is connected to the positive terminal of the conduction adjustment power supply VCC2, and its source is short-circuited to the source of the first conduction switch Q1. The short-circuit point forms a conduction voltage output terminal to output a conduction voltage according to a voltage output command. A shutdown drive module includes a shutdown unit and at least one shutdown adjustment unit. The shutdown unit includes a shutdown power supply VEE1 and a first shutdown switch Q3 whose source is connected to the negative terminal of the shutdown power supply VEE1. Each shutdown adjustment unit includes a shutdown adjustment power supply VEE2 and a second shutdown switch Q4. The positive terminal of the shutdown adjustment power supply VEE2 is connected to the negative terminal of the shutdown power supply VEE1 or the negative terminal of an adjacent shutdown adjustment power supply VEE2. The source of the second shutdown switch Q4 is connected to the negative terminal of the shutdown adjustment power supply VEE2, and its drain is short-circuited with the drain of the first shutdown switch Q3. The short-circuit point forms a shutdown voltage output terminal to output a shutdown voltage according to a voltage output command. The impedance adjustment module has its input terminal connected to either the on-state voltage output terminal or the off-state voltage output terminal. The gate of the device under test is connected to the output of the impedance adjustment module.

[0024] Specifically, the embodiments of the present invention address the problem of limited space for increasing gate peak current by employing a structure in which the turn-on drive module uses a series superposition of a turn-on power supply VCC1 and at least one turn-on regulating power supply VCC2, and the turn-off drive module uses a series superposition of a turn-off power supply VEE1 and at least one turn-off regulating power supply VEE2. Under the triggering of a voltage output command, the first turn-on switch Q1 and the second turn-on switch Q2, and the first turn-off switch Q3 and the second turn-off switch Q4 are simultaneously turned on to output a transient drive potential with a higher amplitude, thereby overcoming the limitations of parasitic parameters and significantly increasing the gate peak current, ensuring the actual application effect of high rate of change voltage.

[0025] To address the problem of difficulty in continuously and stably regulating voltage, embodiments of the present invention generate voltage output commands through a control module, which can independently adjust the output voltage of the power supply VCC2 and the power supply VEE2. Without replacing the impedance adjustment module or relying on capacitor charging and discharging, continuous linear adjustment of the turn-on and turn-off rates can be achieved. Furthermore, the pure power supply architecture can avoid the attenuation characteristics of capacitor discharge. Combined with the design of maintaining a steady state by the first turn-on switch Q1 and the first turn-off switch Q3, the stability of the applied voltage is guaranteed. At the same time, the physical separation of the turn-on and turn-off paths can meet the differentiated needs of different test scenarios.

[0026] In one specific embodiment, the on-power supply VCC1 and the off-power supply VEE1 are the reference positive power supply and the reference negative power supply, respectively; the on-regulation power supply VCC2 and the off-regulation power supply VEE2 are the floating ground positive power supply and the floating ground negative power supply, respectively. Alternatively, the power supply VCC1 and the regulating power supply VCC2, and the power supply VEE1 and the regulating power supply VEE2 can be set as the positive and negative floating ground power supplies, respectively.

[0027] Specifically, this embodiment adopts at least two-level superposition structures on both the on-side and off-side to realize the on- or off-side voltage output, thereby enabling the output of the superposition value of multiple voltage levels, further improving the transient driving potential of the device under test.

[0028] When the power supply VCC1 is the reference positive power supply and the power supply VCC2 is the floating ground positive power supply, a high transient potential can be output through at least two stages of series superposition to meet the requirements of extreme accelerated stress testing of 1V / ns and above. If both the power supply VCC1 and the power supply VCC2 are set as floating ground positive power supplies, the stacked structure can be expanded to further improve the upper limit of transient driving force and greatly broaden the speed regulation range of the drive circuit. It can switch between various needs such as extreme acceleration, routine testing, and compatibility adaptation without changing the hardware, taking into account both test accuracy and versatility.

[0029] When the power supply VEE1 is the reference negative power supply, the positive terminal of the power supply VEE2 is connected to the negative terminal of the power supply VEE1 to form a floating ground superimposed structure. The first power-off switch Q3 and the second power-off switch Q4 are synchronously turned on during the power-off transient, which can output a superimposed high transient potential, greatly improve the power-off transient driving force, and meet the requirements of extreme accelerated stress testing of 1V / ns and above. When the shutdown power supply VEE1 is a floating negative power supply, it can form at least a two-stage floating voltage stacked structure with the shutdown regulating power supply VEE2 to further improve the upper limit of transient drive potential and adapt to more demanding test scenarios. Meanwhile, the shutdown regulating power supply VEE2 is fixed as a floating superimposed negative power supply, which can always ensure its floating characteristics based on the potential of the shutdown power supply VEE1, avoiding voltage overshoot problems caused by common ground potential conflicts. At the same time, in conjunction with the voltage output command of the control module, the output voltage of the shutdown regulating power supply VEE2 can be independently adjusted to achieve continuous linear adjustment of the shutdown rate, adapting to different test requirements without changing the hardware.

[0030] The high-speed drive circuit for dynamic gate stress testing of the present invention also has the following two implementation methods: like Figure 2 As shown, in one embodiment, the conduction drive module further includes only a conduction unit, which includes a conduction power supply VCC1 and a first conduction switch Q1 whose drain is connected to the positive terminal of the conduction power supply VCC1. The source of the first conduction switch Q1 forms a conduction voltage output terminal and is connected to a turn-off voltage output terminal.

[0031] In one specific embodiment, the power supply VCC1 and the power supply VEE1 are the positive and negative reference power supplies, respectively.

[0032] In one specific embodiment, the power supply VEE2 is turned off as a floating negative power supply.

[0033] Specifically, this embodiment adopts a method where the conduction side uses only the conduction power supply VCC1 to achieve the conduction voltage output, while the shutdown side uses at least a two-level superposition structure composed of the shutdown power supply VEE1 and the shutdown regulation power supply VEE2 to achieve the shutdown voltage output. This method is applicable to test scenarios that only require unidirectional high-speed stress testing, thereby simplifying the circuit layout and reducing test costs.

[0034] It is worth noting that since this implementation method only constructs a floating ground stack structure on the turn-off side to achieve high-speed turn-off stress testing, the turn-on power supply VCC1 and the turn-off power supply VEE1 can meet the steady-state turn-on requirements as reference power supplies to establish the grounding foundation of the drive circuit. After grounding, a stable low potential reference can be provided to ensure that the gate-source voltage of the device under test is at a steady-state value that meets the specifications when the device under test is turned on or off.

[0035] like Figure 3As shown, in another embodiment, the shutdown drive module further includes only a shutdown unit, which includes a shutdown power supply VEE1 and a first shutdown switch Q3 whose source is connected to the negative terminal of the shutdown power supply VEE1. The drain of the first shutdown switch Q3 forms a shutdown voltage output terminal and is connected to the conduction voltage output terminal.

[0036] In one specific embodiment, the power supply VCC1 and the power supply VEE1 are the positive and negative reference power supplies, respectively.

[0037] In one specific embodiment, the power supply VCC2 is a floating ground positive power supply.

[0038] Specifically, this embodiment adopts a two-stage superposition structure consisting of a power supply VCC1 and a power supply VCC2 on the conducting side to achieve the conduction voltage output, while the turning-off side only uses the power supply VEE1 to achieve the turning-off voltage output. This can be applied to test scenarios that only require unidirectional high-speed stress testing, thereby simplifying the circuit layout and reducing the test cost.

[0039] Furthermore, it is worth noting that in other embodiments, the dynamic gate stress test high-speed drive circuit of the present invention may also be a number of independent drive circuits composed of one or more of the above three embodiments, and the number of independent drive circuits are all integrated and controlled by the same controller. Each independent drive circuit can independently adjust the gate-source voltage change rate to significantly improve the testing efficiency of power semiconductors.

[0040] In one embodiment, the control module includes a controller with a high-speed digital I / O port. The controller is configured to output pulse width modulation (PWM) signals to the gates of the first on switch Q1, the second on switch Q2, the first off switch Q3, and the second off switch Q4 via the high-speed digital I / O port, and is communicatively connected to a host computer.

[0041] Specifically, the high-speed digital I / O port has a nanosecond-level response speed and can output high-frequency, high-precision PWM signals. The controller outputs PWM signals synchronously to the first on switch Q1 and the second on switch Q2 to achieve the superposition output of the turn-on transient power supply VCC1 and the turn-on regulating power supply VCC2, providing high-current fast charging. By synchronously outputting PWM signals to the first off switch Q3 and the second off switch Q4, the controller achieves the superposition output of the turn-off transient power supply VEE1 and the turn-off regulating power supply VEE2, quickly releasing the gate charge.

[0042] Meanwhile, by precisely controlling the pulse width of the PWM signal, the controller can turn off the second turn-on switch Q2 and the second turn-off switch Q4 in advance when the gate voltage is close to the steady-state value. The steady state is maintained only by the turn-on power supply VCC1 and the turn-off power supply VEE1, which eliminates voltage overshoot in principle and ensures that the gate voltage change rate is stable and meets the test requirements.

[0043] In one specific embodiment, the controller is a Field-Programmable Gate Array (FPGA), a High-speed Complex Programmable Logic Device (CPLD), a High-performance Microcontroller Unit with Nanosecond-level I / O, a Specialized Timing Control Chip (ASIC), or a Digital Signal Processor (DSP). The control principles of these controllers are all existing technologies, and will not be elaborated upon further here.

[0044] In one embodiment, the conduction unit further includes a forward isolation diode D1. The anode of the forward isolation diode D1 is connected to the positive terminal of the conduction power supply VCC1, and the cathode is connected to the drain of the first conduction switch Q1. Specifically, when the control module triggers the conduction voltage output command, and the second conduction switch Q2 of the conduction adjustment unit is turned on, the potential of the conduction adjustment power supply VCC2 is higher than that of the conduction power supply VCC1. The forward isolation diode D1 is in a reverse cutoff state, which can block the reverse current flowing from the conduction adjustment power supply VCC2 to the conduction power supply VCC1, thereby preventing the conduction power supply VCC1 from being overloaded or damaged due to current reverse flow. At the same time, it does not affect the normal drive current provided by the conduction power supply VCC1 to the first conduction switch Q1 in the steady state phase, ensuring the stable operation of the conduction drive module in the transient superposition and steady state maintenance phases.

[0045] In one embodiment, the shutdown unit further includes a reverse isolation diode D2. The cathode of the reverse isolation diode D2 is connected to the negative terminal of the shutdown power supply VEE1, and the anode is connected to the source of the first shutdown switch Q3. Specifically, when the control module triggers the shutdown voltage output command and the second shutdown switch Q4 of the shutdown regulation unit is turned on, the potential of the shutdown regulation power supply VEE2 is lower than that of the shutdown power supply VEE1. The reverse isolation diode D2 is in a reverse cutoff state, which can block the reverse current flowing from the shutdown regulation power supply VEE2 to the shutdown power supply VEE1, preventing the shutdown power supply VEE1 from being overloaded or damaged due to current reverse flow. At the same time, it does not affect the normal shutdown bias current provided by the shutdown power supply VEE1 to the first shutdown switch Q3 in the steady state stage, ensuring the stable operation of the shutdown drive module in the transient superposition and steady state maintenance stages.

[0046] It is worth noting that the forward isolation diode D1 and the reverse isolation diode D2 can also be replaced with circuit isolation technologies such as MOSFET synchronous rectification isolation, optocoupler isolation, or magnetic isolation. MOSFET synchronous rectification isolation, optocoupler isolation, and magnetic isolation are all existing technologies, and their application principles will not be elaborated upon further here.

[0047] In one specific embodiment, the first on switch Q1, the second on switch Q2, the first off switch Q3, and the second off switch Q4 can all be silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs), gallium nitride high electron mobility transistors (GaN HEMTs), insulated gate bipolar transistors (IGBTs), high-speed solid-state relays (SSRs), N-channel metal-oxide-semiconductor field-effect transistors (N-channel MOSFETs), or P-channel metal-oxide-semiconductor field-effect transistors (P-channel MOSFETs).

[0048] Specifically, the drain of the first on-switch Q1 is connected to the positive terminal of the on-power supply VCC1, and the source, as a component of the on-voltage output terminal, can be turned on in the steady-state phase to continuously provide steady-state on-current to the device under test and maintain a stable gate voltage. The drain of the second on-switch Q2 is connected to the positive terminal of the on-conditioning power supply VCC2, and the source is shorted to the source of the first on-switch Q1. It can only be turned on during the turn-on transient, and the potential of the on-conditioning power supply VCC2 is superimposed with that of the on-conditioning power supply VCC1 to output a higher amplitude transient drive voltage, which greatly increases the gate peak current and achieves high-speed turn-on. The source of the first turn-off switch Q3 is connected to the negative terminal of the turn-off power supply VEE1, and the drain, as a component of the turn-off voltage output terminal, can be turned on in the steady state phase to continuously provide steady-state turn-off bias current to the device under test and maintain the gate turn-off state. The source of the second turn-off switch Q4 is connected to the negative terminal of the turn-off regulating power supply VEE2, and its drain is shorted to the drain of the first turn-off switch Q3. It can only be turned on during the turn-off transient, so that the potential of the turn-off regulating power supply VEE2 is superimposed with that of the turn-off power supply VEE1, and a higher amplitude transient discharge voltage is output to quickly release the gate charge and achieve high-speed turn-off.

[0049] In one specific embodiment, the impedance adjustment module includes a gate adjustment resistor Rg. The input terminal of the gate adjustment resistor Rg is connected to the on-state voltage output terminal or the off-state voltage output terminal, and the output terminal is connected to the device under test (DUT). Specifically, during dynamic gate stress testing, the superimposed potential output by the on-state drive module or the superimposed discharge voltage output by the off-state drive module will generate a large transient drive current. The gate adjustment resistor Rg is connected in series between the drive output terminal and the DUT, and its own impedance can limit the peak gate current, preventing excessive current from damaging the DUT. At the same time, the gate adjustment resistor Rg can match the parasitic parameters of the drive circuit, suppress parasitic oscillations of the gate voltage, ensure that the gate voltage change rate is stable and meets the gate stress test requirements, and can be adapted to DUTs with different power levels and different input capacitances by adjusting the resistance value, thus improving the versatility of the drive circuit.

[0050] In one specific embodiment, the gate adjustment resistor Rg can be a metal film resistor, a wire-wound resistor, or a thick-film chip resistor. Of course, it should be understood that the present invention is not limited thereto, and any gate adjustment resistor Rg that can achieve the same technical effect as the present invention is also within the scope of protection of the present invention.

[0051] The dynamic gate stress testing high-speed drive circuit proposed in this invention achieves a significant increase in gate peak current by overcoming parasitic parameter limitations and ensuring the actual application effect of high-rate-of-change voltage through a structure in which the conduction drive module uses a series superposition of conduction power supply VCC1 and conduction regulation power supply VCC2, and the shutdown drive module uses a series superposition of shutdown power supply VEE1 and shutdown regulation power supply VEE2. Furthermore, the output voltage of conduction regulation power supply VCC2 and shutdown regulation power supply VEE2 can be independently adjusted by voltage output commands generated by the control module, enabling continuous linear adjustment of conduction and shutdown rates without hardware replacement. The design of maintaining steady state by the first conduction switch Q1 and the first shutdown switch Q3 achieves stable output of applied voltage under pure power supply architecture, avoiding the decay characteristics of capacitor discharge. Finally, the physical separation design of the conduction drive module and the shutdown drive module enables completely independent adjustment of the turn-on and turn-off rates, meeting the differentiated needs of different testing scenarios.

[0052] refer to Figure 4 Accordingly, embodiments of the present invention also provide a test method for a high-speed drive circuit for dynamic gate stress testing based on any of the above embodiments, including: Step S1: Based on the response of the control module, a voltage output command is generated to output a high-level signal to the first on switch Q1 and the second on switch Q2; Step S2: Adjust the voltage value of the power supply VCC2 according to the preset adjustment parameters; Step S3: After a preset duration t, output a low-level signal to the second on switch Q2; Step S4: Based on the response of the control module, a voltage output command is generated to output a low-level signal to the first on switch Q1 and a high-level signal to the first off switch Q3 and the second off switch Q4. Step S5: Adjust the voltage value of the power supply VEE2 to be turned off according to the preset adjustment parameters; Step S6: After a preset duration t, output a low-level signal to the second off switch Q4, and determine whether the current cycle count has reached the preset number. If so, then terminate the test. If not, then output a high-level signal to the first switch Q1 and the second switch Q2 again until the test is terminated.

[0053] The proposed test method based on a high-speed drive circuit for dynamic gate stress testing utilizes a control module to generate a voltage output command and output a high-level signal to the first turn-on switch Q1 and the second turn-on switch Q2. This enables the simultaneous turn-on of the first turn-on switch Q1 and the second turn-on switch Q2, and outputs the superimposed potential of the turn-on power supply VCC1 and the turn-on adjustment power supply VCC2. This high-voltage, strong drive achieves extremely fast turn-on, effectively improving the gate voltage change rate and overcoming the problem of insufficient transient drive force in existing circuits, which makes it difficult to meet testing requirements.

[0054] The voltage value of the conduction regulating power supply VCC2 is adjusted according to the preset adjustment parameters to achieve independent linear control of the turn-on peak current and turn-on rate. This solves the drawbacks of nonlinearity in traditional variable resistance speed regulation and exponential characteristics of capacitor discharge speed regulation, so as to achieve a wide range of continuous speed regulation effect.

[0055] By outputting a low level to the second on switch Q2 after a preset duration t, the drive output returns to the on power supply VCC1, and the first on switch Q1 independently maintains the steady-state conduction of the device under test. The steady-state voltage of the on power supply VCC1 effectively absorbs residual oscillations and significantly reduces the risk of voltage overshoot.

[0056] Based on the response of the control module, a voltage output command is generated to output a low level to the first turn-on switch Q1 and a high level to the first turn-off switch Q3 and the second turn-off switch Q4. By inserting a dead time, a shoot-through short circuit between the upper and lower bridge arms is prevented. At the same time, the first turn-off switch Q3 and the second turn-off switch Q4 are simultaneously turned on to output the superimposed potential of the turn-off power supply VEE1 and the turn-off regulating power supply VEE2, thereby achieving ultra-fast turn-off. The voltage value of the turn-off regulating power supply VEE2 is adjusted according to the preset adjustment parameters to achieve independent linear control of the turn-off rate, meeting the differentiated requirements of different test scenarios for turn-on and turn-off rates.

[0057] By outputting a low level to the second turn-off switch Q4 after a preset duration t, the drive output returns to the turn-off power supply VEE1 to maintain a stable turn-off state, and the continuous dynamic gate stress test is achieved by judging the number of cycles.

[0058] In one embodiment, before step S1, which generates a voltage output command based on the control module response to output a high level to the first on switch Q1 and the second on switch Q2, the method further includes: The host computer presets the reference voltage values ​​of the power supply VCC1 and the power supply VEE1, as well as the dead time, preset number of times, and preset adjustment parameters.

[0059] Specifically, the reference voltage value, dead time, preset number of tests, and preset adjustment parameters can provide basic parameter support for subsequent dynamic gate stress testing.

[0060] By presetting the reference voltage values ​​of the turn-on power supply VCC1 and the turn-off power supply VEE1, a stable steady-state turn-on and turn-off bias voltage can be provided for the device under test. Combined with the subsequent transient superposition of the turn-on regulation power supply VCC2 and the turn-off regulation power supply VEE2, a voltage synthesis mechanism of "transient high potential superposition and steady-state single power supply maintenance" is realized, which effectively eliminates voltage overshoot and solves the problem of voltage overshoot that is easy to occur in the drive circuit of the existing solution.

[0061] It is worth noting that the preset dead time is ≤50ns, which ensures that there will be no short circuit between the switching devices, avoids damage to the switching devices due to short circuit, and improves test safety.

[0062] The preset number of test cycles enables automated cyclic control of the test process without manual intervention, ensuring that the test reaches the preset stress number and meets the reliability assessment requirements of dynamic gate stress testing. At the same time, in conjunction with the voltage output command generated by the control module, the first conduction switch Q1 and the second conduction switch Q2 are turned on simultaneously, outputting the superimposed potential of the conduction power supply VCC1 and the turn-off power supply VCC2, providing a large peak current to achieve high-speed conduction.

[0063] In addition, the preset adjustment parameters are obtained by the host computer based on the operating parameters of the device under test, such as the threshold voltage Vd, combined with the actual test drive circuit.

[0064] In one embodiment, the preset duration t is in the range of 10ns to 50ns. Specifically, the preset duration t1 in the range of 10ns to 50ns can be less than the total time it takes for the gate voltage of the device under test to rise to a steady state value.

[0065] By controlling the preset on-time t, the charging characteristics of the gate capacitance of the device under test (DUT) can be precisely matched. When the first and second on-switches Q1 and Q2 are simultaneously turned on during transient switching, a large current is provided for rapid charging using the superimposed potential of the on-power supply VCC1 and the on-regulation power supply VCC2. When the gate voltage approaches the steady-state value, the second on-switches Q2 are turned off in advance to avoid voltage overshoot due to continuous superimposed voltage. This ensures sufficient transient driving force, making the gate voltage change rate stable enough to meet the requirements of extreme accelerated stress testing, effectively activating the gate oxide and interface defects of the DUT under high-speed switching transients. At the same time, the steady-state voltage of the on-power supply VCC1 absorbs residual oscillations, achieving zero gate voltage overshoot. Simultaneously, it avoids power loss and device stress overload caused by excessive superimposed voltage time, balancing test accuracy and device safety.

[0066] In one embodiment, in step S1, based on the response of the control module and the generation of a voltage output command, a high-level signal is output to the first on switch Q1 and the second on switch Q2, specifically including: The controller receives the reference voltage value, dead time, preset number of times, and preset adjustment parameters output by the host computer, and outputs a high-level PWM signal. The first switch Q1 and the second switch Q2 receive a high-level PWM signal and are turned on.

[0067] Specifically, after the first conducting switch Q1 and the second conducting switch Q2 are turned on, they can output the superimposed potential of the conducting power supply VCC1 and the conducting regulating power supply VCC2, thereby driving the device under test to turn on extremely quickly with high voltage, so as to improve the gate-source voltage change rate of the device under test.

[0068] At this moment, the instantaneous voltage Vo at the output terminal of the conduction voltage is the vector superposition of the conduction power supply VCC1 and the conduction regulating power supply VCC2: Von = Vcc1 + Vcc2, The instantaneous voltage Vo is directly output to the device under test, generating an injected current Ig: Ig=[(Vcc1+Vcc2)-V gs(th) ] / (Rg+Rgint) In the formula: Vd represents the threshold voltage of the device under test; Rgint represents the internal resistance of the device under test.

[0069] And the rate of change of the gate voltage of the device under test, dV gs for: dV gs / dt=Ig / Ciss=[(Vcc1+Vcc2)-V gs(th) ] / (Rg+Rgint)Ciss In the formula: Ciss represents the input capacitance of the device under test; Therefore, by adjusting the conduction regulation power supply VCC2, the peak current and conduction rate can be linearly controlled. Compared with the method of adjusting the applied voltage by relying on the discharge of resistors or capacitors, it can achieve continuous regulation and stable output of applied voltage.

[0070] In one embodiment, in step S3, after a preset duration t, a low level is output to the second on switch Q2, specifically including: After a preset duration t, the controller outputs a low-level PWM signal to the second on switch Q2, and the second on switch Q2 receives the low-level PWM signal and turns off.

[0071] Specifically, after the second on switch Q2 receives a low-level PWM signal and turns off, the voltage value at the on-voltage output terminal changes instantaneously to the reference voltage of the on-power supply VCC1, and the first on switch Q1 independently maintains the steady-state on-state conduction of the device under test.

[0072] Since the power supply VCC1 is conducting in a steady state, its steady-state voltage can effectively absorb the residual oscillations of voltage changes, significantly reducing the risk of voltage overshoot.

[0073] In one embodiment, in step S4, based on the response of the control module and the generation of a voltage output command, a low-level signal is output to the first on switch Q1, and a high-level signal is output to the first off switch Q3 and the second off switch Q4, specifically including: The controller receives the reference voltage value, dead time, preset number of times and preset adjustment parameters output by the host computer, and outputs a low-level PWM signal to the first on switch Q1 to turn off the first on switch Q1; After the dead time interval, the controller outputs a high-level signal to turn on the first shutdown switch Q3 and the second shutdown switch Q4.

[0074] Specifically, in embodiments of the present invention, by outputting a low-level PWM signal to the first on switch Q1 to turn off the first on switch Q1, the output path of the on drive module can be cut off, avoiding the risk of power short circuit caused by the simultaneous on and off of the drive module, and ensuring circuit safety.

[0075] After the dead time interval, a high-level PWM signal is output to turn on the first turn-off switch Q3 and the second turn-off switch Q4, thereby triggering the voltage superposition mechanism of the turn-off transient. The superposition potential of the turn-off power supply VEE1 and the turn-off regulation power supply VEE2 is output, providing a large transient discharge current to the gate of the device under test and significantly improving the gate voltage change rate.

[0076] At this time, the transient voltage at the output terminal of the shutdown voltage is: V ff =V EE1 +V EE2 , Therefore, the charge stored in the gate capacitor of the device under test is rapidly released through the first turn-off switch Q3 and the second turn-off switch Q4, achieving high-speed turn-off. It can be seen that linear control of the turn-off rate can be achieved by independently adjusting the voltage value of the turn-off regulating power supply VEE2.

[0077] It is worth noting that, in the embodiments of the present invention, the adjustment of the on-state regulating power supply VCC2 and the off-state regulating power supply VEE2, in addition to being based on the level PWM signal, can also be achieved by adjusting the on-time of the second on switch Q2 and the second off switch Q4 to control the output of the on-state regulating power supply VCC2 and the off-state regulating power supply VEE2 to a fixed voltage. The longer the on-time, the larger the drive voltage of the output, thereby reducing the cost of the test hardware. Alternatively, an external high-speed voltage probe can be used to collect the gate voltage waveform of the device under test in real time, calculate the gate voltage change rate, and feed it back to the controller. The controller can then use a PID algorithm to compare the gate voltage change rate with a preset target value, thereby adjusting the regulating power supply VCC2 and the off-state regulating power supply VEE2 in real time, and realizing closed-loop control of the test method.

[0078] While one or more embodiments of the present invention have been described above, those skilled in the art will recognize that the present invention can be implemented in any other form without departing from its spirit and scope. Therefore, the embodiments described above are illustrative and not restrictive, and many modifications and substitutions will be apparent to those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A high-speed driving circuit for dynamic gate stress testing, characterized in that, include: The control module is used to generate voltage output commands; A conduction drive module includes a conduction unit and at least one conduction adjustment unit. The conduction unit includes a conduction power supply and a first conduction switch whose drain is connected to the positive terminal of the conduction power supply. Each conduction adjustment unit includes a conduction adjustment power supply and a second conduction switch. The negative terminal of the conduction adjustment power supply is connected to the positive terminal of the conduction power supply or an adjacent positive terminal of the conduction adjustment power supply. The drain of the second conduction switch is connected to the positive terminal of the conduction adjustment power supply, and its source is short-circuited to the source of the first conduction switch. The short-circuit point forms a conduction voltage output terminal to output a conduction voltage according to the voltage output command. A shutdown drive module includes a shutdown unit and at least one shutdown adjustment unit. The shutdown unit includes a shutdown power supply and a first shutdown switch whose source is connected to the negative terminal of the shutdown power supply. Each shutdown adjustment unit includes a shutdown adjustment power supply and a second shutdown switch. The positive terminal of the shutdown adjustment power supply is connected to the negative terminal of the shutdown power supply or the negative terminal of an adjacent shutdown adjustment power supply. The source of the second shutdown switch is connected to the negative terminal of the shutdown adjustment power supply, and its drain is short-circuited to the drain of the first shutdown switch. The short-circuit point forms a shutdown voltage output terminal to output a shutdown voltage according to the voltage output command. An impedance adjustment module, the input terminal of which is connected to the on-voltage output terminal or the off-voltage output terminal; The gate of the device under test is connected to the output terminal of the impedance adjustment module.

2. The high-speed drive circuit for dynamic gate stress testing according to claim 1, characterized in that, The conduction drive module further includes only a conduction unit, which includes a conduction power supply and a first conduction switch whose drain is connected to the positive terminal of the conduction power supply. The source of the first conduction switch forms a conduction voltage output terminal and is connected to a turn-off voltage output terminal.

3. The high-speed driving circuit for dynamic gate stress testing according to claim 1, characterized in that, The shutdown drive module further includes a shutdown unit, which includes a shutdown power supply and a first shutdown switch whose source is connected to the negative terminal of the shutdown power supply. The drain of the first shutdown switch forms a shutdown voltage output terminal and is connected to the on-state voltage output terminal.

4. The high-speed drive circuit for dynamic gate stress testing according to claim 1, characterized in that, The control module includes a controller with a high-speed digital I / O port, which is configured to output PWM signals to the gates of the first on switch, the second on switch, the first off switch, and the second off switch via the high-speed digital I / O port, and to communicate with a host computer.

5. The high-speed drive circuit for dynamic gate stress testing according to any one of claims 1-3, characterized in that, The conduction unit also includes a forward isolation diode, the anode of which is connected to the positive terminal of the conduction power supply, and the cathode of which is connected to the drain of the first conduction switch.

6. The high-speed drive circuit for dynamic gate stress testing according to any one of claims 1-3, characterized in that, The shutdown unit further includes a reverse isolation diode, the cathode of which is connected to the negative terminal of the shutdown power supply, and the anode of which is connected to the source terminal of the first shutdown switch.

7. The high-speed drive circuit for dynamic gate stress testing according to claim 1, characterized in that, The impedance adjustment module includes a gate adjustment resistor, the input terminal of which is connected to the on-voltage output terminal or the off-voltage output terminal, and the output terminal is connected to the device under test.

8. A test method for a high-speed drive circuit for dynamic gate stress testing based on the above claim 1, characterized in that, include: Based on the response of the control module, a voltage output command is generated to output a high-level signal to the first and second conducting switches; Adjust the voltage value of the power supply according to the preset adjustment parameters; After a preset duration, a low-level signal is output to the second on switch; Based on the response of the control module, the voltage output command is generated to output a low-level signal to the first on switch and a high-level signal to the first off switch and the second off switch. Adjust the voltage value of the power supply to be turned off according to the preset adjustment parameters; After the preset duration, a low-level signal is output to the second off switch, and it is determined whether the current cycle count has reached the preset number. If so, then terminate the test. If not, then output a high-level signal to the first and second conduction switches again until the test is terminated.

9. The test method for high-speed drive circuits based on dynamic gate stress testing according to claim 8, characterized in that, The step of outputting a low level to the second conducting switch after the preset duration specifically includes: After the preset duration, the controller outputs a low-level PWM signal to the second on switch, and the second on switch receives the low-level PWM signal and turns off.

10. The test method for high-speed drive circuit based on dynamic gate stress testing according to claim 9, characterized in that, The step of generating the voltage output command based on the response of the control module to output a low-level signal to the first on switch and a high-level signal to the first off switch and the second off switch specifically includes: The controller receives the reference voltage value, dead time, preset number of times and preset adjustment parameters output by the host computer, and outputs a low-level PWM signal to the first on switch to turn off the first on switch. After the dead time interval, the controller outputs a high-level signal to turn on the first shutdown switch and the second shutdown switch.

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