Wafer acceptance test method

Abstract

The application discloses a wafer acceptance test method, comprising: fixing a wafer on a wafer stage of a WAT test machine, the wafer being formed with a semiconductor device and a test pattern, the test pattern comprising input test pads and output test pads, a probe card of the WAT test machine comprising input probes and output probes; electrically connecting the probe card with the test pattern, so that the input probes are in contact with the input test pads and the output probes are in contact with the output test pads; inputting stepwise increasing scanning voltage to the test pattern through the input probes, measuring output current of the test pattern through the output probes, measuring N times of output current within a time period of any voltage step, N being a natural number, N>=3; when detecting that any output current exceeds a current threshold, stopping inputting scanning voltage to the test pattern and determining input voltage at this time as breakdown voltage of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a wafer acceptance test method. Background Technology

[0002] In wafer acceptance testing (WAT) for semiconductor manufacturing, the breakdown voltage is... BV Breakdown voltage is a standard test parameter. Typically, the method for testing breakdown voltage is to apply a scanning voltage to the device under test while simultaneously measuring the current flowing through the device. When the current reaches a preset breakdown current threshold, the voltage value at that moment is taken as the breakdown voltage of the device.

[0003] However, in actual testing, especially when testing certain types of devices (e.g., power devices), probe card tips often melt (burnt probes) and test pads on the wafer are often charred, sometimes even rendering the entire probe card and wafer unusable. Therefore, there is an urgent need for a wafer-acceptable testing method that can reduce damage to the wafer and probe card when testing the breakdown voltage of the device. Summary of the Invention

[0004] This application provides a wafer acceptance test method, which can solve the problem that wafer acceptance test methods provided in related technologies are prone to damage to wafers and probe cards when measuring breakdown voltage. The method includes: A wafer is fixed on the wafer stage of a WAT ​​test machine. Semiconductor devices and test patterns are formed on the wafer. The test patterns are used to measure the electrical performance of the semiconductor devices. The test patterns include input test pads and output test pads. The probe card of the WAT test machine includes input probes and output probes. Electrically connect the probe card to the test pattern, so that the input probe contacts the input test pad and the output probe contacts the output test pad; The input probe inputs a progressively increasing scanning voltage to the test pattern, and the output probe measures the output current of the test pattern. The output current is measured N times within the duration of any voltage step, where N is a natural number and N≥3. When any output current is detected to exceed the current threshold, the input of scanning voltage to the test pattern is stopped and the input voltage at this time is determined as the breakdown voltage of the semiconductor device.

[0005] In some embodiments, the duration of a voltage step includes a measurement time and other time periods, during which the output current is acquired and output with an integration time period.

[0006] In some embodiments, the integration time is less than the AC power cycle adapted to the WAT test equipment.

[0007] In some embodiments, the integration time is 0.02 to 10 times the AC power cycle.

[0008] In some embodiments, the semiconductor device is a power device, an LDMOS device, or a DMOS device.

[0009] In some embodiments, the method further includes: An alarm signal is generated when any output current exceeds the current threshold. The alarm signal is used to trigger the WAT test machine to generate a display alarm and / or an audio alarm.

[0010] The technical solution of this application has at least the following advantages: When measuring the breakdown voltage of a device under test (DUT) using a WAT ​​tester, a progressively increasing scan voltage is input to the test pattern. The output current is measured N times within the duration of any voltage step. When any output current exceeds the current threshold, the input of the scan voltage to the test pattern is stopped, and the input voltage at this point is determined as the breakdown voltage of the semiconductor device. Because the output current is sampled multiple times within the duration of a voltage step, the changes in output current can be monitored more intensively. Once the output current reaches the current threshold, the continuous input of voltage to the test pattern can be stopped quickly, thereby reducing the probability of damage to the probe card and wafer caused by sudden current changes and excessive instantaneous current. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0012] Figure 1 It is the voltage-time curve of the wafer acceptance test method provided in the related technology at the breakdown voltage of the test device; Figure 2 The current-time curve of the wafer acceptance test method provided in the related technology at the breakdown voltage of the test device during the second measurement time; Figure 3 This is a flowchart of a wafer acceptance test method provided in an exemplary embodiment of this application; Figure 4The current-voltage curve is obtained by measuring the wafer acceptance test method provided in the relevant technology; Figure 5 This is a current-voltage curve measured by a wafer acceptance test method provided in an exemplary embodiment of this application. Detailed Implementation

[0013] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0015] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0016] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0017] When testing the breakdown voltage of a device using the wafer acceptance test method provided in related technologies, as the current of the device under test gradually approaches the preset current threshold, the slope of its current-voltage (IV) curve increases sharply, and the current undergoes a sudden change, far exceeding the preset breakdown current threshold in a very short time. This instantaneous large current flows through the test pad and the probe tip, generating localized high temperatures, which causes the test pad to burn and the probe tip to melt.

[0018] refer to Figure 1It shows the voltage-time curve of the wafer acceptance test method provided in the related art at the breakdown voltage of the test device; Reference Figure 2 It shows the current-time curve of the wafer acceptance test method provided in the related art at the breakdown voltage of the test device during the second measurement time.

[0019] like Figure 1 As shown, during the breakdown voltage test, the input voltage increases in steps. The output current is measured only once within the duration of each voltage step. The time it takes for the test system to acquire data within each voltage step's duration is called the measurement time (TM). For example, Figure 1 The measurement time for voltage step 1 is called measurement time 1, and the measurement time for voltage step 2 is called measurement time 2. Figure 2 As shown, during measurement time 2, the output current continuously increases. When the output current is detected to exceed the current threshold, for example, Figure 1 If the current of the device under test exceeds the current threshold during the time period of voltage step 4, then the breakdown voltage of the device is determined to be voltage step 4.

[0020] The measurement time for each voltage step is determined by the product of the power line cycle (PLC) integration time (hereinafter referred to as "integration time") and the number of measurements (test count), and an average current value is output only at the end of that measurement time. This low-density current sampling method cannot effectively capture the instantaneous current surge. By the time the test system realizes that the current has exceeded the threshold, the large current has already caused irreversible damage, resulting in damage to the wafer and probe card.

[0021] refer to Figure 3 It illustrates a flowchart of a wafer acceptance test method provided in an exemplary embodiment of this application, such as... Figure 3 As shown, the method includes: Step S1: Fix the wafer on the wafer stage of the WAT test machine. Semiconductor devices and test patterns are formed on the wafer. The test patterns are used to measure the electrical performance of the semiconductor devices. The test patterns include input test pads and output test pads. The probe card of the WAT test machine includes input probes and output probes.

[0022] The semiconductor devices formed on this wafer can be double-diffused metal-oxide-semiconductor field-effect transistors (DMOS), lateral double-diffused metal-oxide-semiconductor field-effect transistors (LDMOS), or power devices. The test patterns formed on the wafer are used to measure the electrical performance of the semiconductor devices, such as their breakdown voltage and sheet resistance. R S Threshold voltage V T Leakage current, etc., are examples of semiconductor device breakdown voltage measured by test pattern measurement in this application embodiment. The test pattern includes the device under test, an input test pad, and an output test pad. The input test pad is electrically connected to the input electrode of the device under test, and the output test pad is electrically connected to the output electrode of the device under test.

[0023] Step S2: Electrically connect the probe card to the test pattern, so that the input probe contacts the input test pad and the output probe contacts the output test pad.

[0024] For example, the probe card is pre-installed on the probe card holder of the tester and is electrically connected to the tester via an interface. The optical alignment system identifies the alignment marks on the wafer to calibrate the wafer's position. After alignment is confirmed, the stage carries the wafer and moves along the Z-axis to bring the test pad into contact with the probe tips on the probe card (input probes contact input test pads, and output probes contact output test pads). After the tips contact the test pads, the stage continues to rise a short distance (usually tens of micrometers) to form a stable and reliable electrical contact between the tips and the test pads. By monitoring the contact resistance or the probe mark image, it can be confirmed that each probe is in good contact with the corresponding test pad. If a probe has poor contact, the tip needs to be readjusted or cleaned.

[0025] Step S3: Input a progressively increasing scanning voltage to the test pattern through the input probe, and measure the output current of the test pattern through the output probe. Measure the output current N times within the duration of any voltage step, where N is a natural number and N≥3.

[0026] like Figure 1As shown, the duration of a voltage step includes the measurement time (TM) and other times (for example, the duration of voltage step 1 first includes the trigger time, followed by the hold time (TH), and then the measurement time after the delay time (TD). The duration of voltage step 2 includes both the delay time and the measurement time). During the measurement time, the current measurement value is acquired and output with the integration time as the period (i.e., the measurement time is the product of the integration time and the number of measurements N). The integration time is less than the AC power cycle adapted to the WAT test equipment. For example, the integration time can be 0.02 to 10 times the AC power cycle. Taking the Chinese AC power cycle as an example, the integration time can be 0.02 seconds, and the corresponding number of measurements can be 50 (N=50). Setting the integration time to an integer multiple of 1, 2, or 10 of the AC power supply cycle can suppress AC power frequency noise to the greatest extent, resulting in high-precision and high-stability measurement results. Setting the integration time to a fractional multiple of 0.1 or 0.02 of the AC power supply cycle results in a measurement time of less than one complete cycle, during which noise cannot be effectively canceled. Although the measured data may contain more noise, the measurement speed is faster.

[0027] refer to Figure 4 It shows a schematic diagram of the output current output by the breakdown voltage measurement method provided in the related art; Reference Figure 5 This diagram illustrates the output current output according to an embodiment of this application. Figure 4 As shown, since the output current is measured only once during the duration of a voltage step, each voltage step corresponds to one output current; as... Figure 5 As shown, since the output current is measured N times during the time period of a voltage step, each voltage step corresponds to N output currents (multiple output currents are stacked as an approximate bar chart in the compressed graph).

[0028] In one exemplary embodiment, before testing, an operator or automated test program sets the test parameters according to the type of the device under test. Taking breakdown voltage measurement as an example, the following parameters can be set: Starting voltage: 0 volts (V) Termination voltage: 100V Step voltage: 0.5V Breakdown current threshold: 1 microamp (μA) PLC integration time: 1 power line cycle (approximately 0.2 seconds) Number of measurements N: 50 Step S4: Detect whether there is an output current exceeding the current threshold.

[0029] If any output current is detected to exceed the current threshold, proceed to step S5; if no output current exceeding the current threshold is detected, continue to step S3.

[0030] Step S5: Stop inputting scanning current to the test pattern and determine the corresponding output voltage as the breakdown voltage of the semiconductor device.

[0031] Optionally, when any output current is detected to exceed the current threshold, an alarm signal is generated. This alarm signal is used to trigger the WAT test instrument to generate a display alarm and / or an audio alarm, while stopping the input of scanning current to the test pattern and determining the corresponding output voltage at this time as the breakdown voltage of the semiconductor device.

[0032] In summary, in this embodiment, when measuring the breakdown voltage of the device under test using a WAT ​​tester, a progressively increasing scan voltage is input to the test pattern. The output current is measured N times within the duration of any voltage step. When any output current is detected to exceed the current threshold, the input of the scan voltage to the test pattern is stopped, and the input voltage at this time is determined as the breakdown voltage of the semiconductor device. Since the output current is sampled multiple times within the duration of a voltage step, the changes in output current can be monitored more intensively. After the output current reaches the current threshold, the continuous input of voltage to the test pattern can be stopped quickly, thereby reducing the probability of the probe card and wafer being damaged by a sudden change in current and an excessive instantaneous current.

[0033] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A wafer acceptance test method, characterized in that, include: A wafer is fixed on the wafer stage of a WAT ​​test machine. Semiconductor devices and test patterns are formed on the wafer. The test patterns are used to measure the electrical performance of the semiconductor devices. The test patterns include input test pads and output test pads. The probe card of the WAT test machine includes input probes and output probes. Electrically connect the probe card to the test pattern, so that the input probe contacts the input test pad and the output probe contacts the output test pad; The input probe inputs a progressively increasing scanning voltage to the test pattern, and the output probe measures the output current of the test pattern. The output current is measured N times within the duration of any voltage step, where N is a natural number and N≥3. When any output current is detected to exceed the current threshold, the input of scanning voltage to the test pattern is stopped and the input voltage at this time is determined as the breakdown voltage of the semiconductor device.

2. The method according to claim 1, characterized in that, The duration of a voltage step includes the measurement time and other time periods, during which the output current is acquired and output with an integration time period.

3. The method according to claim 2, characterized in that, The integration time is less than the AC power cycle adapted to the WAT test machine.

4. The method according to claim 3, characterized in that, The integration time is 0.02 to 10 times the AC power supply cycle.

5. The method according to any one of claims 1 to 4, characterized in that, The semiconductor device is a power device, an LDMOS device, or a DMOS device.

6. The method according to claim 5, characterized in that, The method further includes: An alarm signal is generated when any output current exceeds the current threshold. The alarm signal is used to trigger the WAT test machine to generate a display alarm and / or an audio alarm.

Images