An SOC automatic testing method and system based on FPGA and DAC

Abstract

The application relates to the field of FPGA technology, and particularly discloses an SOC automatic testing method based on FPGA and DAC, which comprises the following steps: S1: a host computer issues test target parameters to FPGA; S2: FPGA generates a digital waveform which is output through DAC, and the initial iteration number is set to zero; S3: the SOC response error is calculated, and the counter is operated by one or zero according to the error; S4: the pulse width is adjusted according to the error and iteration, and the reporting is stopped after N times of continuous standard reaching or threshold reaching. The application takes FPGA and DAC as the core to replace expensive ATE, adjusts adaptively through a closed loop, corrects waveform error in real time, ensures test precision, combines mean issuing and retransmission mechanism, and comprehensively solves the bottleneck of analog excitation and system reconstruction.

Description

Technical Field

[0001] This invention relates to the field of FPGA technology, and more specifically to an automatic testing method and system for SOC based on FPGA and DAC. Background Technology

[0002] System-on-a-Chip (SoC) typically integrates digital logic, analog circuits, and various mixed-signal modules. Automated testing of SoCs places stringent demands on the flexibility of stimulus signals and system cost. Currently, SoC testing primarily relies on traditional automated test equipment (ATE). While these ATEs offer high accuracy and reliability, they suffer from a significant technical limitation: they are extremely expensive, and the test programs are tightly coupled with the hardware. Different SoC models require customized test boards and interfaces, resulting in poor system reconfigurability and long development cycles. More importantly, ATEs have limited capabilities in generating complex analog stimulus signals, often requiring separate signal generators to meet testing needs, further increasing overall testing costs and system complexity. Therefore, there is an urgent need for an automated SoC testing method that combines low cost and high flexibility to address the technical bottlenecks of existing ATE solutions in terms of analog stimulus generation capabilities and system reconfigurability. Summary of the Invention

[0003] The purpose of this invention is to provide an automatic testing method and system for SOC based on FPGA and DAC, thereby solving the above-mentioned technical problems.

[0004] The objective of this invention can be achieved through the following technical solutions: An automated testing method for a System-on-a-Chip (SoC) based on FPGA and DAC includes the following steps: S1: Instruct the host computer to send the test target parameters to the FPGA. The test target parameters include the preset target pulse width T. target ; S2: Obtain waveform type A from the host computer, instruct the FPGA to generate a digital waveform consistent with waveform type A with preset initial values, and output the digital waveform to the DAC interface. Preset the initial iteration count k=0. S3: The DAC converts the received digital waveform into an analog current signal, applies this model current signal to the ADC input of the SOC under test, and acquires the digital response signal at the SOC output to obtain the current actual pulse width T. actual (k); Calculation error If W(k) > ε, set the counter to zero; if W(k) ≤ ε, store the result and increment the counter. S4: Preset convergence count N. When the consecutive count values ​​of the counter are not equal to N, adjust the FPGA output waveform parameters, including the following steps: If T actual (k) < T target Increase the pulse width of the FPGA output, and the increased pulse width Tx = T actual (k) + ΔT; If T actual (k) > T target Reduce the pulse width of the FPGA output, and the reduced pulse width Tx = T actual (k)-ΔT, repeat the above steps to increment the value of the iteration number k by one, where ΔT represents the preset adjustment step size; When the continuous count value equals N, the iteration stops, and the FPGA sends the error and adjustment amount of each iteration to the host computer.

[0005] As a further aspect of the present invention: In step S2, instructing the FPGA to generate a digital waveform consistent with waveform type A using preset initial values ​​includes the following steps: If waveform type A is a sine wave, obtain the initial frequency and initial amplitude of the sine wave, instruct the FPGA to read the sine lookup table cyclically with the address step value corresponding to the minimum frequency, and multiply by the amplitude to generate a digital sine sequence, and the DAC outputs an analog sine wave; If waveform type A is a triangular wave, the initial peak-to-peak amplitude of the triangular wave is obtained, and a digital value sequence that linearly increases to the peak value and then linearly decreases is generated by a counter. The DAC outputs an analog triangular wave.

[0006] As a further aspect of the present invention: in step S4, an iteration threshold K is preset. When k≥K, subsequent iteration steps are stopped, and the FPGA sends the error and adjustment amount of each iteration to the host computer.

[0007] As a further aspect of the present invention: In step S1, the host computer repeatedly sends the test target parameter M times to the FPGA. The FPGA receives the pulse width sent each time and calculates the average value of the pulse width sent each time, which is denoted as the target pulse width T. target Where M represents the preset number of tests.

[0008] As a further aspect of the present invention: in step S1, a pre-set waiting time is provided. When the host computer repeatedly sends test target parameters to the FPGA, it waits for the FPGA to return confirmation information after each sending. After receiving the confirmation information, it sends the parameters again. If no confirmation information is received after the preset waiting time, the test target parameters are resent.

[0009] As a further aspect of the present invention: calculating the target pulse width T target Previously, the maximum and minimum values ​​among the M pulse widths were removed before calculating the mean.

[0010] As a further aspect of the present invention: if pulse widths of equal value exist, only the pulse width of the first received pulse is retained.

[0011] An automated test system for a System-on-a-Chip (SoC) based on FPGA and DAC includes: The sending module: instructs the host computer to send test target parameters to the FPGA, wherein the test target parameters include a preset target pulse width T. target ; Output module: Obtain waveform type A from the host computer, instruct the FPGA to generate a digital waveform consistent with waveform type A with preset initial values, and output the digital waveform to the DAC interface. The initial iteration count is preset to k=0. Conversion Module: The DAC converts the received digital waveform into an analog current signal, applies this analog current signal to the ADC input of the SOC under test, and acquires the digital response signal at the SOC output to obtain the current actual pulse width T. actual (k); Calculation error If W(k) > ε, set the counter to zero; if W(k) ≤ ε, store the result and increment the counter. Iteration module: A pre-set convergence count N is used. When the consecutive count values ​​of the counter are not equal to N, the FPGA output waveform parameters are adjusted, including the following steps: If T actual (k) < T target Increase the pulse width of the FPGA output, and the increased pulse width Tx = T actual (k) + ΔT; If T actual (k) > T target Reduce the pulse width of the FPGA output, and the reduced pulse width Tx = T actual (k)-ΔT, repeat the above steps to increment the value of the iteration number k by one, where ΔT represents the preset adjustment step size; When the continuous count value equals N, the iteration stops, and the FPGA sends the error and adjustment amount of each iteration to the host computer.

[0012] The beneficial effects of this invention are as follows: This invention proposes an automatic SOC testing method based on FPGA and DAC. First, this method uses FPGA and DAC as the core to construct an analog excitation generation channel, replacing the expensive dedicated signal generator and customized test board in ATE (Automatic Test Equipment). The hardware structure is simple and universal, reducing the hardware cost and maintenance overhead of the test system. Second, the host computer can flexibly send waveform types and target pulse widths. The FPGA dynamically generates the corresponding digital waveforms through lookup tables or counters, adapting to the testing requirements of different SOC models without hardware replacement. This breaks through the bottleneck of traditional ATE test programs being tightly coupled with hardware and having long development cycles, resulting in highly reconfigurable systems. More importantly, a closed-loop adaptive iterative adjustment mechanism is introduced. By acquiring the digital response signal output by the SOC in real time, the error between the actual pulse width and the target value is calculated, and the FPGA output step size is automatically adjusted until the error converges to the allowable threshold multiple times. This effectively overcomes waveform distortion caused by non-ideal device characteristics or environmental changes in open-loop testing, significantly improving test accuracy and consistency. Furthermore, the method uses multiple sends and averages to determine the target width, combined with a timeout retransmission mechanism, enhancing communication robustness. In summary, this invention, with its low-cost and highly flexible adaptive architecture, solves the technical bottlenecks of traditional ATE in terms of simulation stimulus generation capability and system reconfigurability, and has broad engineering application value. Attached Figure Description

[0013] The invention will now be further described with reference to the accompanying drawings.

[0014] Figure 1 This is a schematic diagram of the structure of an automatic SOC testing method based on FPGA and DAC according to the present invention; Figure 2 This is a flowchart illustrating an automatic testing method for a System-on-a-Chip (SOC) based on FPGA and DAC according to the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] Please see Figure 1 As shown, this invention is an automated testing method for a System-on-a-Chip (SoC) based on FPGA and DAC, comprising: S1: Instruct the host computer to send the test target parameters to the FPGA. The test target parameters include the preset target pulse width T. target ; S2: Obtain waveform type A from the host computer, instruct the FPGA to generate a digital waveform consistent with waveform type A with preset initial values, and output the digital waveform to the DAC interface. Preset the initial iteration count k=0. S3: The DAC converts the received digital waveform into an analog current signal, applies this model current signal to the ADC input of the SOC under test, and acquires the digital response signal at the SOC output to obtain the current actual pulse width T. actual (k); Calculation error If W(k) > ε, set the counter to zero; if W(k) ≤ ε, store the result and increment the counter. S4: Preset convergence count N. When the consecutive count values ​​of the counter are not equal to N, adjust the FPGA output waveform parameters, including the following steps: If T actual (k) < T target Increase the pulse width of the FPGA output, and the increased pulse width Tx = T actual (k) + ΔT; If T actual (k) > T target Reduce the pulse width of the FPGA output, and the reduced pulse width Tx = T actual (k)-ΔT, repeat the above steps to increment the value of the iteration number k by one, where ΔT represents the preset adjustment step size; When the continuous count value equals N, the iteration stops, and the FPGA sends the error and adjustment amount of each iteration to the host computer.

[0017] It should be noted that, firstly, the host computer sends the test target parameters to the FPGA through the communication interface, which includes at least the preset target pulse width T. target To ensure parameter accuracy, the host computer can repeatedly send the target test parameters M times. After each sending, it waits for confirmation from the FPGA. If no confirmation is received within a preset waiting time, the parameters are resent. After receiving the pulse width each time, the FPGA removes the maximum and minimum values ​​from the M pulse widths, calculates the average of the remaining values, and uses this average as the final target pulse width T. target If pulses of equal width occur during reception, only the first one received is retained. This effectively avoids the impact of transient communication interference or abnormal data on the test benchmark.

[0018] Subsequently, the host computer sends the waveform type A to be generated to the FPGA. The waveform type can be a sine wave or a triangle wave. If it is a sine wave, the FPGA obtains the initial frequency and initial amplitude, and cyclically reads the internally stored sine lookup table with the address step value corresponding to the minimum frequency. The read result is then multiplied by the amplitude coefficient to generate a digital sine sequence. If it is a triangle wave, a digital value sequence that first linearly increases to the peak value and then linearly decreases is generated by a counter to obtain a digital triangle waveform. The FPGA generates a digital waveform consistent with waveform type A with the preset initial value and outputs the digital waveform to the DAC interface. At the same time, the initial iteration count k is preset to 0, and the counter used to record the number of consecutive successful iterations is cleared.

[0019] The DAC receives a digital waveform and converts it into an analog current signal. This analog current signal is applied to the input of the ADC of the SOC under test. The ADC inside the SOC samples and converts this analog signal, generating a corresponding digital response signal at its digital output. The test system acquires this digital response signal and parses the current actual pulse width T from it. actual (k). Next, calculate the error. The value of W(k) is compared with the preset allowable error threshold. If W(k) > ε, it means that the pulse width deviates significantly from the target, and the continuous pass counter is set to zero. If W(k) ≤ ε, it means that the result meets the accuracy requirements, the test data is stored, and the value of the continuous pass counter is incremented by one.

[0020] The system presets a convergence count N, indicating how many consecutive successful convergences are required before the parameters are considered stable. As long as the continuous counter value is not equal to N, the FPGA's output waveform parameters continue to be adjusted. The adjustment rules are as follows: if the current actual pulse width T... actual (k) is less than the target value T target Then increase the pulse width of the FPGA output; the increased pulse width Tx = T actual (k) + ΔT; if T_actual(k) is greater than T target Then reduce the output pulse width, and the reduced Tx = T actual(k) - ΔT. After adjustment, the iteration count k is incremented by one, and the entire process from DAC output to error calculation and adjustment is repeated. To prevent infinite iteration due to abnormal conditions, the system also presets an iteration threshold K. When the iteration count k reaches or exceeds K, the iteration will be forcibly stopped even if the number of consecutive qualified tests has not reached N. After the iteration stops, the FPGA packages the error value and adjustment amount recorded during each iteration and uploads them to the host computer for analysis and archiving by the test personnel. When the value of the consecutive qualified test counter reaches N for the first time, it indicates that the pulse width output by the system has been stable within the allowable error range for N consecutive times. At this time, the iteration is stopped immediately, and the historical error and adjustment amount are reported. The entire test process realizes a fully automatic process from feedback acquisition to closed-loop adaptation, without manual intervention.

[0021] In another preferred embodiment of the present invention, instructing the FPGA to generate a digital waveform consistent with waveform type A with preset initial values ​​includes the following steps: If waveform type A is a sine wave, obtain the initial frequency and initial amplitude of the sine wave, instruct the FPGA to read the sine lookup table cyclically with the address step value corresponding to the minimum frequency, and multiply by the amplitude to generate a digital sine sequence, and the DAC outputs an analog sine wave; If waveform type A is a triangular wave, the initial peak-to-peak amplitude of the triangular wave is obtained, and a digital value sequence that linearly increases to the peak value and then linearly decreases is generated by a counter. The DAC outputs an analog triangular wave.

[0022] It is worth noting that the detailed implementation methods for generating different waveform types using FPGAs have clear technical significance. For sine waves, a method of cyclically reading the lookup table and multiplying by the amplitude using address steps can generate high-quality sine signals with controllable frequency and amplitude with minimal hardware resources. For triangular waves, a digital sequence is generated by linearly incrementing and decrementing a counter, resulting in a simple and fast response. This waveform generation method fully leverages the parallel processing and reconfigurability advantages of FPGAs, allowing flexible switching between sine and triangular waves without replacing any hardware. This overcomes the shortcomings of traditional ATE systems that require independent signal generators, improving the flexibility and adaptability of the test system and reducing development and maintenance costs.

[0023] In another preferred embodiment of the present invention, an iteration threshold K is preset. When k≥K, subsequent iteration steps are stopped, and the FPGA sends the error and adjustment amount of each iteration to the host computer.

[0024] Understandably, an iteration threshold K is set. When the number of iterations reaches K, the closed-loop adjustment is forcibly terminated to prevent infinite iteration due to system failure or improper parameter settings, thus ensuring the controllability of the testing process.

[0025] In another preferred embodiment of the present invention, the host computer repeatedly sends the test target parameter M times to the FPGA. The FPGA receives the pulse width sent each time and calculates the average value of the pulse width sent each time, which is denoted as the target pulse width T. target Where M represents the preset number of tests.

[0026] It should be noted that by sending multiple pulses and calculating the average value to determine the target pulse width, the instantaneous noise or transmission errors that may occur during a single communication are suppressed, the accuracy of the target parameters is improved, and the anti-interference capability of the entire test system is enhanced.

[0027] In another preferred embodiment of the present invention, a pre-set waiting time is provided. When the host computer repeatedly sends test target parameters to the FPGA, it waits for the FPGA to return confirmation information after each sending. After receiving the confirmation information, it sends the parameters again. If no confirmation information is received after the preset waiting time, the test target parameters are resent.

[0028] It should be noted that the introduction of acknowledgment and timeout retransmission mechanisms effectively ensures the reliability of communication between the host computer and the FPGA, avoiding errors in target parameters due to data loss or transmission anomalies. At the same time, the explicit handshake process enhances the robustness of the test system, ensuring that each transmission is correctly received, providing stable and accurate initial conditions for subsequent closed-loop iterations.

[0029] In another preferred embodiment of the present invention, the target pulse width T is calculated. target Previously, the maximum and minimum values ​​among the M pulse widths were removed before calculating the mean.

[0030] Understandably, by removing the maximum and minimum values ​​from the M pulse widths before calculating the mean, the contamination of the target reference by abnormal data caused by occasional interference or transmission errors is effectively eliminated, improving the statistical reliability of the target pulse width, thus enabling subsequent closed-loop iterations to be based on real parameters.

[0031] In another preferred embodiment of the present invention, if there are pulse widths with equal values, only the pulse width of the first received pulse is retained.

[0032] It is worth noting that the pulse width of the first receiver is retained when the pulse widths are equal, which avoids the interference of repeated data on the weight of the mean calculation and prevents the same value from being oversampled due to communication retransmission or redundant transmission, thus ensuring the authenticity of the target pulse width statistics.

[0033] An automated test system for a System-on-a-Chip (SoC) based on FPGA and DAC includes: The sending module: instructs the host computer to send test target parameters to the FPGA, wherein the test target parameters include a preset target pulse width T.target ; Output module: Obtain waveform type A from the host computer, instruct the FPGA to generate a digital waveform consistent with waveform type A with preset initial values, and output the digital waveform to the DAC interface. The initial iteration count is preset to k=0. Conversion Module: The DAC converts the received digital waveform into an analog current signal, applies this analog current signal to the ADC input of the SOC under test, and acquires the digital response signal at the SOC output to obtain the current actual pulse width T. actual (k); Calculation error If W(k) > ε, set the counter to zero; if W(k) ≤ ε, store the result and increment the counter. Iteration module: A pre-set convergence count N is used. When the consecutive count values ​​of the counter are not equal to N, the FPGA output waveform parameters are adjusted, including the following steps: If T actual (k) < T target Increase the pulse width of the FPGA output, and the increased pulse width Tx = T actual (k) + ΔT; If T actual (k) > T target Reduce the pulse width of the FPGA output, and the reduced pulse width Tx = T actual (k)-ΔT, repeat the above steps to increment the value of the iteration number k by one, where ΔT represents the preset adjustment step size; When the continuous count value equals N, the iteration stops, and the FPGA sends the error and adjustment amount of each iteration to the host computer.

[0034] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. An automated testing method for a System-on-a-Chip (SoC) based on FPGA and DAC, characterized in that, Includes the following steps: S1: Instruct the host computer to send the test target parameters to the FPGA. The test target parameters include the preset target pulse width T. target ; S2: Obtain waveform type A from the host computer, instruct the FPGA to generate a digital waveform consistent with waveform type A with preset initial values, and output the digital waveform to the DAC interface. Preset the initial iteration count k=0. S3: The DAC converts the received digital waveform into an analog current signal, applies this model current signal to the ADC input of the SOC under test, and acquires the digital response signal at the SOC output to obtain the current actual pulse width T. actual (k); Calculation error If W(k) > ε, set the counter to zero; if W(k) ≤ ε, store the result and increment the counter. S4: Preset convergence count N. When the consecutive count values ​​of the counter are not equal to N, adjust the FPGA output waveform parameters, including the following steps: If T actual (k) < T target Increase the pulse width of the FPGA output, and the increased pulse width Tx = T actual (k) + ΔT; If T actual (k) > T target Reduce the pulse width of the FPGA output, and the reduced pulse width Tx = T actual (k)-ΔT, repeat the above steps to increment the value of the iteration number k by one, where ΔT represents the preset adjustment step size; When the continuous count value equals N, the iteration stops, and the FPGA sends the error and adjustment amount of each iteration to the host computer.

2. The FPGA-based and DAC-based SOC automatic testing method according to claim 1, characterized in that, In step S2, instructing the FPGA to generate a digital waveform consistent with waveform type A using preset initial values ​​includes the following steps: If waveform type A is a sine wave, obtain the initial frequency and initial amplitude of the sine wave, instruct the FPGA to read the sine lookup table cyclically with the address step value corresponding to the minimum frequency, and multiply by the amplitude to generate a digital sine sequence, and the DAC outputs an analog sine wave; If waveform type A is a triangular wave, the initial peak-to-peak amplitude of the triangular wave is obtained, and a digital value sequence that linearly increases to the peak value and then linearly decreases is generated by a counter. The DAC outputs an analog triangular wave.

3. The SOC automatic testing method based on FPGA and DAC according to claim 1, characterized in that, In step S4, an iteration threshold K is preset. When k≥K, subsequent iteration steps are stopped, and the FPGA sends the error and adjustment amount of each iteration to the host computer.

4. The SOC automatic testing method based on FPGA and DAC according to claim 1, characterized in that, In step S1, the host computer repeatedly sends the test target parameter M times to the FPGA. The FPGA receives the pulse width sent each time and calculates the average pulse width of each time, which is denoted as the target pulse width T. target Where M represents the preset number of tests.

5. The FPGA-based and DAC-based SOC automatic testing method according to claim 1, characterized in that, In step S1, a preset waiting time is set. When the host computer repeatedly sends test target parameters to the FPGA, it waits for the FPGA to return confirmation information after each sending. After receiving the confirmation information, it sends the parameters again. If no confirmation information is received after the preset waiting time, the test target parameters are resent.

6. The FPGA-based and DAC-based SOC automatic testing method according to claim 4, characterized in that, Calculate the target pulse width T target Previously, the maximum and minimum values ​​among the M pulse widths were removed before calculating the mean.

7. The FPGA-based and DAC-based SOC automatic testing method according to claim 6, characterized in that, If pulse widths of equal value exist, only the pulse width of the first received pulse is retained.

8. An automated testing system for a System-on-a-Chip (SoC) based on FPGA and DAC, characterized in that, include: The sending module: instructs the host computer to send test target parameters to the FPGA, wherein the test target parameters include a preset target pulse width T. target ; Output module: Obtain waveform type A from the host computer, instruct the FPGA to generate a digital waveform consistent with waveform type A with preset initial values, and output the digital waveform to the DAC interface. The initial iteration count is preset to k=0. Conversion Module: The DAC converts the received digital waveform into an analog current signal, applies this analog current signal to the ADC input of the SOC under test, and acquires the digital response signal at the SOC output to obtain the current actual pulse width T. actual (k); Calculation error If W(k) > ε, set the counter to zero; if W(k) ≤ ε, store the result and increment the counter. Iteration module: A pre-set convergence count N is used. When the consecutive count values ​​of the counter are not equal to N, the FPGA output waveform parameters are adjusted, including the following steps: If T actual (k) < T target Increase the pulse width of the FPGA output, and the increased pulse width Tx = T actual (k) + ΔT; If T actual (k) > T target Reduce the pulse width of the FPGA output, and the reduced pulse width Tx = T actual (k)-ΔT, repeat the above steps to increment the value of the iteration number k by one, where ΔT represents the preset adjustment step size; When the continuous count value equals N, the iteration stops, and the FPGA sends the error and adjustment amount of each iteration to the host computer.

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