A dynamic priority-based chip test multi-station scheduling method and system

Abstract

The application relates to the technical field of chip testing, and particularly discloses a chip testing multi-station scheduling method and system based on dynamic priority, which comprises the following steps: calculating an urgency coefficient based on the test emergency level and the test failure retry number of a chip to be tested; obtaining an expected waiting time by combining a test time estimate value and a station idle time estimate value; obtaining an expected test success probability by associating the test failure retry number with a historical test success rate of the station; dynamically weighting and fusing the three factors to obtain a dynamic priority index according to the real-time load state of the station; performing resource evaluation according to the priority order to obtain a resource matching degree; selecting a target chip and allocating a reserved time window according to the matching degree and the priority index; and packaging and generating a scheduling instruction; and the application can improve the overall resource utilization efficiency of chip testing multi-station scheduling.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a chip testing multi-station scheduling method and system based on dynamic priority. Background Technology

[0002] In chip testing and production processes, multi-station parallel testing is a common configuration for increasing throughput. Existing test scheduling systems typically allocate test stations and time windows to chips under test based on a first-come, first-served principle or preset fixed priority rules. Simultaneously, the scheduling decision process considers parameters such as the urgency level of each chip's test, the number of retry attempts for test failures, and the historical test success rate of each station. These parameters provide a basis for the sequencing of test tasks and station selection. Furthermore, time window reservation mechanisms and allocation strategies based on station load status are also applied in actual test management to coordinate the resource usage relationships among multiple test tasks.

[0003] As chip functionality becomes increasingly complex and testing precision demands rise, the factors influencing test scheduling are becoming more diverse. These include the urgency of the chip itself, idle waiting time at testing stations, expected test success probability, and real-time workload of the testing stations, all of which can directly impact the smoothness of the overall testing process. How to rationally integrate this multi-dimensional information to achieve a more dynamic fit between test resources and chip tasks, thereby improving the overall resource utilization efficiency of multi-station scheduling, has become a focus of attention for those skilled in the art. Therefore, improving the overall resource utilization efficiency of multi-station scheduling in chip testing has become an urgent problem to be solved. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide a chip testing multi-station scheduling method and system based on dynamic priority, so as to solve the problem of dynamically integrating and adapting multi-dimensional information such as chip urgency, station idle waiting time, expected test success probability and station real-time load.

[0005] This invention provides a multi-station scheduling method for chip testing based on dynamic priority, comprising:

[0006] S1. Calculate the urgency coefficient of each chip under test based on the test urgency level and the number of test failure retries for each chip under test;

[0007] S2. The estimated test time of each chip under test and the estimated idle time of the current idle test station are comprehensively evaluated to obtain the expected waiting time of each chip under test at the current idle test station.

[0008] S3. The number of test failure retries for each chip under test is correlated and coupled with the historical test success rate of the current idle test station to obtain the expected test success probability of each chip under test in the current idle test station.

[0009] S4. Based on the real-time load status of the current idle test station, dynamically weight and fuse the urgency coefficient, the expected waiting time, and the expected test success probability to obtain the dynamic priority index of each chip under test.

[0010] S5. Based on the dynamic priority index arranged from high to low, perform resource evaluation on each chip under test to obtain the resource matching degree of the chip under test in the current idle test station.

[0011] S6. Perform a comprehensive matching between the resource matching degree and the dynamic priority index, select the chip with the highest comprehensive matching score as the target chip, and allocate a reserved time window for the target chip in the current idle test station to obtain the reserved time window information of the target chip.

[0012] S7. Encapsulate the reserved time window information of the target chip into a scheduling instruction to obtain the test multi-station scheduling instruction of the target chip.

[0013] Preferably, the process of calculating the urgency coefficient of each chip under test based on its test urgency level and the number of test failure retries is as follows:

[0014] The test urgency level of each chip under test is converted into the base value of the urgency level of each chip under test according to a preset level-value mapping table;

[0015] The number of test failure retries for each chip under test is truncated by a threshold to obtain the effective number of retries for each chip under test;

[0016] The urgent level base value and the effective number of retries are nonlinearly saturated and fused to obtain the urgent fusion value for each chip under test. The calculation formula is as follows: ;

[0017] in, This is the urgent fusion value for each chip under test. This is the base value for the emergency level of each chip under test. It is a logarithmic function with base 2. This represents the effective number of retries for each chip under test.

[0018] The urgency fusion value is range-scaled until it reaches a preset standard dynamic range, thus obtaining the urgency coefficient of each chip under test.

[0019] Preferably, the process of comprehensively evaluating the estimated test time for each chip under test and the estimated idle time of the current idle test station to obtain the expected waiting time of each chip under test at the current idle test station is as follows: Retrieve the estimated test time for each chip under test and the estimated idle time for each chip under test in the current idle test station;

[0020] The estimated idle time is compared with the current idle time of each chip under test to obtain the starting point of the waiting window for each chip under test in the current idle test station.

[0021] The waiting window start point and the idle time estimate are time-series superimposed to obtain the end time of the occupation of each chip under test in the current idle test station.

[0022] The time interval between the end time of the waiting period and the start time of the waiting window is extracted, and the time span experienced by each chip under test in the current idle test station from the start of waiting to the end of the waiting period is extracted to obtain the expected waiting time of each chip under test in the current idle test station.

[0023] Preferably, the number of test failure retries for each chip under test is correlated with the historical test success rate of the current idle test station to obtain the expected test success probability of each chip under test at the current idle test station. The process is as follows:

[0024] The number of test failure retries is compared with a preset retry threshold to obtain the retry level for each chip under test.

[0025] The historical test success rate is compared with a preset success rate threshold to determine the level range, thereby obtaining the success level of each chip under test in the current idle test station.

[0026] By matching the retry level with the success level, the coupling coefficient between each chip under test and the current idle test station is obtained;

[0027] Based on the coupling coefficient, the historical test success rate is adjusted to obtain the expected test success probability of each chip under test in the current idle test station.

[0028] Preferably, the dynamic priority index of each chip under test is obtained by dynamically weighting and fusing the urgency coefficient, the expected waiting time, and the expected test success probability based on the real-time load status of the currently idle test station, as follows:

[0029] Obtain the real-time load status parameters of the currently idle test station, including the number of assigned test tasks, the average test time already assigned, and the length of the assigned chip queue to be processed.

[0030] The number of assigned test tasks, the average test time, and the length of the assigned chip queue are normalized to obtain normalized parameters for the number of assigned test tasks, the average test time, and the length of the assigned chip queue.

[0031] Based on the normalization parameters, the number of allocated test tasks, the average test time allocated, and the length of the allocated chip queue are weighted and fused to obtain the dynamic priority index of each chip under test.

[0032] Preferably, the dynamic priority index of each chip under test is obtained by weighting and fusing the number of allocated test tasks, the average allocated test time, and the length of the allocated chip queue based on the normalization parameters, as follows:

[0033] The historical average number of test tasks at the current idle test station is used as the first dynamic benchmark, the historical average test time is used as the second dynamic benchmark, and the historical average length of the chip queue to be processed is used as the third dynamic benchmark.

[0034] Set the urgency coefficient of each chip under test as the initial dynamic priority index;

[0035] The number of assigned test tasks is compared with the first dynamic benchmark. If the number of assigned test tasks is higher than the first dynamic benchmark, the initial dynamic priority index is increased by one level to obtain the first adjusted priority index of the initial dynamic priority index.

[0036] The allocated average test time is compared with the second dynamic benchmark. If the allocated average test time is lower than the second dynamic benchmark, the first adjusted priority index is increased by one level to obtain the second adjusted priority index of the initial dynamic priority index.

[0037] The length of the allocated chip queue to be processed is compared with the third dynamic benchmark. If the length of the allocated chip queue to be processed is higher than the third dynamic benchmark, the second adjusted priority index is increased by one level to obtain the third adjusted priority index of the initial dynamic priority index.

[0038] The third adjusted priority index is used as the dynamic priority index for each chip under test.

[0039] Preferably, the process of evaluating the resources of each chip under test based on the dynamic priority index in descending order to obtain the resource matching degree of the chip under test in the current idle test station is as follows:

[0040] Based on the dynamic priority index arranged from high to low, the priority of each chip under test is evaluated to obtain the test resource requirement parameter set of each chip under test;

[0041] Obtain the set of station resource supply parameters for the chip under test in the currently idle test station;

[0042] Each item in the set of test resource requirements parameters is screened against the corresponding item in the set of workstation resource supply parameters until it falls completely within the range of the workstation resource supply parameters or is below the upper limit of the workstation resource supply parameters, thus obtaining the number of items that pass in each chip under test.

[0043] By comparing the number of projects with the total number of each chip under test, the resource matching degree of the chip under test in the current idle test station is obtained.

[0044] Preferably, the process of comprehensively matching the resource matching degree with the dynamic priority index, selecting the chip with the highest comprehensive matching score as the target chip, and allocating a reserved time window for the target chip in the current idle test station to obtain the reserved time window information of the target chip is as follows:

[0045] By associating the dynamic priority index with the resource matching degree, the comprehensive matching attributes of each chip under test are obtained.

[0046] Based on the comprehensive matching attributes, each chip under test is selected by optimization to obtain the chip under test with the best comprehensive matching attributes.

[0047] The chip under test is used as the target chip;

[0048] Read the idle start time and idle duration of the target chip at the current idle test station;

[0049] The idle start time and the idle duration are time-series integrated to obtain the reserved time window information of the target chip.

[0050] Preferably, the process of encapsulating the reserved time window information of the target chip into a scheduling instruction to obtain the test multi-station scheduling instruction for the target chip is as follows:

[0051] Obtain the chip identification information of the target chip;

[0052] The chip identification information, the reserved start time and the reserved duration in the reserved time window information of the target chip are arranged according to a preset instruction template to obtain the instruction content body of the target chip;

[0053] The instruction content of the target chip is encapsulated using a protocol to obtain the test multi-station scheduling instruction for the target chip.

[0054] This invention also provides a multi-parameter acquisition and analysis system for data center environments based on edge computing, the system comprising:

[0055] The urgency calculation module is used to calculate the urgency coefficient of each chip under test based on the test urgency level and the number of test failure retries for each chip under test;

[0056] The expected waiting module is used to comprehensively analyze the estimated test time of each chip under test and the estimated idle time of the current idle test station to obtain the expected waiting time of each chip under test at the current idle test station.

[0057] The success rate coupling module is used to associate and couple the number of test failure retries for each chip under test with the historical test success rate of the current idle test station to obtain the expected test success probability of each chip under test in the current idle test station.

[0058] The dynamic priority module is used to dynamically weight and fuse the urgency coefficient, the expected waiting time, and the expected test success probability based on the real-time load status of the current idle test station to obtain the dynamic priority index of each chip under test.

[0059] The resource matching module is used to evaluate the resources of each chip under test based on the dynamic priority index from high to low, and obtain the resource matching degree of the chip under test in the current idle test station.

[0060] The comprehensive matching module is used to comprehensively match the resource matching degree with the dynamic priority index, select the chip with the highest comprehensive matching score as the target chip, and allocate a reserved time window for the target chip in the current idle test station to obtain the reserved time window information of the target chip.

[0061] The scheduling instruction encapsulation module is used to encapsulate the reserved time window information of the target chip into scheduling instructions to obtain the test multi-station scheduling instructions of the target chip.

[0062] As can be seen from the above technical solution, the present invention provides a chip testing multi-station scheduling method and system based on dynamic priority. By calculating the urgency coefficient, expected waiting time, and expected test success probability of the chip under test, and combining them with the real-time load status of the workstation, a dynamic priority index is obtained through dynamic weighted fusion. Then, resource evaluation is performed based on priority ranking to obtain resource matching degree. Finally, the target chip is selected by combining the matching degree and priority index, and a reserved time window is allocated before packaging and generating scheduling instructions. This realizes the dynamic integration and adaptation of multi-dimensional information such as chip urgency, workstation idle waiting time, expected test success rate, and workstation real-time load, effectively improving the overall resource utilization efficiency of chip testing multi-station scheduling. Attached Figure Description

[0063] Other objects and results of the invention will become more apparent and readily understood by referring to the following description taken in conjunction with the accompanying drawings, and with a more complete understanding of the invention. In the drawings:

[0064] Figure 1 This is a flowchart illustrating a multi-station scheduling method for chip testing based on dynamic priority, according to an embodiment of the present invention.

[0065] Figure 2 This is a functional block diagram of a chip testing multi-station scheduling system based on dynamic priority, according to an embodiment of the present invention. Detailed Implementation

[0066] In existing multi-station scheduling schemes for chip testing, scheduling decisions are usually made based on the first-come, first-served principle or preset fixed priority rules. Factors such as test urgency level, number of retries, historical success rate of the workstation, and real-time load status are often referenced independently during the scheduling process, and a dynamic integration mechanism has not yet been formed among them. The priority ranking results are also difficult to adaptively adjust with changes in workstation load. The comprehensive impact of factors such as expected chip waiting time and historical workstation performance on scheduling effectiveness is also rarely incorporated into a unified quantitative framework for correlation consideration.

[0067] To address the aforementioned problems, this invention provides a multi-station scheduling method and system for chip testing based on dynamic priority. The specific embodiments of this invention will be described in detail below with reference to the accompanying drawings.

[0068] To illustrate the chip testing multi-station scheduling method and system based on dynamic priority provided by this invention, Figure 1 An exemplary illustration of a chip testing multi-station scheduling method based on dynamic priority according to an embodiment of the present invention is provided; Figure 2 An exemplary illustration is provided for a chip testing multi-station scheduling system based on dynamic priority according to an embodiment of the present invention.

[0069] The following description of exemplary embodiments is merely illustrative and is in no way intended to limit the invention or its application or use. Techniques and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques and equipment should be considered part of the specification.

[0070] Reference Figure 1 The diagram shown is a flowchart illustrating a multi-station scheduling method for chip testing based on dynamic priority, according to an embodiment of the present invention. In this embodiment, the multi-station scheduling method for chip testing based on dynamic priority includes:

[0071] S1. Calculate the urgency coefficient of each chip under test based on the test urgency level and the number of test failure retries for each chip under test;

[0072] In this embodiment of the invention, the process of calculating the urgency coefficient of each chip under test based on its test urgency level and the number of test failure retries is as follows:

[0073] The test urgency level of each chip under test is converted into the base value of the urgency level of each chip under test according to a preset level-value mapping table;

[0074] The number of test failure retries for each chip under test is truncated by a threshold to obtain the effective number of retries for each chip under test;

[0075] The urgent level base value and the effective number of retries are nonlinearly saturated and fused to obtain the urgent fusion value for each chip under test. The calculation formula is as follows:

[0076] ;

[0077] in, This is the urgent fusion value for each chip under test. This is the base value for the emergency level of each chip under test. It is a logarithmic function with base 2. This represents the effective number of retries for each chip under test.

[0078] The urgency fusion value is range-scaled until it reaches a preset standard dynamic range, thus obtaining the urgency coefficient of each chip under test.

[0079] For the conversion operation of the level-value mapping table, a level-value mapping table is pre-defined. This table sets multiple emergency levels according to the emergency level classification standard commonly used in the chip testing field, and each level uniquely corresponds to a base value.

[0080] Once the test urgency level of a chip under test is obtained, the base value of the urgency level corresponding to that level can be determined by directly querying the mapping table. The magnitude of the base value directly reflects the basic weight of that level in terms of urgency.

[0081] The mapping table was designed with full consideration of the priority of different urgency levels in terms of test resource usage. The higher the level, the larger the base value, thus providing a unified and stable numerical starting point for subsequent urgent fusion.

[0082] For the threshold truncation process of test failure retry count, a retry count threshold is preset. The value of this threshold is determined by finding the turning point where the contribution of increasing retry count to scheduling delay gradually flattens out by statistically analyzing the correlation between the number of retry counts and the total time of subsequent test completion in historical chip test data, and the number of times corresponding to this turning point is determined as the threshold.

[0083] During the truncation operation, the actual number of test failure retries for the chip under test is compared with the threshold. If the actual number does not exceed the threshold, the actual number is directly used as the valid number of retries. If the actual number exceeds the threshold, the threshold is forcibly used as the valid number of retries, and the excess number is no longer included in the subsequent calculation.

[0084] This truncation process limits the effective number of retries to a reasonable range, preserving the true contribution of retries to the urgency while avoiding excessive interference caused by extreme retries.

[0085] When performing nonlinear saturation fusion of the emergency level base value and the effective number of retries, a logarithmic nonlinear fusion method is adopted so that the amplification effect of the effective number of retries on the base value gradually decreases as the number of retries increases.

[0086] In the specific fusion operation, the effective number of retries is first increased by one unit, and then the increased value is logarithmically calculated to base 2. The logarithmic result is then increased by one unit to generate a non-linear amplification factor. The growth rate of this factor decreases as the number of retries increases.

[0087] The amplification factor is then multiplied directly by the base value of the emergency level to obtain the emergency fusion value. This value not only fully retains the basic weight of the emergency level of the test, but also incorporates the non-linear emergency increment brought about by the effective number of retries.

[0088] This fusion method ensures that the amplification effect is significant when the number of retries is low, and gradually flattens out when the number of retries is high, which conforms to the diminishing marginal effect of the number of retries on urgency in actual testing.

[0089] After obtaining the urgent fusion value, it is necessary to perform interval scaling to obtain the urgency coefficient. The standard dynamic range on which this scaling is based is set in advance according to the statistical distribution of the urgent fusion values ​​of all chips under test in the historical operation of the chip test multi-station scheduling system. This range covers the vast majority of historical fusion values ​​and has clear upper and lower limits.

[0090] During scaling, the relative position of the current urgent fusion value in the sequence of urgent fusion values ​​of all chips under test is first determined, and then this position is mapped to a preset standard dynamic range so that the urgency coefficients of all chips under test fall into the same numerical range.

[0091] This scaling operation only adjusts the numerical range distribution of the urgency fusion value, without changing the relative order of urgency among the chips under test.

[0092] The urgency coefficient obtained after interval scaling has dimensions and numerical range that are fully aligned with the requirements of subsequent fusion stages, and can be directly used in the dynamic weighted fusion process.

[0093] The beneficial effects are as follows: By converting urgency levels into base values ​​through a mapping table, the contribution of urgency levels to scheduling decisions has a clear and stable numerical basis, avoiding inconsistencies caused by subjective judgment. Threshold truncation effectively controls the effective range of retry counts. The threshold is determined based on historical data turning points, preserving the reasonable impact of retry behavior on urgency while preventing extreme retry values ​​from over-amplifying urgency assessments, making the inclusion of retry factors more aligned with actual testing scenarios. Through nonlinear saturation fusion based on base-2 logarithms, the urgency level base value and effective retry count are integrated into a fusion value of urgency, realistically simulating the diminishing marginal effect of retry counts on urgency. This makes the fusion result both sensitive and robust, with each mathematical operation in the fusion process having a clear physical meaning. Interval scaling unifies the numerical range of urgency coefficients for all chips under test. The standard dynamic range is set based on historical statistical distribution, eliminating dimensional inconsistencies caused by differences in the original data distribution. This provides reliable and comparable input data for subsequent dynamic weighted fusion with expected waiting times and expected test success probabilities.

[0094] S2. The estimated test time of each chip under test and the estimated idle time of the current idle test station are comprehensively evaluated to obtain the expected waiting time of each chip under test at the current idle test station.

[0095] In this embodiment of the invention, the process of comprehensively judging the estimated test time of each chip under test and the estimated idle time of the current idle test station to obtain the expected waiting time of each chip under test at the current idle test station is as follows:

[0096] Retrieve the estimated test time for each chip under test and the estimated idle time for each chip under test in the current idle test station;

[0097] The estimated idle time is compared with the current idle time of each chip under test to obtain the starting point of the waiting window for each chip under test in the current idle test station.

[0098] The waiting window start point and the idle time estimate are time-series superimposed to obtain the end time of the occupation of each chip under test in the current idle test station.

[0099] The time interval between the end time of the waiting period and the start time of the waiting window is extracted, and the time span experienced by each chip under test in the current idle test station from the start of waiting to the end of the waiting period is extracted to obtain the expected waiting time of each chip under test in the current idle test station.

[0100] The retrieval operation reads two types of time data from the storage unit of the chip test scheduling system. One type is the estimated test time for each chip under test, which represents the estimated time that the chip will take from the start of the test to the completion of the test under ideal, no-wait conditions. The other type is the estimated idle time for each chip under test at the current idle test station, which represents the estimated time when the station will enter the idle state after completing all currently assigned test tasks.

[0101] Both of these estimated values ​​are derived from the time estimation results of the testing process previously calculated by the scheduling system. They are stored in the system's time parameter recording area and are retrieved one by one based on the chip identifier and the workstation identifier.

[0102] When comparing the estimated idle time with the current idle time of the chip under test, the current idle time refers to the moment when the chip under test is released from the previous test stage and waits to be assigned a new workstation.

[0103] The difference comparison operation subtracts the current idle time from the estimated idle time. If the difference is positive, it means that the idle time of the workstation is later than the current idle time of the chip, and the chip needs to wait for the workstation to become idle. If the difference is negative or zero, it means that the workstation is already or just idle, and the chip does not need to wait.

[0104] The result of this difference comparison is directly determined as the starting point of the waiting window for the chip under test in the current idle test station. This starting point is a time value, marking the moment when the chip officially enters the waiting state for the station.

[0105] After obtaining the starting point of the waiting window, the starting point is time-over-time with the estimated idle time. Time-over-time means adding the estimated idle time of the workstation to the duration represented by the estimated chip test time, and the result is a new time point.

[0106] This point in time is the end of the chip under test's occupation of the current idle test station. It indicates the moment when the station is released when the test is completed if the chip occupies the station for a complete test starting from the beginning of the waiting window.

[0107] Then, the time interval between the end time of the placeholder and the start time of the waiting window is extracted. The extraction operation is performed by working backward from the end time of the placeholder to the start time of the waiting window to determine the continuous time interval defined by these two time points. The entire time span from the start of the waiting window (i.e., the start of the waiting period) to the end time of the placeholder is extracted, and this span is a duration value.

[0108] This duration value represents the expected waiting time of the chip under test at the current idle test station. It fully expresses the total time consumed by the chip from the start of waiting to the completion of station occupation, including the waiting before the station becomes idle and the test execution at the station. However, it is included in the subsequent priority fusion as a whole waiting time.

[0109] The beneficial effects are as follows: By retrieving the estimated test time and idle time, the calculation of the expected waiting time is based on the system's existing time estimation data, avoiding the accumulation of errors caused by repeated estimations. By comparing the difference between the estimated idle time and the chip's current idle time, the starting point of the waiting window is accurately defined, clarifying the time boundary for the chip to begin waiting and providing a precise starting benchmark for subsequent time interception. By overlaying the starting point of the waiting window with the estimated idle time through a time sequence overlay operation, the end time of the position is obtained, fully reflecting the end time of the entire process from the start of the chip's waiting to the release of the workstation. By intercepting the time interval between the end time of the position and the starting point of the waiting window and extracting the time span, discrete time information is transformed into a continuous duration. The resulting expected waiting time is output as a single duration value, facilitating dynamic weighted fusion with the urgency coefficient and the expected test success probability with unified dimensions.

[0110] S3. The number of test failure retries for each chip under test is correlated and coupled with the historical test success rate of the current idle test station to obtain the expected test success probability of each chip under test in the current idle test station.

[0111] In this embodiment of the invention, the number of test failure retries for each chip under test is correlated with the historical test success rate of the current idle test station to obtain the expected test success probability of each chip under test at the current idle test station. The process is as follows:

[0112] The number of test failure retries is compared with a preset retry threshold to obtain the retry level for each chip under test.

[0113] The historical test success rate is compared with a preset success rate threshold to determine the level range, thereby obtaining the success level of each chip under test in the current idle test station.

[0114] By matching the retry level with the success level, the coupling coefficient between each chip under test and the current idle test station is obtained;

[0115] Based on the coupling coefficient, the historical test success rate is adjusted to obtain the expected test success probability of each chip under test in the current idle test station.

[0116] The preset retry threshold is one or more values. These values ​​are set based on the statistical correlation between different retry intervals in the chip test history data and the final success rate of subsequent tests. The retry count is divided into several consecutive level intervals, and each interval corresponds to a retry level.

[0117] When comparing grade intervals, the number of test failure retries for the chip under test is taken out, and it is determined which preset grade interval the number of retries falls into. Once the grade interval is determined, the retry grade corresponding to that interval is assigned to the chip under test.

[0118] The comparison operation checks the upper and lower bounds of each interval one by one until a unique interval containing the number of retries is found, thus obtaining the retry level of the chip under test. This level exists in the form of a level identifier, reflecting the level at which the chip's retry count is located.

[0119] The preset success rate thresholds are set based on the distribution of test success rates accumulated in the historical operation records of the currently idle test stations. These thresholds divide the historical test success rates into several continuous level intervals from low to high, with each interval corresponding to a success level.

[0120] When determining the grade range, the historical test success rate of the currently available test station is retrieved, and each success rate value is compared with the upper and lower bounds of the grade range to determine the range to which it belongs.

[0121] Once it is determined which range the historical test success rate falls into, the success level corresponding to that range is taken as the success level of the chip under test in the current idle test station. This level indicates the level to which the station belongs under that success rate level.

[0122] When matching retry levels with success levels, a preset matching rule table is used. This matching rule table pre-defines the pairing mapping relationship between different retry levels and different success levels based on experience in the chip testing field.

[0123] During matching, the retry level and success level of the chip under test are used as two input dimensions. The matching rule table is used to find a value corresponding to the combination of these two levels, which is the coupling coefficient.

[0124] The magnitude of the coupling coefficient reflects the degree of compatibility between the retry level of the chip and the success level of the workstation. The larger the coefficient, the more the combination of the two tends to reinforce each other, while the smaller the coefficient, the more the combination tends to weaken each other.

[0125] When adjusting the historical test success rate based on the coupling coefficient, the coupling coefficient is used as an adjustment factor to correct the historical test success rate of the currently idle test station. The correction method is to adjust the historical test success rate in the same or opposite direction according to the direction and magnitude of the coupling coefficient.

[0126] The adjusted result is the expected success probability of the chip under test in the current idle test station. This probability retains the basic information of the original historical test success rate of the station, and also incorporates the matching effect between the chip's retry level and the station's success level.

[0127] The expected test success probability obtained after matching adjustment has comprehensively reflected the correlation effect between the chip's historical retry behavior and the workstation's historical performance, and can be directly used in the subsequent dynamic weighted fusion process.

[0128] The beneficial effects are as follows: By presetting a retry threshold to divide the grade intervals, the differences in the number of retryes are transformed into discrete grade identifiers, avoiding the ambiguity of comparisons caused by continuous values. The threshold setting is based on historical statistical correlation, ensuring the objectivity of the interval division. By presetting a success rate threshold to divide the grade intervals, the historical test success rate of the workstation is transformed into a success grade, making the workstation performance hierarchical and providing a structured basis for subsequent matching with retry grades. By matching retry grades with success grades to obtain a coupling coefficient, quantitative correlation of grade information from both the chip and workstation dimensions is achieved. The pre-defined mapping relationship in the matching rule table ensures that the coupling coefficient reflects the combined effect in real testing experience. By adjusting the historical test success rate based on the coupling coefficient, the coupling effect is integrated into the success rate prediction, so that the expected test success probability depends not only on the historical performance of the workstation but also on the retry grade characteristics of the chip itself. The adjusted probability value can more accurately indicate the actual test success probability of the chip at that workstation.

[0129] S4. Based on the real-time load status of the current idle test station, dynamically weight and fuse the urgency coefficient, the expected waiting time, and the expected test success probability to obtain the dynamic priority index of each chip under test.

[0130] In this embodiment of the invention, the dynamic priority index of each chip under test is obtained by dynamically weighting and fusing the urgency coefficient, the expected waiting time, and the expected test success probability based on the real-time load status of the currently idle test station. The process is as follows:

[0131] Obtain the real-time load status parameters of the currently idle test station, including the number of assigned test tasks, the average test time already assigned, and the length of the assigned chip queue to be processed.

[0132] The number of assigned test tasks, the average test time, and the length of the assigned chip queue are normalized to obtain normalized parameters for the number of assigned test tasks, the average test time, and the length of the assigned chip queue.

[0133] Based on the normalization parameters, the number of allocated test tasks, the average test time allocated, and the length of the allocated chip queue are weighted and fused to obtain the dynamic priority index of each chip under test.

[0134] The dynamic priority index of each chip under test is obtained by weighting and fusing the number of allocated test tasks, the average allocated test time, and the length of the allocated chip queue based on the normalization parameters, as follows:

[0135] The historical average number of test tasks at the current idle test station is used as the first dynamic benchmark, the historical average test time is used as the second dynamic benchmark, and the historical average length of the chip queue to be processed is used as the third dynamic benchmark.

[0136] Set the urgency coefficient of each chip under test as the initial dynamic priority index;

[0137] The number of assigned test tasks is compared with the first dynamic benchmark. If the number of assigned test tasks is higher than the first dynamic benchmark, the initial dynamic priority index is increased by one level to obtain the first adjusted priority index of the initial dynamic priority index.

[0138] The allocated average test time is compared with the second dynamic benchmark. If the allocated average test time is lower than the second dynamic benchmark, the first adjusted priority index is increased by one level to obtain the second adjusted priority index of the initial dynamic priority index.

[0139] The length of the allocated chip queue to be processed is compared with the third dynamic benchmark. If the length of the allocated chip queue to be processed is higher than the third dynamic benchmark, the second adjusted priority index is increased by one level to obtain the third adjusted priority index of the initial dynamic priority index.

[0140] The third adjusted priority index is used as the dynamic priority index for each chip under test.

[0141] When obtaining the real-time load status parameters of the currently idle test station, three specific data items are directly read from the operation monitoring record corresponding to that station. The first item is the total number of test tasks that have been assigned but not yet completed at that station, i.e., the number of assigned test tasks. The second item is the average time taken for all assigned test tasks at that station from start to finish, i.e., the average test time taken. The third item is the total queue length of the chips under test at that station that have not yet been assigned a specific test start time, i.e., the queue length of the chips to be processed that have been assigned.

[0142] These three data points exist in the workstation monitoring records in their original dimensions and numerical scales, and are extracted from the corresponding storage location according to the workstation identifier when they are retrieved.

[0143] When normalizing the number of assigned test tasks, the average test time, and the length of the assigned chip queue, a uniform numerical range is pre-defined. The lower and upper limits of this range are determined based on the numerical fluctuation range of the three load parameters in the historical operation of the currently idle test station, so that the range can cover all possible input values.

[0144] The normalization operation transforms the three actual load parameter values. During the transformation, the relative position of each actual value within its own historical fluctuation range is first determined, and then this relative position is mapped to the corresponding position in a preset unified interval, thereby obtaining the normalized parameter corresponding to each load parameter.

[0145] After normalization, the number of assigned test tasks, the average test time, and the length of the assigned chip queue each have a normalization parameter. These three normalization parameters are all within the same numerical range and have uniform dimensions.

[0146] When weighting and fusing the number of assigned test tasks, the average test time, and the length of the assigned chip queue based on normalization parameters, a weight value is pre-set for each of these three load parameters. The magnitude of the weight value is determined according to the degree of influence of each load factor on the scheduling urgency in the multi-station scheduling scenario of chip testing, and the sum of all weight values ​​remains fixed.

[0147] The fusion operation combines the normalized parameter of each load parameter with its corresponding weight value, and then sums the results of the three combinations to obtain a fusion value that reflects the overall load level of the currently idle test station.

[0148] Based on this, the fusion value is integrated with the urgency coefficient, expected waiting time, and expected test success probability of each chip under test. During the integration, the weight of each factor in the integration is dynamically determined according to its contribution to the scheduling decision, and finally the dynamic priority index of each chip under test is obtained.

[0149] The dynamic priority index is output as a single numerical value, which comprehensively reflects the urgency of the chip under test, the estimated waiting time at that station, the estimated probability of success at that station, and the real-time load status of the current station.

[0150] When obtaining the historical average number of test tasks for the current idle test station, the arithmetic mean of the number of all recorded test tasks for that station in past operating cycles is directly retrieved, and this average is used as the first dynamic benchmark.

[0151] When obtaining the historical average test time of the currently idle test station as the second dynamic benchmark, the arithmetic average of the time taken from start to finish of all executed test tasks in the past operating cycle of that station is directly retrieved.

[0152] When obtaining the historical average queue length of chips to be processed at the current idle test station as the third dynamic benchmark, the arithmetic mean of the waiting queue length recorded at multiple random moments in the past operating cycle of the station is directly retrieved.

[0153] These three dynamic benchmarks are all derived from the long-term operational statistics of the workstation itself, and are calculated independently without affecting each other.

[0154] When setting the urgency coefficient of each chip under test as the initial dynamic priority index, the previously calculated urgency coefficient value of the chip is directly assigned to the initial dynamic priority index. This initial value is exactly equal to the urgency coefficient and is not modified in any way.

[0155] When comparing the number of assigned test tasks with the first dynamic benchmark, the value of the number of assigned test tasks currently acquired by the workstation in real time is compared with the value of the first dynamic benchmark.

[0156] If the number of assigned test tasks is higher than the first dynamic baseline, a level upgrade operation is performed on the initial dynamic priority index. The level upgrade operation is carried out according to a pre-set fixed level step size, which is the minimum adjustment unit uniformly defined in the scheduling system. After the upgrade, the first adjusted priority index of the initial dynamic priority index is obtained.

[0157] If the number of assigned test tasks is not higher than the first dynamic baseline, the initial dynamic priority index remains unchanged and no promotion operation is performed. In this case, the first adjusted priority index is the same as the initial dynamic priority index.

[0158] When comparing the allocated average test time with the second dynamic benchmark, the value of the allocated average test time currently acquired in real time at this workstation is compared with the value of the second dynamic benchmark.

[0159] If the average test time allocated is lower than the second dynamic benchmark, then the first adjusted priority index will be upgraded again. The upgrade will also be carried out according to the same fixed step size set in advance. After the upgrade, the second adjusted priority index of the initial dynamic priority index will be obtained.

[0160] If the average test time allocated is not lower than the second dynamic benchmark, the first adjusted priority index remains unchanged and no promotion operation is performed. In this case, the second adjusted priority index is the same as the first adjusted priority index.

[0161] When comparing the length of the assigned chip queue to be processed with the third dynamic benchmark, the value of the assigned chip queue length currently acquired by the workstation in real time is compared with the value of the third dynamic benchmark.

[0162] If the length of the allocated chip queue is higher than the third dynamic baseline, then the second adjusted priority index will be upgraded again. The upgrade will still be carried out according to the same fixed step size set in advance. After the upgrade, the third adjusted priority index of the initial dynamic priority index will be obtained.

[0163] If the length of the allocated chip queue is not higher than the third dynamic benchmark, the second adjusted priority index remains unchanged and no promotion operation is performed. In this case, the third adjusted priority index is the same as the second adjusted priority index.

[0164] When using the third adjusted priority index as the dynamic priority index for each chip under test, the third adjusted priority index obtained after the above three comparisons and possible level upgrades is directly and completely assigned to the dynamic priority index of the chip under test.

[0165] The dynamic priority index is the priority value that the chip will ultimately be used for subsequent resource evaluation and target chip selection under the current idle test station. Its value has been adjusted according to the deviation of the station's real-time load from the historical average level compared to the initial urgency coefficient.

[0166] The beneficial effects are as follows: by acquiring three real-time load parameters—the number of test tasks at currently idle test stations, the average test duration, and the length of the pending queue—the dynamic priority index accurately reflects the actual busyness of the workstations, avoiding scheduling biases based on static or outdated data. Normalization unifies the three load parameters, which have different dimensions, into the same numerical range, eliminating fusion barriers caused by differences in the original data scales and ensuring that the three parameters have an equal numerical contribution basis during weighted fusion. Weighted fusion integrates the three normalized parameters into a comprehensive workstation load value. Furthermore, this comprehensive load value is integrated with the urgency coefficient, expected waiting time, and expected test success probability, achieving bidirectional coupling between multi-dimensional attributes of the chip and the real-time load status of the workstation. The dynamic priority index comprehensively expresses four key pieces of information—the urgency of the chip under test, expected waiting time, expected success probability, and workstation load level—in a single numerical form, providing a clear and comprehensive ranking basis for subsequent resource assessment and target chip selection.

[0167] By obtaining the historical average number of test tasks, historical average test time, and historical average queue length for each workstation as three dynamic benchmarks, the comparison references are derived from the actual long-term operation of the workstation itself, avoiding the scenario inapplicability issues caused by using a fixed and uniform standard. By directly setting the urgency coefficient as the initial dynamic priority index, the urgency of the chip itself occupies a fundamental position in the priority, and all subsequent adjustments are superimposed on this, retaining the core dominant role of the urgency coefficient. By comparing the number of assigned test tasks with the first dynamic benchmark, the priority is increased when the number of tasks is higher than the historical average, allowing the workstation to prioritize processing the current chip even when there are many tasks, avoiding excessive backlog at the workstation. By comparing the assigned average test time with the second dynamic benchmark, the priority is increased when the average time is lower than the historical average, meaning that the current tasks at the workstation are generally shorter, allowing for faster completion of the current chip's test and utilizing the workstation's efficient time slots. By comparing the assigned queue length for chips to be processed with the third dynamic benchmark, the priority is increased when the queue length is higher than the historical average, allowing chips to enter the workstation earlier, alleviating queuing pressure and reducing overall waiting time. All three comparisons and grade upgrades were based on the same fixed grade step size, ensuring fairness and consistency in priority adjustments. Each upgrade was the same in magnitude, without varying adjustment amounts due to different comparison items. The third adjusted priority index, obtained after these step-by-step adjustments, retains the initial weight of the urgency coefficient and comprehensively reflects the positive incentives of the three real-time states—two overload conditions and one low latency condition—on priority. Ultimately, the dynamic priority index adaptively adjusts according to the degree to which the workstation load deviates from historical norms, providing a precise and dynamically responsive ranking basis for subsequent resource assessments.

[0168] S5. Based on the dynamic priority index arranged from high to low, perform resource evaluation on each chip under test to obtain the resource matching degree of the chip under test in the current idle test station.

[0169] In this embodiment of the invention, the resource evaluation of each chip under test based on the dynamic priority index arranged from high to low, to obtain the resource matching degree of the chip under test in the current idle test station, is performed as follows:

[0170] Based on the dynamic priority index arranged from high to low, the priority of each chip under test is evaluated to obtain the test resource requirement parameter set of each chip under test;

[0171] Obtain the set of station resource supply parameters for the chip under test in the currently idle test station;

[0172] Each item in the set of test resource requirements parameters is screened against the corresponding item in the set of workstation resource supply parameters until it falls completely within the range of the workstation resource supply parameters or is below the upper limit of the workstation resource supply parameters, thus obtaining the number of items that pass in each chip under test.

[0173] By comparing the number of projects with the total number of each chip under test, the resource matching degree of the chip under test in the current idle test station is obtained.

[0174] According to the dynamic priority index from high to low, the chips under test are taken out one by one for priority evaluation. During the evaluation, based on the chip's own test specifications and technical parameters, the various resource conditions required for chip testing are listed one by one to form the test resource requirement parameter set of the chip under test. This parameter set includes the types of resources required for the chip to complete the test and their corresponding requirements.

[0175] When obtaining the set of station resource supply parameters for the chip under test in the current idle test station, the upper limit of each resource capability that the station can currently provide is directly read, including the station's inherent attributes such as the number of test channels, power supply capability, signal bandwidth, and mechanical interface compatibility. These supply capabilities are then summarized into a set of station resource supply parameters.

[0176] The supply parameter set and the test resource requirement parameter set contain the same category of resource items, so that they can be compared item by item later.

[0177] Each item in the test resource demand parameter set is filtered against its corresponding item in the workstation resource supply parameter set. The filtering operation first takes out a demand parameter and its corresponding supply parameter, and determines whether the demand parameter falls completely within the range defined by the supply parameter item, or whether the demand parameter is lower than the upper limit specified by the supply parameter item.

[0178] If the demand meets the above conditions, the project is marked as passed; if the demand parameters exceed the range of the supply parameters or are higher than the upper limit, the project is marked as failed.

[0179] The screening is performed item by item in the order of the parameters in the set until all items have been compared. The number of items marked as passed is counted to obtain the number of passed items in each chip under test.

[0180] When comparing the number of projects with the total number of projects for each chip under test, the total number of projects refers to the total number of all resource projects participating in the item-by-item screening in the test resource requirement parameter set. This number is determined before the screening begins.

[0181] The benchmarking and evaluation operation divides the number of approved projects by the total number of comparison projects to obtain a ratio. This ratio indicates the degree to which the resource requirements of the chip are met at that workstation.

[0182] This ratio is directly used as the resource matching degree of the chip under test in the current idle test station. The matching degree is output in the form of a ratio. The larger the value, the higher the degree of matching between chip demand and station supply. The smaller the value, the lower the degree of matching.

[0183] The beneficial effects are as follows: By evaluating priority sequentially from high to low based on a dynamic priority index, high-priority chips are given priority in resource matching calculations, ensuring consistency between scheduling and priority ranking. The evaluation yields a set of test resource requirements parameters for each chip under test, systematizing and itemizing the various resource conditions required for chip testing, providing a complete list of requirements for subsequent precise comparison with workstation supply capabilities. By obtaining the workstation resource supply parameter set, the various resource capabilities currently available at the workstation are clearly defined, providing both supply and demand sides with unified project categories and comparison dimensions. Through item-by-item screening, the demand parameters are compared with the supply parameters, determining whether each item falls entirely within the supply range or is below the upper limit. Items that pass and fail are marked, and the number of pass items is counted, ensuring that the matching degree calculation is based on objective item-by-item confirmation, avoiding the uncertainty caused by general estimations. By comparing the number of projects that passed with the total number of projects, the absolute number of projects that passed is transformed into a relative ratio to determine the resource matching degree. This makes the matching degree between different chips comparable. This ratio objectively reflects the overall matching level between chip demand and workstation supply, providing a clear resource dimension scoring basis for subsequent comprehensive matching.

[0184] S6. Perform a comprehensive matching between the resource matching degree and the dynamic priority index, select the chip with the highest comprehensive matching score as the target chip, and allocate a reserved time window for the target chip in the current idle test station to obtain the reserved time window information of the target chip.

[0185] In this embodiment of the invention, the process of comprehensively matching the resource matching degree with the dynamic priority index, selecting the chip with the highest comprehensive matching score as the target chip, and allocating a reserved time window for the target chip in the current idle test station to obtain the reserved time window information of the target chip is as follows:

[0186] By associating the dynamic priority index with the resource matching degree, the comprehensive matching attributes of each chip under test are obtained.

[0187] Based on the comprehensive matching attributes, each chip under test is selected by optimization to obtain the chip under test with the best comprehensive matching attributes.

[0188] The chip under test is used as the target chip;

[0189] Read the idle start time and idle duration of the target chip at the current idle test station;

[0190] The idle start time and the idle duration are time-series integrated to obtain the reserved time window information of the target chip.

[0191] The corresponding association operation combines the two numerical attributes of dynamic priority index and resource matching degree of each chip under test into a composite attribute containing dual information. This composite attribute is the comprehensive matching attribute, which records both the priority ranking position and resource adaptability of the chip. The two coexist in the same attribute in an associated form.

[0192] The selection process is based on the comprehensive matching attributes of each chip under test. A selection rule is pre-defined, which stipulates that the dynamic priority index is compared first, and the chip with the higher index is selected first. If the indices are the same, the resource matching degree is compared, and the chip with the higher matching degree is selected first. The comprehensive matching attributes of all chips under test are reviewed and compared one by one according to this rule. After all comparisons are made, the chip with the best comprehensive matching attributes is determined.

[0193] The selected chip to be tested is directly designated as the target chip, which is the specific chip object targeted by subsequent scheduling instructions.

[0194] Read the idle start time and idle duration of the target chip in the current idle test station. These two time information are directly obtained from the time parameter record of the station. The idle start time is the specific time point when the station is expected to enter the idle state, and the idle duration is the length of time that the station can continuously maintain the idle state from the idle start time.

[0195] The idle start time and idle duration are integrated in a time sequence. The integration operation takes the idle start time as the starting point of the time window and the idle duration as the duration extending from the starting point. The two are combined to form a continuous time period. This time period determines the specific start and end points of the workstation that the target chip can occupy. This time period is the reserved time window information for the target chip. This information includes two elements: the window start time and the window duration.

[0196] The beneficial effects are as follows: By merging the dynamic priority index and resource matching degree into a comprehensive matching attribute through corresponding association, the ranking advantage and resource adaptation advantage of each chip are presented simultaneously in the same attribute, providing an integrated evaluation basis for subsequent optimization. Optimal selection based on the comprehensive matching attribute, using a hierarchical comparison rule with the priority index as the primary comparison item and resource matching degree as the secondary comparison item, ensures that scheduling decisions first follow priority ranking, while also considering resource matching effects when priorities are the same, making the selection result both responsive to urgency requirements and reasonable in resource utilization. By determining the optimal chip as the target chip, all subsequent time window operations focus on the uniquely selected chip, avoiding conflicts caused by multiple chips occupying the same workstation in parallel. By reading the idle start time and idle duration of the target chip in the current idle test workstation, the time boundary of the workstation that can be occupied is accurately obtained, providing an accurate time data foundation for the construction of time windows. By integrating the idle start time and idle duration, the time point and duration are merged into a reserved time window information in the form of a continuous time period. This information fully describes the target chip's occupation plan for the workstation with a clear start point and duration, providing a clear time parameter structure for subsequent scheduling instruction encapsulation.

[0197] S7. Encapsulate the reserved time window information of the target chip into a scheduling instruction to obtain the test multi-station scheduling instruction of the target chip.

[0198] In this embodiment of the invention, the process of encapsulating the reserved time window information of the target chip into scheduling instructions to obtain the test multi-station scheduling instructions for the target chip is as follows:

[0199] Obtain the chip identification information of the target chip;

[0200] The chip identification information, the reserved start time and the reserved duration in the reserved time window information of the target chip are arranged according to a preset instruction template to obtain the instruction content body of the target chip;

[0201] The instruction content of the target chip is encapsulated using a protocol to obtain the test multi-station scheduling instruction for the target chip.

[0202] When obtaining the chip identification information of the target chip, the unique identification code of the chip in the scheduling system is read directly. This code is a fixed identity mark that is assigned to each chip under test and recorded in the system storage unit when it enters the test process. This mark is used to uniquely distinguish different chip objects in all subsequent scheduling operations.

[0203] When arranging the chip identification information, the reserved start time, and the reserved duration in the reserved time window information of the target chip according to the preset instruction template, the instruction template is uniformly formulated in advance according to the instruction format that can be recognized by different test stations or test equipment in the chip test system. The template specifies the arrangement order and position of the chip identification information, the reserved start time, and the reserved duration in the instruction content body. The arrangement operation fills the above three pieces of information into the corresponding fields in the order specified by the template. After the three pieces of information are filled, a structured instruction data set is formed, which is the instruction content body of the target chip.

[0204] When encapsulating the instruction content of the target chip according to the protocol, the data transmission protocol followed by the communication between various devices within the chip testing system is used. This protocol specifies the frame structure that the instruction must have during transmission. The encapsulation operation frames the instruction content according to the frame format specified by the protocol, and adds the control information and verification information required by the protocol before and after the instruction content to ensure that the encapsulated data meets the requirements of internal system transmission and parsing. The data frame obtained after encapsulation is the test multi-station scheduling instruction for the target chip, which can be directly sent to the corresponding test station to execute the chip test task.

[0205] The beneficial effects are as follows: by obtaining the chip identification information of the target chip, the final generated scheduling instructions can clearly point to a unique chip under test, avoiding object confusion that may occur when scheduling multiple chips simultaneously. By arranging the chip identification information, reserved start time, and reserved duration into the instruction content body according to a preset instruction template, the three key pieces of information are organized together in a unified and standardized structure, ensuring the integrity and format consistency of the instruction content. The preset template is based on the common interface specifications of the devices at each workstation within the system, ensuring that the arrangement result can be correctly received by the subsequent encapsulation stage. By encapsulating the instruction content body according to the protocol, the structured data set is converted into a complete scheduling instruction that conforms to the system communication protocol requirements. The encapsulation process adds the pre-transmission control and tail check required for the instruction, ensuring the integrity and parsability of the instruction during transmission within the test system. The test multi-workstation scheduling instruction generated through the above steps carries the three key pieces of information—chip identification, reserved start time, and reserved duration—in a unified communication format within the system. This instruction can be directly issued to the target workstation for execution, realizing a seamless transformation from scheduling decision results to executable instructions, and providing the final output carrier for the closed-loop implementation of the scheduling method.

[0206] As can be seen from the above embodiments, the chip testing multi-station scheduling method provided by the present invention calculates the urgency coefficient, expected waiting time, and expected test success probability of the chip under test, and performs dynamic weighted fusion with the real-time load status of the workstation to obtain a dynamic priority index. Then, resource evaluation is performed according to the priority ranking to obtain the resource matching degree. Finally, the target chip is selected by combining the matching degree and the priority index, and a reserved time window is allocated before the scheduling instruction is packaged and generated. This realizes the dynamic integration and adaptation of multi-dimensional information such as chip urgency, workstation idle waiting time, expected test success rate, and workstation real-time load, effectively improving the overall resource utilization efficiency of chip testing multi-station scheduling.

[0207] like Figure 2 The diagram shown is a functional block diagram of a chip testing multi-station scheduling system 100 based on dynamic priority provided in an embodiment of the present invention, including an urgency calculation module 101, an expected waiting module 102, a success rate coupling module 103, a dynamic priority module 104, a resource matching module 105, a comprehensive matching module 106, and a scheduling instruction encapsulation module 107.

[0208] In this embodiment, the functions of each module are as follows:

[0209] The urgency calculation module 101 is used to calculate the urgency coefficient of each chip under test based on the test urgency level and the number of test failure retries for each chip under test.

[0210] The expected waiting module 102 is used to comprehensively analyze the estimated test time of each chip under test and the estimated idle time of the current idle test station to obtain the expected waiting time of each chip under test at the current idle test station.

[0211] The success rate coupling module 103 is used to associate and couple the number of test failure retries for each chip under test with the historical test success rate of the current idle test station to obtain the expected test success probability of each chip under test in the current idle test station.

[0212] The dynamic priority module 104 is used to dynamically weight and fuse the urgency coefficient, the expected waiting time and the expected test success probability based on the real-time load status of the current idle test station to obtain the dynamic priority index of each chip under test.

[0213] The resource matching module 105 is used to evaluate the resources of each chip under test based on the dynamic priority index from high to low, and obtain the resource matching degree of the chip under test in the current idle test station.

[0214] The comprehensive matching module 106 is used to comprehensively match the resource matching degree with the dynamic priority index, select the chip with the highest comprehensive matching score as the target chip, and allocate a reserved time window for the target chip in the current idle test station to obtain the reserved time window information of the target chip.

[0215] The scheduling instruction encapsulation module 107 is used to encapsulate the reserved time window information of the target chip into scheduling instructions to obtain the test multi-station scheduling instructions of the target chip.

[0216] As can be seen from the above embodiments, the chip testing multi-station scheduling system provided by the present invention calculates the urgency coefficient, expected waiting time, and expected test success probability of the chip under test, and performs dynamic weighted fusion with the real-time load status of the workstation to obtain a dynamic priority index. Then, resource evaluation is performed according to the priority ranking to obtain the resource matching degree. Finally, the target chip is selected by combining the matching degree and the priority index, and a reserved time window is allocated before the scheduling instruction is packaged and generated. This realizes the dynamic integration and adaptation of multi-dimensional information such as chip urgency, workstation idle waiting time, expected test success rate, and workstation real-time load, effectively improving the overall resource utilization efficiency of chip testing multi-station scheduling.

[0217] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0218] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A multi-station scheduling method for chip testing based on dynamic priority, characterized in that, The method includes: S1. Calculate the urgency coefficient of each chip under test based on the test urgency level and the number of test failure retries for each chip under test; S2. The estimated test time of each chip under test and the estimated idle time of the current idle test station are comprehensively evaluated to obtain the expected waiting time of each chip under test at the current idle test station. S3. The number of test failure retries for each chip under test is correlated and coupled with the historical test success rate of the current idle test station to obtain the expected test success probability of each chip under test in the current idle test station. S4. Based on the real-time load status of the current idle test station, dynamically weight and fuse the urgency coefficient, the expected waiting time, and the expected test success probability to obtain the dynamic priority index of each chip under test. S5. Based on the dynamic priority index arranged from high to low, perform resource evaluation on each chip under test to obtain the resource matching degree of the chip under test in the current idle test station. S6. Perform a comprehensive matching between the resource matching degree and the dynamic priority index, select the chip with the highest comprehensive matching score as the target chip, and allocate a reserved time window for the target chip in the current idle test station to obtain the reserved time window information of the target chip. S7. Encapsulate the reserved time window information of the target chip into a scheduling instruction to obtain the test multi-station scheduling instruction of the target chip.

2. The chip testing multi-station scheduling method based on dynamic priority as described in claim 1, characterized in that, The urgency coefficient of each chip under test is calculated based on its test urgency level and the number of test failure retries. The process is as follows: The test urgency level of each chip under test is converted into the base value of the urgency level of each chip under test according to a preset level-value mapping table; The number of test failure retries for each chip under test is truncated by a threshold to obtain the effective number of retries for each chip under test; The urgent level base value and the effective number of retries are nonlinearly saturated and fused to obtain the urgent fusion value for each chip under test. The calculation formula is as follows: ； in, This is the urgent fusion value for each chip under test. This is the base value for the emergency level of each chip under test. It is a logarithmic function with base 2. This represents the effective number of retries for each chip under test. The urgency fusion value is range-scaled until it reaches a preset standard dynamic range, thus obtaining the urgency coefficient of each chip under test.

3. The chip testing multi-station scheduling method based on dynamic priority as described in claim 1, characterized in that, The process of comprehensively evaluating the estimated test time of each chip under test with the estimated idle time of the current idle test station to obtain the expected waiting time of each chip under test at the current idle test station is as follows: Retrieve the estimated test time for each chip under test and the estimated idle time for each chip under test in the current idle test station; The estimated idle time is compared with the current idle time of each chip under test to obtain the starting point of the waiting window for each chip under test in the current idle test station. The waiting window start point and the idle time estimate are time-series superimposed to obtain the end time of the occupation of each chip under test in the current idle test station. The time interval between the end time of the waiting period and the start time of the waiting window is extracted, and the time span experienced by each chip under test in the current idle test station from the start of waiting to the end of the waiting period is extracted to obtain the expected waiting time of each chip under test in the current idle test station.

4. The chip testing multi-station scheduling method based on dynamic priority as described in claim 1, characterized in that, The process of correlating the number of test failure retries for each chip under test with the historical test success rate of the current idle test station to obtain the expected test success probability of each chip under test at the current idle test station is as follows: The number of test failure retries is compared with a preset retry threshold to obtain the retry level for each chip under test. The historical test success rate is compared with a preset success rate threshold to determine the level range, thereby obtaining the success level of each chip under test in the current idle test station. By matching the retry level with the success level, the coupling coefficient between each chip under test and the current idle test station is obtained; Based on the coupling coefficient, the historical test success rate is adjusted to obtain the expected test success probability of each chip under test in the current idle test station.

5. The chip testing multi-station scheduling method based on dynamic priority as described in claim 1, characterized in that, The dynamic priority index of each chip under test is obtained by dynamically weighting and fusing the urgency coefficient, the expected waiting time, and the expected test success probability based on the real-time load status of the currently idle test station. The process is as follows: Obtain the real-time load status parameters of the currently idle test station, including the number of assigned test tasks, the average test time already assigned, and the length of the assigned chip queue to be processed. The number of assigned test tasks, the average test time, and the length of the assigned chip queue are normalized to obtain normalized parameters for the number of assigned test tasks, the average test time, and the length of the assigned chip queue. Based on the normalization parameters, the number of allocated test tasks, the average test time allocated, and the length of the allocated chip queue are weighted and fused to obtain the dynamic priority index of each chip under test.

6. The chip testing multi-station scheduling method based on dynamic priority as described in claim 5, characterized in that, The dynamic priority index of each chip under test is obtained by weighting and fusing the number of allocated test tasks, the average allocated test time, and the length of the allocated chip queue based on the normalization parameters, as follows: The historical average number of test tasks at the current idle test station is used as the first dynamic benchmark, the historical average test time is used as the second dynamic benchmark, and the historical average length of the chip queue to be processed is used as the third dynamic benchmark. Set the urgency coefficient of each chip under test as the initial dynamic priority index; The number of assigned test tasks is compared with the first dynamic benchmark. If the number of assigned test tasks is higher than the first dynamic benchmark, the initial dynamic priority index is increased by one level to obtain the first adjusted priority index of the initial dynamic priority index. The allocated average test time is compared with the second dynamic benchmark. If the allocated average test time is lower than the second dynamic benchmark, the first adjusted priority index is increased by one level to obtain the second adjusted priority index of the initial dynamic priority index. The length of the allocated chip queue to be processed is compared with the third dynamic benchmark. If the length of the allocated chip queue to be processed is higher than the third dynamic benchmark, the second adjusted priority index is increased by one level to obtain the third adjusted priority index of the initial dynamic priority index. The third adjusted priority index is used as the dynamic priority index for each chip under test.

7. The chip testing multi-station scheduling method based on dynamic priority as described in claim 1, characterized in that, The process of evaluating the resources of each chip under test based on the dynamic priority index in descending order to obtain the resource matching degree of the chip under test in the current idle test station is as follows: Based on the dynamic priority index arranged from high to low, the priority of each chip under test is evaluated to obtain the test resource requirement parameter set of each chip under test; Obtain the set of station resource supply parameters for the chip under test in the currently idle test station; Each item in the set of test resource requirements parameters is screened against the item in the set of workstation resource supply parameters until it falls completely within the range of the workstation resource supply parameters or is below the upper limit of the workstation resource supply parameters, thus obtaining the number of items that pass in each chip under test. By comparing the number of projects with the total number of each chip under test, the resource matching degree of the chip under test in the current idle test station is obtained.

8. The chip testing multi-station scheduling method based on dynamic priority as described in claim 1, characterized in that, The process of comprehensively matching the resource matching degree with the dynamic priority index, selecting the chip with the highest comprehensive matching score as the target chip, and allocating a reserved time window for the target chip in the current idle test station to obtain the reserved time window information of the target chip is as follows: By associating the dynamic priority index with the resource matching degree, the comprehensive matching attributes of each chip under test are obtained. Based on the comprehensive matching attributes, each chip under test is selected by optimization to obtain the chip under test with the best comprehensive matching attributes. The chip under test is used as the target chip; Read the idle start time and idle duration of the target chip at the current idle test station; The idle start time and the idle duration are time-series integrated to obtain the reserved time window information of the target chip.

9. The chip testing multi-station scheduling method based on dynamic priority as described in claim 1, characterized in that, The process of encapsulating the reserved time window information of the target chip into scheduling instructions to obtain the test multi-station scheduling instructions for the target chip is as follows: Obtain the chip identification information of the target chip; The chip identification information, the reserved start time and the reserved duration in the reserved time window information of the target chip are arranged according to a preset instruction template to obtain the instruction content body of the target chip; The instruction content of the target chip is encapsulated using a protocol to obtain the test multi-station scheduling instruction for the target chip.

10. A chip testing multi-station scheduling system based on dynamic priority, characterized in that, The system is used to implement the dynamic priority-based multi-station scheduling method for chip testing according to any one of claims 1-9, the system comprising: The urgency calculation module is used to calculate the urgency coefficient of each chip under test based on the test urgency level and the number of test failure retries for each chip under test; The expected waiting module is used to comprehensively analyze the estimated test time of each chip under test and the estimated idle time of the current idle test station to obtain the expected waiting time of each chip under test at the current idle test station. The success rate coupling module is used to associate and couple the number of test failure retries for each chip under test with the historical test success rate of the current idle test station to obtain the expected test success probability of each chip under test in the current idle test station. The dynamic priority module is used to dynamically weight and fuse the urgency coefficient, the expected waiting time, and the expected test success probability based on the real-time load status of the current idle test station to obtain the dynamic priority index of each chip under test. The resource matching module is used to evaluate the resources of each chip under test based on the dynamic priority index from high to low, and obtain the resource matching degree of the chip under test in the current idle test station. The comprehensive matching module is used to comprehensively match the resource matching degree with the dynamic priority index, select the chip with the highest comprehensive matching score as the target chip, and allocate a reserved time window for the target chip in the current idle test station to obtain the reserved time window information of the target chip. The scheduling instruction encapsulation module is used to encapsulate the reserved time window information of the target chip into scheduling instructions to obtain the test multi-station scheduling instructions of the target chip.

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