A circuit board electrical fault detection method based on thermoelectric cycle excitation

Abstract

The present application relates to the technical field of circuit board fault detection, in particular to a circuit board electrical fault detection method based on thermoelectric cycle excitation, comprising applying thermoelectric cycle excitation, collecting transient current waveform data and surface temperature decay curve data in the cooling stage within a period; calculating the shortest time regularization path distance parameter of the waveform, and performing a multi-exponential peeling algorithm on the temperature curve to separate out high, medium and low frequency time constants representing different depth thermal characteristics; generating a fault identification when the distance parameter meets the condition, comparing the offset of each time constant relative to the reference period, and outputting the level corresponding to the maximum offset as the fault location. The present application extracts transient distortion characteristics to realize early warning to prevent thermal collapse and burning, and separates thermal constants of different depths to non-destructively locate the abnormal structure level, realizing the cooperative diagnosis of electrical warning and internal damage depth.

Description

Technical Field

[0001] This invention relates to the field of circuit board fault detection technology, specifically to a method for detecting electrical faults in circuit boards based on thermoelectric cycle excitation. Background Technology

[0002] During circuit board lifespan testing, the standard procedure involves fixing the circuit board on a stand and connecting it to a test suite containing a controller, sensors, inverter, and fan via wires. During testing, the controller activates the inverter, supplying a set current to the circuit board to continuously heat it. When the surface sensor detects that the temperature has reached a preset maximum value, the inverter disconnects, and the fan activates to cool the board. Once the temperature reaches the minimum, the inverter is activated again, and this cycle repeats until the circuit board burns out or short-circuits. During this continuous thermoelectric cycle, due to the inconsistent thermal expansion coefficients of the silicon wafer, copper-clad laminate, and tin alloy solder, microcracks gradually develop inside the interconnect solder joints due to shear stress.

[0003] In some circuit board aging test processes that use the upper and lower limits of surface temperature as the basis for cycle control, if electrical transient response and thermal transient response are not collected simultaneously, it is difficult to identify the degradation trend of interconnect solder joints, solder connection layers or substrate heat conduction paths in the early stage of thermoelectric cycle. In particular, it is difficult to give fault warnings and suspected structural level prompts before complete open circuit, short circuit or irreversible thermal damage occurs. As a result, it is not only impossible to determine whether the abnormality is located in the surface silicon wafer, the middle layer solder or the bottom substrate, but also to blindly inject large current when the internal solder joint is on the verge of breaking, which can easily cause local instantaneous thermal collapse, directly burn out and destroy the physical cross-section site required for subsequent microscopic inspection. To address this, a circuit board electrical fault detection method based on thermoelectric cycle excitation is proposed. Summary of the Invention

[0004] The purpose of this invention is to provide a circuit board electrical fault detection method based on thermoelectric cycle excitation to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A method for detecting electrical faults in a circuit board based on thermoelectric cycling excitation, comprising: The circuit board is subjected to alternating thermoelectric cycle excitation using a test all-in-one machine. Transient current waveform data at the moment the inverter is disconnected is collected in each cycle of the thermoelectric cycle excitation, and surface temperature decay curve data during the continuous cooling phase of the cooling fan is collected simultaneously. The transient current waveform data is input into the dynamic time warping algorithm model to calculate the shortest time warping path distance parameter between the transient current waveform data extracted in the current cycle and the preset non-destructive health reference waveform; the multi-exponential stripping algorithm is executed on the surface temperature decay curve data to sequentially separate and output the high-frequency time constant, mid-frequency time constant and low-frequency time constant representing the thermal response characteristics of different physical layers of the circuit board. When the shortest time warp path distance parameter meets the preset fault triggering condition, an electrical fault identifier is generated for the circuit board under test. After generating the electrical fault identifier, the offset values ​​of the high-frequency time constant, the medium-frequency time constant and the low-frequency time constant relative to the initial reference period are extracted and compared. The depth physical level corresponding to the maximum offset value is output as the structural location information of the electrical fault.

[0006] Preferably, the alternating thermoelectric cycle excitation is a periodic excitation sequence consisting of an alternating power-on self-heating stage and a power-off air-cooling stage; in the power-on self-heating stage, the inverter injects working current into the circuit board under test to heat up its internal physical layers to a preset upper temperature limit; in the power-off air-cooling stage, the inverter is controlled to disconnect to cut off the working current input, and the cooling fan is simultaneously started to force heat dissipation of the circuit board under test until its surface temperature drops to a preset lower temperature limit.

[0007] Preferably, the dynamic time warping algorithm model is a two-dimensional feature distance matrix data that reflects the local peak and valley morphological misalignment of the waveform based on the transient current waveform data and the preset lossless health reference waveform; Based on the two-dimensional feature distance matrix data, global cumulative deformation trajectory data characterizing the nonlinear scaling evolution process of the transient waveform on the time axis is generated; based on the global cumulative deformation trajectory data, the shortest time warp path distance parameter representing the overall distortion degree of the waveform is generated.

[0008] Preferably, the process of obtaining the shortest time regularized path distance parameter is to extract the actual regularized connection path formed by the global cumulative deformation trajectory data in the two-dimensional time matrix; and to construct an ideal diagonal straight line connecting the start and end points of the two-dimensional time matrix. The ideal diagonal straight line represents the reference state in which the measured transient waveform and the preset non-destructive health reference waveform are in absolute synchronous alignment on the time axis. Calculate the geometric enclosed area formed by the deviation of the actual regularized connecting path from the ideal diagonal line, and extract the number of inflection points on the actual regularized connecting path where direction deflection occurs to generate path tortuosity features; construct a two-dimensional distance feature vector using the geometric enclosed area and the path tortuosity features, and output the shortest time regularized path distance parameter by calculating the magnitude of the two-dimensional distance feature vector.

[0009] Preferably, the multi-exponential stripping algorithm is to construct the surface temperature decay curve data into a transient heat transfer model with three superimposed exponential values. The time axis segment of the surface temperature decay curve data is fitted to separate the low-frequency time constant representing the heat transfer characteristics of the bottom substrate, and the corresponding low-frequency component is removed to obtain primary residual data; the time axis segment of the primary residual data is fitted to separate the mid-frequency time constant representing the heat transfer characteristics of the intermediate layer solder, and the corresponding mid-frequency component is removed to obtain secondary residual data; the time axis segment of the secondary residual data is fitted to separate the high-frequency time constant representing the thermal characteristics of the surface silicon wafer; the high-frequency time constant, mid-frequency time constant, and low-frequency time constant are respectively mapped to the surface silicon wafer, intermediate layer solder, and bottom substrate.

[0010] Preferably, the low-frequency time constant is the negative reciprocal of the slope obtained by linear fitting after taking the natural logarithm of the last segment of the time axis of the surface temperature decay curve data; the mid-frequency time constant is the negative reciprocal of the slope obtained by linear fitting after taking the natural logarithm of the middle segment of the time axis of the first residual data; and the high-frequency time constant is the negative reciprocal of the slope obtained by linear fitting after taking the natural logarithm of the first segment of the time axis of the second residual data.

[0011] Preferably, the preset fault triggering condition is that the shortest time warp path distance parameter of the current period is greater than the product of the shortest time warp path distance parameter of the initial reference period and the maximum thermal hysteresis coefficient; wherein, the maximum thermal hysteresis coefficient is calculated by calculating the ratio of the high-frequency time constant, mid-frequency time constant and low-frequency time constant of the current period to the high-frequency time constant, mid-frequency time constant and low-frequency time constant corresponding to the initial reference period, and extracting the maximum value of the three ratios as the maximum thermal hysteresis coefficient.

[0012] Preferably, the process of obtaining the offset value is as follows: calculate the high-frequency time constant, mid-frequency time constant and low-frequency time constant of the current period respectively, and divide the absolute value of the difference between the high-frequency time constant, mid-frequency time constant and low-frequency time constant corresponding to the initial reference period by the high-frequency time constant, mid-frequency time constant and low-frequency time constant of the corresponding depth physical layer in the initial reference period to obtain the relative degradation rate corresponding to each depth physical layer; use the relative degradation rate corresponding to each depth physical layer as the offset value of the corresponding depth physical layer. The initial reference period is calculated by sequentially calculating the sum of the high-frequency time constant, the mid-frequency time constant, and the low-frequency time constant for each consecutive cycle under the alternating thermoelectric cycle excitation; sequentially calculating the first-order absolute difference of the sum of the three time constants corresponding to two consecutive adjacent cycles, constructing a sequence of absolute difference values ​​arranged according to the cycle number; and extracting the cycle corresponding to the minimum inflection point in the sequence of absolute difference values ​​as the initial reference period.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention utilizes a test unit to capture high-frequency transient current waveforms at the instant the inverter is disconnected, and introduces a dynamic time warping algorithm to extract the geometric encirclement area and path tortuosity features that deviate from the ideal state. This solves the problem that existing technologies only monitor macroscopic temperature extremes and cannot utilize electrical transient windows. This invention sensitively captures the weak contact resistance hysteresis and electrical waveform distortion caused by the initiation of early microcracks inside interconnect solder joints, and achieves adaptive early warning of faults before the circuit board is completely short-circuited. This effectively avoids the technical defects of blindly injecting large currents, which can lead to local instantaneous thermal collapse and burnout, thus destroying the physical cross-section of subsequent microscopic imaging for investigation.

[0014] 2. This invention collects surface temperature decay curve data during the power-off air-cooling cooling phase and executes a multi-exponential stripping algorithm to sequentially separate low-frequency, mid-frequency, and high-frequency time constants at the end, middle, and beginning of the time axis, and then strips the corresponding residual data layer by layer. This solves the technical problem that traditional methods cannot determine the specific structural depth of anomalies. Because this application constructs the surface temperature decay curve as a transient heat transfer model with triple exponential superposition, it can accurately map the time constants of different frequency bands to the bottom substrate, intermediate solder layer, and surface silicon wafer respectively by taking the negative reciprocal of the slope obtained by linear fitting after calculating the natural logarithm. This achieves the deep physical layer positioning of heat transfer delay anomalies caused by internal microcracks without disassembly.

[0015] 3. This invention solves the problem of false alarms and missed alarms caused by traditional detection methods that use fixed thresholds by calculating the relative degradation rate of the time constants of each physical layer at each depth as the offset value and constructing a dynamically adjusted preset fault triggering condition by combining the maximum thermal hysteresis coefficient extracted from the ratio of the three time constants. This method adaptively correlates the degree of electrical waveform distortion with the thermal degradation state across domains. It can not only eliminate the influence of parameter fluctuations in the early stage of the test through adaptive anchoring of the initial reference period, but also directly compare the magnitude of the relative degradation rates of the three layers after generating the fault identifier, and output the layer corresponding to the maximum offset as the structural position information. Thus, it realizes the collaborative diagnosis of the electrical fault occurrence state and the depth of physical defects under complex thermoelectric cycle excitation. Attached Figure Description

[0016] Figure 1 This is a schematic flowchart of a circuit board electrical fault detection method based on thermoelectric cycle excitation provided by an embodiment of the present invention; Figure 2 This is a schematic diagram of the alternating thermoelectric cycle excitation control process provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the execution flow of the multi-index stripping algorithm provided in an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Please see Figure 1 This invention provides a method for detecting electrical faults in circuit boards based on thermoelectric cycle excitation, the technical solution of which is as follows: A method for detecting electrical faults in a circuit board based on thermoelectric cycling excitation, comprising: The circuit board is subjected to alternating thermoelectric cycle excitation using a test all-in-one machine. Transient current waveform data at the moment the inverter is disconnected is collected in each cycle of the thermoelectric cycle excitation, and surface temperature decay curve data during the continuous cooling phase of the cooling fan is collected simultaneously. The transient current waveform data is input into the dynamic time warping algorithm model to calculate the shortest time warping path distance parameter between the transient current waveform data extracted in the current cycle and the preset non-destructive health reference waveform; the multi-exponential stripping algorithm is executed on the surface temperature decay curve data to sequentially separate and output the high-frequency time constant, mid-frequency time constant and low-frequency time constant representing the thermal response characteristics of different physical layers of the circuit board. When the shortest time warp path distance parameter meets the preset fault triggering condition, an electrical fault identifier is generated for the circuit board under test. After generating the electrical fault identifier, the offset values ​​of the high-frequency time constant, the medium-frequency time constant and the low-frequency time constant relative to the initial reference period are extracted and compared. The depth physical level corresponding to the maximum offset value is output as the structural location information of the electrical fault.

[0019] Example 1: The circuit board is subjected to alternating thermoelectric cycle excitation using a test all-in-one machine. Transient current waveform data at the moment the inverter is disconnected is collected in each cycle of the thermoelectric cycle excitation, and surface temperature decay curve data during the continuous cooling phase of the cooling fan is collected simultaneously. See Figure 2The alternating thermoelectric cycle excitation is a periodic excitation sequence consisting of an alternating power-on self-heating stage and a power-off air-cooling stage. In the power-on self-heating stage, the inverter injects working current into the circuit board under test to heat up its internal physical layers to the upper limit of the preset temperature. In the power-off air-cooling stage, the inverter is controlled to disconnect to cut off the working current input, and the cooling fan is simultaneously started to force heat dissipation of the circuit board under test until its surface temperature drops to the lower limit of the preset temperature.

[0020] Specifically, the alternating thermoelectric cycle excitation is a periodic excitation sequence consisting of alternating power-on self-heating stage and power-off air-cooling cooling stage; before executing the alternating thermoelectric cycle excitation, the main control chip of the test unit first performs the initialization calculation of the test parameters.

[0021] The initial calculation of the test parameters includes: obtaining the rated continuous operating current value in the design parameters of the circuit board under test, and using it as the injection calibration value for the power-on self-heating stage; obtaining the glass transition temperature value of the substrate of the circuit board under test, and calculating 80% of the glass transition temperature value as the preset upper temperature limit in order to avoid irreversible plastic deformation of the board during the test and to retain a reasonable thermal safety margin; measuring the indoor ambient temperature of the current test environment, and using the indoor ambient temperature plus 5 degrees Celsius as the preset lower temperature limit.

[0022] The initialization calculation of the test parameters also includes: obtaining the nominal turn-off time parameter of the switching devices inside the inverter; in order to fully capture the rich high-frequency transient distortion information contained in the turn-off moment, the value of ten times the reciprocal of the nominal turn-off time parameter is calculated as the preset first sampling frequency according to the Nyquist-Shannon sampling theorem and the high-frequency component distribution characteristics of the transient waveform; obtaining the theoretical thermal conduction time constant of the smallest physical layer inside the circuit board under test, the theoretical thermal conduction time constant is obtained by looking up a table or pre-calculating based on the density, specific heat capacity, thickness and thermal conductivity parameters of the material of the physical layer; in order to ensure that the fastest thermal decay process can be effectively identified without spectral aliasing, the value of twice the reciprocal of the theoretical thermal conduction time constant is calculated as the preset second sampling frequency; at the same time, reading the maximum background noise amplitude measured by the high-speed current sampling module in the resting state without power supply, and storing the maximum background noise amplitude as the zero-point judgment threshold.

[0023] During the power-on self-heating stage, the main control chip generates a corresponding pulse width modulation control signal according to the injection calibration value and sends it to the gate drive circuit of the inverter to control the switching devices inside the inverter to turn on and continuously inject a working current equal to the injection calibration value into the circuit board under test.

[0024] During the injection of working current, the temperature sensor arranged on the surface of the circuit board under test is used to collect the current characterization temperature at the highest point in real time. The main control chip continuously compares the current characterization temperature with the preset upper limit of temperature according to the set main cycle. When it is determined that the current characterization temperature is greater than or equal to the preset upper limit of temperature, a disconnection trigger signal is generated and the power-off air cooling stage is entered.

[0025] During the power outage and air cooling phase, the main control chip immediately sends a low-level shutdown signal to the inverter's gate drive circuit based on the disconnection trigger signal, forcing the switching devices inside the inverter to disconnect and cut off the operating current.

[0026] Within the same hardware clock cycle when a low-level shutdown signal is sent to the gate drive circuit, the main control chip synchronously performs two operations: the first operation is to output a start-up level signal to the motor drive module of the cooling fan to control the cooling fan to run at its maximum rated speed to perform forced convection heat dissipation on the surface of the circuit board under test; the second operation is to send a synchronous sampling trigger level to the high-speed current sampling module.

[0027] Upon receiving the synchronous sampling trigger level, the high-speed current sampling module immediately begins to collect the current amplitude flowing through the power supply circuit of the circuit board under test at a preset first sampling frequency. The main control chip extracts the collected current amplitude in real time and compares it with the zero-point determination threshold one by one. When the current amplitude of five consecutive sampling cycles is less than or equal to the zero-point determination threshold, the high-speed current sampling module stops working and arranges all the current amplitudes collected during this period according to the corresponding timestamps to generate the transient decay current waveform data of the current cycle.

[0028] During the period when the cooling fan continuously performs forced convection cooling, the main control chip controls the temperature sensor to periodically collect the real-time temperature value of the surface of the circuit board under test at the preset second sampling frequency; the main control chip compares the real-time temperature value collected each time with the preset lower limit of temperature.

[0029] When the collected real-time temperature value drops to less than or equal to the preset lower limit, the main control chip outputs a stop signal to the motor drive module of the cooling fan to turn off the cooling fan. At the same time, the temperature sensor stops collecting data, and all real-time temperature values ​​recorded during this air-cooling period are sequentially spliced ​​according to the corresponding timestamps to generate the surface temperature decay curve data for the current cycle. This completes one cycle of alternating thermoelectric cycle excitation and data acquisition process.

[0030] To ensure that the acquired transient current waveform data accurately reflects the contact resistance hysteresis caused by microcracks in the interconnect solder joints, the integrated test unit and test bench in this embodiment employ a low-parasitic-inductance wiring harness and fixture design. Simultaneously, by strictly synchronizing the low-level shutdown signal and sampling trigger level sent by the main control chip within the same hardware clock cycle, interference from inverter switching jitter and external wiring parasitic parameters is effectively eliminated. This ensures that the current decay waveform distortion within this specific short window is primarily dominated by the electrical degradation state of the physical interconnect layers within the circuit board under test.

[0031] The transient current waveform data is input into the dynamic time warping algorithm model to calculate the shortest time warping path distance parameter between the transient current waveform data extracted in the current cycle and the preset non-destructive health reference waveform. The dynamic time warping algorithm model generates a two-dimensional feature distance matrix data that reflects the misalignment of local peak and valley morphology of the waveform based on the transient current waveform data and the preset non-destructive health reference waveform. Based on the two-dimensional feature distance matrix data, global cumulative deformation trajectory data characterizing the nonlinear scaling evolution process of the transient waveform on the time axis is generated; based on the global cumulative deformation trajectory data, the shortest time warp path distance parameter representing the overall distortion degree of the waveform is generated.

[0032] The process of obtaining the shortest time regularized path distance parameter is to extract the actual regularized connection path formed by the global cumulative deformation trajectory data in the two-dimensional time matrix; and to construct an ideal diagonal straight line connecting the start and end points of the two-dimensional time matrix. The ideal diagonal straight line represents the reference state in which the measured transient waveform and the preset non-destructive health reference waveform are in absolute synchronous alignment on the time axis. Calculate the geometric enclosed area formed by the deviation of the actual regularized connecting path from the ideal diagonal line, and extract the number of inflection points on the actual regularized connecting path where direction deflection occurs to generate path tortuosity features; construct a two-dimensional distance feature vector using the geometric enclosed area and the path tortuosity features, and output the shortest time regularized path distance parameter by calculating the magnitude of the two-dimensional distance feature vector; Specifically, the method for obtaining the preset non-destructive health benchmark waveform is as follows: A circuit board of the same batch and model as the circuit board under test, and which has been determined to be non-destructive and healthy by physical testing, is selected as a reference board. Under the same initial ambient temperature as the current test, the reference board is subjected to the exact same alternating thermoelectric cycle excitation using a testing all-in-one machine. The transient current amplitude time series of the reference board at the instant the inverter is disconnected is extracted and stored as a string of length [length missing]. The preset non-destructive health baseline waveform vector; Extract the length collected in the current period as The transient current waveform data is aligned point-by-point with the preset non-destructive health reference waveform; the first transient current waveform data is calculated. amplitude at each sampling point The first one in the preset non-destructive health reference waveform Amplitude of each sampling point The Euclidean distance between them is calculated using the following formula: ; By traversal and Calculate the Euclidean distance between all point pairs to generate a magnitude reflecting the local peak and trough morphological misalignment of the waveform. Two-dimensional feature distance matrix data.

[0033] A dynamic programming matrix of the same dimension as the two-dimensional feature distance matrix data is constructed, and spatial optimization is performed using the state transition equation; the state transition equation is: ; in, To evolve to the current coordinate point The minimum cumulative distance is calculated by iteratively calculating each element in the entire dynamic programming matrix row by row and column by column. The calculation results of each element in the matrix are then used to generate global cumulative deformation trajectory data that characterizes the nonlinear scaling evolution process of the transient waveform on the time axis.

[0034] In the dynamic programming matrix corresponding to the global cumulative deformation trajectory data, from the endpoint coordinates Initially, following the principle of searching backwards for the minimum cumulative distance among the three surrounding neighboring nodes, we gradually backtrack to connect to the starting coordinates. Extract the set of all discrete coordinate points traversed during the backtracking process, which serves as the actual regularized connection path formed in the two-dimensional time matrix.

[0035] Using the two-point form of the straight line equation, construct a connection between the starting points. and the finish line The linear analytical expression: ; The ideal diagonal line represents the reference state in which the measured transient waveform and the preset non-destructive health reference waveform are in absolute synchronization and alignment on the time axis.

[0036] Iterate through each discrete coordinate point in the set of actual regularized connecting paths. Calculate the perpendicular geometric distance from the discrete coordinate point to the ideal diagonal line; sum all the perpendicular geometric distances from the point to the line, and in the discrete matrix space, define the sum of these distances as the geometrically enclosed area; wherein, when microcracks initiate inside the interconnect solder joint of the circuit board under complex thermal stress, its local contact resistance The crack will increase in size as it propagates. During the extremely short transient window when the inverter is disconnected during the power outage and air-cooling phase, the system's equivalent discharge time constant, including this contact resistance, is [not specified]. The changes, among which To test the inherent equivalent resistance of the circuit, The equivalent parasitic capacitance of the system; this time delay effect is macroscopically manifested as the overall translation and broadening of the transient current discharge waveform on the time axis; after inputting the distorted waveform data into the dynamic time warping algorithm model, its actual warping connection path will inevitably deviate from the ideal diagonal straight line representing absolute synchronization alignment, directly leading to an increase in the geometric enclosed area. Therefore, the geometric enclosed area can theoretically quantitatively characterize the degree of macroscopic electrical discharge delay caused by the increase in contact resistance.

[0037] Each time, three consecutive coordinate points are extracted from the actual regularized connecting path in the order of connection. The slope of the first direction between the first two coordinate points and the slope of the second direction between the last two coordinate points are calculated. When the slope of the first direction is not equal to the slope of the second direction, the intermediate coordinate point is determined to be an inflection point where the direction deflection occurs. After traversing the entire path, the total number of determined inflection points is counted, and the total number of inflection points is used as the path tortuosity feature. Among them, the unevenness of the microcrack interface can easily cause a weak contact interface micro-arc or nonlinear transient resistance change at the moment when the inverter cuts off the large current, resulting in high-frequency electrical distortion and jitter signals superimposed on the transient current waveform. This high-frequency micro jitter requires frequent nonlinear scaling adjustments of the time axis when searching for the alignment of local peaks and troughs, which leads to a sharp increase in the number of inflection points where the direction deflection occurs on the actual regularized connecting path, that is, an increase in path tortuosity. Therefore, path tortuosity can sensitively map the micro-nonlinear electrical distortion caused by the instability of the crack interface.

[0038] To eliminate the influence of different units on distance calculation, the dimension of the two-dimensional feature distance matrix is ​​extracted. and Calculate the actual area of ​​the matrix (i.e. and The product of ( ) and the area of ​​the reference square (i.e. and The square of the maximum value in the middle is used as an equalization coefficient to multiply the path tortuosity feature for scaling. The geometrically enclosed area is used as the abscissa component, and the amplified path tortuosity feature is used as the ordinate component to construct a two-dimensional distance feature vector. The squares of the abscissa component and the squares of the ordinate component are added together, and the square root of the sum is taken. The resulting dimensionless scalar value is output as the shortest time warped path distance parameter representing the overall distortion of the waveform. The shortest time warped path distance parameter does not refer to the cumulative cost of dynamic programming in the traditional sense, but rather to a comprehensive transient distortion evaluation parameter based on dynamic time warped path morphology features (i.e., combining the geometrically enclosed area and path tortuosity). By introducing a dynamic time warping algorithm to perform in-depth analysis of the transient current waveform at the moment of inverter disconnection, the nonlinear time shift interference caused by thermoelectric evolution in conventional comparison is effectively overcome. At the same time, by calculating the geometric enclosing area of ​​the actual warped path deviating from the ideal state and the path tortuosity characteristics reflecting high-frequency fluctuations, the macroscopic trend distortion of the transient waveform and the microscopic transient jitter are integrated. The dimensionless distance parameter output can sensitively and stably quantify the early degradation state inside the circuit board before the macroscopic temperature changes significantly, providing reliable early warning data support for timely cutting off large currents and avoiding local thermal collapse.

[0039] The surface temperature decay curve data is subjected to a multi-exponential stripping algorithm to sequentially separate and output the high-frequency time constant, mid-frequency time constant and low-frequency time constant, which represent the thermal response characteristics of different physical layers of the circuit board at different depths. The multi-exponential stripping algorithm constructs a transient heat transfer model by superimposing three exponentials from the surface temperature decay curve data. The time axis segment of the surface temperature decay curve data is fitted to separate the low-frequency time constant representing the heat transfer characteristics of the bottom substrate, and the corresponding low-frequency component is removed to obtain primary residual data; the time axis segment of the primary residual data is fitted to separate the mid-frequency time constant representing the heat transfer characteristics of the intermediate layer solder, and the corresponding mid-frequency component is removed to obtain secondary residual data; the time axis segment of the secondary residual data is fitted to separate the high-frequency time constant representing the thermal characteristics of the surface silicon wafer; the high-frequency time constant, mid-frequency time constant, and low-frequency time constant are respectively mapped to the surface silicon wafer, intermediate layer solder, and bottom substrate.

[0040] The low-frequency time constant is the negative reciprocal of the slope obtained by linear fitting after taking the natural logarithm of the last segment of the time axis of the surface temperature decay curve data; the mid-frequency time constant is the negative reciprocal of the slope obtained by linear fitting after taking the natural logarithm of the middle segment of the time axis of the first residual data; the high-frequency time constant is the negative reciprocal of the slope obtained by linear fitting after taking the natural logarithm of the first segment of the time axis of the second residual data. Specifically, the process of obtaining the upper and lower limits of the alternating thermoelectric cycle excitation and the initial reference period is as follows: A brand-new circuit board that has been physically tested and determined to be undamaged and healthy is connected to the integrated testing machine, and thermoelectric cycling is performed until it enters the steady-state stage of thermoelectric equilibrium. The reference cycle of the steady-state stage is established as the initial reference period. During the power-on self-heating stage, the surface temperature is continuously differentiated in real time. When the surface temperature rise slope over time is detected to be close to the thermal saturation critical point at multiple consecutive sampling points, the temperature peak value at this time is extracted as the upper limit of the temperature for subsequent cycles. During the power-off air cooling stage, when the surface temperature drop slope is detected to be close to zero and thermal equilibrium is formed with the ambient room temperature, the temperature valley value at this time is extracted as the lower limit of the temperature. The temperature data collected during the power-off cooling stage of the initial reference period is subtracted from the lower limit of the temperature data and stored as the surface temperature decay curve data of the initial reference period.

[0041] See Figure 3 The process of constructing the surface temperature decay curve data into a three-exponential superposition transient heat transfer model is as follows: Based on the physical characteristics of the anisotropic thermal resistance and thermal capacity network of the surface silicon wafer, intermediate solder layer, and bottom substrate inside the circuit board, the mathematical relationship of the surface temperature decay curve data evolving with time is constructed into a three-term exponential decay analytical expression: ; in, For the current discrete time point The corresponding surface decay temperature value; , , These represent the initial heat transfer amplitude coefficients corresponding to the surface silicon wafer, the intermediate solder layer, and the bottom substrate, respectively. , , These represent the high-frequency time constant, the mid-frequency time constant, and the low-frequency time constant, respectively.

[0042] The process of separating the low-frequency time constant representing the heat transfer characteristics of the underlying substrate is as follows: The natural logarithm of each temperature amplitude in the surface temperature decay curve data is calculated to generate a global logarithmic decay sequence; starting from the last coordinate of the time axis, a dynamic sliding window is used to expand backwards towards the beginning, and linear regression is performed on the data points within the window to calculate the sum of squared residuals under different window lengths; the largest continuous data segment corresponding to the point where the sum of squared residuals reaches its minimum extreme value is extracted, and this segment is objectively truncated as the last segment of the time axis; the slope of the fitted straight line obtained from the linear regression of this last segment of the time axis is extracted. With intercept By calculating the slope of the fitted straight line The negative reciprocal of the output is the low-frequency time constant representing the heat transfer characteristics of the bottom substrate; and the intercept... Perform natural exponent calculations (i.e.) The output is the low-frequency amplitude coefficient of the underlying layer. ; The process of obtaining residual data by stripping the corresponding low-frequency components and separating the mid-frequency time constant is as follows: using the obtained low-frequency time constant... With low frequency amplitude coefficient Constructing the theoretical attenuation trajectory equation for low frequency By iterating through all discrete sampling moments at the beginning and middle of the time axis, the calculated low-frequency theoretical attenuation value is subtracted point by point from the original surface attenuation temperature value. The resulting set of subtracted values ​​is output as the primary residual data, excluding thermal interference from the underlying substrate. The natural logarithm of the primary residual data is calculated, and the sliding window optimization rule of minimizing the fitting residual is used to find the optimal linearly decreasing interval in the middle, which is then truncated as the middle segment of the time axis. The slope of the straight line obtained by linear fitting in the middle segment of the time axis is extracted. With intercept By calculating the slope of the fitted straight line The negative reciprocal output is the mid-frequency time constant representing the heat transfer characteristics of the intermediate layer solder. and the intercept The natural exponent calculation outputs the intermediate frequency amplitude coefficients of the intermediate layer. ; The process of obtaining the secondary residual data by stripping the corresponding intermediate frequency component and separating the high frequency time constant is as follows: using the obtained intermediate frequency time constant... and mid-frequency amplitude coefficient Construct the theoretical attenuation trajectory equation for the intermediate frequency. Iterate through all discrete sampling moments in the earliest segment of the time axis, subtracting the calculated mid-frequency attenuation value from the primary residual data point by point. Output the resulting set of subtracted values ​​as the secondary residual data, excluding the dual thermal interference from the bottom substrate and intermediate layer solder. Calculate the natural logarithm of the secondary residual data, and extract the linear region of rapid attenuation in its initial stage as the early segment of the time axis. Extract the slope of the straight line obtained by linear fitting of this early segment of the time axis. By calculating the slope of the line The negative reciprocal output is the high-frequency time constant representing the thermal characteristics of the surface silicon wafer. ; The process of mapping the high-frequency, mid-frequency, and low-frequency time constants to the surface silicon wafer, intermediate solder layer, and bottom substrate, respectively, involves obtaining the high-frequency, mid-frequency, and low-frequency time constants separated by a multi-exponential peeling algorithm. The specific values ​​of these three time constants are then compared and sorted in ascending order. According to the principles of transient heat transfer, the time constant characterizes the thermal inertia and thermal response hysteresis of a specific physical structure. A smaller value indicates a faster thermal response, while a larger value indicates stronger thermal inertia and slower temperature decay.

[0043] Because the vertical heat conduction medium of a circuit board is continuous, its thermal time constant spectrum theoretically exhibits a continuous distribution. To achieve hierarchical diagnosis, the three-exponential superimposed transient heat transfer model constructed in this application adopts the engineering principle of order reduction using lumped parameter equivalent thermal networks. In the vertical heat conduction path of the circuit board under test, the surface silicon wafer with extremely small heat capacity, the intermediate solder layer with abrupt material changes, and the bottom substrate with large thermal inertia exhibit step-like discontinuous differences in physical properties such as material density, specific heat capacity, and thermal conductivity. This discontinuous difference makes the continuous heat transfer path equivalent to three absolutely dominant lumped thermal resistance-capacitance nodes. The high-frequency, mid-frequency, and low-frequency discrete time constants extracted by the multi-exponential stripping algorithm are essentially the characteristic response peaks representing these three dominant lumped nodes separated and locked from the complex continuous thermal spectrum. Through this order reduction discretization equivalent mechanism, it is ensured that the extracted discrete characteristic constants can establish an accurate and unique one-to-one mapping relationship with the actual three-dimensional solid core packaging structure. Based on the top-down three-dimensional solid packaging structure of the circuit board under test, the material physical properties and spatial positions of each layer along the vertical heat conduction path are extracted. The surface silicon wafer is determined to be located at the center of the direct heat source, with the smallest physical thickness and thermal volume in the overall structure. The bottom substrate is determined to be the end of the heat conduction path and the main large-area heat dissipation carrier, with the largest thermal volume. The intermediate solder layer is determined to be the connecting layer, located at the vertical heat conduction interface between the surface silicon wafer and the bottom substrate, with its thermal volume distribution between the self-heating source and the final heat dissipation end.

[0044] Perform a spatial mapping matching operation between the numerical characteristics of the time constant and the three-dimensional deep physical hierarchy: extract the time constant with the smallest value after comparison and sorting, which is the high-frequency time constant. Since the surface silicon wafer is located at the direct heat source and has the smallest heat volume, it has an extremely fast external thermal response and exhibits the fastest transient heat dissipation rate. Therefore, the high-frequency time constant is directly mapped to the surface silicon wafer.

[0045] The intermediate frequency time constant is extracted based on the median value after comparison and sorting. Since the thermal resistance and heat transfer hysteresis of the intermediate layer solder are between the fastest-responding surface layer and the slowest-responding bottom layer, exhibiting a moderate step temperature decay rate, the intermediate frequency time constant is mapped to the intermediate layer solder.

[0046] The time constant with the largest value after comparison and sorting is extracted, which is the low-frequency time constant. Since the bottom substrate has the largest volume and thermal capacity, it has extremely strong thermal inertia, resulting in the process of absorbing and dissipating heat exhibiting the latest and slowest smooth decay characteristics. The low-frequency time constant is then mapped to the bottom substrate.

[0047] Mapping the three time constants to the surface silicon wafer, intermediate solder layer, and bottom substrate is an equivalent thermal response hierarchy mapping based on a known three-dimensional solid package thermal resistance and thermal capacitance network model of the circuit board under test (such as power device components). In practical applications, this mapping relationship can be calibrated using a pre-established calibration table combined with physical inspection methods such as microscopy, X-ray, or infrared thermography. By decoupling the complex nonlinear heat conduction process through a dynamic sliding window and a multi-exponential successive stripping algorithm, the subjective bias caused by manually selecting data intervals in traditional fitting is avoided. At the same time, the calculated multidimensional time constants are mapped in depth space to the transient thermal properties of the three-dimensional solid packaging structure (surface silicon wafer, middle solder layer, and bottom substrate) according to their numerical values. This transforms the mathematical solution into a specific physical level correspondence, effectively distinguishing the thermal response of different structural layers. This enables the layered localization of hidden damage such as internal solder voids or aging. When the shortest time warp path distance parameter meets the preset fault triggering condition, an electrical fault identifier is generated for the circuit board under test. After generating the electrical fault identifier, the offset values ​​of the high-frequency time constant, the medium-frequency time constant and the low-frequency time constant relative to the initial reference period are extracted and compared. The depth physical level corresponding to the maximum offset value is output as the structural location information of the electrical fault.

[0048] The preset fault triggering condition is that the shortest time warp path distance parameter of the current period is greater than the product of the shortest time warp path distance parameter of the initial reference period and the maximum thermal hysteresis coefficient; wherein, the maximum thermal hysteresis coefficient is calculated by calculating the ratio of the high-frequency time constant, mid-frequency time constant and low-frequency time constant of the current period to the high-frequency time constant, mid-frequency time constant and low-frequency time constant corresponding to the initial reference period, and extracting the maximum value of the three ratios as the maximum thermal hysteresis coefficient.

[0049] Specifically, the process of obtaining the relevant parameters of the initial reference period is as follows: the system pre-sets and stores a preset non-destructive health reference waveform based on the factory standard circuit board; the circuit board under test, which is determined to be non-destructive and healthy by physical testing, is connected to the integrated testing machine, and a thermoelectric cycle of self-heating upon power-on and air cooling upon power-off is started, and the initial reference period is established after the thermoelectric steady state is determined to be entered; within the initial reference period, transient current waveform data at the moment the inverter is disconnected and surface temperature decay curve data during the continuous cooling phase of the cooling fan are simultaneously collected; the transient current waveform data of the initial reference period and the preset non-destructive health reference waveform stored in the system are time-warped, and the non-zero distance value obtained is stored as the shortest time-warped path distance parameter of the initial reference period; at the same time, a multi-exponential stripping algorithm is performed on the surface temperature decay curve data to extract and store the high-frequency time constant, mid-frequency time constant and low-frequency time constant corresponding to the initial reference period.

[0050] The process of calculating the maximum thermal hysteresis coefficient is as follows: After the circuit board under test undergoes multiple alternating thermoelectric cycles, the high-frequency time constant, mid-frequency time constant, and low-frequency time constant calculated in real time for the current cycle are extracted; the high-frequency time constant for the current cycle is divided by the high-frequency time constant corresponding to the initial reference cycle to output the high-frequency hysteresis ratio; the mid-frequency time constant for the current cycle is divided by the mid-frequency time constant corresponding to the initial reference cycle to output the mid-frequency hysteresis ratio; the low-frequency time constant for the current cycle is divided by the low-frequency time constant corresponding to the initial reference cycle to output the low-frequency hysteresis ratio; the three ratios of the high-frequency hysteresis ratio, the mid-frequency hysteresis ratio, and the low-frequency hysteresis ratio are compared, and the maximum value among these three ratios is extracted, assigned, and output as the maximum thermal hysteresis coefficient.

[0051] The process of determining the preset fault triggering condition and triggering subsequent procedures is as follows: Extract the shortest time warp path distance parameter calculated in real-time based on the dynamic time warp algorithm model for the current period; call the multiplication operation logic to multiply the extracted maximum thermal hysteresis coefficient with the stored shortest time warp path distance parameter of the initial reference period to calculate the dynamic threshold; call the comparison and judgment logic to determine whether the shortest time warp path distance parameter of the current period is strictly greater than the dynamic threshold; when the judgment result is true, that is, the shortest time warp path distance parameter of the current period is greater than the product of the shortest time warp path distance parameter of the initial reference period and the maximum thermal hysteresis coefficient, the preset fault triggering condition is determined to be met. The essence of the dynamic threshold mechanism is to utilize the relative deviation of thermal hysteresis to amplify the tolerance envelope of the electrical waveform, thereby effectively filtering out the systematic electrical parameter drift caused by overall heat accumulation in the later stages of the test. An electrical fault is triggered only when the transient distortion of the electrical waveform (i.e., the current distance parameter) caused by a local microcrack is extremely severe, even exceeding the adaptive envelope threshold raised by the current severe thermal degradation state.

[0052] By extracting the largest term among the ratios of high, medium, and low frequency time constant changes, the system can objectively capture the most significant local thermal degradation characteristics at each physical level of the circuit board. At the same time, by using this coefficient to multiply and scale the reference distance of the electrical waveform, a judgment mechanism that mutually restricts electrothermal characteristics is established, so that the fault judgment threshold is no longer a rigid fixed constant, but can be reasonably and dynamically adjusted according to the initial individual differences of the tested component and the actual physical aging process.

[0053] The process of obtaining the offset value is as follows: calculate the high-frequency time constant, mid-frequency time constant, and low-frequency time constant of the current period respectively, and divide the absolute value of the difference between the high-frequency time constant, mid-frequency time constant, and low-frequency time constant corresponding to the initial reference period by the high-frequency time constant, mid-frequency time constant, and low-frequency time constant of the corresponding depth physical layer in the initial reference period to obtain the relative degradation rate corresponding to each depth physical layer; use the relative degradation rate corresponding to each depth physical layer as the offset value of the corresponding depth physical layer. The initial reference period is calculated by sequentially calculating the sum of the high-frequency time constant, the mid-frequency time constant, and the low-frequency time constant for each consecutive cycle under the alternating thermoelectric cycle excitation; sequentially calculating the first-order absolute difference of the sum of the three time constants for two consecutive adjacent cycles to construct a sequence of absolute difference values ​​arranged according to the cycle number; and extracting the cycle corresponding to the minimum inflection point in the sequence of absolute difference values ​​as the initial reference period. Specifically, the process of establishing the initial reference period involves, after the circuit board is connected to the integrated test machine and the alternating thermoelectric cycle excitation is started, using the calculation unit to sequentially extract the high-frequency time constant, mid-frequency time constant, and low-frequency time constant separated by the multi-exponential stripping algorithm in each consecutive period starting from the first period; for any given period... For each cycle, the high-frequency time constant, the mid-frequency time constant, and the low-frequency time constant within the same cycle are summed to obtain the sum of the three time constants for the current cycle. ; Invoke the caching mechanism to calculate two consecutive adjacent cycles (the first cycle). Period and the The absolute value of the first-order difference is obtained by taking the absolute value of the difference between the sums of the three time constants corresponding to the period. The calculation formula is as follows: ; According to the order in which the test cycles occurred, the results of each calculation were... Arranged sequentially, a sequence of absolute difference values ​​is constructed according to the period sequence number. This sequence is then iterated and optimized to filter out high-amplitude fluctuations caused by initial power-on instability at the beginning of the sequence. The first local minimum point in the sequence where the value changes from a continuously decreasing trend to an increasing trend is located and defined as the minimum inflection point. This minimum inflection point indicates that the circuit board has officially entered a steady-state stage of thermoelectric equilibrium. The first physical test cycle immediately following this minimum inflection point on the time axis is extracted and established as the initial reference cycle. The three time constants corresponding to this cycle are then solidified and stored as high-frequency time constants corresponding to the initial reference cycle. Intermediate frequency time constant and low-frequency time constant ; The process of obtaining the offset value is as follows: when the shortest time regularization path distance parameter meets the preset fault triggering condition, after the system generates the electrical fault identifier, it extracts the high-frequency time constant, medium-frequency time constant, and low-frequency time constant of the current period that triggered the fault, and marks them as the high-frequency time constant corresponding to the current period. Intermediate frequency time constant and low-frequency time constant ; The subtraction and absolute value operation logic is invoked to calculate the absolute value of the difference between the three time constants of the current period and the three time constants of the initial reference period, respectively: that is, to calculate... As the absolute value of the difference corresponding to the surface silicon wafer, calculate As the absolute value of the difference corresponding to the intermediate layer solder, calculate As the absolute value of the difference corresponding to the underlying substrate; the division operation logic is invoked to divide the absolute value of the difference corresponding to each physical depth by the time constant of the corresponding physical depth in the initial reference period, so as to calculate the relative degradation rate corresponding to each physical depth. : Relative degradation rate of surface silicon wafers The calculation is as follows: ; Relative degradation rate of intermediate layer solder The calculation is as follows: ; Relative degradation rate of the underlying substrate The calculation is as follows: ; The relative degradation rate corresponding to the surface silicon wafer is used as the offset value corresponding to the surface silicon wafer; the relative degradation rate corresponding to the intermediate layer solder is used as the offset value corresponding to the intermediate layer solder; and the relative degradation rate corresponding to the bottom substrate is used as the offset value corresponding to the bottom substrate. The offset values ​​of the high-frequency time constant, the mid-frequency time constant, and the low-frequency time constant relative to the initial reference period are extracted and compared. The depth physical level corresponding to the maximum offset value is output as the structural location information of the electrical fault. In this step, considering the characteristic that thermal coupling exists between different physical layers, resulting in a global decay response in the surface temperature curve, the physical location is determined based on the dominant pole separation mechanism in the thermal equivalent RC network. When local damage or microcrack propagation occurs in a specific physical layer of the circuit board (such as inside the intermediate layer solder), the local contact thermal resistance at the defect interface will undergo a drastic change. Due to the order-of-magnitude difference in thermal volume between the surface silicon wafer, the intermediate layer solder, and the bottom substrate, their thermal response frequency bands are naturally isolated. The sudden change in local thermal resistance at this layer will cause the most significant parameter drift at the dominant response pole corresponding to this layer in the global thermal response. Therefore, by calculating the relative degradation rate (i.e., offset) of the stripped high-frequency, mid-frequency, and low-frequency time constants, the maximum offset value can eliminate the global basic thermal drift interference caused by system coupling, and physically map the dominant defect layer with the largest increase in local contact thermal resistance and the most severe physical degradation, thereby achieving single-physical-layer fault location in a strongly coupled system. This invention acquires transient current waveforms at the moment of inverter disconnection and extracts distortion features using a dynamic time warping algorithm. This enables early warning before local thermal collapse burns out the circuit board, effectively protecting the physical cross-section required for subsequent microscopic inspection. Furthermore, addressing the challenge of determining the physical depth of anomalies using existing technologies, this invention acquires surface temperature decay curves during the air-cooling stage and executes a multi-exponential stripping algorithm to separate high-frequency, mid-frequency, and low-frequency time constants that characterize the thermal response at different depths. By comparing the offset of the time constants at each level, the invention can directly pinpoint whether the anomaly is located on the surface silicon wafer, the intermediate solder layer, or the bottom substrate, achieving collaborative diagnosis of electrical fault warning and internal structural damage location.

[0054] Example 2: This embodiment applies a circuit board electrical fault detection method based on thermoelectric cycle excitation to the pre-shipment reliability aging test of the core power amplifier circuit board of a communication base station. In the reliability aging test workshop for 5G base station power amplifier circuit boards, testers assemble the circuit board under test onto a dedicated test stand of the high and low temperature testing machine. After the test starts, the system applies alternating thermoelectric cycle excitation, and the inverter continuously injects a large operating current into the power amplifier circuit board according to the set injection calibration value to make it self-heating; when the surface temperature sensor detects that the temperature has reached the preset upper limit, the power-off air cooling stage is triggered. During this stage, the system collects transient current waveform data caused by the hysteresis of internal parasitic inductance and contact resistance at high frequency at the moment the inverter is disconnected, and simultaneously records the continuous decay curve data of the surface temperature during the full-speed cooling of the cooling fan; The main control computing unit inputs the transient current waveform data collected in the current cycle into the dynamic time warping algorithm model, compares it point-to-point with the non-destructive health reference waveform measured in advance on the power boards of the same batch of healthy base stations, finds the minimum cumulative distance by constructing a state transition equation, and generates the actual warping connection path; extracts the geometric enclosed area of ​​the path deviating from the ideal absolute synchronization diagonal line, and calculates a dimensionless scalar as the shortest time warping path distance parameter in the current cycle by combining the number of directional deflection inflection points on the path (i.e., path tortuosity characteristics); Meanwhile, a multi-exponential stripping algorithm is applied to the acquired surface temperature decay curve data, treating it as a three-exponential superimposed transient heat transfer model consisting of the surface silicon wafer, intermediate solder layer, and bottom substrate. A dynamic sliding window is used to preferentially calculate the natural logarithm of the time axis segment of the temperature curve and perform linear fitting, extracting the negative reciprocal of the slope as the low-frequency time constant representing the heat transfer characteristics of the bottom substrate. After stripping the low-frequency components sequentially, the mid-frequency time constant representing the intermediate solder layer is obtained by fitting the middle segment of the time axis of the first residual data. After stripping the mid-frequency components again, the early segment of the time axis of the second residual data is fitted to separate the high-frequency time constant representing the thermal characteristics of the surface power chip. After 100 thermoelectric cycle tests, microcracks may have formed inside the base station power circuit board due to inconsistent thermal expansion coefficients of the materials. Real-time monitoring revealed that the shortest time-normalized path distance parameter of the current cycle is significantly greater than the product of the reference distance parameter of the initial reference cycle and the currently extracted maximum thermal hysteresis coefficient (i.e., the largest term among the ratios of the current three-layer time constants relative to the initial cycle). Once this preset fault trigger condition is met, it is determined that the circuit board has suffered early damage affecting electrical performance. An electrical fault flag is immediately generated, and subsequent high-current injection tests are automatically cut off before localized instantaneous thermal collapse and burnout. After successfully triggering the electrical fault flag, the system automatically enters the structural damage location diagnosis process. The calculation unit extracts the high-frequency, mid-frequency, and low-frequency time constants within the current cycle of the triggered fault, calculates the absolute value of the difference between these values ​​and the corresponding constant of the initial reference cycle, and divides them by the corresponding constant of the initial reference cycle to obtain the relative degradation rate (i.e., offset value) of the three layers: the surface silicon wafer, the intermediate solder layer, and the bottom substrate. The three offset values ​​are compared. If the value representing the relative degradation rate of the intermediate solder layer is found to be the largest, the intermediate solder layer is directly output as the structural location information of this electrical fault, providing physical depth guidance for subsequent microscopic sectioning inspection by quality control engineers.

[0055] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for detecting electrical faults in a circuit board based on thermoelectric cycle excitation, characterized in that, include: The circuit board is subjected to alternating thermoelectric cycle excitation using a test all-in-one machine. Transient current waveform data at the moment the inverter is disconnected is collected in each cycle of the thermoelectric cycle excitation, and surface temperature decay curve data during the continuous cooling phase of the cooling fan is collected simultaneously. The transient current waveform data is input into the dynamic time warping algorithm model to calculate the shortest time warping path distance parameter between the transient current waveform data extracted in the current cycle and the preset non-destructive health reference waveform. The surface temperature decay curve data is subjected to a multi-exponential stripping algorithm to sequentially separate and output the high-frequency time constant, mid-frequency time constant and low-frequency time constant, which represent the thermal response characteristics of different physical layers of the circuit board at different depths. When the shortest time warp path distance parameter meets the preset fault triggering condition, an electrical fault identifier is generated for the circuit board under test. After generating the electrical fault identifier, the offset values ​​of the high-frequency time constant, the medium-frequency time constant and the low-frequency time constant relative to the initial reference period are extracted and compared. The depth physical level corresponding to the maximum offset value is output as the structural location information of the electrical fault.

2. The circuit board electrical fault detection method based on thermoelectric cycle excitation according to claim 1, characterized in that, The alternating thermoelectric cycle excitation is a periodic excitation sequence consisting of an alternating power-on self-heating stage and a power-off air-cooling stage. In the power-on self-heating stage, the inverter injects working current into the circuit board under test, causing its internal physical layers to heat up to the preset upper temperature limit. In the power-off air-cooling stage, the inverter is controlled to disconnect to cut off the working current input, and the cooling fan is simultaneously started to force heat dissipation of the circuit board under test until its surface temperature drops to the preset lower temperature limit.

3. The circuit board electrical fault detection method based on thermoelectric cycle excitation according to claim 1, characterized in that, The dynamic time warping algorithm model generates a two-dimensional feature distance matrix data that reflects the misalignment of local peak and valley morphology of the waveform based on the transient current waveform data and the preset non-destructive health reference waveform. Based on the two-dimensional feature distance matrix data, global cumulative deformation trajectory data characterizing the nonlinear scaling evolution process of the transient waveform on the time axis is generated; based on the global cumulative deformation trajectory data, the shortest time warp path distance parameter representing the overall distortion degree of the waveform is generated.

4. The circuit board electrical fault detection method based on thermoelectric cycle excitation according to claim 3, characterized in that, The process of obtaining the shortest time regularized path distance parameter is to extract the actual regularized connection path formed by the global cumulative deformation trajectory data in the two-dimensional time matrix; and to construct an ideal diagonal straight line connecting the start and end points of the two-dimensional time matrix. The ideal diagonal straight line represents the reference state in which the measured transient waveform and the preset non-destructive health reference waveform are in absolute synchronous alignment on the time axis. Calculate the geometric area enclosed by the deviation of the actual regular line path from the ideal diagonal line, and extract the number of inflection points on the actual regular line path where the direction deflection occurs to generate path tortuosity features; A two-dimensional distance feature vector is constructed using the geometrically enclosed area and the path tortuosity feature. The magnitude of the two-dimensional distance feature vector is calculated and output as the shortest time regularized path distance parameter.

5. The circuit board electrical fault detection method based on thermoelectric cycle excitation according to claim 1, characterized in that, The multi-exponential stripping algorithm constructs a transient heat transfer model by superimposing three exponentials from the surface temperature decay curve data. The time axis segment of the surface temperature decay curve data is fitted to separate the low-frequency time constant representing the heat transfer characteristics of the bottom substrate, and the corresponding low-frequency component is removed to obtain primary residual data; the time axis segment of the primary residual data is fitted to separate the mid-frequency time constant representing the heat transfer characteristics of the intermediate layer solder, and the corresponding mid-frequency component is removed to obtain secondary residual data; the time axis segment of the secondary residual data is fitted to separate the high-frequency time constant representing the thermal characteristics of the surface silicon wafer; the high-frequency time constant, mid-frequency time constant, and low-frequency time constant are respectively mapped to the surface silicon wafer, intermediate layer solder, and bottom substrate.

6. The circuit board electrical fault detection method based on thermoelectric cycle excitation according to claim 5, characterized in that, The low-frequency time constant is the negative reciprocal of the slope obtained by linear fitting after taking the natural logarithm of the last segment of the time axis of the surface temperature decay curve data; the mid-frequency time constant is the negative reciprocal of the slope obtained by linear fitting after taking the natural logarithm of the middle segment of the time axis of the first residual data; the high-frequency time constant is the negative reciprocal of the slope obtained by linear fitting after taking the natural logarithm of the first segment of the time axis of the second residual data.

7. The circuit board electrical fault detection method based on thermoelectric cycle excitation according to claim 1, characterized in that, The preset fault triggering condition is that the shortest time warp path distance parameter of the current period is greater than the product of the shortest time warp path distance parameter of the initial reference period and the maximum thermal hysteresis coefficient; wherein, the maximum thermal hysteresis coefficient is calculated by calculating the ratio of the high-frequency time constant, mid-frequency time constant and low-frequency time constant of the current period to the high-frequency time constant, mid-frequency time constant and low-frequency time constant corresponding to the initial reference period, and extracting the maximum value of the three ratios as the maximum thermal hysteresis coefficient.

8. The method for detecting electrical faults in a circuit board based on thermoelectric cycle excitation according to claim 1, characterized in that, The process of obtaining the offset value is as follows: calculate the high-frequency time constant, mid-frequency time constant, and low-frequency time constant of the current period respectively, and divide the absolute value of the difference between the high-frequency time constant, mid-frequency time constant, and low-frequency time constant corresponding to the initial reference period by the high-frequency time constant, mid-frequency time constant, and low-frequency time constant of the corresponding depth physical layer in the initial reference period to obtain the relative degradation rate corresponding to each depth physical layer; use the relative degradation rate corresponding to each depth physical layer as the offset value of the corresponding depth physical layer. The initial reference period is calculated by sequentially calculating the sum of the high-frequency time constant, the mid-frequency time constant, and the low-frequency time constant for each consecutive cycle under the alternating thermoelectric cycle excitation; sequentially calculating the first-order absolute difference of the sum of the three time constants corresponding to two consecutive adjacent cycles, constructing a sequence of absolute difference values ​​arranged according to the cycle number; and extracting the cycle corresponding to the minimum inflection point in the sequence of absolute difference values ​​as the initial reference period.

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