A novel highly integrated analog front end circuit for automotive battery management systems

Abstract

The application discloses a novel highly integrated analog front-end circuit for an automobile battery management system. The application integrates a level shifter, a programmable gain amplifier and a low-pass filter into a single switched capacitor architecture, including a high-voltage chopping module, an operational amplifier module, a gain control module, a low-pass filter module, an offset elimination module and a charge buffer module. The high-voltage chopping module realizes a level shifting function, reduces an input high-voltage common-mode voltage to a low-voltage common-mode voltage, the operational amplifier module provides high gain and high bandwidth to realize accurate clamping and rapid establishment, the gain control module sets programmable gain through a capacitor ratio, the low-pass filter module controls a -3dB cutoff frequency through a capacitor ratio to realize anti-aliasing filtering, the offset elimination module eliminates operational amplifier offset through an offset storage principle, and the charge buffer module stabilizes an output voltage and reduces noise bandwidth. The application has the advantages of high integration, simple structure and high precision.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuits, and specifically relates to a novel highly integrated analog front-end circuit for automotive battery management systems. Background Technology

[0002] In existing battery management systems, traditional analog front-end circuits typically employ a cascaded architecture, connecting level shifters, programmable gain amplifiers, and low-pass filters as independent discrete modules in sequence. The level shifter reduces the high common-mode voltage of the battery pack to a range that low-voltage circuits can handle; the programmable gain amplifier adjusts the signal amplitude to match the full-scale range of the analog-to-digital converter; and the low-pass filter implements anti-aliasing filtering. However, this multi-stage cascaded approach has drawbacks: a large number of components, high system complexity, and significant power consumption and chip area consumption, making it unsuitable for application in automotive battery management systems with stringent performance and integration requirements. Summary of the Invention

[0003] To address the above problems, this invention proposes a novel, highly integrated analog front-end circuit for automotive battery management systems.

[0004] The technical solution of this invention is: a novel highly integrated analog front-end circuit for an automotive battery management system, comprising a high-voltage chopper module, an operational amplifier module, a gain control module, a low-pass filter module, an offset cancellation module, and a charge buffer module; the high-voltage chopper module implements a level shifting function, reducing the input high-voltage common-mode voltage to a low-voltage common-mode voltage; the operational amplifier module provides high gain and high bandwidth for precise clamping and rapid setup; the gain control module sets a programmable gain through a capacitor ratio; the -3dB cutoff frequency of the low-pass filter module is controlled by a capacitor ratio for anti-aliasing filtering; the offset cancellation module eliminates operational amplifier offset through offset storage; and the charge buffer module stabilizes the output voltage and reduces noise bandwidth; by integrating the three functions of the level shifter, programmable gain amplifier, and low-pass filter into a single switched-capacitor architecture, system complexity and power consumption are reduced, achieving high-precision measurement of automotive battery voltage.

[0005] Furthermore, the novel highly integrated analog front-end circuit integrates level shifting, programmable gain amplification, and low-pass filtering within a single switched-capacitor architecture. This novel highly integrated analog front-end circuit includes an operational amplifier OPA, high-voltage switches S1-S4, and capacitor C. 1P -C 4P Capacitor C 1N -C 4N Capacitor C5, Switches S5-S 14 Resistance R 1P -R 1N ;

[0006] The positive terminals of switches S1 and S3 are both connected to the input terminal VIP; the positive terminals of switches S2 and S4 are both connected to the input terminal VIN; the negative terminal of switch S3 is connected to the negative terminal of switch S2, and its connection point is also connected to capacitor C. 1P The positive terminal of switch S4 is connected to the negative terminal of switch S1, and the connection point is also connected to capacitor C. 1N The positive terminal connection; the capacitor C 1P The negative terminal and capacitor C 2P The positive terminal is connected, and its connection point is also connected to the positive terminal of switch S7, the positive terminal of switch S5, and the negative input terminal of the operational amplifier; the capacitor C 1N The negative terminal and capacitor C 2N The positive terminal is connected, and its connection point is also connected to the positive terminal of switch S6, the positive terminal of switch S8, and the non-inverting input terminal of the operational amplifier; the capacitor C 2P The negative terminal of the circuit is connected to the positive terminal of switch S9, and its connection point is also connected to switch S... 11 The positive terminal connection; the capacitor C 2N The negative terminal and switch S 10 The positive terminal is connected, and its connection point is also connected to switch S. 12 The positive terminal of the switch S9 is connected; the negative terminal of the switch S9 is connected to the common-mode voltage VCM; the switch S... 10 The negative terminal of the circuit is connected to the common-mode voltage VCM; the negative terminal of the switch S7 is connected to the switch S... 11 The negative terminal is connected, and its connection point is also connected to capacitor C. 3P The negative terminal, the non-inverting output terminal of the operational amplifier, and switch S 13 The positive terminal of the switch S8 is connected to the negative terminal of the switch S1. 12 The negative terminal is connected, and its connection point is also connected to capacitor C. 3N The negative terminal, the negative output terminal of the operational amplifier, and switch S 14 The positive terminal of the switch S5 is connected to the capacitor C; the negative terminal of the switch S5 is connected to the capacitor C. 3P The positive terminal of the switch S6 is connected to the capacitor C; the negative terminal of the switch S6 is connected to the capacitor C. 3N The positive terminal connection; the switch S 13 The negative terminal and resistor R 1P The positive terminal connection; the switch S 14 The negative terminal and resistor R 1N The positive terminal is connected; the resistor R 1P The negative terminal and capacitor C 4P The positive terminal is connected, and its connection point is also connected to the positive terminal and output terminal VOP of capacitor C5; the resistor R 1N The negative terminal and capacitor C 4N The positive terminal of the capacitor is connected, and its connection point is also connected to the negative terminal and output terminal VON of capacitor C5; the capacitor C 4Pnegative terminal, capacitor C 4N The negative terminal is grounded.

[0007] Furthermore, the novel high-voltage switch includes LDMOS transistors M1 and M2; MOS transistors M3, M4, and M5; MOS transistors M6 and M7 with high-voltage ISO isolation rings; and an external current source I. dc Resistor R1; Maximum / Minimum Voltage Selection Circuit.

[0008] The current source I dc The positive terminal is connected to the power supply voltage AVDD; the current source I dc The negative terminal of the transistor is connected to the drain of LDMOS transistor M1, and its connection point is also connected to the gate of LDMOS transistor M1 and the gate of LDMOS transistor M2; the source of LDMOS transistor M1 is connected to the drain of MOS transistor M4, and its connection point is also connected to the gate of MOS transistor M4 and the gate of MOS transistor M5; the sources of MOS transistor M4 and MOS transistor M5 are both grounded; the drain of MOS transistor M5 is connected to the source of MOS transistor M3; the gate of MOS transistor M3 is connected to the clock signal φ; the MO The drain of S-channel MOSFET M3 is connected to the source of MOSFET M2; the drain of MOSFET M2 is connected to the positive terminal of resistor R1, and its connection point is also connected to the gates of MOSFETs M6 and M7; the negative terminal of resistor R1 is connected to the source of MOSFET M6, and its connection point is also connected to the source of MOSFET M7; the drain of MOSFET M6 is connected to the input terminal Vin; the drain of MOSFET M7 is connected to the output terminal Vout; the base (B) terminal of MOSFET M6 is connected to the maximum / minimum voltage selection circuit V... max The connection point is also connected to the base (B) terminal of MOSFET M7; the ISO terminal of MOSFET M6 is connected to the ISO terminal of MOSFET M7; the ISUB terminal of MOSFET M6 is connected to the ISUB terminal of MOSFET M7, and the connection point is also connected to the maximum / minimum voltage selection circuit V. min Terminal connections. One input terminal of the maximum / minimum voltage selection circuit is connected to the input signal VIP, and the other input terminal is connected to the input signal VIN.

[0009] Furthermore, the output voltage of the maximum / minimum voltage selection circuit is generated by a NMOS / PMOS cross-coupled pair with its source floating. This maximum / minimum voltage selection circuit includes MOS transistors MN1, MN2, MP1, and MP2 with high-voltage ISO isolation rings.

[0010] The source of MOSFET MN1 is connected to the gate of MOSFET MN2, and the connection point is also connected to the gate of MOSFET MP2, the source of MOSFET MP1, and the input terminal VIP. The gate of MOSFET MN1 is connected to the source of MOSFET MN2, and the connection point is also connected to the gate of MOSFET MP1, the source of MOSFET MP2, and the input terminal VIN. The drain of MOSFET MN1 is connected to the drain of MOSFET MN2, and the connection point is also connected to the base (B) terminals of MOSFET MN1 and MN2, the ISUB terminal of MOSFET MP1, the ISUB terminal of MOSFET MP2, and the output terminal VIN. min Connection; the drain of MOSFET MP1 is connected to the drain of MOSFET MP2, and the connection point is also connected to the base (B) of MOSFET MP1, the base (B) of MOSFET MP2, and the output terminal V. max Connections are made as follows: the ISO terminal of MOS transistor MP1 is connected to the ISO terminal of MOS transistor MP2; the ISO terminal of MOS transistor MN1 is connected to the ISO terminal of MOS transistor MN2.

[0011] The advantages of this invention are: high integration, simple structure, and suitability for the analog front-end design of low-power and high-precision electric vehicle battery management systems. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the structure of a novel highly integrated analog front-end circuit;

[0013] Figure 2 This is a schematic diagram of a MOSFET with an ISO isolation ring.

[0014] Figure 3 This is a schematic diagram of the high-voltage switch.

[0015] Figure 4 Schematic diagram of the maximum / minimum voltage selection circuit;

[0016] Figure 5 This is a graph showing the input and output signals in one embodiment of the present invention;

[0017] Figure 6 This is a frequency response curve diagram in one embodiment of the present invention;

[0018] Figure 7 This is a verification effect diagram of the imbalance elimination scheme in one embodiment of the present invention. Detailed Implementation

[0019] The embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0020] like Figure 1As shown, this invention proposes a novel highly integrated analog front-end circuit for an automotive battery management system, comprising a high-voltage chopper module, an operational amplifier module, a gain control module, a low-pass filter module, an offset cancellation module, and a charge buffer module. The high-voltage chopper module performs a level shifting function, reducing the input high-voltage common-mode voltage to a low-voltage common-mode voltage. The operational amplifier module provides high gain and high bandwidth for precise clamping and rapid setup. The gain control module sets a programmable gain through capacitor ratios. The -3dB cutoff frequency of the low-pass filter module is controlled by capacitor ratios to achieve anti-aliasing filtering. The offset cancellation module eliminates operational amplifier offset through offset storage principles. The charge buffer module stabilizes the output voltage and reduces noise bandwidth. By integrating the level shifter, programmable gain amplifier, and low-pass filter into a single switched-capacitor architecture, system complexity and power consumption are reduced, enabling high-precision measurement of automotive battery voltage.

[0021] In embodiments of the present invention, such as Figure 1 As shown, the novel highly integrated analog front-end circuit integrates level shifting, programmable gain amplification, and low-pass filtering in a single switched-capacitor architecture. This novel highly integrated analog front-end circuit includes an operational amplifier OPA, high-voltage switches S1-S4, and capacitor C. 1P -C 4P Capacitor C 1N -C 4N Capacitor C5, Switches S5-S 14 Resistance R 1P -R 1N ;

[0022] The positive terminals of switches S1 and S3 are both connected to the input terminal VIP; the positive terminals of switches S2 and S4 are both connected to the input terminal VIN; the negative terminal of switch S3 is connected to the negative terminal of switch S2, and its connection point is also connected to capacitor C. 1P The positive terminal of switch S4 is connected to the negative terminal of switch S1, and the connection point is also connected to capacitor C. 1N The positive terminal connection; the capacitor C 1P The negative terminal and capacitor C 2P The positive terminal is connected, and its connection point is also connected to the positive terminal of switch S7, the positive terminal of switch S5, and the negative input terminal of the operational amplifier; the capacitor C 1N The negative terminal and capacitor C 2N The positive terminal is connected, and its connection point is also connected to the positive terminal of switch S6, the positive terminal of switch S8, and the non-inverting input terminal of the operational amplifier; the capacitor C 2P The negative terminal of the circuit is connected to the positive terminal of switch S9, and its connection point is also connected to switch S... 11 The positive terminal connection; the capacitor C 2N The negative terminal and switch S 10The positive terminal is connected, and its connection point is also connected to switch S. 12 The positive terminal of the switch S9 is connected; the negative terminal of the switch S9 is connected to the common-mode voltage VCM; the switch S... 10 The negative terminal of the circuit is connected to the common-mode voltage VCM; the negative terminal of the switch S7 is connected to the switch S... 11 The negative terminal is connected, and its connection point is also connected to capacitor C. 3P The negative terminal, the non-inverting output terminal of the operational amplifier, and switch S 13 The positive terminal of the switch S8 is connected to the negative terminal of the switch S1. 12 The negative terminal is connected, and its connection point is also connected to capacitor C. 3N The negative terminal, the negative output terminal of the operational amplifier, and switch S 14 The positive terminal of the switch S5 is connected to the capacitor C; the negative terminal of the switch S5 is connected to the capacitor C. 3P The positive terminal of the switch S6 is connected to the capacitor C; the negative terminal of the switch S6 is connected to the capacitor C. 3N The positive terminal connection; the switch S 13 The negative terminal and resistor R 1P The positive terminal connection; the switch S 14 The negative terminal and resistor R 1N The positive terminal is connected; the resistor R 1P The negative terminal and capacitor C 4P The positive terminal is connected, and its connection point is also connected to the positive terminal and output terminal VOP of capacitor C5; the resistor R 1N The negative terminal and capacitor C 4N The positive terminal of the capacitor is connected, and its connection point is also connected to the negative terminal and output terminal VON of capacitor C5; the capacitor C 4P negative terminal, capacitor C 4N The negative terminals are all grounded.

[0023] like Figure 1 As shown, to process differential input signals with high common-mode voltage and to amplify and filter the differential signals, this design employs a novel, highly integrated analog front-end circuit. During the nth cycle, in the reset phase (φ1), switches S3, S4, S7, S9, S8, and S... 10 The circuit is turned on, and switches S1, S2, S5, S6, and S are simultaneously activated. 11 S 12 S 13 S 14 Disconnect, capacitor C 1P The positive terminal is connected to the input signal VIP[n], and the capacitor C 1N The positive terminal is connected to the input signal VIN[n]; capacitor C 1P The negative electrode and capacitor C 1N The negative terminals are all clamped to common-mode voltage by the operational amplifier; during the amplification stage (φ2), switches S1, S2, S5, S6, and S... 11 S 12 S13 S 14 The circuit is turned on, and switches S3, S4, S7, S9, S8, and S1 are simultaneously activated. 10 Disconnect, capacitor C 1P The positive terminal is connected to the input signal VIN[n], and the capacitor C 1N The negative terminal is connected to the input signal VIP[n], and the capacitor C 1P The negative electrode and capacitor C 1N The negative terminal remains clamped to the common-mode voltage by the operational amplifier. During the circuit's transition from the reset phase to the amplification phase, capacitor C... 1P The change in charge on the positive plate is:

[0024]

[0025] Similarly, capacitor C 1N The change in charge on the positive plate is:

[0026]

[0027] At the end of the previous cycle, capacitor C 3P The amount of charge stored on the negative electrode plate is:

[0028]

[0029] Similarly, at the end of the previous cycle, capacitor C 3N The amount of charge stored on the negative electrode plate is:

[0030]

[0031] According to the principle of charge conservation, the capacitance C during the amplification stage can be obtained. 2P and C 3P The total charge stored on the negative plate is:

[0032]

[0033] Similarly, during the amplification stage, the capacitor C 2N and C 3N The total charge stored on the negative plate is:

[0034]

[0035] At the end of the amplification phase, the output voltage VOP[n] is:

[0036]

[0037] Similarly, at the end of the amplification stage, the output voltage VON[n] is:

[0038]

[0039] According to formulas (7) and (8), the common-mode voltages of the output signals VOP and VON are both VCM. Therefore, this design implements the level shifting function, and the specific output differential signal is:

[0040]

[0041] in , , , (Because the circuit is perfectly symmetrical, C) 1P =C 1N =C1,C 2P =C 2N =C2,C 3P =C 3N =C3,C 4P =C 4N Applying the z-transform to the signal in formula (9) yields the transfer function from the input signal to the output signal:

[0042]

[0043] According to formula (10), this is the transfer function of a low-pass filter, and its DC amplification factor is:

[0044]

[0045] Its cutoff frequency is:

[0046]

[0047] By controlling the ratio between capacitors C1, C2, and C3, the DC amplification factor and the cutoff frequency of the low-pass filter in this analog front-end circuit can be controlled, thereby achieving variable gain amplification and low-pass filtering functions.

[0048] In a specific embodiment, such as Figure 5 As shown, the input signal is amplified by 5 times and then filtered by a low-pass filter with a cutoff frequency of 1.6kHz.

[0049] In a specific embodiment, such as Figure 6 As shown, the gain of this novel analog front-end circuit is adjustable and the cutoff frequency is 1.6 kHz at different gains.

[0050] Consider the input offset voltage V of the operational amplifier OPA OS At that time, formula (9) was modified to:

[0051]

[0052] According to formula (13), the output offset voltage can be seen. As time monotonically decreases and eventually approaches 0, the verification effect diagram of the imbalance elimination scheme in one embodiment of the present invention is shown below. Figure 7 As shown.

[0053] like Figure 1 As shown, the charge buffer provides instantaneous charge to the sampling capacitor of the subsequent analog-to-digital converter, thereby reducing the common-mode voltage drop at the OPA output. This charge buffer also functions as a low-pass filter, reducing the noise bandwidth of the analog front-end circuit.

[0054] like Figure 2 As shown, the ISO terminal of the MOS transistor with ISO isolation ring is connected to the N-type buried layer (NBL); the B terminal of the NMOS transistor with ISO isolation ring is connected to the P-well inside the ISO ring; the B terminal of the PMOS transistor with ISO isolation ring is connected to the N-well inside the ISO ring; and the ISUB terminal of the PMOS transistor with ISO isolation ring is connected to the P-well inside the ISO ring.

[0055] like Figure 3 As shown, the novel high-voltage switch includes LDMOS transistors M1 and M2; MOS transistors M3, M4, and M5; MOS transistors M6 and M7 with high-voltage ISO isolation rings; and an external current source I. dc Resistor R1; Maximum / Minimum Voltage Selection Circuit.

[0056] The current source I dc The positive terminal is connected to the power supply voltage AVDD; the current source I dc The negative terminal of the transistor is connected to the drain of LDMOS transistor M1, and its connection point is also connected to the gate of LDMOS transistor M1 and the gate of LDMOS transistor M2; the source of LDMOS transistor M1 is connected to the drain of MOS transistor M4, and its connection point is also connected to the gate of MOS transistor M4 and the gate of MOS transistor M5; the sources of MOS transistor M4 and MOS transistor M5 are both grounded; the drain of MOS transistor M5 is connected to the source of MOS transistor M3; the gate of MOS transistor M3 is connected to the clock signal φ; the MO The drain of S-channel MOSFET M3 is connected to the source of MOSFET M2; the drain of MOSFET M2 is connected to the positive terminal of resistor R1, and its connection point is also connected to the gates of MOSFETs M6 and M7; the negative terminal of resistor R1 is connected to the source of MOSFET M6, and its connection point is also connected to the source of MOSFET M7; the drain of MOSFET M6 is connected to the input terminal Vin; the drain of MOSFET M7 is connected to the output terminal Vout; the base (B) terminal of MOSFET M6 is connected to the maximum / minimum voltage selection circuit V... maxThe connection point is also connected to the base (B) terminal of MOSFET M7; the ISO terminal of MOSFET M6 is connected to the ISO terminal of MOSFET M7; the ISUB terminal of MOSFET M6 is connected to the ISUB terminal of MOSFET M7, and the connection point is also connected to the maximum / minimum voltage selection circuit V. min Terminal connections. One input terminal of the maximum / minimum voltage selection circuit is connected to the input signal VIP, and the other input terminal is connected to the input signal VIN.

[0057] like Figure 3 As shown, to meet the high common-mode input voltage tolerance requirement, MOSFETs M6 and M7 are PMOS devices with high-voltage ISO isolation rings. The maximum / minimum voltage selection circuit selects the maximum voltage V in the differential input signal. max and minimum voltage V min To properly bias MOSFETs M6 and M7, the ISO terminals of MOSFETs M6 and M7 are connected but left floating to ensure that the ISO isolation loop potential of MOSFETs M6 and M7 fluctuates with the input signal. By connecting two MOSFETs M6 and M7 in series, at least one MOSFET is ensured to be off regardless of whether Vin > Vout or Vin < Vout. External current source I... dc LDMOS transistors M1, M2, M3, M4, and M5 form a current source. MOSFET M3 controls the switching on and off of this current source. When M3 is on, a constant current I flows through resistor R1, resulting in a constant voltage drop across R1. This constant voltage provides a constant gate-source voltage for MOSFETs M6 and M7, keeping their on-resistance constant and thus ensuring the high linearity of the high-voltage switch. LDMOS transistors M1 and M2 not only serve as common-source, common-gate transistors for the current mirror to improve its current replication accuracy, but their gate-drain characteristics also allow them to withstand high voltages. Therefore, LDMOS transistors M1 and M2 are also used to isolate the high-voltage input signal from the low-voltage MOSFETs M3, M4, and M5. The supply voltage AVDD of the external current source and the high level of the clock signal φ can be much lower than the common-mode voltage of the input signal. Therefore, the high-voltage switch can be directly controlled by a low-voltage clock, greatly simplifying the interface circuit with digital circuits.

[0058] like Figure 4 As shown, the output voltage of the maximum / minimum voltage selection circuit is generated by a NMOS / PMOS cross-coupled pair with its source floating. This maximum / minimum voltage selection circuit includes MOS transistors MN1, MN2, MP1, and MP2 with high-voltage ISO isolation rings.

[0059] The source of MOSFET MN1 is connected to the gate of MOSFET MN2, and the connection point is also connected to the gate of MOSFET MP2, the source of MOSFET MP1, and the input terminal VIP. The gate of MOSFET MN1 is connected to the source of MOSFET MN2, and the connection point is also connected to the gate of MOSFET MP1, the source of MOSFET MP2, and the input terminal VIN. The drain of MOSFET MN1 is connected to the drain of MOSFET MN2, and the connection point is also connected to the base (B) terminals of MOSFET MN1 and MN2, the ISUB terminal of MOSFET MP1, the ISUB terminal of MOSFET MP2, and the output terminal VIN. min Connection; the drain of MOSFET MP1 is connected to the drain of MOSFET MP2, and the connection point is also connected to the base (B) of MOSFET MP1, the base (B) of MOSFET MP2, and the output terminal V. max Connections are made as follows: the ISO terminal of MOS transistor MP1 is connected to the ISO terminal of MOS transistor MP2; the ISO terminal of MOS transistor MN1 is connected to the ISO terminal of MOS transistor MN2.

[0060] like Figure 4 As shown, the maximum voltage selection circuit consists of a pair of cross-coupled PMOS transistors with their sources floating. The cross-coupled PMOS transistors MP1 and MP2 form a positive feedback loop, which forces the PMOS transistor connected to the higher potential side to turn on and the PMOS transistor connected to the lower potential side to turn off. Therefore, the output voltage V... max The maximum value between the input signals VIP and VIN is given. Similarly, the minimum voltage selection circuit consists of a pair of NMOS transistors with their sources floating. The cross-coupled NMOS transistors MN1 and MN2 form a positive feedback loop, which forces the NMOS transistor connected to the lower potential side to turn on and the NMOS transistor connected to the higher potential side to turn off. Therefore, the output voltage V... min It is the minimum value between the input signal VIP and the input signal VIN.

[0061] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A novel highly integrated analog front-end circuit for an automotive battery management system, characterized in that, The system includes a high-voltage chopper module, an operational amplifier module, a gain control module, a low-pass filter module, an offset cancellation module, and a charge buffer module. The high-voltage chopper module performs a level shifting function, reducing the input high-voltage common-mode voltage to a low-voltage common-mode voltage. The operational amplifier module provides high gain and high bandwidth for precise clamping and rapid setup. The gain control module sets the programmable gain through capacitor ratios. The -3dB cutoff frequency of the low-pass filter module is controlled by capacitor ratios to achieve anti-aliasing filtering. The offset cancellation module eliminates operational amplifier offset through offset storage principles. The charge buffer module stabilizes the output voltage and reduces noise bandwidth. By integrating the level shifter, programmable gain amplifier, and low-pass filter into a single switched-capacitor architecture, the system complexity and power consumption are reduced, enabling high-precision measurement of automotive battery voltage.

2. The novel highly integrated analog front-end circuit for an automotive battery management system according to claim 1, characterized in that, The novel highly integrated analog front-end circuit integrates level shifting, programmable gain amplification, and low-pass filtering in a single switched-capacitor architecture. This novel highly integrated analog front-end circuit includes an operational amplifier (OPA), high-voltage switches (S1-S4), and capacitor C. 1P -C 4P Capacitor C 1N -C 4N Capacitor C5, Switches S5-S 14 Resistance R 1P -R 1N ; The positive terminals of switches S1 and S3 are both connected to the input terminal VIP; the positive terminals of switches S2 and S4 are both connected to the input terminal VIN; the negative terminal of switch S3 is connected to the negative terminal of switch S2, and its connection point is also connected to capacitor C. 1P The positive terminal of switch S4 is connected to the negative terminal of switch S1, and the connection point is also connected to capacitor C. 1N The positive terminal connection; the capacitor C 1P The negative terminal and capacitor C 2P The positive terminal is connected, and its connection point is also connected to the positive terminal of switch S7, the positive terminal of switch S5, and the negative input terminal of the operational amplifier; the capacitor C 1N The negative terminal and capacitor C 2N The positive terminal is connected, and its connection point is also connected to the positive terminal of switch S6, the positive terminal of switch S8, and the non-inverting input terminal of the operational amplifier; the capacitor C 2P The negative terminal of the circuit is connected to the positive terminal of switch S9, and its connection point is also connected to switch S... 11 The positive terminal connection; the capacitor C 2N The negative terminal and switch S 10 The positive terminal is connected, and its connection point is also connected to switch S. 12 The positive terminal of the switch S9 is connected to the negative terminal of the switch S1. 10 The negative terminals of both are connected to the common-mode voltage VCM; the negative terminal of switch S7 is connected to switch S... 11 The negative terminal is connected, and its connection point is also connected to capacitor C. 3P The negative terminal, the non-inverting output terminal of the operational amplifier, and switch S 13 The positive terminal of the switch S8 is connected to the negative terminal of the switch S1. 12 The negative terminal is connected, and its connection point is also connected to capacitor C. 3N The negative terminal, the negative output terminal of the operational amplifier, and switch S 14 The positive terminal of the switch S5 is connected to the capacitor C; the negative terminal of the switch S5 is connected to the capacitor C. 3P The positive terminal of the switch S6 is connected to the capacitor C; the negative terminal of the switch S6 is connected to the capacitor C. 3N The positive terminal connection; the switch S 13 The negative terminal and resistor R 1P The positive terminal connection; the switch S 14 The negative terminal and resistor R 1N The positive terminal is connected; the resistor R 1P The negative terminal and capacitor C 4P The positive terminal is connected, and its connection point is also connected to the positive terminal and output terminal VOP of capacitor C5; the resistor R 1N The negative terminal and capacitor C 4N The positive terminal of the capacitor is connected, and its connection point is also connected to the negative terminal and output terminal VON of capacitor C5; the capacitor C 4P The negative electrode and capacitor C 4N The negative terminal is grounded.

3. The high-voltage switch according to claim 2, characterized in that, This novel high-voltage switch includes LDMOS transistors M1 and M2; MOS transistors M3, M4, and M5; MOS transistors M6 and M7 with high-voltage ISO isolation rings; and an external current source I. dc Resistor R1; Maximum / Minimum Voltage Selection Circuit; The current source I dc The positive terminal is connected to the power supply voltage AVDD; the current source I dc The negative terminal of the transistor is connected to the drain of LDMOS transistor M1, and its connection point is also connected to the gate of LDMOS transistor M1 and the gate of LDMOS transistor M2; the source of LDMOS transistor M1 is connected to the drain of MOS transistor M4, and its connection point is also connected to the gate of MOS transistor M4 and the gate of MOS transistor M5; the sources of MOS transistor M4 and MOS transistor M5 are both grounded; the drain of MOS transistor M5 is connected to the source of MOS transistor M3; the gate of MOS transistor M3 is connected to the clock signal φ; the MO The drain of S-channel MOSFET M3 is connected to the source of MOSFET M2; the drain of MOSFET M2 is connected to the positive terminal of resistor R1, and its connection point is also connected to the gates of MOSFETs M6 and M7; the negative terminal of resistor R1 is connected to the source of MOSFET M6, and its connection point is also connected to the source of MOSFET M7; the drain of MOSFET M6 is connected to the input terminal Vin; the drain of MOSFET M7 is connected to the output terminal Vout; the base (B) terminal of MOSFET M6 is connected to the maximum / minimum voltage selection circuit V... max The connection point is also connected to the base (B) terminal of MOSFET M7; the ISO terminal of MOSFET M6 is connected to the ISO terminal of MOSFET M7; the ISUB terminal of MOSFET M6 is connected to the ISUB terminal of MOSFET M7, and the connection point is also connected to the maximum / minimum voltage selection circuit V. min Terminal connection; one input terminal of the maximum / minimum voltage selection circuit is connected to the input signal VIP, and the other input terminal is connected to the input signal VIN.

4. The maximum / minimum voltage selection circuit according to claim 3, characterized in that, Its output voltage is generated by a floating-source NMOS / PMOS cross-coupled pair. This maximum / minimum voltage selection circuit includes MOS transistors MN1, MN2, MP1, and MP2 with high-voltage ISO isolation rings. The source of MOSFET MN1 is connected to the gate of MOSFET MN2, and the connection point is also connected to the gate of MOSFET MP2, the source of MOSFET MP1, and the input terminal VIP. The gate of MOSFET MN1 is connected to the source of MOSFET MN2, and the connection point is also connected to the gate of MOSFET MP1, the source of MOSFET MP2, and the input terminal VIN. The drain of MOSFET MN1 is connected to the drain of MOSFET MN2, and the connection point is also connected to the base (B) terminals of MOSFET MN1 and MN2, the ISUB terminal of MOSFET MP1, the ISUB terminal of MOSFET MP2, and the output terminal VIN. min Connection; the drain of MOSFET MP1 is connected to the drain of MOSFET MP2, and the connection point is also connected to the base (B) of MOSFET MP1, the base (B) of MOSFET MP2, and the output terminal V. max Connections are made as follows: the ISO terminal of MOS transistor MP1 is connected to the ISO terminal of MOS transistor MP2; the ISO terminal of MOS transistor MN1 is connected to the ISO terminal of MOS transistor MN2.

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