Offset correction techniques in distributed radar systems
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NXP USA INC
- Filing Date
- 2026-01-15
- Publication Date
- 2026-08-07
Smart Images
Figure CN122525505A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an offset correction technique in a distributed radar system. Background Technology
[0002] Many systems rely on radar to provide accurate information about the surrounding environment. For example, modern vehicles use radar to implement Advanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) systems, which perform functions such as adaptive cruise control, automatic steering, and emergency braking. In some cases, vehicle radar systems use radar modulation schemes (e.g., frequency-modulated continuous waveform (FMCW) radar), which modulate radar signals at frequencies in the 76 GHz to 81 GHz band in a sequence commonly referred to as radar chirp, or simply chirp. Radar systems using these types of radar modulation schemes sense the surrounding environment by: transmitting a chirp sequence, receiving the chirped reflections after the chirps have been reflected from one or more objects, and processing the received reflections to obtain the distance distribution of the one or more objects and the velocity of the objects. To provide a more robust and accurate perception of the surrounding environment, radar systems employ various radar transmission and signal processing techniques. Summary of the Invention
[0003] A method includes: upsampling a first signal having a first frequency to a second signal having a second frequency higher than the first frequency at an upconverter at a first radar front-end in a distributed radar system; generating a first radar chirp signal at a chirp generator at the first radar front-end, wherein the chirp generator modulates the time period between consecutive chirps in the first radar chirp signal based on the second signal; and transmitting the first radar chirp signal from the first radar front-end.
[0004] The method may further include: generating a second radar chirp signal at a chirp generator at a second radar front-end in the distributed radar system; and transmitting the second radar chirp signal from the second radar front-end. The chirp generator at the first radar front-end may modulate the time period between consecutive chirps in the first radar chirp signal based on the start time of the second signal and the chirps in the second radar chirp signal.
[0005] The start time of each chirp in the first radar chirp signal and the start time of the corresponding chirp in the second radar chirp signal can be aligned with each other within a tolerance threshold determined based on the second frequency of the second signal. The alignment can be based on the second frequency at the front end of the first radar.
[0006] The tolerance threshold can be less than about 2 nanoseconds.
[0007] The first radar front-end and the second radar front-end can have different dwell time settings. The dwell time setting of the first radar front-end can be set based on aligning the chirp of the first radar chirp signal with the chirp of the second radar chirp signal.
[0008] The method may further include modulating the dwell time of the first radar front end based on the frequencies of the second signal and the second radar chirp signal.
[0009] The center frequencies of the chirps in the first radar chirp signal and the second radar chirp signal can be aligned with each other within a frequency threshold based on the measured reference clock frequency offset between the first radar front-end and the second radar front-end.
[0010] The method may further include: receiving a reflected radar signal at the first radar front end; and sampling the reflected radar signal at an analog-to-digital converter (ADC) at the first radar front end at a sampling frequency based on the second signal.
[0011] The upconverter in the first radar front-end may include a first phase-locked loop (PLL) circuit system. The chirp generator in the first radar front-end may include a second PLL circuit system different from the first PLL.
[0012] A radar front-end includes an up-conversion converter. The up-conversion converter is configured to receive a first signal from a reference clock source of the radar front-end. The first signal has a first frequency. The up-conversion converter is configured to up-convert the first signal into a second signal having a second frequency. The radar front-end includes a chirp generator configured to generate a first radar chirp signal by modulating the time period between consecutive chirps in the first radar chirp signal based on the second signal. The radar front-end includes a transmitter configured to transmit the first radar chirp signal.
[0013] The radar front end may additionally include digital hardware configured to provide timing signals to modulate the time period between successive chirps of the first radar chirp signal generated by the chirp generator based on the second signal.
[0014] The radar front end may additionally include an analog-to-digital converter (ADC) configured to sample the reflected signal received at the radar front end based on the second signal at the start of sampling.
[0015] The time period between consecutive chirps in the first radar chirp signal can be modulated into a constant time period.
[0016] The first time period between the first pair of consecutive chirps in the first radar chirp signal can be modulated to a first time length. By adjusting the number of clock cycles between the second pair of consecutive chirps in the first radar chirp signal, the second time period between the second pair of consecutive chirps can be modulated to a second time length different from the first time length.
[0017] The chirp generator can be further configured to modulate the frequency of the first radar chirp signal based on the second signal.
[0018] The upconverter at the radar front end may include a first phase-locked loop (PLL) circuit system. The chirp generator at the radar front end may include a second PLL circuit system different from the first PLL.
[0019] A distributed radar system includes a first radar front-end configured to generate a first radar chirp signal based on a reference clock signal received from a first reference clock source. The distributed radar system also includes a second radar front-end configured to generate a second radar chirp signal by modulating the time period between consecutive chirs in the second radar chirp signal based on a second frequency signal. The second frequency signal is generated by up-converting the reference clock signal received from a second reference clock source.
[0020] The second radar front-end can be further configured to generate the second radar chirp signal based on aligning the chirps in the second radar chirp signal with the corresponding chirps in the first radar chirp signal within a tolerance threshold. Alignment can be performed by modulating the number of clock cycles between the chirps in the second radar chirp signal.
[0021] The distributed radar system may additionally include a radar processor configured to detect one or more objects based on received reflected signals from the first radar chirp signal and the second radar chirp signal.
[0022] The distributed radar system may further include one or more additional radar front-ends. Each of the one or more additional radar front-ends may be configured to generate a corresponding additional radar chirp signal by modulating the time period between consecutive chirs in a corresponding additional radar chirp signal based on a corresponding second frequency signal. The corresponding second frequency signal may be generated by up-converting the reference clock signal received from the reference clock source. Attached Figure Description
[0023] This disclosure can be better understood by referring to the accompanying drawings, which will make its numerous features and advantages clear to those skilled in the art. The same reference numerals are used in different drawings to indicate similar or identical items.
[0024] Figure 1 and 2 Examples of radar front-end and radar main controller processing unit in a radar system having a transmission configuration configured to minimize frequency and timing offsets between radar front-ends are shown respectively, according to various embodiments.
[0025] Figure 3 This illustrates a distributed radar system (e.g., according to various embodiments) Figure 1 and 2 Examples of vehicle control systems (such as radar systems).
[0026] Figure 4 Examples of radar front-ends according to various embodiments are shown, which have components that minimize or eliminate frequency and / or timing offsets with other radar front-ends in a distributed radar system.
[0027] Figure 5 The diagram shows a first graph and a second graph in a distributed radar system with similar dwell time settings in two radar front-ends according to conventional technology. The first graph shows a first chirped sequence transmitted by a first radar front-end, and the second graph shows a second chirped sequence transmitted by a second radar front-end.
[0028] Figure 6 The diagram shows a first graph and a second graph according to some embodiments with different dwell time settings in the radar front end. The first graph shows a first chirp sequence emitted by a first radar front end, and the second graph shows a second chirp sequence emitted by a second radar front end.
[0029] Figure 7 Examples of flowcharts according to various embodiments are shown, illustrating a method for generating radar chirp signals based on higher frequency signals to modulate the dwell time between chirps. Detailed Implementation
[0030] Some radar systems include multiple radar sensors (also referred to herein as "radar front-ends" or "radar heads") to increase awareness of the surrounding environment. For example, Distributed Coherent Radar (DCR) FMCW radar systems employ multiple radar front-ends and combine reflections received at the radar front-ends to improve the angular resolution of the radar system. In some cases, radar systems seek to improve the coherence of the combined reflections by estimating and compensating for the frequency offsets between the multiple radar front-ends. The frequency offset is generated by each radar front-end, which has its own crystal oscillator that provides a reference clock signal to the chirp generator phase-locked loop (PLL) circuitry system in the radar front-end and the timing engine of the radar front-end, which controls the slope of the chirp and the sampling timing of the analog-to-digital converters (ADCs) in the receiver chain of the radar front-end.
[0031] This disclosure and accompanying drawings provide several techniques for minimizing or eliminating frequency and / or timing offsets between radar front-ends by adapting the settings of upconverters in one or more radar front-ends, to provide improved control over the "dwell time" (or time period) between chimes and the center frequency of the chimes in a radar chirped signal. In some embodiments, the techniques described herein implement the upconverter as a PLL circuit system to upconvert a lower-frequency reference clock signal received at the radar front-end to a higher-frequency signal, which is then used to provide finer-tuned control (e.g., on a 1.5 nanosecond scale) over the dwell time between consecutive chimes in the transmitted radar signal. By modulating the dwell time between chimes in the transmitted radar signal based on the higher-frequency signal, the radar front-end is able to better align the chimes in its transmitted radar signal with the corresponding chimes of another radar signal transmitted from another radar front-end in the radar system. That is, by employing a higher-frequency signal to provide improved dwell time control, the radar front-end is able to align its transmitted chimes with chimes transmitted from another radar front-end within a smaller tolerance threshold. The tolerance threshold depends on the frequency of the higher-frequency signal. For example, for a higher-frequency signal of 640 MHz, the tolerance threshold is approximately 1.5 nanoseconds, which is significantly less than the 25 nanosecond tolerance threshold if a conventional 40 MHz clock signal is used. Additionally, the higher-frequency signal is used to control the sampling start time of the ADC in the radar front-end. By modulating the dwell time between chirps and the ADC sampling start time based on the higher-frequency signal in the radar front-end, the technique described in this paper increases the signal-to-noise ratio (SNR) of the received reflections, thereby improving the performance of the radar system without relying on expensive hardware (e.g., more expensive crystal oscillators) and without introducing artifacts or noise that could degrade system performance.
[0032] In some embodiments, the distributed radar system includes a first radar front-end and a second radar front-end, each having its own reference clock source. The reference clock source of each radar front-end is configured to generate a reference clock signal for the corresponding radar front-end. The reference clock signal generated at the second radar front-end has a known frequency offset relative to the reference clock signal generated at the first radar front-end. The first radar front-end is configured to generate a first radar chirp signal based on the reference clock signal received from its reference clock source. The second radar front-end is configured to generate a second radar chirp signal by modulating the time period between consecutive chirs in the second radar chirp signal based on a second frequency signal. The second radar front-end generates the second frequency signal by up-converting the reference clock signal received from its reference clock source. For example, the second radar front-end includes a PLL circuit system that receives the reference clock signal and generates the second frequency signal at a higher frequency. The second signal is input to a chirp generator circuit system at the second radar front-end to generate the second radar chirp signal. In some embodiments, the second signal is also input to the timing engine of the second radar front-end to control the start time of each chirp in the second radar chirp signal and to set the sampling start time of the ADC of the second radar front-end. For example, the timing engine utilizes the second signal (whose frequency is higher than the reference clock signal) to more finely control the number of clock cycles between consecutive chirs in the second radar chirp signal based on a known frequency offset from the first radar front-end. That is, for example, the timing engine can control or adjust the number of clock cycles between consecutive chirs in the second radar signal based on the higher-frequency second signal. In this way, the second radar front-end is able to generate and transmit a second radar chirp signal whose chirps are more closely aligned with the chirs in the first radar chirp signal transmitted by the first radar front-end within a tolerance threshold (e.g., in the time and / or frequency domains). This increases the SNR of the received reflections, thereby improving system performance.
[0033] In some embodiments, any element, component, or block shown subsequently in the figures is implemented as software executing on a processor, hard-wired hardware (e.g., a circuit system) performing the various operations described herein, or a combination thereof. For example, one or more of the described blocks or components (e.g., blocks or components associated with the techniques described herein) represent software instructions executed by hardware such as a digital signal processor, application-specific integrated circuit (ASIC), a set of logic gates, a field-programmable gate array (FPGA), a programmable logic device (PLD), a hardware accelerator, a parallel processor, or any other type of hard-coded or programmable circuit. As another example, one or more of the described blocks or components represent hardware such as a PLL circuit system.
[0034] Figure 1 and 2A radar system 100 (including) illustrates techniques for minimizing or eliminating frequency and timing offsets between radar front-ends according to various embodiments. Figure 1 The first radar system part 100-1 and Figure 2 Example of the second radar system part 100-2). Figure 1 The radar front-end 102 of the radar system 100 is shown, and Figure 2 The radar main controller processing unit (MCPU) 138 of the radar system 100 is shown.
[0035] refer to Figure 1 In some embodiments, the radar front-end 102 includes a plurality of transmitters 104-1 to 104-N (collectively referred to as transmitter 104). In some embodiments, each transmitter 104 includes a power amplifier (PA) 106 and a radio frequency (RF) signal conditioning assembly 108. The PA 106 converts a lower-power RF signal into a higher-power RF signal before transmission. For example, in some embodiments, the PA 106 is configured to convert a lower-power RF signal including multiple chirps into a higher-power RF signal. The RF conditioning assembly 108 includes hardware and / or software for modifying (i.e., conditioning) the signal received from the chirp generator 137 before it is provided to the PA 106. For example, in some embodiments, the RF conditioning assembly 108 includes one or more filters that filter the RF signal before signal power amplification at the PA 106.
[0036] In some embodiments, radar front-end 102 receives a program, a control trigger, and a radar system reference clock signal 136, which is used for chirp generation at chirp generator 137 or for received signal processing in receiver 110. For example, the reference clock signal is a local oscillator (LO) signal, and the control trigger is a chirp start trigger signal input to chirp generator 137 to generate radar chirp sequences, which are further processed (e.g., by RF conditioning components 108 and PA 106) before being transmitted by transmit antenna 120 of radar front-end 102. Chirp generator 137 is configured to generate one or more radar chirp sequences for each of transmitters 104-1 to 104-N. For example, chirp generator 137 is configured to generate a single radar chirp sequence, which is then transmitted to each of transmitters 104-1 to 104-N. In some embodiments, chirp generator 137 includes a phase-locked loop (PLL) that generates a linear frequency modulated chirp sequence. For example, the PLL in chirp generator 137 generates an FMCW chirp sequence for transmission by transmitter 104. In the illustrated embodiment, the transmit signal generation component is chirp generator 137. In other embodiments, the transmit signal generation component is a pulse generator or a digital radar modulation component. Therefore, while the following embodiments describe transmission and signal processing techniques related to chirped radar waveforms, in other embodiments, transmit power shaping and signal processing techniques can also be applied to pulse-based and digitally modulated radar waveforms.
[0037] The radar front-end 102 also includes a transmitting antenna 120. In some embodiments, each transmitter 104 is configured with its own transmitting antenna 120 (i.e., transmitter 104-1 with transmitting antenna 120-1, transmitter 104-2 with transmitting antenna 120-2, transmitter 104-3 with transmitting antenna 120-3, and transmitter 104-N with transmitting antenna 120-N). The transmitter 104 transmits a transmitted signal 124 to one or more objects 126 (one is shown for clarity). The transmitted signal is reflected from the object 126, and the object-reflected signal 128 (also referred to herein as "radar reflection" or simply reflection) is guided back to the radar system 100. The reflection 128 is received by receiving antennas 130-1 to 130-M. In some embodiments, each receiver 110 is configured with its own receiving antenna 130 (i.e., receiver 110-1 with receiving antenna 130-1, receiver 110-2 with receiving antenna 130-2, receiver 110-3 with receiving antenna 130-3, and receiver 110-M with receiving antenna 130-M). In addition to receiving the reflected signal 128, receiver 110 may also receive other unwanted signals. For example, interference source 132 (in this example, radar signal from another vehicle) emits interference 134, which is also received by receiver 110.
[0038] In some embodiments, the radar front-end 102 further includes a plurality of receivers 110-1 to 110-M (collectively referred to as receivers 110). One or more receivers 110 include a low-noise amplifier (LNA) 112, a de-slope mixer 114, a high-pass filter (HPF) 116, a power amplifier 118, a low-pass filter (LPF) 121, and an analog-to-digital converter (ADC) 122, which digitizes the received radar signal before providing it to a radar signal processor to estimate the range and velocity of the object 126. In this manner, the ADC 122 of each of receivers 110-1 to 110-N is as follows: Figure 2 The processor in the radar main controller processing unit shown generates the digitized received radar signal (indicated by the circle 2).
[0039] Now for reference Figure 2In some embodiments, the radar system 100 includes a radar main controller processing unit (MCPU) 138. In some embodiments, the radar MCPU 138 includes a radar controller 140 and a receiver (RX) processor 142. The radar controller 140 provides a program, control trigger, and radar system reference clock signal 136 as described above. The receiver processor 142 receives digitized signals from the radar front end 102, such as from the ADC 122 of the receiver 110. In some embodiments, the RX processor 142 includes an interference cancellation component 144 that provides interference-suppressed ADC samples 146. A fast-time (range) spectrum component 148 receives and processes the interference-suppressed ADC samples 146. For example, the fast-time spectrum component 148 applies a first window in the fast time to the interference-suppressed ADC samples 146, and then applies an FFT in the fast time of the windowed samples. In this way, the fast-time spectrum component 148 provides range chirp data 150 indicating chirped reflections received at the receiving antenna 130. In some embodiments, the range chirp data 150 is cubiced using the x and y axes composed of fast-time data and the z axis representing the data of each of the receiving antennas 130. The range chirp data 150 is received and processed by a slow-time (velocity or Doppler) spectrum component 152. For example, the slow-time spectrum component 152 applies a second window in the slow time to the range chirp data 150, and then applies an FFT to the windowed samples in the slow time. In this way, the slow-time spectrum component 152 provides range-Doppler data 154, which is cubiced using the x and y axes composed of slow-time data and the z axis representing the data of each of the receiving antennas 130. In some embodiments, the range-Doppler data 154 is received and processed by a constant false alarm rate (CFAR) detection component 156. The detection component 156 provides detected range and Doppler cell data 158. A multiple-input multiple-output (MIMO) array measurement construction component 160 receives and processes detected range and Doppler cell data 158. The MIMO array measurement construction component 160 provides an array measurement vector 162. The array measurement vector is received and processed by an object angle of arrival (AoA) estimation component 164. The object AoA estimation component 164 provides object information 166, attributed to the object 126 detected by the radar system 100, to other components via a data interface 170. These other components may include, for example, software modules executed by a processor to implement advanced driver assistance systems (ADAS) or autonomous driving (AD) perception and vehicle control systems.
[0040] In some embodiments, the radar system 100, including radar front-end 102 and radar MCPU 138, is configured to perform the frequency and timing offset correction techniques described herein. For example, in some cases, radar front-end 102 is one of multiple radar front-ends 102, and radar system 100 is a distributed radar system. Radar front-end 102 includes an up-conversion circuitry system 175 (also referred to herein as an "up-conversion converter") to up-convert a radar front-end 102 reference clock signal (e.g., generated by a local reference clock source at radar front-end 102) into a second signal 177 with a higher frequency, which is input to other components of radar front-end 102 (e.g., chirp generator 137). Chirp generator 137 uses the second signal 177 to modulate the dwell time between chirps of the generated radar chirp signal. For example, the chirp generator 137 modulates the dwell time between chirps so that the chirp is more closely aligned with the corresponding chirp of another radar chirp signal generated at another radar front-end 102 in the distributed radar system 100. In this way, multiple radar front-ends 102 transmit radar signals with minimized or eliminated frequency and timing offsets, which improves the performance of the radar system 100.
[0041] Figure 3 An example of a vehicle control system 300 according to some embodiments is shown. The vehicle control system 300 is implemented, for example, in a car and can be used to assist driver assistance or autonomous driving functions. As shown, the vehicle control system 300 includes a distributed radar system 301, which includes radar front-ends 306, 308 and a radar MCPU 304. In some embodiments, each of the radar front-ends 306, 308 corresponds to... Figure 1 A separate implementation of the radar front-end 102, and the radar MCPU 304 corresponding to Figure 2 The radar MCPU 138 in the system.
[0042] In some embodiments, the vehicle control system 300 includes an electronic control unit (ECU) 302. The ECU 302 includes a radar MCPU 304 and other processing circuitry, such as a central processing unit (CPU), for performing various processing functions related to vehicle control. The radar MCPU 304 is coupled to radar front-ends 306, 308 via an interface 320. Although Figure 3Two radar front-ends 306, 308 are shown, but this number is for clarity and can be expanded to a larger number. In some embodiments, radar front-ends 306, 308 are located at various locations around the vehicle housing the vehicle control system 300. For example, one radar front-end 306 is located at the front of the vehicle, while the other radar front-end 308 is located at the rear of the vehicle. In some embodiments, radar front-end 306 includes a plurality of antennas 316, 318. For example, the plurality of antennas 316 are transmitting antennas, and the plurality of antennas 318 are receiving antennas. Similarly, in some embodiments of radar front-end 308, the plurality of antennas 326 are transmitting antennas, and the plurality of antennas 328 are receiving antennas. In some embodiments, the plurality of antennas associated with each of radar front-ends 306, 308 support a MIMO radar configuration. Although two antennas are shown for each of the plurality of antennas 316, 318, 326, 328, this number is for clarity and can be expanded to a larger number (e.g., three, four, or more antennas) in some embodiments.
[0043] In some embodiments, the radar MCPU 304 is implemented as a microcontroller unit (MCU) or other processing unit configured to perform radar signal processing tasks, such as, but not limited to, calculations of object recognition, object range, object velocity, and object orientation (collectively, "radar information"). In some embodiments, the radar MCPU 304 is further configured to generate control signals based on the radar information. The radar MCPU 304 is configured, for example, to generate calibration signals, receive data signals, receive sensor signals, generate spectrum shaping signals (e.g., signals associated with the FCMW radar technology described herein) and / or state machine signals for RF circuit enable sequences. Additionally, in some embodiments, the radar MCPU 304 is configured to program the radar front-ends 306, 308 to transmit MIMO waveforms for use with radar signals from radar front-ends 306, 308. Figure 3 The combination of distributed apertures formed by the multiple transmitting and receiving antennas shown constructs virtual apertures to operate in a coordinated manner.
[0044] In some embodiments, radar front-ends 306, 308 include radar front-end chip circuitry coupled to corresponding plurality of antennas to transmit radar signals (e.g., in the form of radar chirp sequences), receive reflected radar signals, and digitize these received radar signals for forwarding to radar MCPU 304 via interface 320. In some embodiments, radar MCPU 304 performs radar processing tasks based on the digitized radar signals received from radar front-ends 306, 308 to provide radar information to ECU 302. ECU 302 uses this radar information to control one or more actuators 310, such as steering actuators, brake actuators, or throttle actuators, to assist driver assistance or autonomous driving functions. In some embodiments, ECU 302 displays the radar information or associated information via a user interface 312 (e.g., a screen display, speaker, or light) (e.g., in a side mirror or on the dashboard) to warn the driver of the presence of an object nearby.
[0045] Figure 4 An example of a radar front-end 400 employing frequency and timing offset minimization techniques according to some embodiments is shown. The radar front-end 400, for example, corresponds to... Figure 1 The radar front end 102, or Figure 3 One of radar front-ends 306 and 308. In the illustrated embodiment, radar front-end 400 includes an up-conversion converter 402, a chirp generator 404, digital hardware 406 implementing a timing engine 408, a receive (Rx) chain 412, and an ADC 414. Radar front-end 400 also includes one or more transmit antennas 422 (one transmit antenna is shown for clarity) and one or more receive antennas 424 (one receive antenna is shown for clarity). In some embodiments, up-conversion converter 402 corresponds to Figure 1 The up-conversion circuit system 175, the chirp generator 404 corresponds to Figure 1 The chirp generator 137, the transmitting antenna 422 corresponds to Figure 1 The transmitting antenna is 120-1, and the receiving antenna corresponds to... Figure 1 The receiving antenna 130-1, Rx chain 412 corresponds to Figure 1 Components 112, 114, 116, 118, and 121, and ADC 414 corresponds to Figure 1 The ADC 122. In some cases, the radar front-end 400 includes additional components not shown in the illustrated embodiment.
[0046] Upconverter 402 is configured to receive a reference clock signal 430 at a first frequency (e.g., 10-100 MHz). The reference clock signal 430 is generated, for example, by a reference clock 470 of radar front-end 400. Upconverter 402 upconverts the lower-frequency reference clock signal 430 with the first frequency into a second signal 432 with a higher frequency. For example, if the reference clock signal 430 is 40 MHz, upconverter 402 generates a second signal 432 of 640 MHz. Upconverter 402 outputs the second signal 432 to chirp generator 404, timing engine 408 in digital hardware 406, and ADC 414. In some embodiments, upconverter 402 includes hardware, software, or a combination thereof to perform the upconversion. For example, in some cases, upconverter 402 includes a PLL circuit system such as a phase detector, a low-pass filter, and a voltage-controlled oscillator (VCO) to generate the second signal 432 based on the received reference clock signal 430.
[0047] Digital hardware 406 includes hardware, software, or a combination thereof to implement a timing engine 408 for radar front-end 400. For example, digital hardware 406 includes one or more processors or other circuitry that execute instructions associated with implementing timing engine 408. Digital hardware 406 and timing engine 408 generate timing control signals that are used by other components in radar front-end 400 to perform various functions. For example, timing engine 408 generates a chirp timing control signal 435 based on a second signal 432 received from upconverter 402. Timing engine 408 outputs chirp timing control signal 435 to chirp generator 404 to control the amount of time (i.e., dwell time) between consecutive chirps in the generated radar chirp signal 438 (e.g., by controlling the number of clock cycles). For example, in some embodiments, timing engine 408 generates chirp timing control signals to increase the number of clock cycles between a pair of consecutive chirps in the generated radar chirp signal 438 (thus increasing the dwell time). In some cases, the increase in the number of clock cycles between consecutive chirps is constant (i.e., the same) across all chirps in the generated radar chirp signal 438. In other cases, the increase in the number of clock cycles between consecutive chirps is applied every x chirps, where x is a positive integer greater than 1, such as 2, 3, 4, or more. In the illustrated embodiment, digital hardware 406 also generates an ADC control signal 437, which is output to ADC 414 to, for example, control the sampling start time of ADC 414. In some cases, digital hardware 406 is also configured to receive a chirp string start signal 434 based on a second signal 432. In some cases, the chirp string start signal 434 is an asynchronous chirp string start signal with a specific jitter value. For example, if the second signal 432 is 640 MHz, the jitter value in the chirp string start signal 434 is 1.5 ns.
[0048] Chirp generator 404 receives a second signal 432 from an upconversion converter and a chirp timing control signal 435 from a timing engine 408 as inputs, and generates a radar chirp signal 438 as output. In some embodiments, chirp generator 404 includes a PLL circuit system, such as a phase detector, a low-pass filter, and a VCO, to generate the radar chirp signal 438. In the illustrated embodiment, chirp generator 404 also generates an output signal 436, which is fed to Rx chain 412 for processing the received radar reflection 442. For example, output signal 436 is input to a mixer in Rx chain 412 (e.g., corresponding to...). Figure 1 (The mixer of the de-ramp mixer 114). The radar chirp signal 438 includes one or more radar frames with multiple chirs. For example, in some cases, the radar frame includes 256 chirs, for example... Figure 6The chirp is shown. The chirp generator 404 generates a radar chirp signal 438 by modulating a plurality of parameters, including one or more of the center frequency, dwell time between consecutive chirs, and chirp slope, based on the received second signal 432 and / or chirp timing control signal 435. Although not shown in the illustrated embodiment, in some cases, the radar front-end 400 includes additional hardware between the chirp generator and the transmitting antenna 422, for example, corresponding to… Figure 1 The hardware of the RF signal conditioning component 108 and the power amplifier 106.
[0049] The transmitting antenna 422 transmits a radar signal 440 based on a radar chirp signal 438 received from the chirp generator 404 into the surrounding environment, and the receiving antenna 424 receives the reflection 442 of the transmitted radar chirp signal 440 after it has been reflected from one or more objects 480 in the surrounding environment. The receiving antenna 424 outputs the received radar reflection signal 450 to the Rx chain 412. The Rx chain 412 includes various processing and filtering components (e.g., such as...) that output the signal 452 to the ADC 414. Figure 1 LNA 112 and other LNAs, for example Figure 1 De-ramp mixers such as 114, etc. Figure 1 HPF 116 and other HPF, for example Figure 1 Power amplifiers such as the 118 power amplifier, and such as Figure 1 The ADC 414, using an LPF such as LPF 121, samples the output signal 452 based on other inputs (e.g., one or more of signals 437, 432) to generate a digital signal 454 output from the radar front-end 400. For example, the digital signal 454 is transmitted to the radar MCPU, such as... Figure 2 The radar MCPU 138.
[0050] In some embodiments, the radar front-end 400 is, for example... Figure 3Radar front-end 400 is one of multiple radar front-ends in a distributed radar system, such as radar system 300. Radar front-end 400 is configured to compensate for frequency and / or timing offsets with other radar front-ends in the distributed radar system by modulating one or more of the center frequency and dwell time of the chirp in the transmitted radar signal 440 and implementing additional signal processing techniques. By employing an up-converter 402 to generate a second signal 432 at a higher frequency than the reference clock signal 430, radar front-end 400 can achieve finer granularity (e.g., on a nanosecond scale) for modulating the dwell time between radar chirps to better align the chirp with other radar front-ends in the radar system within a tolerance threshold (2 nanoseconds or less, e.g., about 1.5-1.6 nanoseconds for the higher frequency second signal 432 at 640 MHz), and for controlling the center frequency to minimize the frequency offset of the chirp relative to other transmitted radar signals from other radar front-ends. Additionally, the higher frequency second signal 432 provides the additional benefit of reducing jitter in the chirp string start signal 434.
[0051] In other words, the radar front-end 400 compensates for crystal frequency shifts caused by tolerances and temperature differences between crystals in multiple radar front-ends of a distributed radar system by implementing a frequency upconverter 402 to generate a higher-frequency signal (i.e., the second signal 432) for chirp generation. Furthermore, compared to conventional techniques employing, for example, digital crystal oscillators, the radar front-end 400 does not cause frequency shifts in the generated range-Doppler data (e.g., Figure 2 This introduces additional artifacts or distortions into the range Doppler data (154). Furthermore, by using a high clock frequency (of the second signal 432) to drive the timing engine 408 in the digital hardware 406, the radar front-end 400 can control the dwell time between chirps to reduce timing offset compared to other radar front-ends in the radar system.
[0052] Figure 5 The diagram illustrates a first graph 500 and a second graph 520 in a distributed radar system with similar dwell time settings in two radar front-ends according to conventional technology. The first graph 500 shows a first chirped sequence 502 transmitted by a first radar front-end, and the second graph 520 shows a second chirped sequence 522 transmitted by a second radar front-end. The x-axis in both graphs represents time, and the y-axis represents frequency.
[0053] Referring to graph 500, the first chirp sequence 502 includes a first plurality of chirps 502-1, 502-2, 502-3, and 502-4. The dwell time in the first chirp sequence 502 is the time period between consecutive chirps. Lines 510-1, 510-2, 510-3, and 510-4 show the end time of each chirp in the first plurality of chirps 502-1, 502-2, 502-3, and 502-4, respectively (i.e., line 510-1 shows the starting point of the dwell time between chirps 502-1 and 502-2, and the end point of the dwell time between chirps 502-1 and 502-2 is the beginning of chirp 502-2). On the y-axis of graph 500, X represents the center frequency, and X+B represents the center frequency (X) plus the chirp bandwidth (B).
[0054] Referring to graph 520, the second chirp sequence 522 includes a second plurality of chirps 522-1, 522-2, 522-3, and 522-4. The dwell time in the second chirp sequence 522 is the time period between consecutive chirps. For example, the dwell time 524 between chirps 522-1 and 522-2 is marked. On the y-axis of graph 520, X(1+Δ) represents the influence of the frequency offset (Δ) of the center frequency (X) relative to the first chirp sequence 502 of graph 500, and (X+B)(1+Δ) represents the influence of the frequency offset (Δ) and chirp bandwidth (B) of the second chirp sequence 522 on the center frequency (X).
[0055] exist Figure 5In the distributed radar system, a first radar front-end transmits a first chirp sequence 502, and a second radar front-end in the same system transmits a second chirp sequence 522 using the same dwell time, PLL chirp slope, and center frequency settings. However, due to the crystal clock frequency offset between the radar front-ends, the first and second radar front-ends use different crystal clock frequencies. This difference in crystal clock frequencies results in a frequency offset (Δ) in the center frequency of the chirp, an increase in the chirp slope of one chirp sequence relative to the other, and an increase in the maximum chirp bandwidth value, as indicated by the chirp bandwidth offset δ. Furthermore, the difference in crystal clock frequencies causes the start times of the corresponding chirps of the first chirp sequence 502 and the second chirp sequence 522 to drift significantly apart. That is, when the first chirp 502-1 in the first chirp sequence 502 and the first chirp 522-1 in the second chirp sequence 522 are aligned to overlap each other during a time period in the radar frame (e.g., defined by the time period preceding line 510-1), subsequent chirps in the chirp sequences drift further and further apart from each other. For example, the fourth chirp 502-4 in the first radar chirp sequence 502 and the fourth chirp 522-4 in the second radar chirp sequence 522 overlap each other only to a relatively small extent, especially when compared to the first chirps 502-1 and 522-1 in the corresponding chirp sequences 502 and 522. This difference causes the first radar front-end to sample the received radar reflections when the second radar front-end is not transmitting. This reduces the SNR of the received radar reflections, thereby degrading the performance of the radar system.
[0056] Figure 6 A first graph 600 and a second graph 620 are shown according to some embodiments with different dwell time settings in the radar front end. The first graph 600 shows a first chirp sequence 602 transmitted by a first radar front end, and the second graph 620 shows a second chirp sequence 622 transmitted by a second radar front end. The x-axis in the first graph 600 and the second graph 620 represents time, and the y-axis in the first graph 600 and the second graph 620 represents frequency.
[0057] Referring to graph 600, the first chirp sequence 602 includes a first plurality of chirps 602-1, 602-2, 602-3, and 602-4. The dwell time in the first chirp sequence 602 is the time period between consecutive chirps. Lines 610-1, 610-2, 610-3, and 610-4 show the end time of each chirp in the first plurality of chirps 602-1, 602-2, 602-3, and 602-4, respectively (i.e., line 610-1 shows the starting point of the dwell time between chirps 602-1 and 602-2, and the end point of the dwell time between chirps 602-1 and 602-2 is the beginning of chirp 602-2). On the y-axis of graph 600, X represents the center frequency, and X+B represents the center frequency (X) plus the chirp bandwidth (B).
[0058] Referring to graph 620, the second chirp sequence 622 includes a second plurality of chirps 622-1, 622-2, 622-3, and 622-4. The dwell time in the second chirp sequence 622 is the time period between consecutive chirps. For example, dwell time 624-1 is between the first chirp 622-1 and the second chirp 622-2, dwell time 624-2 is between the second chirp 622-2 and the third chirp 622-3, and dwell time 624-3 is between the third chirp 622-3 and the fourth chirp 622-4. On the y-axis of graph 620, X represents the center frequency (X), and X+B(1+Δ) represents the center frequency (X) plus the chirp bandwidth (B) affected by the frequency offset (Δ) of the second chirp sequence 622 relative to the first chirp sequence 602.
[0059] like Figure 6 As shown, with Figure 5 Compared to chirp sequences 502 and 522, the corresponding chirps in the first chirp sequence 602 and the second chirp sequence 622 are more closely aligned with each other. That is, by employing different dwell time settings at each of the first and second radar front-ends, the radar system can achieve improved coherence between the radar front-ends. The different dwell time settings are at least partially attributable to at least one of the radar front-ends (e.g., the second radar front-end corresponding to curve 620) employing an up-conversion converter (e.g., Figure 1 Up-converter 175 or Figure 4 The up-conversion converter 402 generates a higher frequency signal from the lower frequency reference clock signal received at the second radar front end. This is achieved by up-converting the lower frequency reference clock signal to a higher frequency signal (e.g., corresponding to...). Figure 4(The second signal 432), the timing engine of the radar front end can more finely tune the dwell time between chirps in the second chirp sequence 622 in order to more closely align the chirps with the chirps in the first chirp sequence 602 within a tolerance threshold determined based on the frequency of the upconverted higher frequency signal. For example, a higher frequency signal of 640 MHz allows the dwell time between chirps in the second chirp sequence 622 to be tuned with a granularity of about 1.5-1.6 nanoseconds, the granularity corresponding to the tolerance threshold used to align the chirps in the second chirp sequence 622 with the chirps in the first chirp sequence 602. That is, in some embodiments, the tolerance threshold may be defined by 1 / X, where X is the upconverted higher frequency. In some cases, the timing engine in the second radar front end (such as...) Figure 4 (As shown) The dwell times 624-2, 624-3 are set by modulating (e.g., increasing or decreasing) the number of clock cycles between radar chimes 622-3, 622-4 to better align the radar chimes 622-3, 622-4 with the corresponding radar chimes 602-3, 602-4 of the first radar chime sequence 602 in the time domain (i.e., along the x-axis). That is, the second radar front end provides this improved dwell time control due to the higher frequency second signal generated by the upconverter, which in turn allows the timing engine to control the dwell time between chimes with finer resolution. For example, if the upconverter generates a 640 MHz signal from a 40 MHz reference clock signal, the second radar front end is able to modulate the dwell time between radar chimes with a granularity of approximately 1.5 nanoseconds (ns) compared to the 25 ns granularity when only a 40 MHz reference clock signal is used. In addition, by using a higher frequency signal (e.g., Figure 4 The second signal 432), the second radar front-end can also reduce or eliminate the frequency offset (Δ) with the first radar front-end. Therefore, generating Figure 6 The radar system with the chirped sequence shown employs an up-converter (e.g., as shown in the image) in at least one of the two radar front-ends. Figure 4 As shown, this improves coherence in both the time and frequency domains of the radar sequences generated at each of its two radar front-ends. This increases the SNR of the received reflections, thereby improving the performance of the radar system.
[0060] In some embodiments, the second radar front end corresponding to the curvature 620 modulates the dwell time 624 between chimes by a constant amount. In other embodiments, the second radar front end corresponding to the curvature 620 modulates the dwell time 624 between chimes by a dynamic amount. For example, the second radar front end modulates the dwell time based on the number of chimes in the radar frame (e.g., later chimes have a larger dwell time, or the dwell time increases for every x chimes, where x is a positive integer greater than 1).
[0061] Figure 7 An example of a flowchart 700 according to some embodiments is shown, illustrating a method for generating radar chirp signals based on higher frequency signals to modulate the dwell time between chirps. In some aspects, the method shown in flowchart 700 is derived from, for example... Figure 4 The radar front-end 400 and other radar front-end implementations.
[0062] At block 702, the radar front end receives a first signal having a first frequency. For example, the up-converter 402 in the radar front end 400 receives a reference clock signal 430 having a frequency of 40 MHz from the reference clock source 470 of the radar front end 400.
[0063] At block 704, an up-converter in the radar front end up-converts the first signal to a second signal with a second frequency. For example, up-converter 402 up-converts the reference clock signal 430 to a second signal 432 with a frequency of 640 MHz.
[0064] At block 706, the radar front-end generates a first radar chirp signal by modulating the time period (or dwell time) between chirps based on a second frequency. For example, the chirp generator 404 in the radar front-end 400 generates a radar chirp signal 438 based on a second signal 432 having a frequency of 640 MHz. That is, in some embodiments, the chirp generator 404 generates the radar chirp signal 438 based on a chirp timing control signal 435 received from a timing engine 408 in the digital hardware 406, wherein the chirp timing control signal 435 is generated based on the second signal 432.
[0065] At box 708, the radar front-end transmits a first radar chirp signal. For example, radar front-end 400 transmits radar signal 440 from transmit antenna 422 based on radar chirp signal 438 generated at chirp generator 404.
[0066] In some embodiments, certain aspects of the techniques described above may be implemented by one or more processors of a processing system executing software. Software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. Software may include instructions and certain data that, when executed by the one or more processors, manipulate the one or more processors to perform one or more aspects of the techniques described above. Non-transitory computer-readable storage media may include, for example, disk or optical disk storage devices, solid-state storage devices (e.g., flash memory), caches, random access memory (RAM), or other non-volatile memory devices. Executable instructions stored on the non-transitory computer-readable storage medium may be source code, assembly language code, object code, or other instruction formats that can be interpreted or otherwise executed by one or more processors.
[0067] Computer-readable storage media can include any storage medium or combination of storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media can include, but are not limited to, optical media (e.g., compact disc (CD), digital versatile disc (DVD), Blu-ray disc), magnetic media (e.g., floppy disk, magnetic tape, or magnetic hard disk), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical systems (MEMS) based storage media. Computer-readable storage media can be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., magnetic hard disk), removably attached to a computing system (e.g., optical disc or USB-based flash memory), or coupled to a computer system via a wired or wireless network (e.g., network accessible storage device (NAS)).
[0068] It should be noted that not all activities or elements described in the general description above are necessary. A particular activity or part of the apparatus may be unnecessary and may perform one or more additional activities besides those described, or may include one or more additional elements besides those described. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. These concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes can be made without departing from the scope of this disclosure as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative rather than restrictive sense, and all such modifications are contemplated to be included within the scope of this disclosure.
[0069] The benefits, other advantages, and solutions to the problem have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to the problem, and any features that may cause any benefit, advantage, or solution to appear or become more apparent should not be construed as essential, necessary, or fundamental features of any or all claims. Furthermore, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter can be modified and practiced in different but equivalent ways, as will be apparent to those skilled in the art who benefit from the teachings herein. No limitation is intended to be imposed on the details of the constructions or designs shown herein, other than those set forth in the appended claims. It is therefore apparent that the specific embodiments disclosed above can be altered or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as set forth in the appended claims.
Claims
1. A method, characterized in that, include: In a distributed radar system, a first signal with a first frequency is up-converted at the up-conversion converter at the first radar front-end to a second signal with a second frequency higher than the first frequency. A first radar chirp signal is generated at a chirp generator at the front end of the first radar, wherein the chirp generator modulates the time period between consecutive chirs in the first radar chirp signal based on a second signal; and The first radar chirp signal is transmitted from the front end of the first radar.
2. The method according to claim 1, characterized in that, In addition, including: A second radar chirp signal is generated at the chirp generator at the second radar front-end of the distributed radar system; as well as The second radar chirp signal is transmitted from the front end of the second radar. The chirp generator of the first radar front end modulates the time period between consecutive chirps in the first radar chirp signal based on the start time of the second signal and the chirps in the second radar chirp signal.
3. The method according to claim 2, characterized in that, The start time of each chirp in the first radar chirp signal and the start time of the corresponding chirp in the second radar chirp signal are aligned with each other within a tolerance threshold determined based on the second frequency of the second signal, wherein the alignment is based on the second frequency at the front end of the first radar.
4. The method according to claim 2, characterized in that, The first radar front-end and the second radar front-end have different dwell time settings, wherein the dwell time setting of the first radar front-end is set based on aligning the chirp of the first radar chirp signal with the chirp of the second radar chirp signal.
5. The method according to claim 2, characterized in that, In addition, including: The dwell time of the first radar front end is modulated based on the frequencies of the second signal and the second radar chirp signal.
6. A radar front-end, characterized in that, include: Upconverter, which is configured to: A first signal is received from a reference clock source at the radar front end, wherein the first signal has a first frequency, and The first signal is up-frequency converted into a second signal with a second frequency; A chirp generator, configured as follows: The first radar chirp signal is generated by modulating the time period between consecutive chirps in the first radar chirp signal based on the second signal; and The transmitter is configured to transmit the first radar chirp signal.
7. The radar front-end according to claim 6, characterized in that, The first time period between the first pair of consecutive chirps in the first radar chirp signal is modulated to a first time length, and wherein the second time period between the second pair of consecutive chirps is modulated to a second time length different from the first time length by adjusting the number of clock cycles between the second pair of consecutive chirps in the first radar chirp signal.
8. A distributed radar system, characterized in that, include: The first radar front-end is configured to generate a first radar chirp signal based on a reference clock signal received from a first reference clock source; as well as The second radar front-end is configured to generate the second radar chirp signal by modulating the time period between consecutive chirps in the second radar chirp signal based on a second frequency signal, the second frequency signal being generated by up-converting a reference clock signal received from a second reference clock source.
9. The distributed radar system according to claim 8, characterized in that, The second radar front end is further configured to generate the second radar chirp signal based on aligning the chirp in the second radar chirp signal with the corresponding chirp in the first radar chirp signal within a tolerance threshold, wherein the alignment is performed by modulating the number of clock cycles between the chirps in the second radar chirp signal.
10. The distributed radar system according to claim 8, characterized in that, In addition, including: One or more additional radar front-ends, each of which is configured to generate a corresponding additional radar chirp signal by modulating the time period between consecutive chirps in a corresponding additional radar chirp signal based on a corresponding second frequency signal, the corresponding second frequency signal being generated by up-converting the reference clock signal received from the reference clock source.