A chip mapping method and program product for space-borne synthetic aperture radar imaging

Abstract

The embodiment of the application provides a chip mapping method and program product for space-borne synthetic aperture radar imaging, the method comprising: performing structural analysis on a data flow graph describing a synthetic aperture radar imaging algorithm, determining a mapping anchor point from the data flow graph, the mapping anchor point being a sink node in the data flow graph having at least two in-edges and at least two out-edges; determining a communication efficiency measurement value of each computing unit in a hardware platform of a target chip; determining an initial mapping position for the mapping anchor point from the hardware platform based on attribute information of the mapping anchor point and the communication efficiency measurement value, and performing mapping search starting from the initial mapping position. The mapping search space is compressed from the source, invalid search branches are reduced, and the mapping efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of radar technology, and more specifically, to a chip mapping method and program product for spaceborne synthetic aperture radar imaging. Background Technology

[0002] Synthetic Aperture Radar (SAR), as an active microwave imaging sensor, possesses all-weather, all-day Earth observation capabilities and is an integral part of modern Earth observation technology. On-orbit real-time processing technology for spaceborne SAR is currently a research hotspot. It deploys high-performance computing units on satellite platforms to directly process raw echo data, thereby shortening the information acquisition chain and improving response capabilities for scenarios with extremely high timeliness requirements, such as disaster monitoring and military reconnaissance.

[0003] However, the implementation of on-orbit processing technology for spaceborne SAR faces a contradiction: the power consumption, size, and weight budgets of satellite platforms are extremely stringent, while SAR imaging algorithms (such as Range Doppler Algorithm (RDA) and Linear Frequency Scaling Algorithm (CSA)) are computationally intensive and have huge data throughput. This makes it difficult for traditional solutions based on general-purpose processors or FPGAs to simultaneously meet the requirements of high performance and flexibility within a limited power budget.

[0004] Against this backdrop, multi-core computing chips, especially heterogeneous multi-core chips designed for specific domains, have become a highly promising solution due to their ideal balance between energy efficiency and flexibility. Unlike traditional single-core processors or homogeneous multi-core processors, multi-core computing chips for SAR imaging typically integrate multiple heterogeneous computing elements (PEs) on a single chip. These computing elements are not simple CPU core copies, but contain hardware units designed for specific operations, such as Fast Fourier Transform (FFT) units, coordinate rotating digital computers (CORDIC) units, and complex multipliers. They are connected through efficient on-chip interconnect networks (such as crossbars or multilayer switching networks) to form a reconfigurable computing array. This architecture has significant advantages: it eliminates the overhead of instruction fetching and decoding through dedicated computing units, achieving extremely high computational density and energy efficiency; through on-chip networks and configurable data flow scheduling, it can flexibly adapt to changes in the operation modes of different algorithms and processing stages in SAR imaging; its regular array structure and deterministic interconnects naturally match the regular data flow of SAR imaging, supporting deep static optimization by the compiler.

[0005] Currently, there are successful cases of integrating multi-mode SAR imaging processing into a single ASIC chip. One example is a multi-mode SAR imaging chip based on a reconfigurable SoC architecture with dual computing engines and a multi-layer switching network. This chip analyzes the extended Chirp Scaling (ECS) algorithm, decomposing computational operations into eight types of dual computing engines (including FFT-multiplication, multiplication-exponential, multiplication-addition, multiplication-division, two multiplications, square root-multiplication, square root-addition, trigonometric function-division, etc.). Each engine uses a unified three-input, one-output interface and internally includes a data preprocessing unit (DI), a computational core (CORE), and a data post-processing unit (DO). The chip uses a three-layer switching network to connect these engines: the top layer network handles data interaction between the factor calculation part and the FFT-multiplication part; the second layer network is dedicated to the FFT-multiplication part (containing two parallel FFT modules); and the third layer network provides fine-grained data exchange for factor calculation. The entire network is based on the AXI4 architecture and supports data flow-driven scheduling. The chip adopts a SoC architecture, integrating an ARM CPU subsystem, a data transfer subsystem, a computing engine subsystem, a memory subsystem (20MB on-chip storage, supporting external DDR3), a high-speed interface (SERDES), and global control logic. The CPU is responsible for scheduling the engine according to the imaging mode to implement a data stream-driven processing flow. The chip is implemented using a 65nm SMIC process, with a chip area of ​​35mm × 35mm, integrating approximately 20 million logic gates, operating at a frequency of 200MHz, and a typical power consumption of 6.147W. It processes 16384×16384 pixel stripe mode data in 9.2 seconds, with a total system power consumption of 6.9W. This verifies that a multi-core processor for SAR imaging can meet the stringent requirements of spaceborne real-time processing in terms of performance, area, and power consumption.

[0006] However, the chip's computing engine scheduling and task mapping are still handled by the CPU through software instructions. When the algorithm complexity increases further or more modes need to be supported, manual or semi-automatic mapping methods will face a huge search space. Therefore, a more intelligent and automated mapping method is needed. Summary of the Invention

[0007] The purpose of this application is to provide a chip mapping method and program product for spaceborne synthetic aperture radar imaging, so as to achieve the technical effect of compressing the chip mapping search space.

[0008] The first aspect of this application provides a chip mapping method for spaceborne synthetic aperture radar imaging, the method comprising: A structural analysis is performed on the data flow graph describing the synthetic aperture radar imaging algorithm, and mapping anchor points are determined from the data flow graph. The mapping anchor points are the convergence nodes in the data flow graph that have at least two incoming edges and at least two outgoing edges. Determine the communication efficiency metric for each computing unit in the hardware platform of the target chip; Based on the attribute information of the mapping anchor point and the communication efficiency metric, an initial mapping position is determined for the mapping anchor point from the hardware platform, and a mapping search is performed starting from the initial mapping position.

[0009] In the above implementation, by identifying nodes with multi-source convergence characteristics from the data flow graph describing the SAR imaging algorithm as mapping anchors, and determining the optimal initial mapping position for these anchors based on the communication efficiency metric of the hardware platform, the starting point of subsequent global mapping searches can be guided to a highly promising finite subspace. This compresses the mapping search space from the source, reduces invalid search branches, and improves mapping efficiency.

[0010] Furthermore, the structural analysis of the data flow graph describing the synthetic aperture radar imaging algorithm, and the determination of mapping anchor points from the data flow graph, includes: Perform a mandatory node analysis on the data flow graph to identify one or more mandatory nodes as candidate anchor points; When multiple candidate anchor points are identified, the mapping anchor point is determined from the multiple candidate anchor points based on the number of available computing units on the target chip for each candidate anchor point.

[0011] In the above implementation process, the multi-source convergence nodes in the SAR imaging algorithm data flow graph are identified as candidate anchor points through the analysis of necessary nodes. Based on the scarcity of hardware resources (i.e. the number of available computing units), a unique mapping anchor point is selected from them. This transforms the original random or fixed rule-dependent mapping starting point selection into a deterministic selection guided by the algorithm structure characteristics and hardware resource distribution, thereby reducing invalid search branches.

[0012] Furthermore, the step of performing mandatory node analysis on the data flow graph to identify one or more mandatory nodes as candidate anchor points includes: In the data flow graph, a virtual super source node is determined, and the virtual super source node is connected to all actual source nodes in the data flow graph whose incoming edges are empty. Traverse every node in the data flow graph except for the virtual super source node and all actual source nodes, and for the currently traversed node, perform a search starting from the virtual super source node and prohibit the search through the currently traversed node; If it is impossible to reach the endpoint where all outgoing edges of the data flow graph are empty, then the currently traversed node is determined as the required node.

[0013] In the above implementation process, by introducing a virtual super source point, the multiple source points scattered in the SAR imaging algorithm data flow graph are unified into a single starting point. By adopting the methods of prohibiting passage and depth-first search, the necessary nodes that must be passed from all source points to all endpoints are accurately identified as candidate anchor points. In this way, the inherent multi-source convergence characteristics in the algorithm data flow are automatically captured without manual intervention, providing an accurate and complete candidate set. This ensures that the selection of the mapping starting point can truly focus on the key intersection points of the algorithm structure and guarantees the reliability of search space compression.

[0014] Further, determining the mapping anchor point from multiple candidate anchor points based on the number of available computing units on the target chip for each candidate anchor point includes: The candidate anchor point is selected from multiple candidate anchor points, and the number of computing units in the target chip that are compatible with the candidate anchor point type meets the preset scarcity condition as the mapping anchor point.

[0015] In the above implementation process, from multiple candidate anchor points identified through analysis of necessary nodes, the node with the number of available computing units in the target chip that meets the preset scarcity condition is selected as the final mapping anchor point. This locks the "root" of the mapping search onto the critical node where hardware resources are most scarce. Since the available locations of scarce resources in the chip are extremely limited, this selection strategy compresses the possible placement space of anchor points from the source, allowing the subsequent initial positioning based on communication efficiency to complete the selection within a very small range. This resolves the allocation conflict of scarce resources at the very beginning of the mapping process, avoiding backtracking and mapping failures caused by scarce resource allocation issues.

[0016] Furthermore, the communication efficiency metric for each computing unit in the hardware platform of the target chip includes: The hardware platform is abstracted as a resource graph including computing nodes and routing nodes; For each computing node, the average shortest path distance from the computing node to all routing nodes is determined, and the average shortest path distance is used as a communication efficiency metric for the computing node.

[0017] In the above implementation, the hardware platform is abstracted into a resource graph containing compute nodes and routing nodes. The average shortest path distance from each compute node to all routing nodes is calculated as a communication efficiency metric. This transforms the abstract communication efficiency into an objective and quantifiable numerical indicator—a smaller value indicates a more central topological position of the compute node in the network and lower average communication overhead with other potential compute nodes in the system. This provides an objective and efficient quantitative basis for the initial positioning of mapping anchor points, ensuring that critical nodes are preferentially placed on hardware resources with optimal communication efficiency.

[0018] Furthermore, the communication efficiency metric is calculated using the following formula: ; In the formula, Q represents the total number of routing nodes, and r j This represents the j-th routing node. Indicates from compute node pe i To routing node r j The number of hops for the shortest path.

[0019] In the above implementation, all routing nodes are used as reference points, and the average shortest path hop count is taken. The smaller the value, the stronger the topological centrality of the computing node in the network and the lower the average communication overhead with other potential computing nodes in the system. This ensures that critical nodes can be preferentially placed on hardware resources with the best communication efficiency.

[0020] Further, determining the initial mapping position for the mapping anchor point from the hardware platform based on the attribute information of the mapping anchor point and the communication efficiency metric includes: Select a set of candidate computing units that have the same functional type as the mapping anchor from all computing units; The computing units in the candidate computing unit set are sorted according to the communication efficiency metric, and the initial mapping position of the mapping anchor point is determined from the candidate computing unit set according to the sorting result.

[0021] In the above implementation process, by first selecting a set of candidate computing units with the same functional type as the mapping anchor point, and then sorting the candidate units according to the communication efficiency metric and selecting the best to determine the initial mapping position, the initial position of the anchor point is locked on the hardware resource with the best communication efficiency. Since the communication efficiency metric objectively reflects the centrality of the computing unit in the network topology (the smaller the value, the lower the average communication overhead with other potential computing units in the system), this strategy ensures that the most critical aggregation node in the data flow graph is placed on the hardware resource with a superior topological position from the beginning, thereby providing an efficient starting point for subsequent global mapping search and effectively reducing the overall communication overhead.

[0022] Further, the step of sorting the computing units in the candidate computing unit set according to the communication efficiency metric, and determining the initial mapping position of the mapping anchor point from the candidate computing unit set according to the sorting result, includes: The computing units in the candidate computing unit set are sorted in ascending order according to the communication efficiency metric, and the computing units whose communication efficiency metric meets the preset sorting requirements are determined as the initial mapping positions of the mapping anchor points.

[0023] In the above implementation, ascending sorting ensures that the candidate set is arranged in descending order of communication efficiency, with the computation unit with the best communication efficiency located at the beginning of the sequence. The selection operation only needs to access the first element of the sorted list to complete the operation.

[0024] Further, the step of performing a mapping search starting from the initial mapping position includes: Using the constraint that the mapping anchor point is fixed at the initial mapping position, a global mapping search is performed on the remaining nodes in the data flow graph.

[0025] In the above implementation process, by fixing the mapping anchor point at the initial mapping position with the best communication efficiency as a hard constraint, the problem of allocating scarce resources is solved in advance, so that the subsequent global mapping search can be carried out in a significantly compressed solution space. Since the anchor point has been locked at the optimal position and no longer participates in the subsequent competition, the mapping of the remaining nodes only needs to be carried out in the remaining resources, the number of search branches is greatly reduced, and the convergence speed is improved.

[0026] A second aspect of this application provides a computer program product, the computer program product including a computer program, which, when executed by a processor, implements any of the methods described in the first aspect. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic flowchart illustrating a chip mapping method for spaceborne synthetic aperture radar imaging provided in this application embodiment; Figure 2 This is a schematic diagram of a data flow graph mandatory node detection process provided in an embodiment of this application. Detailed Implementation

[0029] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0030] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0031] Efficiently mapping algorithms (typically modeled as data flow graphs, DFGs) to multi-core processors is a well-known NP-hard problem. The mapping process requires selecting a location for each operation node in the DFG among the numerous cores of the chip and choosing a routing path for each data dependency edge in the interconnect network. As the size of the DFG and the chip increases, the solution space grows exponentially. To address this problem, the main related technologies include the following categories: (1) Metaheuristic search methods: represented by Simulated Annealing (SA), such as the DRESC method. This method finds feasible solutions by performing iterative optimization and random search in a 3D resource graph. These methods can handle large-scale search spaces and ensure basic mapping feasibility. However, their search process is highly random, has a slow convergence speed, and is sensitive to the initial solution—the choice of the initial point directly affects the quality of the final solution and the convergence speed. Due to the lack of guidance on the search direction, the algorithm needs to wander in the huge solution space for a long time to find a feasible solution, resulting in low compilation efficiency.

[0032] (2) Mathematical optimization method: The mapping problem is modeled as Integer Linear Programming (ILP), aiming to find the theoretically global optimal solution. This type of method can guarantee the optimality of the solution, but its computational complexity increases exponentially with the problem size (such as the number of DFG nodes N and the number of computational cores M). For medium-sized problems with dozens of nodes and dozens of computational cores, the solution time of ILP is often several hours or even unacceptable. When N and M increase further, the ILP method will face "exponential explosion" and will be completely unapplicable to large-scale mapping problems in actual engineering.

[0033] (3) Deterministic search and heuristic methods: In order to improve compilation efficiency, researchers have proposed a variety of methods based on deterministic search or heuristic rules, which propose how to determine the mapping order of nodes.

[0034] Priority-based sorting methods, exemplified by GraphMinor, first perform critical path and cycle analysis on the DFG (Dead Path Tree). For each node, the slack (the time difference between ALAP and ASAP) is calculated; lower slack indicates a more critical node. Based on this, GraphMinor generates a list of mapped nodes according to the following priority order: ① Nodes within a cycle take precedence over those outside the cycle; ② Within the same cycle, nodes are sorted by slack from lowest to highest; ③ Nodes outside the cycle are sorted by slack from lowest to highest. The mapping process strictly follows this priority list. This strategy, by prioritizing the mapping of time-critical nodes, can expose performance bottlenecks early and reduce unnecessary backtracking.

[0035] Methods based on graph traversal order, exemplified by PathSeeker, employ a reverse breadth-first search (BFS) approach to determine the mapping order of nodes—that is, mapping successor nodes (nodes closer to the output) first, followed by their predecessor nodes. The motivation behind this design is that once a successor node has been mapped, the predecessor node can proactively select the processing unit connected to it, thereby ensuring data path connectivity and reducing the probability of mapping failures due to connectivity issues.

[0036] However, its limitations are as follows: GraphMinor's priority ranking is entirely based on the DFG graph structure (critical path + cycle), failing to recognize hardware heterogeneity and communication cost distribution, and its ranking strategy does not consider critical nodes converging from multiple sources in the data stream. PathSeeker's inverse BFS order is based on the assumption that the DFG has a single output—inverse BFS requires traversing backwards from a clear endpoint. When the DFG has multiple output nodes, this method cannot directly determine the traversal starting point, requiring additional manual specification or rule selection. SAR imaging algorithms' DFGs often have multiple outputs (such as image output and auxiliary parameter output), and their data convergence nodes (such as intermediate images after range compression) are usually located in the middle of the DFG, neither source nor sink. PathSeeker's inverse BFS cannot identify the criticality of such nodes.

[0037] In summary, the core problem with correlation mapping methods when dealing with multi-core computing chips for spaceborne SAR imaging is excessively long compilation time, partly due to the enormous search space of the mapping problem. Under this premise, correlation methods have the following limitations in their search strategies: (1) Lack of effective guidance on node mapping order. In related methods, the node order is either randomly selected or uses fixed rules (such as input-output order, inverse BFS traversal), failing to prioritize key nodes according to the algorithm's structural characteristics, resulting in a lack of directionality in the search process and wasting a lot of time on invalid branches.

[0038] (2) Lack of consideration in initial hardware positioning. When determining the location of the first mapping node, the relevant methods usually only consider type compatibility and do not take into account the differences in topological location of different computing cores, thus introducing unnecessary resource competition and routing overhead from the source.

[0039] To address any of the aforementioned problems, embodiments of this application provide a chip mapping method for spaceborne synthetic aperture radar (SAR) imaging. By leveraging the data flow structure of depth-sensing SAR imaging algorithms and utilizing their inherent multi-source convergence characteristics, a unique mapping anchor point is automatically identified. Based on the communication cost model of the hardware platform, the optimal initial hardware location is locked for the anchor point, thereby guiding the subsequent global search to a highly promising finite subspace. (Refer to...) Figure 1 , Figure 1 This is a schematic flowchart illustrating a chip mapping method for spaceborne synthetic aperture radar imaging provided in an embodiment of this application.

[0040] In this embodiment, the method includes: Step S10: Perform structural analysis on the data flow graph describing the synthetic aperture radar imaging algorithm, and determine the mapping anchor point from the data flow graph. The mapping anchor point is the convergence node in the data flow graph that has at least two incoming edges and at least two outgoing edges. Optionally, the synthetic aperture radar imaging algorithm includes a range Doppler algorithm, a linear frequency modulation scaling algorithm, or a back projection algorithm.

[0041] It should be noted that this embodiment uses the example of mapping the range-Doppler algorithm (RDA) of a certain spaceborne synthetic aperture radar (SAR) onto a chip containing multiple heterogeneous computing units to illustrate the chip mapping method proposed in this application, but it is not limited to this algorithm and chip architecture.

[0042] Specifically, the RDA algorithm is described as a directed data flow graph (DFG) G=(V,E). This DFG contains multiple operation nodes, such as FFT nodes, complex multiplication nodes, complex addition nodes, etc. Edges represent data dependencies. The purpose of structural analysis of the DFG is to find a node with multi-source convergence characteristics as the mapping anchor point.

[0043] The processing flow of spaceborne SAR imaging algorithms (such as RDA, CSA, NCSA, and BPA) exhibits typical multi-source convergence characteristics. This characteristic stems from the inherent mechanism of the imaging process: after the raw broadband signal emitted by the system is scattered by the ground, its echo data needs to undergo multiple sequential processing stages, including range migration correction, range compression, azimuth phase correction, and azimuth compression. In each stage, the processing result of the previous stage is used as input, and is subjected to complex multiplication, filtering, transformation, and other operations with the correction factor or reference function of the current stage, merging to generate an intermediate image, which serves as the input for the next stage. This staged processing-convergence mode is manifested in DFG as the existence of one or more key convergence points (Pivot Nodes), which are the intersections of multiple preceding paths (such as input data and correction factors), and whose output is simultaneously depended upon by multiple subsequent nodes.

[0044] See Figure 2 To automatically locate this critical anchor point, for example, an algorithm based on the detection of necessary nodes is used, the process of which is as follows: Graph preprocessing: In the original DFG, add a virtual super source node S and connect S to all actual source nodes in the DFG with an in-degree of 0 (e.g., original echo data nodes, reference function nodes) with directed edges. Required node detection: Traverse all nodes in the DFG except the source node. For the currently traversed node v, perform a depth-first search (DFS) starting from the super source node S. During the search, traversing node v is prohibited. If, under this constraint, DFS cannot reach all endpoints of the DFG (i.e., nodes with an out-degree of 0, such as the final image output node), then node v is considered a "must-pass" on all possible paths, and is marked as a candidate anchor (a candidate anchor is a candidate key merging point).

[0045] Unique Anchor Point Determination: When multiple key convergence point candidates are detected, a unique anchor point (i.e., the mapping anchor point) needs to be determined. A possible strategy is to select the node with the fewest processing units (PEs) compatible with its functional type on the target hardware platform as the final anchor point. For example, if the hardware platform integrates 4 FFT-specific units and 10 general-purpose arithmetic units, then an FFT-type convergence point is scarcer than a general-purpose arithmetic-type convergence point, and therefore will be preferentially selected as the anchor point. The principle behind this design is that a scarcity-based selection strategy can compress the subsequent search space to the greatest extent. Because scarce units have very few possible mapping positions, locking them as anchor points means that the "root" of the subsequent global search is fixed on a few candidate points, significantly reducing the number of search branches from the source.

[0046] For example, after detection, two candidate anchor points were obtained: Node A: A complex multiplication node located in the distance migration correction stage, used to multiply the distance-compressed data with the migration correction factor. In the hardware platform, this node has four type-compatible computational units (PE_CMUL1-PE_CMUL4), i.e., C_A=4.

[0047] Node B: An FFT node located in the azimuth compression stage, used to perform Fourier transform on the azimuth signal. In the hardware platform, this node has two type-compatible computational units (PE_FFT1, PE_FFT2), i.e., C_B=2.

[0048] Based on the scarcity selection strategy, since C_B(2) is less than C_A(4), meaning that FFT units are scarcer than complex multipliers, node B (the FFT node) is determined as the final mapping anchor. This node, within the RDA's DFG, receives data from multiple preceding processing paths (incoming edges ≥ 2), and its output is also distributed to multiple subsequent processing nodes (outgoing edges ≥ 2), making it a key convergence point in the entire algorithm flow.

[0049] Step S20: Determine the communication efficiency metric of each computing unit in the hardware platform of the target chip; For example, the target chip is a multi-core processor chip that includes multiple heterogeneous computing units, and the computing units include at least one of a fast Fourier transform unit, a coordinate rotation digital computer unit, or a complex multiplier.

[0050] It should be noted that, in order to quantify the communication efficiency of each computing unit, this embodiment evaluates the communication performance of the target chip's hardware platform.

[0051] The hardware platform of the target chip includes the following resources: Computational units: 2 dedicated FFT units (PE_FFT1, PE_FFT2), 4 complex multiplier units (PE_CMUL1-PE_CMUL4), and 8 general-purpose arithmetic logic units (PE_ALU1-PE_ALU8). Each computational unit has a unique physical address in the network.

[0052] Routing Nodes: The chip uses a 2x2 mesh on-chip network (NoC) as its interconnect architecture, containing four routing nodes (R1, R2, R3, R4). Computing units are connected to the nearest routing node. For example, PE_FFT1 and PE_ALU1, ALU2 are connected to R1, PE_CMUL1, CMUL2 are connected to R2, and so on.

[0053] Step S30: Based on the attribute information of the mapping anchor point and the communication efficiency metric, determine the initial mapping position for the mapping anchor point from the hardware platform, and perform a mapping search starting from the initial mapping position.

[0054] It should be noted that the goal of determining the initial mapping position based on anchor point attribute information and communication efficiency metrics and performing mapping search is to find an optimal initial position for the already determined anchor point (such as node B, FFT node) on the hardware platform.

[0055] Specifically, based on the anchor point's attribute information (such as the node type being FFT), a set of type-compatible nodes, PE_compatible={PE_FFT1,PE_FFT2}, is selected from all hardware computing units.

[0056] Cost sorting: Based on the pre-calculated communication efficiency metric values ​​mentioned above, the cells in PE_compatible are sorted in ascending order. An example of the sorting result is shown below: Rank 1: PE_FFT1 (communication efficiency metric 1.0) – Optimal; Second place: PE_FFT2 (communication efficiency metric 1.2).

[0057] Starting point locking: The optimal computational unit in the sorting, i.e., PE_FFT1, is determined as the initial mapping position of the mapping anchor point (such as node B).

[0058] At this point, the starting point of the entire mapping search has been locked onto the scarce resource PE_FFT1, which has the optimal topological position. Subsequently, the compiler can execute the subsequent mapping search with "node B is fixed in PE_FFT1" as the starting point and constraint. The subsequent mapping search can employ any global search algorithm, such as simulated annealing (SA), backtracking, or heuristic search. Since the critical, scarce anchor point has been placed in the optimal position, the scope of the subsequent search is greatly compressed, and the search process can converge to a high-quality solution more quickly, avoiding wasting computational resources on a large number of impossible or inefficient initial branches. For example, the subsequent search only needs to find suitable mapping positions for the remaining nodes in the DFG among the remaining dozen or so PEs, and because the anchor point is located at the center of the network, the communication paths with other nodes are more likely to satisfy latency constraints.

[0059] In this embodiment, by identifying nodes with multi-source convergence characteristics from the data flow graph describing the SAR imaging algorithm as mapping anchors, and determining the optimal initial mapping position for these anchors based on the communication efficiency metric of the hardware platform, the starting point of subsequent global mapping searches can be guided to a highly promising finite subspace. This compresses the mapping search space from the source, reduces invalid search branches, and improves mapping efficiency.

[0060] Based on any of the above embodiments, the step of performing structural analysis on the data flow graph describing the synthetic aperture radar imaging algorithm and determining the mapping anchor point from the data flow graph includes: Perform a mandatory node analysis on the data flow graph to identify one or more mandatory nodes as candidate anchor points; When multiple candidate anchor points are identified, the mapping anchor point is determined from the multiple candidate anchor points based on the number of available computing units on the target chip for each candidate anchor point.

[0061] It should be noted that mandatory node analysis is a graph theory analysis method used to identify nodes that must be traversed from all source points to all destination points. In DFG, mandatory nodes represent key points where data flows must converge, and are a mathematical abstraction of the multi-source convergence characteristics of SAR imaging algorithms.

[0062] Required nodes: In a data flow graph, these are nodes that must be traversed from any source point to any destination point. In SAR imaging algorithms, these nodes correspond to data intersections during processing stages such as range compression and azimuth compression.

[0063] Candidate anchor points: One or more nodes identified after the analysis of necessary nodes are selected as potential mapping anchor points.

[0064] Specifically, the implementation of the necessary node analysis is as follows: Graph preprocessing: In the original DFG, a virtual super source point S is added, and directed edges are used to connect S to all actual source points in the DFG with an in-degree of zero (i.e., nodes with empty in-edges). The significance of this operation is that: SAR imaging algorithms typically have multiple source points in their DFG (such as raw echo data nodes, reference function nodes, etc.). Adding a virtual super source point can unify all source points into a single starting point, thereby simplifying the logic for determining necessary nodes. Required Node Detection: Traverse every node v in the DFG except for the virtual super source and all actual source nodes. For the currently traversed node v, perform a depth-first search (DFS) starting from the virtual super source S, and prohibit traversing node v during the search. If, under this constraint, DFS cannot reach all endpoints of the DFG (i.e., nodes with an out-degree of zero, such as image output nodes and auxiliary parameter output nodes), then node v is a required path on all paths and is marked as a candidate anchor point. Conversely, if DFS can still reach all endpoints, then there exists a path that does not pass through node v, and node v is not a required node.

[0065] Pathway analysis can automatically identify nodes located at the intersection of all paths in a DFG (Factor-Driven Geographic Array) without manual specification. It is particularly suitable for complex scenarios where SAR imaging algorithms have multiple source and destination points in their DFG, overcoming the limitation of related technologies that rely on a single output assumption.

[0066] Number of available compute units: The total number of compute units (PEs) in the target chip hardware platform that are compatible with the candidate anchor type. For example, if the candidate anchor is an FFT node, then the number of available compute units is the number of dedicated FFT units on the chip.

[0067] Optionally, the node with the fewest number of computing units compatible with its functional type in the target chip can be selected as the final anchor point.

[0068] In this embodiment, multi-source convergence nodes in the SAR imaging algorithm data flow graph are identified as candidate anchor points through mandatory node analysis. Based on the scarcity of hardware resources (i.e., the number of available computing units), a unique mapping anchor point is selected from these candidates. This transforms the original random or rule-dependent selection of the mapping starting point into a deterministic selection guided by both the algorithm's structural features and the distribution of hardware resources, thereby reducing invalid search branches.

[0069] Based on any of the above embodiments, the step of performing mandatory node analysis on the data flow graph to identify one or more mandatory nodes as candidate anchor points includes: In the data flow graph, a virtual super source node is determined, and the virtual super source node is connected to all actual source nodes in the data flow graph whose incoming edges are empty. Traverse every node in the data flow graph except for the virtual super source node and all actual source nodes, and for the currently traversed node, perform a search starting from the virtual super source node and prohibit the search through the currently traversed node; If it is impossible to reach the endpoint where all outgoing edges of the data flow graph are empty, then the currently traversed node is determined as the required node.

[0070] It should be noted that a virtual super source point refers to a virtual node that is determined by humans to unify all the scattered source points in the data flow graph into a common starting point, thereby simplifying the logic for determining necessary nodes.

[0071] An actual source node with empty incoming edges refers to a node in the data flow graph that has no input edges, representing the initial input data of the algorithm. In SAR imaging algorithms, such nodes include raw echo data, reference functions, correction factors, etc.

[0072] It should be understood that the data flow graph of SAR imaging algorithms typically has multiple source points. For example, in the DFG of the Range-Doppler (RDA) algorithm, the raw echo data is one source point, the range migration correction factor is another, and the azimuth reference function is yet another. These source points are scattered across different locations in the DFG, making it difficult to determine essential nodes—because essential nodes require all paths from all source points to all destination points to pass through that node. To address this, this embodiment proposes adding a virtual super source point S and connecting S to all nodes with empty incoming edges using directed edges. In this way, any node in the DFG can be reached from S, and any path from S to the destination point must pass through some actual source point. After this processing, determining whether a node v is an essential node is transformed into determining whether all paths from S to the destination point must pass through v.

[0073] For example, depth-first search (DFS) or breadth-first search (BFS) algorithms can be used to explore all reachable nodes starting from a virtual super source node. DFS can efficiently traverse the graph structure and terminate early if the destination cannot be reached. DFS starts from S, proceeds along directed edges, and skips branches when it encounters forbidden nodes.

[0074] Specifically, for the currently traversed node v, in the search starting from the virtual super source node S, passing through v is prohibited (i.e., v is temporarily deleted from the graph). If, under this restriction, the search can reach all endpoints of the data flow graph, it means that there exists a path that does not pass through v, and v is not a necessary node; conversely, if the search cannot reach all endpoints, it means that all paths from S to the endpoints must pass through v, and v is a necessary node.

[0075] Understandably, an empty endpoint refers to a node in the data flow graph that has no output edges, representing the final output of the algorithm. In SAR imaging algorithms, such nodes include the final SAR image output node, auxiliary parameter output nodes, etc.

[0076] In this embodiment, by introducing a virtual super source point, multiple scattered source points in the SAR imaging algorithm data flow graph are unified into a single starting point. By employing the methods of prohibiting passage and depth-first search, the necessary nodes that must be passed from all source points to all endpoints are accurately identified as candidate anchor points. This automatically captures the inherent multi-source convergence characteristics in the algorithm data flow without manual intervention, providing an accurate and complete candidate set. This ensures that the selection of the mapping starting point can truly focus on the key intersection points of the algorithm structure, guaranteeing the reliability of search space compression.

[0077] Based on any of the above embodiments, determining the mapping anchor point from multiple candidate anchor points according to the number of available computing units on the target chip for each candidate anchor point includes: The candidate anchor point is selected from multiple candidate anchor points, and the number of computing units in the target chip that are compatible with the candidate anchor point type meets the preset scarcity condition as the mapping anchor point.

[0078] It should be noted that type compatibility means that the operation type represented by the candidate anchor (such as FFT, complex multiplication, CORDIC, etc.) matches the functional type of the computing unit in the hardware platform. For example, an FFT type node can only be mapped to an FFT-specific unit, and not to a general-purpose arithmetic unit.

[0079] The number of available computing units refers to the total number of computing units in the target chip hardware platform that can perform this type of operation.

[0080] Preset scarcity conditions: Pre-defined criteria used to determine the scarcity level of nodes.

[0081] Optionally, the preset scarcity condition can be the condition of having the smallest quantity.

[0082] The mapping anchor point is the finally determined unique node, whose initial mapping position will be locked first, serving as the starting point and constraint condition for subsequent global mapping searches.

[0083] Specifically, in the data flow graph of the SAR imaging algorithm, each operation node corresponds to an operation type. For example, the FFT node requires Fast Fourier Transform; the complex multiplication node requires complex multiplication; the CORDIC node requires trigonometric functions or coordinate transformations; and the general arithmetic node requires basic operations such as addition and multiplication. For each candidate anchor point, its operation type is analyzed, and then the number of computational units compatible with that type is counted in the hardware platform. Taking a certain chip architecture as an example, this chip integrates 2 dedicated FFT units, 4 complex multiplier units, and several general arithmetic units. If the candidate anchor points include node A: FFT type, number of available computational units = 2; node B: complex multiplication type, number of available computational units = 4; and node C: general arithmetic type, number of available computational units = 8, then the selection is based on a preset scarcity condition: since the number of dedicated FFT units is the smallest (only 2), node A has the strongest scarcity, so node A is determined as the final mapping anchor point. The rationale for this selection strategy is that scarce resources are limited in number in the chip. By locking them as anchor points, the solution space for subsequent mapping searches is compressed. At the same time, the allocation conflict of scarce resources is resolved in advance at the initial stage of mapping, thereby minimizing backtracking and failures in subsequent searches.

[0084] In this embodiment, from multiple candidate anchor points identified through analysis of necessary nodes, the node with the number of available computing units in the target chip that meets the preset scarcity condition is selected as the final mapping anchor point. This locks the "root" of the mapping search onto the critical node where hardware resources are most scarce. Since the available locations of scarce resources in the chip are extremely limited, this selection strategy compresses the possible placement space of anchor points from the source. This allows the subsequent initial positioning based on communication efficiency to complete the selection within a very small range, thereby resolving the allocation conflict of scarce resources at the very beginning of the mapping process and avoiding backtracking and mapping failures caused by scarce resource allocation issues.

[0085] Based on any of the above embodiments, determining the communication efficiency metric of each computing unit in the hardware platform of the target chip includes: The hardware platform is abstracted as a resource graph including computing nodes and routing nodes; For each computing node, the average shortest path distance from the computing node to all routing nodes is determined, and the average shortest path distance is used as a communication efficiency metric for the computing node.

[0086] It should be noted that a resource graph is a graph theory abstraction model that transforms the physical structure of a hardware platform into a directed graph, used to describe the connection relationships between computing units and interconnect networks. In compiler design, it is often referred to as MRRG (Modular Resource Graph).

[0087] Compute node: Represents a computing unit (Processing Element, PE) in a hardware platform, such as a dedicated FFT unit, a complex multiplier, or a general-purpose arithmetic logic unit. Each compute node corresponds to a hardware resource capable of performing an operation.

[0088] Routing nodes: These represent interconnecting network nodes in a hardware platform, such as crossbars, switching network nodes, and routers. Routing nodes are responsible for forwarding data between computing nodes.

[0089] Average shortest path distance: For each compute node, calculate the shortest path distance to all routing nodes, and then take the average. The average shortest path distance reflects the centrality of the compute node in the overall network topology.

[0090] A smaller communication efficiency metric indicates higher communication efficiency for the computing node (i.e., a more central topological location) and lower average communication overhead with other potential computing nodes in the system.

[0091] In this embodiment, the hardware platform is abstracted as a resource graph containing compute nodes and routing nodes. The average shortest path distance from each compute node to all routing nodes is calculated as a communication efficiency metric. This transforms the abstract communication efficiency into an objective and quantifiable numerical indicator—a smaller value indicates a more central topological position of the compute node in the network and lower average communication overhead with other potential compute nodes in the system. This provides an objective and efficient quantitative basis for the initial positioning of mapping anchor points, ensuring that critical nodes are preferentially placed on hardware resources with optimal communication efficiency.

[0092] Based on any of the above embodiments, the communication efficiency metric is calculated using the following formula: ; In the formula, Q represents the total number of routing nodes, and r j This represents the j-th routing node. Indicates from compute node pe i To routing node r j The number of hops for the shortest path.

[0093] It should be noted that after determining the anchor points in the DFG, it is necessary to find their optimal initial mapping positions in the hardware platform (usually abstracted as MRRG, i.e., Modular Resource Graph). To quantify "optimal," this embodiment proposes a communication cost-aware static pre-computation method. Specifically, for a hardware platform containing P compute nodes (PEs) and Q routing nodes (such as crossbars or switching network nodes), for each compute node... Pre-calculate a static communication cost score The fraction is defined as follows: ; in, This represents the j-th routing node; Indicates from the compute node To the routing node The shortest path hop count in an interconnected network. The value represents the average distance from this compute node to all routing nodes in the network. The smaller this value, the more centrally located the compute node is in the network, and the lower its average communication overhead (latency, power consumption) with any other potential compute nodes in the system. Therefore... This can be used to measure the communication efficiency of a processing core. The above pre-computation process only needs to be executed once after the hardware platform design is completed, and its results can be stored in the compiler as a lookup table.

[0094] In this embodiment, all routing nodes are used as reference points, and the average shortest path hop count is taken. The smaller the value, the stronger the topological centrality of the computing node in the network and the lower the average communication overhead with other potential computing nodes in the system. This ensures that critical nodes can be preferentially placed on hardware resources with the best communication efficiency.

[0095] Based on any of the above embodiments, determining the initial mapping position for the mapping anchor point from the hardware platform based on the attribute information of the mapping anchor point and the communication efficiency metric includes: Select a set of candidate computing units that have the same functional type as the mapping anchor from all computing units; The computing units in the candidate computing unit set are sorted according to the communication efficiency metric, and the initial mapping position of the mapping anchor point is determined from the candidate computing unit set according to the sorting result.

[0096] It should be noted that this embodiment first narrows down the candidate range based on functional type compatibility, and then sorts and selects the best based on communication efficiency metrics, thereby ensuring that key nodes can be preferentially placed on hardware resources with the best communication efficiency.

[0097] Same functional type means that the operation type supported by the hardware computing unit is exactly the same as the operation type represented by the mapped anchor node. For example, an FFT type anchor can only be mapped to an FFT-specific unit, and cannot be mapped to a complex multiplier or a general arithmetic unit. This restriction ensures that only hardware resources capable of performing the operation can be included as candidates.

[0098] All computation units in the candidate computation unit set have the ability to perform the operation represented by the mapping anchor.

[0099] In this embodiment, by first selecting a set of candidate computing units with the same functional type as the mapping anchor point, and then sorting the candidate units according to the communication efficiency metric and selecting the best to determine the initial mapping position, the initial position of the anchor point is locked on the hardware resource with the best communication efficiency. Since the communication efficiency metric objectively reflects the centrality of the computing unit in the network topology (the smaller the value, the lower the average communication overhead with other potential computing units in the system), this strategy ensures that the most critical aggregation node in the data flow graph is placed on a hardware resource with a superior topological position from the beginning, thereby providing an efficient starting point for subsequent global mapping search and effectively reducing the overall communication overhead.

[0100] Based on any of the above embodiments, the step of sorting each computing unit in the candidate computing unit set according to the communication efficiency metric, and determining the initial mapping position of the mapping anchor point from the candidate computing unit set according to the sorting result, includes: The computing units in the candidate computing unit set are sorted in ascending order according to the communication efficiency metric, and the computing units whose communication efficiency metric meets the preset sorting requirements are determined as the initial mapping positions of the mapping anchor points.

[0101] It's important to note that the reason for sorting the computing units in ascending order is that a smaller communication efficiency metric indicates a shorter average shortest path distance from that unit to all routing nodes. This means the unit is more centrally located in the network topology and has lower average communication overhead with other potential computing nodes. Therefore, sorting in ascending order (from smallest to largest) places the most efficient computing units at the beginning of the sequence, facilitating the selection process starting with the optimal candidates.

[0102] Preset sorting requirements refer to pre-defined criteria used to select computational units from the sorted candidate set. These criteria can be: the principle of minimum quantity (selecting the first computational unit in the sorted list, i.e., the unit with the smallest communication efficiency metric), or other custom rules.

[0103] Understandably, after obtaining the anchor point's type information and the communication cost scores of all hardware PEs, the initial anchor point location process becomes straightforward and efficient: Step 1: Type Filtering. From all hardware PEs, filter out the set of PEs that are compatible with the anchor type. .

[0104] Step 2: Cost Ranking. Based on the pre-calculated communication cost scores... ,right The PEs in the list are sorted in ascending order to form an initial candidate position priority list from optimal (i.e., the lowest communication cost) to worst (i.e., the highest communication cost).

[0105] Step 3: Starting Point Locking. The first element in the priority list, i.e., the PE with the lowest communication cost, is determined as the optimal initial mapping position for the anchor point. This position will serve as the sole starting point for all subsequent detailed mapping search algorithms.

[0106] In this embodiment, ascending order ensures that the candidate set is arranged in descending order of communication efficiency, with the computational unit with the best communication efficiency located at the beginning of the sequence. The selection operation only needs to access the first element of the sorted list to complete the operation.

[0107] Based on any of the above embodiments, the step of performing a mapping search starting from the initial mapping position includes: Using the constraint that the mapping anchor point is fixed at the initial mapping position, a global mapping search is performed on the remaining nodes in the data flow graph.

[0108] It should be noted that the constraint of fixing the mapping anchor point to the initial mapping position means that, in the subsequent global mapping search process, the determined mapping anchor point and its initial mapping position are considered as fixed assignments that cannot be changed. Specifically: Fixedness: Mapping anchor points can only be placed at a defined initial mapping position and cannot be reassigned or moved during the search process; Constraints: This fixed position serves as a hard constraint for the global search, and the mapping of all other nodes must be performed under this constraint.

[0109] Performing a global mapping search on the remaining nodes in the data flow graph means, with the anchor point position fixed, searching for the mapping position of all nodes in the data flow graph except the anchor point. Specifically, this includes: Search scope: All nodes in the data flow graph except anchor points (N-1 nodes); Available resources: Remaining resources in the hardware platform excluding the computing units occupied by the anchor point; Search objective: To find a feasible mapping location for each node and a feasible routing path for each data dependency edge; Global: The search covers the entire data flow graph and the entire hardware resource space, rather than local optimization.

[0110] Optionally, the global mapping search employs at least one of the simulated annealing algorithm, backtracking algorithm, or heuristic search algorithm.

[0111] It should be understood that the chip mapping method for spaceborne synthetic aperture radar imaging, through anchor point detection and hardware-based sensing and positioning, compresses the mapping search space from the source, specifically in the following ways: 1. The theoretical upper limit of the search space: Consider a typical multi-core processing chip containing M processing cores (PEs) and a data flow graph (DFG) to be mapped containing N operation nodes. Without considering node type constraints, the solution space size for node placement is the number of permutations: ; After introducing type compatibility, let the size of the PE set available to node i be Ci, then the upper bound of the solution space can be expressed as: (Ignoring resource conflicts between nodes), the actual number of feasible solutions is much smaller than this value, but the complexity of the search algorithm is closely related to this upper bound.

[0112] 2. Compression effect: The search space is compressed through the following two steps: (1) Identify a key node (anchor point) in the DFG, whose type is often scarce in the hardware platform. Assume that the anchor point is compatible with a certain number of PEs. ,generally Much smaller than the average Ci (for example, in a typical heterogeneous chip, there may only be 2 to 4 dedicated FFT cells). (2) Hardware location: From the pre-calculated communication cost score, from The unique optimal position is selected from the candidate PEs as the starting point for the anchor point mapping.

[0113] After the above two steps, the possible placement locations of the anchor points are from... The number of possible solutions is reduced to one, while the available PE sets for other nodes are slightly reduced due to anchor point occupancy (at most one less). Therefore, the upper bound of the solution space is... Reduced to:

[0114] In this embodiment, by fixing the mapping anchor point at the initial mapping position with the best communication efficiency as a hard constraint, the problem of allocating scarce resources is solved in advance, so that the subsequent global mapping search can be carried out in a significantly compressed solution space. Since the anchor point has been locked at the optimal position and no longer participates in the subsequent competition, the mapping of the remaining nodes only needs to be carried out in the remaining resources, the number of search branches is greatly reduced, and the convergence speed is improved.

[0115] Based on the methods described in any of the above embodiments, this application also provides a computer program product, which includes one or more computer programs or instructions. The computer program or instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. When executed by a processor, the computer program implements the methods described in any of the above embodiments.

[0116] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0117] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0118] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0119] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0120] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0121] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A chip mapping method for spaceborne synthetic aperture radar imaging, characterized in that, The method includes: A structural analysis is performed on the data flow graph describing the synthetic aperture radar imaging algorithm, and mapping anchor points are determined from the data flow graph. The mapping anchor points are the convergence nodes in the data flow graph that have at least two incoming edges and at least two outgoing edges. Determine the communication efficiency metric for each computing unit in the hardware platform of the target chip; Based on the attribute information of the mapping anchor point and the communication efficiency metric, an initial mapping position is determined for the mapping anchor point from the hardware platform, and a mapping search is performed starting from the initial mapping position.

2. The method according to claim 1, characterized in that, The structural analysis of the data flow graph describing the synthetic aperture radar imaging algorithm, and the determination of mapping anchor points from the data flow graph, includes: Perform a mandatory node analysis on the data flow graph to identify one or more mandatory nodes as candidate anchor points; When multiple candidate anchor points are identified, the mapping anchor point is determined from the multiple candidate anchor points based on the number of available computing units on the target chip for each candidate anchor point.

3. The method according to claim 2, characterized in that, The step of performing mandatory node analysis on the data flow graph to identify one or more mandatory nodes as candidate anchor points includes: In the data flow graph, a virtual super source node is determined, and the virtual super source node is connected to all actual source nodes in the data flow graph whose incoming edges are empty. Traverse every node in the data flow graph except for the virtual super source node and all actual source nodes, and for the currently traversed node, perform a search starting from the virtual super source node and prohibit the search through the currently traversed node; If it is impossible to reach the endpoint where all outgoing edges of the data flow graph are empty, then the currently traversed node is determined as the required node.

4. The method according to claim 2, characterized in that, The step of determining the mapping anchor point from multiple candidate anchor points based on the number of available computing units on the target chip for each candidate anchor point includes: The candidate anchor point is selected from multiple candidate anchor points, and the number of computing units in the target chip that are compatible with the candidate anchor point type meets the preset scarcity condition as the mapping anchor point.

5. The method according to claim 1, characterized in that, The communication efficiency metrics of each computing unit in the hardware platform for determining the target chip include: The hardware platform is abstracted as a resource graph including computing nodes and routing nodes; For each computing node, the average shortest path distance from the computing node to all routing nodes is determined, and the average shortest path distance is used as a communication efficiency metric for the computing node.

6. The method according to claim 5, characterized in that, The communication efficiency metric is calculated using the following formula: ； In the formula, Q represents the total number of routing nodes, and r j This represents the j-th routing node. Indicates from compute node pe i To routing node r j The number of hops for the shortest path.

7. The method according to claim 1, characterized in that, The process of determining the initial mapping position for the mapping anchor point from the hardware platform based on the attribute information of the mapping anchor point and the communication efficiency metric includes: Select a set of candidate computing units that have the same functional type as the mapping anchor from all computing units; The computing units in the candidate computing unit set are sorted according to the communication efficiency metric, and the initial mapping position of the mapping anchor point is determined from the candidate computing unit set according to the sorting result.

8. The method according to claim 7, characterized in that, The step of sorting the computing units in the candidate computing unit set according to the communication efficiency metric, and determining the initial mapping position of the mapping anchor point from the candidate computing unit set based on the sorting result, includes: The computing units in the candidate computing unit set are sorted in ascending order according to the communication efficiency metric, and the computing units whose communication efficiency metric meets the preset sorting requirements are determined as the initial mapping positions of the mapping anchor points.

9. The method according to claim 1, characterized in that, The step of performing a mapping search starting from the initial mapping position includes: Using the constraint that the mapping anchor point is fixed at the initial mapping position, a global mapping search is performed on the remaining nodes in the data flow graph.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method described in any one of claims 1-9.

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