Submount transition substrate for high-density pad optical chip package, preparation method and application thereof

Abstract

The application discloses a Submount transition substrate for high-density pad optical chip packaging, a preparation method and application thereof, and belongs to the technical field of optical chips. The Submount transition substrate comprises an insulating substrate, a Ti adhesion layer, an AlCu metal layer and a passivation protective layer; the AlCu metal layer forms a plurality of metal pads, fine-line-width metal leads and overlay marks; and the passivation protective layer forms a retracted window structure in the area corresponding to the metal pads. The preparation method comprises the following steps: sequentially sputtering the Ti adhesion layer and the AlCu metal layer on the insulating substrate, forming the metal pads, the metal leads and the overlay marks through photolithography and etching, depositing the passivation protective layer and patterning to form a retracted window, forming a protective glue layer to cover the pad and the window area before dicing, and removing the glue after dicing to obtain the substrate. The application can reduce the risk of metal falling off, narrow-pitch residual short circuit and pad contamination in high-density pad packaging, and improve the substrate preparation yield and lead bonding reliability.

Description

Technical Field

[0001] This invention relates to the fields of optical chip packaging, optoelectronic device packaging and semiconductor micromachining technology, and particularly to a submount transition substrate for high-density pad optical chip packaging, its preparation method and application. Background Technology

[0002] In the packaging of optical communication, laser, and photoelectric detection devices, the submount is a critical intermediate support structure positioned between the optical chip and the packaging substrate or external circuitry. For high-density pad optical chip packages with multiple electrodes, close-pitch pads, and fan-out interconnects, the submount not only provides a flat mounting platform for the optical chip but also, through multiple metal pads and fine-linewidth metal leads, stably leads out the functional electrodes on the chip, achieving electrical interconnection and wire bonding with external circuitry. Therefore, the structural integrity, metal pattern accuracy, window overlay accuracy, and pad surface quality of the submount directly affect the mechanical connection strength, signal transmission stability, and long-term operational reliability of the high-density pad package.

[0003] As optical chips evolve towards miniaturization, arraying, and high-density pad interconnects, the number of chip electrodes increases, the size of individual electrodes decreases, and the spacing between adjacent pads and metal leads further shrinks. This places higher demands on the metal pattern resolution of submounts, the cleanliness of etching in narrow-pitch areas, the accuracy of passivation layer window placement, and the cleanliness of pad bonding surfaces. Currently, a typical submount uses a silicon wafer with a silicon oxide insulating layer formed by surface thermal oxidation as the substrate, deposits an AlCu alloy thin film as the metal interconnect layer on it, covers it with a passivation protective layer, and etches the passivation layer above the pads to form windows, exposing the bonding area. However, this structure and fabrication process still face several technical challenges in high-density pad packaging applications.

[0004] First, when AlCu metal films are directly deposited on the surface of silicon oxide substrates, the interfacial adhesion is insufficient. During subsequent photolithography, etching, cleaning, and wire bonding processes, the metal film is prone to localized peeling, blistering, or even complete detachment. For high-density pad packaging, localized detachment not only damages the bonding surface of individual pads but may also affect the continuity of adjacent fine leads, making it difficult to reliably complete the wire bonding process.

[0005] Secondly, in the metal pattern etching process, if residual photoresist is not completely removed after development, it can locally block etching, resulting in incomplete removal of AlCu between adjacent metal lines and forming metal residue. In high-density pad interconnect layouts with narrow linewidths and narrow pitches, even a small amount of metal residue can cause short circuits between adjacent pads or leads. According to conventional process flows, the photoresist is removed and cleaned immediately after etching, and defect inspection is only performed afterward. This post-inspection mode often makes it impossible to detect short circuit defects in a timely manner; once residue is confirmed after photoresist removal, the entire batch of substrates is usually difficult to rework using simple methods, and can only be scrapped or subjected to a costly re-photolithography process, significantly increasing process costs and cycle time.

[0006] Third, during the process of dicing a whole wafer into individual substrates, silicon chips, oxide debris, and coolant generated by high-speed dicing can directly splash onto the exposed metal pads. For high-density pad packages, with a large number of pads and a small bonding window, particles and liquid stains are more likely to occupy the effective bonding area and cause bonding defects. Residual contaminants will degrade the bonding strength of the wire bonding interface, causing the bond points to fall off easily or the contact resistance to increase, affecting the electrical connection stability and final lifespan of the device.

[0007] In summary, how to simultaneously improve the bonding reliability between the metal layer and the substrate, the processing cleanliness of narrow-pitch metal patterns, and the anti-contamination capability of the pad bonding surface in high-density pad optical chip packaging scenarios is a technical problem that urgently needs to be solved in the submount manufacturing field. Summary of the Invention

[0008] The technical problem to be solved by the present invention is that in the preparation of submounts for high-density pad optical chip packaging, the AlCu metal film is easy to fall off from the silicon oxide substrate, the narrow-pitch metal pattern area is prone to etching residue, and the dicing contamination can reduce the reliability of pad bonding, resulting in difficulty in improving yield and high rework and scrap rates.

[0009] To address the above problems, the present invention proposes the following technical solution: In a first aspect, the present invention provides a method for preparing a submount transition substrate for high-density pad optical chip packaging, comprising the following steps: An insulating substrate is provided, and the insulating substrate is cleaned and subjected to plasma pretreatment; Ti adhesion layer and AlCu metal layer are sputtered sequentially on a pretreated insulating substrate; Metal pattern photolithography is performed on the AlCu metal layer to form a photoresist mask containing multiple metal pad patterns, metal lead patterns and overlay mark patterns. The multiple metal pad patterns and metal lead patterns are arranged in a high-density pad package interconnection layout. The AlCu metal layer is etched using the photoresist mask to form metal pads, metal leads, and overlay marks; Remove the photoresist mask; A passivation protective layer is deposited on the structure after the photoresist mask is removed; The passivation protective layer is patterned to form a passivation protective layer window, the size of which is smaller than the size of the metal pad; A protective adhesive layer is formed on the structural surface where the passivation protective layer window is formed, and the protective adhesive layer covers the metal pad, the metal lead and the passivation protective layer window area; The structure with the protective adhesive layer formed is diced to obtain a single substrate; The protective adhesive layer on the surface of the single substrate is removed and cleaned to obtain the Submount transition substrate for high-density pad optical chip packaging.

[0010] Furthermore, after etching is completed, before removing the photoresist mask, while retaining the photoresist mask, EDS detection is performed on the area exposed by the opening of the photoresist mask. After confirming that there are no residual Al and / or Cu elements, the photoresist mask is removed.

[0011] Furthermore, before the step of etching the AlCu metal layer with the photoresist mask, the method further includes: performing O2 plasma treatment on the area where the photoresist mask is formed to remove residual photoresist.

[0012] Furthermore, when the passivation protective layer is patterned, the window pattern of the passivation protective layer and the metal pad pattern are aligned through the overlay marks, with an alignment accuracy of no more than ±1 μm.

[0013] In a second aspect, the present invention provides a submount transition substrate for high-density pad optical chip packaging, comprising: Insulating substrate; A Ti adhesion layer is disposed on the insulating substrate; An AlCu metal layer is disposed on the Ti adhesion layer. The AlCu metal layer includes multiple metal pads, metal leads, and overlay marks. The multiple metal pads and the metal leads are arranged in an array or fan-out high-density pad interconnection layout. A passivation protective layer is applied over the AlCu metal layer. The passivation protective layer has a window in the area corresponding to the metal pad. The size of the window is smaller than the size of the metal pad, so as to expose the bonding area while covering the edge area of ​​the metal pad.

[0014] Furthermore, the thickness of the Ti adhesion layer is 5–100 nm.

[0015] Furthermore, the material of the passivation protective layer is selected from silicon oxide, silicon nitride, or silicon oxynitride.

[0016] Furthermore, the insulating substrate is a silicon wafer with a silicon oxide layer on its surface, the thickness of which is 400–600 nm; the thickness of the AlCu metal layer is 0.8–1.2 μm, and the mass percentage content of Cu is 0.5–2 wt%.

[0017] Furthermore, the length and width of the opening are smaller than the length and width of the metal pad, respectively, and the single-sided inward reduction of the opening is 5 to 10 μm.

[0018] Furthermore, the minimum linewidth of the metal leads is 14–16 μm, and the minimum spacing between adjacent metal leads is 22–28 μm, to meet the fine-pitch interconnect requirements of high-density pad optical chip packaging.

[0019] Furthermore, the overprinted marks are cross-shaped and distributed at the four corners of the layout.

[0020] The present invention also provides the application of the aforementioned Submount transition substrate in high-density pad optical chip packaging, wherein the optical chip is a laser chip, a detector chip, an optical modulation chip, or an optical communication chip.

[0021] Furthermore, the Submount transition substrate is used for wire bonding interconnection between an optical chip with multiple closely spaced electrodes and a packaging carrier or external circuit.

[0022] Compared with the prior art, the technical effects achieved by the present invention include: The high-density pad optical chip packaging submount transition substrate provided by this invention has a Ti adhesion layer between the insulating substrate and the AlCu metal layer. The Ti adhesion layer forms a good bond with both the insulating substrate and the AlCu metal layer, alleviating the peeling or detachment problems caused by insufficient interfacial adhesion when the AlCu metal layer is directly placed on the insulating substrate, and improving the structural integrity and process tolerance of the metal interconnect layer. Multiple metal pads and fine-linewidth metal leads in the AlCu metal layer are arranged in a high-density pad interconnect layout, which can meet the fan-out interconnect requirements of multi-electrode optical chips. In this high-density layout, the spacing between adjacent pads is reduced, and the risk of contamination and short circuits caused by exposed pad edges is more prominent. Therefore, this invention covers the AlCu metal layer with a passivation protective layer and sets windows in the areas corresponding to the metal pads, the size of which is smaller than the size of the metal pad. Through this dimensional relationship, the window defines the bonding area of ​​the pads, and the pad edges not exposed by the window are covered by a passivation protective layer, which shields the pad edges and reduces the risk of contaminants penetrating along the pad edges during dicing, cleaning and subsequent processes, thus balancing the accessibility of the bonding area and the need for pad edge protection.

[0023] The fabrication method provided by this invention involves sequentially sputtering a Ti adhesion layer and an AlCu metal layer onto an insulating substrate. The Ti layer serves as an adhesion transition, improving the insufficient adhesion between AlCu and the insulating substrate. After forming metal pads, metal leads, and overlay marks adapted for high-density pad packaging through metal patterning and etching, a passivation protective layer is deposited and patterned to form a passivation protective layer window smaller than the metal pad, achieving coverage and protection of the pad edges. Before dicing, a protective adhesive layer is formed on the structure surface, covering the metal pads, metal leads, and the passivation protective layer window area. The structure covered with the protective adhesive layer is then diced. The protective adhesive layer acts as a physical barrier during dicing, preventing silicon chips, particles, and coolant from directly contacting the metal pad surface, thereby maintaining the cleanliness of the pad bonding surface. This method, through the seamless integration of each step, systematically reduces the impact of metal detachment, narrow-pitch residual short circuits, and pad contamination on substrate quality, which is beneficial for improving substrate yield and reducing rework and scrap due to pad defects.

[0024] The Submount transition substrate provided by this invention can be used in high-density pad optical chip packaging such as laser chips, detector chips, optical modulation chips or optical communication chips. It can meet the requirements of the above-mentioned optical chips for the flatness of the carrier platform, the electrical interconnection accuracy of multiple pads, the window overlay accuracy and the reliability of wire bonding, and has good prospects for industrial application. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the Submount transition substrate structure for high-density pad optical chip packaging according to the present invention; Figure 2 This is another schematic diagram of the Submount transition substrate for high-density pad optical chip packaging of the present invention; Figure 3 This is a schematic diagram of the recessed window structure of the metal pad and passivation protective layer of the present invention. Figure 4 This is a schematic diagram of the overlay markings on the Submount transition substrate for high-density pad optical chip packaging according to the present invention; Figure 5 This is a process flow diagram of the submount transition substrate fabrication for high-density pad optical chip packaging according to the present invention; Figure 6 This is a view of the pad surface before process optimization in an embodiment of the present invention; Figure 7 This is the result of microscopic examination of the metal pattern photolithography of the present invention; Figure 8 This is the result of EDS detection of resist residue after etching according to an embodiment of the present invention; Figure 9 The results are from the thickness ellipsometry test after PECVD in this invention. Figure 10 This is a comparison of tensile test results before and after optimization in an embodiment of the present invention.

[0026] Figure Labels Transition substrate 100, insulating substrate 10, Ti adhesion layer 20, AlCu metal layer 30, metal pad 31, overlay mark 32, passivation protection layer 40. Detailed Implementation

[0027] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Similar component reference numerals in the drawings represent similar components. Obviously, the embodiments described below are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0028] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0029] It should also be understood that the terminology used in the specification of embodiments of the present invention is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of the present invention. As used in the specification of embodiments of the present invention and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0030] See Figure 1 and Figure 2 This invention provides a Submount transition substrate for high-density pad optical chip packaging. As shown in the figure, the Submount transition substrate 100 includes an insulating substrate 10, a Ti adhesion layer 20, an AlCu metal layer 30, and a passivation protection layer 40.

[0031] The insulating substrate 10 provides mechanical support and electrical isolation for the substrate. The insulating substrate 10 can be a silicon-based substrate with an insulating dielectric layer on its surface, or a monolithic substrate made of insulating material. In a silicon-based substrate with an insulating dielectric layer on its surface, the silicon substrate provides structural strength and a smooth surface, while the insulating dielectric layer provides electrical insulation and process isolation. The insulating dielectric layer can be made of silicon oxide, silicon nitride, or silicon oxynitride, with a thickness of 400–600 nm, such as 400 nm, 450 nm, 500 nm, 550 nm, or 600 nm. This thickness range ensures sufficient insulation withstand voltage while avoiding stress accumulation due to excessive film thickness. When silicon oxide is used as the insulating dielectric layer, it can be formed by thermal oxidation or PECVD processes; when silicon nitride or silicon oxynitride is used, it can be formed by PECVD or LPCVD processes. A monolithic substrate made of insulating material can be a glass sheet, quartz sheet, or ceramic sheet. Such substrates are themselves insulators, eliminating the need for an additional insulating dielectric layer, offering advantages such as low material cost and simplified fabrication process. The selection of different insulating substrates can be determined based on the specific requirements of the packaging application for properties such as thermal conductivity, coefficient of thermal expansion, and light transmittance.

[0032] The Ti adhesion layer 20 is disposed on the insulating substrate 10, located between the insulating substrate 10 and the AlCu metal layer 30, which can improve the adhesion between the AlCu metal layer 30 and the insulating substrate 10. Ti can form a good interfacial bond with the underlying insulating substrate material and the upper AlCu alloy, avoiding film detachment caused by insufficient physical adsorption force when AlCu is directly deposited on the surface of the insulating substrate. The Ti adhesion layer 20 is deposited by magnetron sputtering, and the sputtering power and gas flow rate are controlled during the deposition process to obtain a uniform and continuous film layer. The thickness of the Ti adhesion layer 20 is preferably such that it can form a continuous and dense film layer without introducing excessive stress, and can be controlled in the range of 5 to 100 nm, for example, 5 nm, 10 nm, 20 nm, 30 nm, 50 nm, 80 nm or 100 nm. In other embodiments, in addition to pure Ti, the Ti adhesion layer 20 can also be made of TiW alloy or TiN. These Ti-containing materials can also form an effective bond with the insulating substrate and the AlCu layer, and can be selected according to specific diffusion barrier requirements or process compatibility requirements.

[0033] An AlCu metal layer 30 is disposed on the Ti adhesion layer 20, forming a metal interconnect layer suitable for high-density pad packaging. The AlCu metal layer 30 includes three functional regions: multiple metal pads 31, metal leads, and overlay marks 32. The thickness of the AlCu metal layer 30 is 0.8–1.2 μm, for example, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, or 1.2 μm. This thickness range provides sufficient mechanical strength for wire bonding while ensuring the controllability of photolithography and etching processes. The AlCu metal layer 30 is made of AlCu alloy, with a Cu mass percentage content of 0.5–2 wt%, for example, 0.5 wt%, 0.8 wt%, 1.0 wt%, 1.2 wt%, 1.5 wt%, or 2.0 wt%. Adding an appropriate amount of Cu can suppress Al electromigration and improve the long-term reliability of the metal interconnect. In other embodiments, in addition to AlCu alloy, the AlCu metal layer can also be replaced with AlSi alloy or AlSiCu alloy, wherein the addition of Si can also suppress electromigration and improve electrochemical corrosion resistance, and can be selected according to the specific type of chip electrode material and wire bonding process.

[0034] Metal pads 31 are areas on the substrate used for wire bonding to the electrodes of the optical chip or external leads. In high-density pad packaging, multiple metal pads 31 can be arranged in an array, parallel, or fan-out layout to accommodate the electrode distribution of multi-electrode optical chips. The dimensions of the metal pads 31 are 110–130 μm in length and 220–260 μm in width, for example, lengths of 110 μm, 115 μm, 120 μm, 125 μm, or 130 μm, and widths of 220 μm, 230 μm, 240 μm, 250 μm, or 260 μm. This size range meets the pad area requirements of wire bonding processes and is advantageous for arranging a large number of pads within a limited submount area. The shape of the metal pads 31 is usually rectangular, but they can also be designed as squares or other polygons depending on the chip electrode layout. The number and arrangement of the metal pads 31 are determined based on the electrode distribution and functional pin positions of the optical chip.

[0035] Metal leads are used to route chip electrode signals from pads to designated locations on the substrate or to interconnect pads. The minimum linewidth of a metal lead is 14–16 μm, for example, 14 μm, 15 μm, or 16 μm. The minimum spacing between adjacent metal leads is 22–28 μm, for example, 22 μm, 24 μm, 25 μm, 26 μm, or 28 μm. These linewidth and spacing ranges meet the requirements of high-density pad optical chip packaging for metal interconnect density and electrical isolation, while remaining within the capability window of conventional photolithography and etching processes.

[0036] like Figure 4 In this embodiment, the overlay marks 32 are typically located at the four corners of the layout and are cross-shaped. The cross-shaped marks facilitate identification and precise positioning within the lithography machine alignment system. The overlay marks 32 are used for alignment during subsequent patterning of the passivation protection layer 40, ensuring precise alignment between the window pattern of the passivation protection layer 40 and the metal pad 31 pattern, with an alignment accuracy not exceeding ±1 μm. In other embodiments, besides the cross shape, the overlay marks 32 can also adopt other geometric shapes such as a square, a circle, or a rectangle, as long as they can be effectively identified by the lithography machine alignment system. In other embodiments, the position of the overlay marks 32, in addition to the layout... Figure 4 Outside the corners, the marking lines can also be set in the edge area of ​​the plate or in the non-effective area to achieve alignment and improve the accuracy of the whole plate engraving.

[0037] A passivation protective layer 40 covers the AlCu metal layer 30 and protects the metal leads and pad edges from external contamination and mechanical damage. The material of the passivation protective layer 40 is selected from silicon oxide, silicon nitride, or silicon oxynitride, all of which possess good insulation, chemical stability, and adhesion to the metal layer. The thickness of the passivation protective layer 40 can be determined according to the required protection level and stress control requirements, typically in the range of 100–500 nm.

[0038] The passivation layer 40 has an opening in the area corresponding to the metal pad 31. The size of the opening is smaller than the size of the metal pad 31, that is, the single-sided indentation of the opening is 5-10 μm relative to the size of the metal pad 31. Specifically, the length is 100-120 μm and the width is 210-240 μm, for example, lengths of 100 μm, 105 μm, 110 μm, 115 μm or 120 μm, and widths of 210 μm, 220 μm, 230 μm or 240 μm. Figure 3 As shown, the window exposes a portion of the metal pad 31 for wire bonding; the pad edge area outside the window is covered by a passivation protective layer 40, which serves as edge shielding and protection. For high-density pad packages, because the effective bonding window is more concentrated and the spacing between adjacent pads is smaller, this recessed window can reduce edge contamination and short-circuit risk in adjacent areas while ensuring the bonding area.

[0039] In this invention, the boundary of the passivation protective layer 40 window is inwardly contracted in both the length and width directions relative to the boundary of the metal pad 31, so that the planar projection of the window falls entirely within the planar projection range of the metal pad 31. A ring of pad edge covered by the passivation protective layer 40 is left between each of the four sides of the window and the four sides of the pad. This structure is an inwardly contracted window (e.g., ...). Figure 3 Compared to flush-mount or outward-expanding window designs, flush-mount windows have their opening boundaries essentially aligned with the pad boundaries, while outward-expanding windows extend beyond the pad boundaries. In both of these cases, the pad edges are not covered by a passivation protection layer, and the pad sidewalls are directly exposed to the external environment. This invention employs a recessed window structure, which, while ensuring effective bonding area, covers and shields the pad sidewalls and edges with a passivation protection layer. This reduces the risk of dicing debris, coolant, ambient moisture, and chemical contaminants intruding from the pad edges, making it particularly suitable for high-density pad packaging scenarios with a large number of pads and small spacing between adjacent pads or leads.

[0040] If the passivation protection layer 40 window size is too large, close to or equal to the pad size, the pad edges will lose passivation layer protection, increasing the risk of edge contamination and corrosion. If the window size is too small, the bonding area will be insufficient, reducing the lead bonding strength and making it prone to cold solder joints or bond point detachment. For high-density pad packages, the above dimensional relationship can also reduce the risk of adjacent pad edges being exposed due to window offset.

[0041] See further Figure 5 The aforementioned high-density pad optical chip packaging submount transition substrate structure can be achieved through the following preparation method.

[0042] Step 1: Substrate preparation.

[0043] In a specific embodiment, an insulating substrate is provided, and the substrate is cleaned and subjected to plasma pretreatment. Cleaning removes particles, organic contaminants, and residual moisture from the substrate surface, and can be performed using wet or dry cleaning methods. Wet cleaning can employ a combination of organic solvents and deionized water, for example, sequential ultrasonic cleaning with acetone, isopropanol, and deionized water; dry cleaning can use ultraviolet ozone cleaning or plasma cleaning. Plasma pretreatment further enhances the surface activity of the substrate. Typically, argon or oxygen plasma is used to bombard the substrate surface, removing adsorbed residual contaminants and generating dangling bonds or polar groups to strengthen the adhesion between the subsequently sputtered metal film and the substrate. Plasma pretreatment can be performed within the pre-vacuum chamber of the sputtering equipment to prevent the pretreated surface from being re-contaminated by the atmosphere during the transfer process.

[0044] Step 2, metal layer deposition.

[0045] In this specific embodiment, a Ti adhesion layer and an AlCu metal layer are sequentially deposited on a pretreated insulating substrate using physical vapor deposition (PVD). Magnetron sputtering is the preferred PVD process, but electron beam evaporation or thermal evaporation can also be used. The Ti adhesion layer is deposited first, followed by the AlCu metal layer. Both processes can be completed continuously within the same sputtering chamber by switching targets or in different chambers. If a multi-chamber sputtering system is used, a vacuum environment can be maintained between the two steps to prevent oxidation or adsorption of contaminants on the Ti layer surface from affecting the bonding quality of the subsequent AlCu layer. Argon is typically used as the sputtering atmosphere, with the operating pressure controlled within the range of 0.2–1.0 Pa. The sputtering power is determined based on the desired deposition rate and film quality. The film thickness can be precisely controlled during deposition by adjusting the sputtering time or using an online film thickness monitoring system.

[0046] Step 3: Metal pattern photolithography.

[0047] In a specific embodiment, photoresist is coated onto the surface of an AlCu metal layer, and after exposure and development, a photoresist mask containing multiple metal pad patterns, metal lead patterns, and overlay marking patterns is formed. The multiple metal pad patterns and metal lead patterns are arranged according to a high-density pad package interconnection layout, which can form an array, parallel, or fan-out pad interconnection structure. Positive or negative photoresist can be used. Spin coating or spray coating is used, with the spin coating speed determined according to the required film thickness. After coating, pre-baking removes the solvent from the photoresist, allowing the film to solidify. The film thickness uniformity deviation is controlled within ±5% to ensure uniform energy distribution across the entire surface during exposure. Exposure can be performed using contact exposure, proximity exposure, or step-through projection exposure; the appropriate exposure method is selected based on the required resolution and overlay accuracy. The exposure dose is determined according to the photoresist type and thickness, and is controlled to avoid overexposure and underexposure. The type of developer and development time are determined based on the type of photoresist and the pattern size. After development, the linewidth of the metal lead pattern should deviate from the design value by no more than ±1 μm. After development, the sidewall morphology and pattern integrity of the photoresist mask are inspected using an optical microscope or automated optical inspection equipment to ensure that the mask sidewalls are steep and the edges are neat. After development, a post-baking hardening process is performed, with the heating temperature controlled at 100–140℃, for example, 110℃, 120℃, or 130℃, for 5–20 minutes. This further cross-links and cures the photoresist, enhancing its resistance to etching and its adhesion to the substrate surface.

[0048] Step four: etching and removing adhesive.

[0049] In a specific implementation, before etching, the area where the photoresist mask is formed is treated with oxygen plasma (O2 plasma). O2 plasma treatment is performed in a plasma resist remover or a reactive ion etching machine, using oxygen as the working gas. The active oxygen free radicals in the oxygen plasma react with trace amounts of residual organic matter in the photoresist opening area, decomposing it into CO2 and H2O, which are then removed by a vacuum system. The treatment time is typically 30 seconds to 3 minutes, for example, 30 seconds, 1 minute, 2 minutes, or 3 minutes, with an RF power of 50–300 W. This treatment effectively removes the thin resist and organic residue remaining in the metal etching area after development, preventing residual resist from locally blocking the etchant from contacting the AlCu surface during subsequent metal etching, thus preventing metal residue and short circuits between adjacent metal lines caused by localized etching inhibition. Besides O2 plasma, UV ozone treatment or ozone water treatment can also achieve the same residual resist removal effect.

[0050] In this specific embodiment, the AlCu metal layer is etched using a photoresist mask, transferring the mask pattern to the AlCu metal layer to form multiple metal pads, metal leads, and overlay marks. Wet etching or dry etching can be used, and the etching rate is measured before etching. The wet etching rate can be adjusted by controlling the temperature and concentration of the etching solution, while the dry etching rate can be adjusted by parameters such as RF power, gas flow rate, and chamber pressure. In this embodiment, the main etching time is determined based on the thickness of the AlCu metal layer, and an additional 5% to 15% is added to the main etching time as the actual etching time, for example, an increase of 5%, 8%, 10%, 12%, or 15%. The increase in etching time ensures that the AlCu in the area between the metal lines is sufficiently removed, while compensating for localized insufficient etching caused by differences in the etching rate within the wafer.

[0051] In a specific implementation, after etching, while retaining the photoresist mask, EDS (Electronic Direct Staining) is performed on the area exposed by the opening of the photoresist mask. After confirming the absence of Al and / or Cu elements, the photoresist mask is removed. EDS is performed using a scanning electron microscope or a separate EDS analysis system. The electron beam is focused between adjacent metal lines, adjacent pads, or other narrow-pitch interconnect regions to collect the characteristic X-ray energy spectrum of the excited material. If no signal intensity exceeding the background level is detected at the characteristic energy peaks of Al and Cu, it is confirmed that there are no Al or Cu residues in the relevant area, and subsequent resist removal and cleaning can proceed. If Al or Cu characteristic signals are detected, it indicates that there is incomplete metal etching in that area. The location and extent of the residue can be specifically determined, and supplementary etching or re-etching after adjusting process parameters can be performed. The purpose of retaining the photoresist mask is to maintain the original surface state after etching before inspection, avoiding the mechanical and chemical actions during resist removal and cleaning processes from masking or removing residual traces, which could lead to missed defects. This invention moves the discovery point of short-circuit defects to before the passivation process through EDS detection, which is particularly beneficial for reducing the risk of residual short circuits in narrow-pitch areas in high-density pad interconnect layouts, reducing rework costs and shortening the overall process development cycle.

[0052] Photoresist removal can be performed using either a wet or dry method. Wet removal uses organic stripping solutions or a sulfuric acid-hydrogen peroxide mixture to dissolve or strip the photoresist; dry removal uses O2 plasma to ash the photoresist. After stripping, the substrate is cleaned and dried to remove residual photoresist and reaction products, resulting in a clean metal pattern structure.

[0053] Step 5: Deposition of passivation protective layer.

[0054] In a specific embodiment, a passivation protective layer is deposited on the structure after the photoresist mask has been removed. The passivation protective layer is deposited using PECVD, but LPCVD, APCVD, ALD, or sputtering processes can also be used. PECVD utilizes plasma energy to excite chemical reaction precursors at relatively low temperatures; the deposition temperature is typically between 200 and 400°C, such as 250°C, 300°C, or 350°C. This is suitable for substrates with completed metal patterns and will not cause excessive grain growth or interface diffusion degradation in the AlCu metal layer. The material of the passivation protective layer is selected from silicon oxide, silicon nitride, or silicon oxynitride. Silicon oxide can be deposited using silane and nitrous oxide or tetraethoxysilane as precursors; silicon nitride can be deposited using silane and ammonia as precursors; silicon oxynitride can be deposited using a mixture of silane, ammonia, and nitrous oxide as precursors, with the refractive index and stress of the thin film controlled by adjusting the flow ratio of ammonia to nitrous oxide. The thickness of the passivation protective layer is determined based on the required protection level and stress control requirements, and is precisely controlled by adjusting the deposition time or using an online film thickness monitoring system. After the passivation protective layer is deposited, the film thickness and refractive index can be tested and confirmed using an ellipsometer or reflectance spectrometer.

[0055] Step 6: Graphical processing of the passivation protective layer.

[0056] In a specific implementation, the passivation protective layer is patterned to form windows, the size of which is smaller than the size of the metal pads. The patterning process includes coating the passivation protective layer surface with photoresist, forming a window mask pattern using photolithography, and then etching the passivation protective layer with photoresist or a hard mask. The etching of the passivation protective layer can be performed using dry etching or wet etching. Dry etching can employ reactive ion etching, using fluorine-containing gas as the main etching gas, which exhibits high etching rates and selectivity for silicon oxide, silicon nitride, and silicon oxynitride. Wet etching can use buffered oxide etching solutions or diluted hydrofluoric acid solutions, offering simpler and lower-cost etching operations. Before etching, the etching rate is measured, and the main etching time is determined based on the thickness of the passivation protective layer. The actual etching time is then increased by 5% to 15% from the main etching time, for example, by 5%, 8%, 10%, 12%, or 15%, to ensure that the passivation layer in the windowed area is completely removed and the surface of the metal pads is fully exposed. For high-density pad packages, the window pattern can be set to correspond one-to-one with multiple pads, and the inward size design ensures that the edges of each pad retain passivation protection layer coverage.

[0057] During the graphical processing, through the version Figure 4Overlay marks at corners or other locations align the passivation protection layer window pattern with the metal pad pattern, with an alignment accuracy not exceeding ±1μm. Controlling this alignment accuracy directly affects the window position accuracy. If the alignment deviation exceeds ±1μm, the window position will shift relative to the pad, potentially causing insufficient exposure of one pad, affecting the bonding area, or the other pad edge losing passivation layer protection. In high-density pad packaging, it may also increase the risk of exposure or contamination of adjacent pad areas. After window etching, the photoresist of the window mask is removed, and the window area is inspected to confirm accurate window position, complete window opening, full exposure of the metal pad surface, and that the metal pad edge area remains covered by the passivation layer. Inspection methods can include optical microscopy, SEM, EDS, or probe contact testing.

[0058] Step 7: Divide the area into zones.

[0059] In a specific embodiment, a protective adhesive layer is formed on the structural surface with passivation protection layer openings. This protective adhesive layer covers the metal pads, metal leads, and the passivation protection layer opening area. The protective adhesive layer is formed by spin coating, with the spin coating speed and time determined based on the adhesive viscosity and the required film thickness. The protective adhesive can be a thermoplastic resin or photoresist, requiring appropriate viscosity and flowability to completely cover the exposed pad surface in the opening area, forming a uniform protective film that is not easily washed away by coolant during subsequent dicing processes. For high-density pad packaging, the protective adhesive layer covers multiple pads and their adjacent fine lead areas to prevent dicing particles from concentrating in smaller bonding windows. After spin coating, a curing process is performed according to the protective adhesive material characteristics, such as heat curing or UV curing, to form a stable coating. The protective adhesive layer can also be formed by spraying or lamination. Spray coating is suitable for substrates with significant surface undulations or high aspect ratios, providing uniform coverage of complex morphologies. Film lamination involves applying a pre-formed protective film to the substrate surface, offering ease of operation, good film thickness uniformity, and convenient removal. The specific formation method of the protective adhesive layer can be selected based on the substrate surface morphology, production cycle time, and cost requirements. During subsequent dicing, the protective adhesive layer acts as a physical barrier, preventing silicon chips, oxide debris, and coolant generated by the high-speed dicing process from directly contacting and adhering to the metal pad surface.

[0060] In a specific implementation, the structure with the protective adhesive layer is diced to obtain individual substrates. Dicing can be performed using a diamond blade (mechanical dicing) or a laser dicing. Mechanical dicing uses a high-speed rotating diamond blade to cut along the dicing path, dividing the entire wafer into individual substrates. Laser dicing uses a focused laser beam to ablate or stealth-cut along the dicing path, resulting in low stress and minimal edge chipping, making it suitable for applications sensitive to mechanical stress or with thin substrates. During dicing, coolant or deionized water is used to cool the blade and rinse away debris. After dicing, the protective adhesive layer on the surface of each individual substrate is removed and the substrate is cleaned. Adhesive removal can be performed using appropriate methods depending on the type of protective adhesive material, such as soaking in organic solvents to dissolve, peeling with alkaline adhesive remover, or tearing. Cleaning can be performed using a combination of organic solvents and deionized water to remove adhesive remover residue and trace contaminants that may have adhered during the dicing process. After cleaning, a high-density pad optical chip packaging submount transition substrate with clean pad surface is obtained. There are no obvious scratches, particles and coolant residues on the pad surface, and it can be directly used for subsequent optical chip mounting and wire bonding processes.

[0061] The submount transition substrate prepared through the above steps can be used for high-density pad optical chip packaging. The optical chip can be a laser chip, detector chip, optical modulation chip, or optical communication chip, or other optoelectronic chips with multiple closely spaced electrodes requiring fan-out interconnection. The optical chip is mounted at predetermined positions on the submount transition substrate, and multiple electrodes of the optical chip are electrically interconnected with multiple metal pads on the substrate via wire bonding. Because the surface of the substrate pads is protected during preparation through recessed windows and a protective adhesive layer, the surface cleanliness of the pads is high before bonding, allowing for reliable bonding between the gold or aluminum wires and the pads during wire bonding, ensuring bonding strength and electrical connection consistency. Wire bonding can be performed using ultrasonic thermocompression bonding or ultrasonic wedge bonding, with appropriate bonding parameters selected based on the chip electrode material and pad metal type. After wire bonding, hermetically sealed or hermetically sealed packaging can be performed as needed to form a complete optoelectronic device.

[0062] Example After completing the wafer-level fabrication of the Ti / AlCu silicon-based submount transition substrate according to the above preparation method, the substrate is subjected to wire bonding testing and reliability evaluation. This embodiment illustrates the impact of the fabrication process of the present invention on the bondability and reliability of the pads by comparing the process before and after optimization.

[0063] Substrate and metal layer parameters In this embodiment, the insulating substrate is a 4-inch silicon wafer with a thermally oxidized SiO2 insulating layer of approximately 500 nm thickness on its surface. The Ti adhesion layer is approximately 10 nm thick, the AlCu metal layer is approximately 1 μm thick, and the Cu content in the AlCu metal layer is approximately 1 wt% by mass.

[0064] Process parameters before optimization and problem manifestations In the original fabrication process, the AlCu metal layer was sputtered and then directly subjected to metal patterning photolithography. AZ1518 positive photoresist was used for photolithography, and the spin-coated film thickness was approximately 1.5 μm. The exposure dose was 200 mJ / cm². 2 The development time was 40 s. No O2 plasma photoresist removal step was performed after development. AlCu etching was performed using ICP etching with Cl2 / BCl3 / Ar as the etching gas at a flow rate ratio of 3:2:2, for approximately 7 min (no over-etching was set based on the main etching time). Photoresist was removed directly after etching without retaining it for EDS inspection before removal. The passivation protective layer was deposited using PECVD with SiO2 approximately 1 μm thick at a deposition temperature of 200 ℃. SiO2 windowing etching was performed using ICP etching with CF4 / CHF3 / Ar as the etching gas at a flow rate ratio of 25:8:10, for approximately 310 s. No over-etching was set. Photoresist was removed directly after windowing etching without EDS confirmation. No protective resist layer was applied before dicing. Surface cleaning before bonding was performed using plasma surface cleaning, with a 10 min interval between cleaning and bonding. The wire bonding uses 25μm diameter Au gold wire, and the bonding method is ultrasonic thermo-press bonding. The bonding pressure is 35 cN, the ultrasonic power is 90 mW, the bonding time is 25 ms, and the platform temperature is 150℃.

[0065] like Figure 6 Under the above process conditions, during wire bonding testing, some AlCu pads showed no obvious solder joint footprints on their surfaces. In the tensile test (results see...),... Figure 10 The average pull force of the solder joint was 3.18g, which is lower than the lower limit of the technical specification of 4.3g. Based on the process flow analysis, this failure may be related to the AlCu layer thickness, photoresist residue, etching by-product residue, SiO2 window integrity, natural oxidation of the solder pad surface, and dicing contamination.

[0066] Optimized process parameters and effects To address the aforementioned issues, this embodiment optimizes each process step in subsequent batches.

[0067] After photolithography and development, an O2 plasma process is added to remove residual photoresist. The processing time is 60 seconds and the RF power is 150W. Figure 7 The results of the metal pattern photolithography microscope inspection in this embodiment show that the optimized metal lead boundaries are clear and the edges are neat, the photoresist mask pattern is complete, and there is no rough edge phenomenon caused by residual photoresist.

[0068] Before etching AlCu, the etching rate was measured. Based on the AlCu layer thickness, the main etching time was determined to be 7 minutes, with an additional 1 minute for over-etching. After etching, while retaining the photoresist mask, EDS analysis was performed on the area exposed by the photoresist mask openings to confirm the absence of Al and Cu residues before removing the photoresist and cleaning. Figure 8 The results of EDS detection of the photoresist residue after etching in this embodiment show that no characteristic signals of Al and Cu were detected in the EDS energy spectrum of the area exposed by the opening of the photoresist mask, indicating that Al and Cu in the area between the metal lines have been completely removed and there is no risk of short circuit caused by metal residue.

[0069] A SiO2 passivation protective layer was deposited by PECVD at a temperature controlled at 300℃. Figure 9 The thickness ellipsometry test results after PECVD in this embodiment show that the average SiO2 film thickness is about 1 μm. The film thickness uniformity is good at multiple points within the wafer, which meets the process requirements for passivation protection and window etching.

[0070] Before the SiO2 window etching, the etching rate was measured. An additional 50 seconds of over-etching was added to the main etching time of 310 seconds. After the window etching was completed, EDS detection was performed to confirm that the AlCu on the pad surface was effectively exposed.

[0071] Before dicing, a 1.5 μm thick layer of AZ1518 protective adhesive is spin-coated to cover the metal pads, metal leads, and passivation protection layer opening areas. Before bonding, the substrate undergoes wet cleaning and plasma cleaning, with the time interval between cleaning and bonding controlled to be within 2 hours.

[0072] Figure 10 The results are from the tensile test. Maintaining the same lead bonding parameters as before optimization, the average tensile force of the solder joints in the optimized lead-bonded samples increased to 10.46g. The main failure mode changed from non-adhesive pad and interface peeling before optimization to lead breakage or neck breakage, indicating that the bond strength between the lead and pad interface has exceeded the strength of the lead body, and the bonding interface is no longer the weakest link.

[0073] This embodiment illustrates that reliable wire bonding of Ti / AlCu silicon-based submounts is an interface reliability issue jointly determined by the pad material structure, surface condition, window integrity, cleaning window, and dicing contamination control. By implementing the process flow of this invention, potential defects scattered in each step are incorporated into unified management, which can effectively improve pad bonding capability and bonding reliability.

[0074] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0075] The above description describes specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a submount transition substrate for high-density pad optical chip packaging, characterized in that, Includes the following steps: An insulating substrate is provided, and the insulating substrate is cleaned and subjected to plasma pretreatment; Ti adhesion layer and AlCu metal layer are sputtered sequentially on a pretreated insulating substrate; Metal pattern photolithography is performed on the AlCu metal layer to form a photoresist mask containing multiple metal pad patterns, metal lead patterns and overlay mark patterns. The multiple metal pad patterns and metal lead patterns are arranged in a high-density pad package interconnection layout. The AlCu metal layer is etched using the photoresist mask to form metal pads, metal leads, and overlay marks; Remove the photoresist mask; A passivation protective layer is deposited on the structure after the photoresist mask is removed; The passivation protective layer is patterned to form a passivation protective layer window, the size of which is smaller than the size of the metal pad; A protective adhesive layer is formed on the structural surface where the passivation protective layer window is formed, and the protective adhesive layer covers the metal pad, the metal lead and the passivation protective layer window area; The structure with the protective adhesive layer formed is diced to obtain a single substrate; The protective adhesive layer on the surface of the single substrate is removed and cleaned to obtain the Submount transition substrate for high-density pad optical chip packaging.

2. The preparation method according to claim 1, characterized in that, After etching is completed, before removing the photoresist mask, EDS detection is performed on the area exposed by the opening of the photoresist mask while retaining the photoresist mask. After confirming that there are no residual Al and / or Cu elements, the photoresist mask is removed.

3. The preparation method according to claim 1, characterized in that, Before the step of etching the AlCu metal layer with the photoresist mask, the method further includes: treating the area where the photoresist mask is formed with O2 plasma to remove residual photoresist.

4. The preparation method according to claim 1, characterized in that, When the passivation protective layer is patterned, the window pattern of the passivation protective layer is aligned with the pattern of the metal pad through the overlay mark, and the alignment accuracy does not exceed ±1μm.

5. A submount transition substrate for high-density pad optical chip packaging, characterized in that, include: Insulating substrate; A Ti adhesion layer is disposed on the insulating substrate; An AlCu metal layer is disposed on the Ti adhesion layer. The AlCu metal layer includes multiple metal pads, metal leads, and overlay marks. The multiple metal pads and the metal leads are arranged in an array or fan-out high-density pad interconnection layout. A passivation protective layer is applied over the AlCu metal layer. The passivation protective layer has an opening in the area corresponding to the metal pad, and the size of the opening is smaller than the size of the metal pad.

6. The Submount transition substrate according to claim 5, characterized in that, The material of the passivation protective layer is selected from silicon oxide, silicon nitride, or silicon oxynitride.

7. The Submount transition substrate according to claim 5, characterized in that, The insulating substrate is a silicon wafer with a silicon oxide layer on its surface, the thickness of which is 400–600 nm; the AlCu metal layer has a thickness of 0.8–1.2 μm and a Cu mass percentage content of 0.5–2 wt%.

8. The Submount transition substrate according to claim 5, characterized in that, The length and width of the opening are smaller than the length and width of the metal pad, respectively, and the single-sided inward reduction of the opening is 5 to 10 μm.

9. The Submount transition substrate according to claim 5, characterized in that, The minimum linewidth of the metal leads is 14–16 μm, and the minimum spacing between adjacent metal leads is 22–28 μm.

10. The application of a submount transition substrate according to any one of claims 5 to 9 in high-density pad optical chip packaging, characterized in that, The Submount transition substrate is used to wire bond and interconnect an optical chip with multiple closely spaced electrodes to a packaging carrier or external circuit. The optical chip is a laser chip, a detector chip, an optical modulation chip, or an optical communication chip.

Images