Spaceborne Ka TT&C communication machine star-ground time difference measurement method

Abstract

The application discloses a space-ground time difference measurement method of a spaceborne Ka TT&C communication machine, and relates to the technical field of spacecraft TT&C communication.The method adopts an AD9361 plus FPGA architecture, acquires an external 10MHz clock which is shaped through a Schmitt trigger, and converts a PPS signal into a single-ended signal through a 422 chip.FPGA utilizes a reference clock to generate 4 paths of homologous and different-phase clocks, and simultaneously uses rising edges and falling edges to sample Start and Stop signals, so that 1 / 8 clock period resolution is obtained.Crude counting, Start fine counting and Stop fine counting are obtained according to the sampling results, and time difference is calculated, and finally filled into a downlink measurement frame.The application reduces radio frequency complexity, increases hardware very little, and has simple logic, so that high-precision time difference measurement function can be realized, and large-scale satellite networking requirements can be met.

Description

Technical Field

[0001] This invention belongs to the field of spacecraft telemetry, tracking, and command (TT&C) technology, and in particular relates to a method for measuring the time difference between space and ground on a spaceborne Ka-band TT&C system. Background Technology

[0002] The spaceborne Ka-band telemetry and control unit (TT&C) is an important payload on spacecraft, primarily used to establish a satellite-to-ground link with ground-based TT&C stations to perform tasks such as satellite-to-ground remote control, telemetry, high-speed data uploading, ranging, and time difference measurement. It typically has the capability to perform pseudocode measurement on uplink frames to generate downlink telemetry frames, thereby cooperating with ground stations to achieve satellite ranging, velocity measurement, and time difference measurement.

[0003] With the development of large-scale satellite networking technology, higher requirements have been placed on obtaining high-precision satellite-to-ground time difference data to meet the needs of services such as navigation enhancement. This requires that the onboard telemetry, tracking, and command (TT&C) equipment must have high-precision time difference measurement capabilities, and the measurement accuracy typically needs to be within 6.5 ns.

[0004] However, existing telemetry and control (TT&C) receiving equipment typically employs a complex hardware architecture to achieve the aforementioned functions, including antennas, antenna networks, amplifiers, filters, mixers, local oscillators, and analog-to-digital converters. This traditional architecture is overly complex, increasing system size and power consumption, and failing to meet the current design requirements for miniaturization and lightweight spacecraft transponders. Furthermore, achieving high-precision time difference measurement within a complex RF architecture often further increases hardware resource consumption and system design complexity. Therefore, there is an urgent need for a simple, miniaturized, and high-precision spaceborne Ka-band TT&C satellite ground time difference measurement method. Summary of the Invention

[0005] To address the challenges of complex receiver architectures in existing spaceborne telemetry and communication systems, which hinder transponder miniaturization and high-precision time difference measurement while simplifying the architecture, a new method for measuring satellite-to-ground time difference in spaceborne Ka-band telemetry and communication systems is proposed. This method employs a simplified hardware architecture, significantly reducing radio frequency complexity while meeting the high-precision satellite-to-ground time difference measurement requirements of large-scale satellite networking and navigation enhancement services.

[0006] To achieve the above objectives, the technical solution of the present invention is implemented as follows: A method for measuring the time difference between satellite and ground in a spaceborne Ka-band telemetry and communication unit is applied to a spaceborne Ka-band telemetry and communication unit, which includes an FPGA. The method includes: An external 10MHz clock signal is acquired, shaped by a Schmitt trigger, and output to the FPGA as a reference clock; a PPS differential signal is acquired, converted into a single-ended signal by a 422 chip, and given to the FPGA as a Start signal; the Start signal is a PPS signal, valid on the falling edge, corresponding to the start of a whole second; the sampling time of the measurement frame is acquired as the Stop signal; the Stop signal is the trailing edge signal of the last bit of the measurement frame synchronization code, valid on the falling edge. The FPGA uses a reference clock to generate four clocks of the same origin but different phases, and simultaneously uses the rising and falling edges of the four clocks to sample the Start and Stop signals respectively, to obtain a sampling accuracy of 1 / 8 clock cycle resolution. Based on the sampling results, obtain the coarse count, the start fine count, and the stop fine count; Calculate the time difference based on the coarse count, the start fine count, and the stop fine count; Fill the time difference into the downlink measurement frame.

[0007] Furthermore, the FPGA uses a reference clock to generate four co-originating clocks with different phases, specifically including: The FPGA internally generates four 125MHz clocks: the first has a phase of 0 degrees, the second has a phase of 45 degrees, the third has a phase of 90 degrees, and the fourth has a phase of 135 degrees. By using the rising and falling edges of four clocks simultaneously, eight different phase clock effects are simulated.

[0008] Furthermore, the Start fine count is obtained based on the sampling results, specifically including: The input Start signal is latched in three stages using eight different phase clocks. When the falling edge of the Start signal is detected at the rising edge of the 0-degree phase clock, the signals after each latching stage are latched again to obtain phase state values ​​D0 to D8, each of which is 0 or 1. Add D1 to D8 to obtain the precise phase P_START between the falling edge of the Start signal and the rising edge of the nearest 0-degree phase clock before that falling edge. Calculate the time difference between the falling edge of the Start signal and the rising edge of the nearest 0-degree phase clock after that falling edge. The calculation formula is: ; The unit is 1 ns.

[0009] Furthermore, based on the sampling results, a detailed count of Stops is obtained, specifically including: The input Stop signal is latched in three stages using eight different phase clocks. When the falling edge of the Stop signal is detected at the rising edge of the 0-degree phase clock, the signals after each latching stage are latched again to obtain phase state values ​​D1 to D8, each of which is 0 or 1. Add D1 to D8 to obtain the precise phase P_STOP of the Stop signal falling edge relative to the nearest 0-degree phase rising edge of the clock preceding that falling edge, in units of 1ns; The time difference between the falling edge of the Stop signal and the rising edge of the nearest 0-degree phase clock after that falling edge. It equals P_STOP.

[0010] Furthermore, a coarse count is obtained based on the sampling results, specifically including: Count the number of rising edges of the 0-degree phase clock between the falling edge of the Start signal and the falling edge of the Stop signal, and subtract 1 from the count to obtain the coarse count value N.

[0011] Furthermore, the time difference is calculated based on the coarse count, the start fine count, and the stop fine count, specifically including: Calculate time difference Its value is N multiplied by Add P_STOP and P_START, where The clock cycle is measured in 1 ns. Will Converted to units of 0.2 ns The calculation formula is: ; Inside the FPGA Shift left by 2 bits and then AND Adding them together achieves the effect of multiplying by 5.

[0012] Furthermore, the time difference is filled into the downlink measurement frame, specifically including: The downlink measurement frame is 500 bits in total; Will The result is filled into bits 27 to 59 of the downlink measurement frame; The whole-second counts within bits 10 to 26 are obtained by the MCU via the CAN bus and forwarded to the FPGA. The FPGA then directly calls and fills the bits 10 to 26.

[0013] Furthermore, the methods also include: Each input signal of the measurement is processed by synchronizing it to avoid metastability of asynchronous signals.

[0014] Furthermore, the communication unit uses an external 10MHz high-stability crystal oscillator for high-precision time measurement, while using an internal 40MHz ordinary temperature-compensated crystal oscillator for the operation of the radio frequency module; in the absence of an external 10MHz high-stability crystal oscillator, the communication unit relies on a 40MHz clock to complete remote control, telemetry, distance measurement and speed measurement functions.

[0015] Compared with existing technologies, the satellite-to-ground time difference measurement method of the spaceborne Ka telemetry and communication system of the present invention has the following advantages: (1) This invention adopts an architecture based on AD9361 and FPGA, which greatly reduces the complexity of radio frequency and is conducive to the miniaturization and lightweight design of spacecraft transponders. For the time difference measurement part, the hardware circuit of this invention only adds a Schmitt trigger and a 422 differential to single-ended driver, with very few additional components, effectively reducing hardware costs and design difficulty. The telemetry and communication device of this invention can complete remote control, telemetry, ranging, and speed measurement functions with a 40MHz clock, and only the time difference part uses a 10MHz external clock. In the absence of a 10MHz external clock, the telemetry and control functions can still work normally, thereby significantly improving the reliability of the system.

[0016] (2) The present invention uses four clocks of the same source but different phases, and simultaneously uses the rising edge and falling edge to sample the input pulse, thereby obtaining a sampling accuracy of 1 / 8 clock cycle resolution, which greatly improves the time resolution. The time difference measurement part of the present invention has simple logic and does not require complex algorithm calculations, so it can achieve a measurement accuracy of less than 6.5ns, which fully meets the needs of large-scale satellite networking for high-precision satellite-to-ground time difference measurement.

[0017] (3) The method of the present invention has good versatility and is also applicable to S-band, X-band and QV-band telemetry and communication equipment, as well as to situations where the signal to be measured is a falling edge; higher precision measurement can be achieved by increasing the sampling clock frequency, and it has good precision expansion capability. Attached Figure Description

[0018] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the receiving link according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the transmission channel according to an embodiment of the present invention; Figure 3 This is a block diagram and interface schematic diagram of the Ka measurement and control terminal according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the baseband system according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a 10MHz clock shaping circuit according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the RS422 interface circuit according to an embodiment of the present invention; Figure 7 This is a schematic block diagram of the FPGA TDC measurement implementation according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the FPGA timing relationship in an embodiment of the present invention; Figure 9 The following are the FPGA program simulation results for the time difference measurement section of this invention. Figure 1 Schematic diagram; Figure 10 The following are the FPGA program simulation results for the time difference measurement section of this invention. Figure 2 Schematic diagram; Figure 11 This is a schematic diagram of the test results for the time difference measurement function in an embodiment of the present invention. Detailed Implementation

[0019] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0020] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0021] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0022] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0023] This invention provides a hardware system architecture for a spaceborne Ka telemetry and control communication device. In this embodiment, a spaceborne Ka telemetry and control communication device is provided. This communication device operates in the Ka band and is mainly used for telemetry and control communication between space and ground, including functions such as remote control, telemetry, ranging, and time difference measurement.

[0024] like Figure 3 As shown, the spaceborne Ka telemetry, tracking, and command (TT&C) system consists of one Ka TT&C communication unit, two Ka TT&C receiving antennas, and two Ka TT&C transmitting antennas. The Ka TT&C receiving antennas are used to receive Ka remote control signals transmitted from the ground. The Ka TT&C transmitting antennas are used to radiate and transmit the telemetry radio frequency signals output by the TT&C communication unit.

[0025] The Ka-band telemetry and communication unit performs functions such as Ka-band signal RF reception, modulation and transmission, baseband processing, and interface. The unit consists of a Ka-band RF transceiver module and a Ka-band baseband board. The Ka-band RF transceiver module includes a network, an RF receiving channel, and an RF transmitting channel.

[0026] like Figure 1 As shown, the Ka-band receiving channel mainly consists of a power divider, ceramic filter, low-noise amplifier, mixer, gain amplifier, attenuator, and LTCC low-pass filter. The specific link is as follows: the signal sequentially passes through the power divider, bandpass filter, amplifier, mixer, amplifier, temperature-compensated attenuator, bandpass filter, amplifier, attenuator, and finally outputs through the low-pass filter. This channel primarily enables cross-connection of signals from two antennas, performing low-noise amplification, down-conversion, filtering, and amplification on the uplink RF signal.

[0027] like Figure 2 As shown, the input signal to the transmit channel comes from the baseband, is amplified to the corresponding level, and then radiated by the antenna. The transmit channel consists of a temperature-compensated attenuator, filter, mixer, amplifier, isolator, etc. The specific link is as follows: the signal sequentially passes through a temperature-compensated attenuator, bandpass filter, amplifier, temperature-compensated attenuator, mixer, attenuator, bandpass filter, amplifier, bandpass filter, isolator, amplifier, and finally outputs through a power divider. This channel filters and amplifies the transmitted S-band signal, performs up-conversion and power amplification, and sends it to the antenna for transmission.

[0028] The Ka baseband board handles tasks such as providing 422, CAN, and OC interfaces, as well as processing measurement and control baseband signals. For example... Figure 4As shown, the baseband of the communication unit adopts a general-purpose hardware platform of FPGA and MCU. The FPGA mainly implements demodulation, decoding, and OC command execution of the uplink intermediate frequency signal. It performs framing, modulation, encoding, and filtering of the telemetry data signal received from the 422 receiver before sending it to the transmission channel for RF processing. It also implements measurement and high-precision time difference measurement functions. The MCU software is mainly used for external interface processing, acquiring analog telemetry data from the telemetry and control communication unit and converting it into digital status telemetry data; completing CAN bus communication to send status telemetry data and receive bus commands; and obtaining the second count within a day through the CAN bus and forwarding it to the FPGA. The core RF chip of the baseband uses the AD9361, which works in conjunction with a 40MHz temperature-compensated crystal oscillator.

[0029] In another embodiment, the present invention provides a time difference measurement interface circuit, which, compared with conventional measurement and control functions, adds a 10MHz external clock and a PPS signal to the hardware.

[0030] like Figure 5 As shown, the 10M clock signal is connected to the SSMA-K connector on the communication device via a coaxial cable, and is shaped by a Schmitt trigger before being output to the FPGA. This circuit uses a Schmitt trigger to shape the input 10M signal, which can reduce glitches in the clock signal and output a 10M_FPGA signal.

[0031] like Figure 6 As shown, the PPS interface uses an AM26LV32 RS422 chip powered by 3.3V to receive differential signals and convert them into single-ended signals for further processing by the FPGA. This circuit is an RS422 interface circuit. The PPS+ and PPS- differential signals are converted by a resistor network and the chip, and the single-ended PPS output is connected to the FPGA.

[0032] In another embodiment, the present invention provides a method for measuring the time difference between satellite and ground on a spaceborne Ka-band telemetry and communication device, the method comprising: An external 10MHz clock signal is acquired, shaped by a Schmitt trigger, and output to the FPGA as a reference clock; a PPS differential signal is acquired, converted into a single-ended signal by a 422 chip, and given to the FPGA as a Start signal; the Start signal is a PPS signal, valid on the falling edge, corresponding to the start of a whole second; the sampling time of the measurement frame is acquired as the Stop signal; the Stop signal is the trailing edge signal of the last bit of the measurement frame synchronization code, valid on the falling edge. The FPGA uses a reference clock to generate four clocks of the same origin but different phases, and simultaneously uses the rising and falling edges of the four clocks to sample the Start and Stop signals respectively, to obtain a sampling accuracy of 1 / 8 clock cycle resolution. Based on the sampling results, obtain the coarse count, the start fine count, and the stop fine count; Calculate the time difference based on the coarse count, the start fine count, and the stop fine count; Fill the time difference into the downlink measurement frame.

[0033] In this embodiment, an architecture based on AD9361 and FPGA is adopted. The telemetry and communication unit uses an external 10MHz high-stability crystal oscillator for high-precision time measurement, and also uses an internal 40MHz ordinary temperature-compensated crystal oscillator for the operation of the RF chip AD9361 and the RF module. Even without the external 10MHz high-stability crystal oscillator, the telemetry and communication unit can still perform remote control, telemetry, distance measurement, and speed measurement functions using a 40MHz clock; only the time difference component cannot function. For the time difference component, the circuit only adds a Schmitt trigger and a 422 differential-to-single-ended driver.

[0034] Both on-board and ground sampling times are based on the trailing edge of the synchronization code of the downlink measurement frame. The measurement data timestamp is the time when the on-board sampling pulse is formed, which is the trailing edge of the synchronization code of the downlink measurement frame. The ground station subtracts the downlink transmission delay from the ground time corresponding to the trailing edge of the synchronization code of the received downlink measurement frame to obtain the accurate timestamp. The downlink measurement frame format is shown in Table 1.

[0035] Table 1 The downlink measurement frame is 500 bits in total. Bits 10 to 26 are the count of whole seconds within a day; bits 27 to 59 are the count of seconds within a second, with a quantization unit of 0.2 ns.

[0036] like Figure 7 As shown, the measurement and control algorithm software runs within the processing FPGA, completing a series of tasks including uplink signal downconversion, despreading, demodulation, and decoding; downlink signal spread spectrum, modulation, encoding, and time difference measurement. The core of the time difference measurement section lies in the TDC module. The navigation output differential 422 signal is converted into a PPS signal by the 422 chip as the Start signal, and the navigation output 10M signal is shaped into a 10M reference clock by a Schmitt trigger. The sampling time of the measurement frame is used as the Stop signal. The FPGA_DCM module uses the 10M reference clock to generate a multi-phase clock input to the TDC module. The TDC module outputs coarse counts, Start fine counts, and Stop fine counts to the time data processing module, which, combined with the intraday whole-second count provided by the ARM, finally generates the downlink measurement frame.

[0037] The basic formula for time difference measurement is as follows: ; in, The time difference is the measurement. For a 125MHz sampling clock, the clock cycle is [number] cycles. Equals 8ns; N is the number of rising edges of the Sys_Clk125_P0 clock between the falling edge of the Start signal and the falling edge of the STOP signal minus 1; This is the time difference between the falling edge of the Start signal and the rising edge of the first clock cycle Sys_Clk125_P0 on the right. This is the time difference between the falling edge of the Stop signal and the rising edge of the first clock cycle Sys_Clk125_P0 on the right.

[0038] The Start signal is the PPS signal, valid on the falling edge, corresponding to the start of a whole second. The STOP signal is the signal following the last bit of the synchronization code of the measurement frame, valid on the falling edge.

[0039] The FPGA internally generates four 125MHz clock channels. The first channel has a phase of 0 degrees, the second channel has a phase of 45 degrees, the third channel has a phase of 90 degrees, and the fourth channel has a phase of 135 degrees. They are named Sys_Clk125_P0, Sys_Clk125_P45, Sys_Clk125_P90, and Sys_Clk125_P135, respectively.

[0040] The process of obtaining the Start count is as follows: First, perform the following processes simultaneously: Using the rising edge of the Sys_Clk125_P0 clock, latch the input Start signal to obtain P0_Start_D0; using the rising edge of the Sys_Clk125_P0 clock, latch the P0_Start_D0 signal to obtain P0_Start_D1; using the rising edge of the Sys_Clk125_P0 clock, latch the P0_Start_D1 signal to obtain P0_Start_D2.

[0041] Using the rising edge of the Sys_Clk125_P45 clock, latch the input Start signal to obtain P45_Start_D0; using the rising edge of the Sys_Clk125_P45 clock, latch the P45_Start_D0 signal to obtain P45_Start_D1; using the rising edge of the Sys_Clk125_P45 clock, latch the P45_Start_D1 signal to obtain P45_Start_D2.

[0042] Using the rising edge of the Sys_Clk125_P90 clock, latch the input Start signal to obtain P90_Start_D0; using the rising edge of the Sys_Clk125_P90 clock, latch the P90_Start_D0 signal to obtain P90_Start_D1; using the rising edge of the Sys_Clk125_P90 clock, latch the P90_Start_D1 signal to obtain P90_Start_D2.

[0043] Using the rising edge of the Sys_Clk125_P135 clock, latch the input Start signal to obtain P135_Start_D0; using the rising edge of the Sys_Clk125_P135 clock, latch the P135_Start_D0 signal to obtain P135_Start_D1; using the rising edge of the Sys_Clk125_P135 clock, latch the P135_Start_D1 signal to obtain P135_Start_D2.

[0044] Using the falling edge of the Sys_Clk125_P0 clock, latch the input Start signal to obtain N0_Start_D0; using the falling edge of the Sys_Clk125_P0 clock, latch the N0_Start_D0 signal to obtain N0_Start_D1; using the falling edge of the Sys_Clk125_P0 clock, latch the N0_Start_D1 signal to obtain N0_Start_D2.

[0045] Similarly, using the falling edges of the Sys_Clk125_P45, Sys_Clk125_P90, and Sys_Clk125_P135 clocks, the Start signal is latched in three stages to obtain N45_Start_D0 to N45_Start_D2, N90_Start_D0 to N90_Start_D2, and N135_Start_D0 to N135_Start_D2.

[0046] Secondly, at the rising edge of the Sys_Clk125_P0 clock, if P0_Start_D1 is 0 and P0_Start_D2 is 1, then P0_Start_D2, P45_Start_D2, P90_Start_D2, P135_Start_D2, N0_Start_D2, N45_Start_D2, N90_Start_D2, and N135_Start_D2 are latched to obtain D0, D1, D2, D3, D4, D5, D6, D7, and D8, each of which is either 0 or 1.

[0047] Adding the phase values ​​obtained above, we get the precise phase P_START between the falling edge of the Start signal and the rising edge of the nearest clock Sys_Clk125_P0 preceding that falling edge. The calculation formula is as follows: ; The time difference between the falling edge of the Start signal and the rising edge of the nearest clock cycle Sys_Clk125_P0 after that falling edge is calculated using the following formula: ; The unit is 1 ns.

[0048] The process for obtaining the STOP count is similar, and the STOP signal is processed in the same way: Using the rising and falling edges of the Sys_Clk125_P0, Sys_Clk125_P45, Sys_Clk125_P90, and Sys_Clk125_P135 clocks, the STOP signal is latched in three stages to obtain a total of 32 signals, from P0_STOP_D0 to P0_STOP_D2.

[0049] At the rising edge of the Sys_Clk125_P0 clock, if P0_STOP_D1 is 0 and P0_STOP_D2 is 1, then P0_STOP_D2, P45_STOP_D2, P90_STOP_D2, P135_STOP_D2, N0_STOP_D2, N45_STOP_D2, N90_STOP_D2, and N135_STOP_D2 are latched to obtain D1, D2, D3, D4, D5, D6, D7, and D8, each with a value of 0 or 1.

[0050] Adding the phase values ​​obtained above, we obtain the precise phase P_STOP between the falling edge of the Stop signal and the rising edge of the nearest clock Sys_Clk125_P0 preceding that falling edge. The calculation formula is as follows: ; The unit is 1 ns.

[0051] The time difference between the falling edge of the Stop signal and the rising edge of the nearest clock Sys_Clk125_P0 clock signal that follows that falling edge. It equals P_STOP.

[0052] The coarse count acquisition process is as follows: At the rising edge of the Sys_Clk125_P0 clock, if P0_Start_D1 is 0 and P0_Start_D2 is 1, then the coarse counter n is cleared.

[0053] At each subsequent rising edge of Sys_Clk125_P0, if no Stop signal transition is detected, n equals n plus 1. At the rising edge of the Sys_Clk125_P0 clock, if P0_STOP_D1 is 0 and P0_STOP_D2 is 1, i.e., a Stop signal transition is detected, the current n is latched to obtain N, and the operation of n equals n plus 1 is not performed at this time.

[0054] The time difference results are processed as follows: The time difference formula is N multiplied by Ts plus... add .

[0055] The formula for calculating the time difference T_Data_1ns is: ; in, The clock cycle is measured in 1 ns.

[0056] Converting to T_Data in units of 0.2ns, the calculation formula is as follows: ; The FPGA internally achieves the effect of multiplying by 5 by shifting T_Data_1ns left by 2 bits and then adding it to T_Data_1ns.

[0057] The obtained T_Data result is filled into bits 27 to 59 of the downlink measurement frame. Bits 10 to 26, representing whole-second counts within the day, are obtained by the MCU via the CAN bus and forwarded to the FPGA, which then directly calls the data to fill the data.

[0058] like Figure 8 The figure shows the timing relationship at a main frequency of 125MHz and a period of 8ns. By using a 4-channel clock design with different phases and simultaneously using both the rising and falling edges of the clock, 8 different phase clock effects are simulated. Theoretically, a time resolution of Ts divided by 8, i.e., 1ns, can be achieved. The time difference measurement needs to consider the variation of two clock edges, with an error of approximately 2ns, which meets the design requirement of 6.5ns.

[0059] For example: the falling edge of START corresponds to D0 to D8 as 1, 1, 0, 0, 0, 0, 0, 0, 0 respectively. Equal to 6ns. The falling edge of STOP corresponds to D0 to D8 as 1, 1, 1, 1, 0, 0, 0, 0, 0 respectively. The time difference is 4ns. N equals 4. Therefore, the required calculation time difference is 42ns.

[0060] Example 4: Simulation and Testing Verification Each measurement requires the input signal to be synchronized to avoid metastability of asynchronous signals.

[0061] like Figure 9 The image shows the simulation results of the FPGA program for the time difference measurement section. With an actual start-stop rising edge interval of 410.1 ns, the time difference module calculates a time difference of 2050 ns (0.2 ns in units), which is 410 ns, consistent with expectations.

[0062] like Figure 10As shown, the actual time interval between the start and stop rising edges is 2260.3ns, and the time difference calculated by the time difference module is 11305, in units of 0.2ns, which is 2261ns, which is in line with expectations.

[0063] like Figure 11 As shown, the time difference measurement function of the KA telemetry and communication device was tested using a commercial telemetry and control ground-based testing unit. The commercial ground-based testing unit uses a 200MHz clock sampling frequency and does not employ multi-phase clock sampling technology; its accuracy is 0 to 5 ns. Test results show that the time difference curve fluctuation is within a reasonable range, with a maximum standard deviation of approximately 5.25 ns. Therefore, the current design can meet the requirement of a satellite-to-ground time difference accuracy of less than or equal to 6.5 ns.

[0064] The above method is also applicable to S-band, X-band, and QV-band telemetry and communication devices, and is also suitable for situations where the measured signal is a falling edge. Higher precision measurement error can be achieved by increasing the sampling clock frequency; for example, a 250MHz sampling clock improves the single-edge resolution to 0.5ns.

[0065] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A satellite-to-ground time difference measurement method for a spaceborne Ka-band telemetry and communication unit, applied to a spaceborne Ka-band telemetry and communication unit, the communication unit including an FPGA, characterized in that... The methods include: An external 10MHz clock signal is acquired, shaped by a Schmitt trigger, and then output to the FPGA as a reference clock. The PPS differential signal is acquired and converted into a single-ended signal by the 422 chip, which is then sent to the FPGA as the Start signal. The Start signal is the PPS signal, which is valid on the falling edge and corresponds to the start of the whole second. The sampling time of the measurement frame is acquired as the Stop signal. The Stop signal is the trailing edge signal of the last bit of the measurement frame synchronization code, which is valid on the falling edge. The FPGA uses a reference clock to generate four clocks of the same origin but different phases, and simultaneously uses the rising and falling edges of the four clocks to sample the Start and Stop signals respectively, to obtain a sampling accuracy of 1 / 8 clock cycle resolution. Based on the sampling results, obtain the coarse count, the start fine count, and the stop fine count; Calculate the time difference based on the coarse count, the start fine count, and the stop fine count; Fill the time difference into the downlink measurement frame.

2. The satellite-to-ground time difference measurement method for a spaceborne Ka-band telemetry and communication device according to claim 1, characterized in that, The FPGA uses a reference clock to generate four co-source clocks with different phases, specifically including: The FPGA internally generates four 125MHz clocks: the first has a phase of 0 degrees, the second has a phase of 45 degrees, the third has a phase of 90 degrees, and the fourth has a phase of 135 degrees. By using the rising and falling edges of four clocks simultaneously, eight different phase clock effects are simulated.

3. The satellite-to-ground time difference measurement method for a spaceborne Ka-band telemetry and communication device according to claim 2, characterized in that, The Start fine count is obtained based on the sampling results, specifically including: The input Start signal is latched in three stages using eight different phase clocks. When the falling edge of the Start signal is detected at the rising edge of the 0-degree phase clock, the signals after each latching stage are latched again to obtain phase state values ​​D0 to D8, each of which is 0 or 1. Add D1 to D8 to obtain the precise phase P_START between the falling edge of the Start signal and the rising edge of the nearest 0-degree phase clock before that falling edge. Calculate the time difference between the falling edge of the Start signal and the rising edge of the nearest 0-degree phase clock after that falling edge. The calculation formula is: ； The unit is 1 ns.

4. The satellite-to-ground time difference measurement method for a spaceborne Ka-band telemetry and communication device according to claim 3, characterized in that, The Stop count is obtained based on the sampling results, specifically including: The input Stop signal is latched in three stages using eight different phase clocks. When the falling edge of the Stop signal is detected at the rising edge of the 0-degree phase clock, the signals after each latching stage are latched again to obtain phase state values ​​D1 to D8, each of which is 0 or 1. Add D1 to D8 to obtain the precise phase P_STOP of the Stop signal falling edge relative to the nearest 0-degree phase rising edge of the clock preceding that falling edge, in units of 1ns; The time difference between the falling edge of the Stop signal and the rising edge of the nearest 0-degree phase clock after that falling edge. It equals P_STOP.

5. The satellite-to-ground time difference measurement method for a spaceborne Ka-band telemetry and communication device according to claim 4, characterized in that, A coarse count is obtained based on the sampling results, specifically including: Count the number of rising edges of the 0-degree phase clock between the falling edge of the Start signal and the falling edge of the Stop signal, and subtract 1 from the count to obtain the coarse count value N.

6. The satellite-to-ground time difference measurement method for a spaceborne Ka-band telemetry and communication device according to claim 5, characterized in that, The time difference is calculated based on the coarse count, the start fine count, and the stop fine count, specifically including: Calculate time difference Its value is N multiplied by add add ,in The clock cycle is measured in 1 ns. Will Converted to units of 0.2 ns The calculation formula is: ； Inside the FPGA Shift left by 2 bits and then AND Adding them together achieves the effect of multiplying by 5.

7. The satellite-to-ground time difference measurement method for a spaceborne Ka-band telemetry and communication device according to claim 1, characterized in that, Filling the time difference into the downlink measurement frame specifically includes: The downlink measurement frame is 500 bits in total; Will The result is filled into bits 27 to 59 of the downlink measurement frame; The whole-second counts within bits 10 to 26 are obtained by the MCU via the CAN bus and forwarded to the FPGA. The FPGA then directly calls and fills the bits 10 to 26.

8. The satellite-to-ground time difference measurement method for a spaceborne Ka-band telemetry and communication device according to claim 1, characterized in that, The method also includes: Each input signal of the measurement is processed by synchronizing it to avoid metastability of asynchronous signals.

9. The satellite-to-ground time difference measurement method for a spaceborne Ka-band telemetry and communication device according to claim 1, characterized in that, The communication unit uses an external 10MHz high-stability crystal oscillator for high-precision time measurement, while using an internal 40MHz ordinary temperature-compensated crystal oscillator for the operation of the radio frequency module. In the absence of an external 10MHz high-stability crystal oscillator, the communication unit relies on a 40MHz clock to complete remote control, telemetry, distance measurement and speed measurement functions.

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