Integrated circuit power-aware remote control instruction scheduling method

Abstract

The application relates to the field of integrated circuit thermal management awareness remote scheduling and energy efficiency control, and discloses an integrated circuit power consumption awareness remote control instruction scheduling method, which comprises the following steps: acquiring real-time junction temperature information of an integrated circuit, determining the bottom layer thermal field evolution trend according to the difference between the junction temperature and the frequency reduction critical temperature, and then determining the instantaneous power consumption quota of the scheduling computing power limited dimension; meanwhile, the thermal power consumption properties of the instruction flow are calibrated, the expected thermal load of the to-be-dispatched instruction sequence is counted in a sliding window, when the thermal increment overflows, the emission timing of high-heat-consumption instructions and low-heat-consumption instructions is arranged, the chip internal thermal field distribution is regulated by inserting low-heat-consumption instructions in the high-heat-consumption instruction interval, the application achieves the certain thermal hedging without loss of throughput, converts the physical cooling time consumption into auxiliary task promotion time, eliminates the control timing jitter caused by temperature control frequency reduction, maintains the timing certainty of the industrial control system and improves the hardware service life.

Description

Technical Field

[0001] This invention relates to a remote control command scheduling method for integrated circuit power consumption sensing, belonging to the field of remote scheduling and energy efficiency control technology for integrated circuit thermal management sensing. Background Technology

[0002] Currently, in distributed industrial remote control systems, edge control nodes issue control commands to computing devices on the production line. The underlying integrated circuits respond in real time according to task priorities. This common scheduling method is based on the assumption that logical guarantees and physical thermal effects are completely separated. The scheduling decision depends only on the temporal weight of the tasks and does not involve the instantaneous energy density fluctuations generated by the instruction sequence at the physical level. However, as the computational complexity of precision servo control increases, floating-point operations or high-frequency input / output commands with nonlinear clustering characteristics are issued in batches in a short period of time, causing a sharp increase in current density inside the chip computing unit and generating instantaneous hot spots. This physical thermal effect has evolved into a core factor restricting system stability, causing computing devices to face the risk of decreased physical reliability due to thermal stress impact under complex operating conditions.

[0003] While the underlying hardware passive protection measures have been strengthened, the static scheduling of control logic still fails to resolve the mismatch between physical constraints and real-time requirements. For example, Chinese invention patent CN108845657B discloses a computing system and processor with fast power surge detection and command throttling to provide a low-cost power unit. It monitors the power extraction status of the power unit through hardware sensing circuits, and when a surge exceeds the limit, it triggers command throttling using a fast signal path. Existing technologies use frequency reduction signals or insert idle cycles into the command stream after the hardware junction temperature exceeds the limit to deal with thermal shocks. However, the hysteresis response mode causes nonlinear time delay jitter in the control closed loop at the thermal limit boundary, which cannot meet the requirements of deterministic control timing in precision industrial scenarios.

[0004] Therefore, how to utilize the real-time thermal margin of integrated circuits to adjust the instruction sequence execution process, and ensure that the control flow timing no longer generates nonlinear jitter while maintaining the continuous advancement of the logic pipeline, has become the technical problem to be solved by this invention. Summary of the Invention

[0005] To address the problems in the background art, the technical solution of the present invention is as follows: A remote control command scheduling method with integrated circuit power consumption awareness, comprising the following steps: Step S1: The junction temperature data of the integrated circuit is obtained in real time using the on-chip temperature sensing unit. Based on the deviation between the junction temperature data and the preset frequency reduction critical temperature, the evolution trend of the underlying physical thermal field of the chip and the real-time mapping relationship between the scheduler's configurable computing power space are established using the preset proportional-differential conversion rule, so as to calculate the instantaneous power consumption quota characterizing the computing power scheduling constraint dimension. Step S2: Identify the thermal power consumption attributes of each instruction in the instruction sequence to be processed based on the preset instruction power consumption feature library, mark state polling instructions with power consumption weight coefficients lower than the preset threshold as low thermal power consumption instructions, and mark floating-point arithmetic instructions with power consumption weight coefficients higher than the preset threshold as high thermal power consumption instructions. Step S3: Maintain a sliding observation window for the instruction sequence to be processed. By accumulating the power consumption weight coefficients of all instructions to be dispatched within the sliding observation window, obtain the expected total heat load of the instruction stream within the sliding observation window, and calculate the heat increment overflow value of the expected total heat load relative to the instantaneous power consumption quota. Step S4: When the thermal increment overflow value exceeds the preset safety threshold, while keeping the instruction pipeline continuously advancing, the timing of the high thermal dissipation instruction and the low thermal dissipation instruction are arranged. By precisely interspersing the low thermal dissipation instruction in the interval between the high thermal dissipation instructions, the internal thermal field distribution of the integrated circuit is controlled by the low toggle operation corresponding to the low thermal dissipation instruction.

[0006] Preferably, the instruction power consumption feature library is constructed in the following way: during the offline calibration stage, single-quantity assignment tests are performed on each original instruction in the instruction set; the instantaneous current increment and the temperature rise slope of the hot spot area of ​​each original instruction before and after assignment are measured; the product of the instantaneous current increment and the temperature rise slope is defined as the power consumption weight coefficient of the corresponding instruction; and a mapping between the instruction identifier and the power consumption weight coefficient is established.

[0007] Preferably, step S3 includes: setting the step size of the sliding observation window according to the deterministic delay requirements of the industrial control task; retrieving the power weight coefficient corresponding to the newly added instruction entering the window from the instruction power consumption feature library during the shifting process of the sliding observation window with the sequence of instructions to be processed; accumulating the sum of the power weight coefficients of each instruction in the sliding observation window, and comparing the sum with the instantaneous power consumption quota.

[0008] Preferably, low-heat-dissipation instructions include status register polling instructions, watchdog feed instructions, and low-frequency input / output interaction instructions; high-heat-dissipation instructions include matrix operation instructions, complex floating-point transformation instructions, and high-frequency bus toggle instructions; by identifying the opcode field and operand type of the instruction code, the corresponding power consumption weight coefficient is matched from the instruction power consumption feature library to complete the instruction attribute calibration.

[0009] Preferably, step S4 includes: when the thermal increment overflow value exceeds a preset safety threshold, suspending the currently assigned high thermal power instruction, and retrieving the low thermal power instruction with low power consumption attribute from the instruction sequence to be processed for pre-assignment; by dynamically adjusting the assignment ratio of the high thermal power instruction and the low thermal power instruction, the average power consumption intensity of the pipeline is converged to the threshold range defined by the instantaneous power consumption quota.

[0010] Preferably, the method further includes a timing deviation compensation step: calculating the delay time of the high thermal power instruction caused by the pre-dispatch of the low thermal power instruction; after the integrated circuit enters the physical cooling cycle, the processor frequency is increased using a clock stepping compensation rule to compensate for the delay time, so that the average instruction dispatch time deviation within a control cycle is within the accuracy range of 10μs, ensuring the deterministic timing of industrial control tasks.

[0011] Preferably, the update frequency of the instantaneous power consumption quota is consistent with the acquisition cycle of the real-time junction temperature data, and the shift cycle of the sliding observation window is synchronized with the instruction pipeline clock cycle of the integrated circuit to achieve nanosecond-level real-time sensing of thermal shock; when the instantaneous power consumption quota is dynamically reduced, the instruction assignment priority in the sliding observation window is adjusted in real time.

[0012] Preferably, the method further includes a heat dissipation environment correction step: real-time acquisition of external heat dissipation parameters of the edge device on which the integrated circuit is deployed; dynamic correction of the power consumption weight coefficient of each instruction in the instruction power consumption feature library based on the external heat dissipation parameters, so as to offset the nonlinear superposition effect of the temperature rise of the external heat dissipation environment on the internal thermal field distribution of the integrated circuit, and improve the accuracy of power consumption perception under different industrial site environments.

[0013] Preferably, the timing of the high thermal power consumption instruction and the low thermal power consumption instruction is arranged as follows: when the instantaneous power consumption quota is dynamically reduced, the interleaving density of the low thermal power consumption instruction between the high thermal power consumption instruction is increased, and the physical cooling time is converted into the task advancement time represented by the low thermal power consumption instruction, so that the integrated circuit can maintain the instruction throughput of the logic pipeline without exceeding the 85°C thermal safety boundary.

[0014] Compared with the prior art, the beneficial effects of the present invention are: 1. In remote control command scheduling with circuit power consumption awareness, this invention establishes a direct feedback mechanism between physical state and logic execution at the scheduling level by pre-calibrating the power consumption characteristics of the command and real-time mapping the physical thermal margin of the chip. This mechanism enables the scheduler to obtain quantitative sensing capability before thermal shock occurs by predicting the power consumption accumulation of the command sequence to be issued, thereby transforming the traditional hysteresis protection into regulation, eliminating control delay jitter caused by random frequency reduction triggered by hardware junction temperature exceeding the limit, and ensuring the timing determinism of industrial control processes.

[0015] 2. By using the logic heat-absorbing instructions and high-energy-consuming instructions identified by the instruction-level power consumption feature library for phase interleaving scheduling, an equivalent cooling cycle is provided for the integrated circuit at the physical level. This spatiotemporal weaving method of heterogeneous instructions replaces the stagnation strategy in the existing technology of exchanging heat dissipation space by inserting no-operation instructions or forcibly suspending the pipeline. It transforms the physical time required for the cooling process into effective advancement time for low-power background tasks, achieving thermal offsetting while maintaining the continuous and uninterrupted operation of the logic pipeline, and ensuring that the logic throughput of the control closed loop is lossless under thermal limit boundary conditions.

[0016] 3. The instantaneous power consumption quota based on dynamic allocation of thermal margin and the clock step compensation mechanism work together to transform the physical thermal constraints of the underlying hardware into controllable logical variables within the scheduler. This cross-layer coupling architecture of physical and logical components enables the system to smooth the current density fluctuations within the chip by finely adjusting the ratio of hot and cold instructions without exceeding the chip's thermal safety boundary. This suppresses the impact of instantaneous hot spots on the physical stress of the silicon structure. At the same time, clock compensation ensures that the average instruction execution time deviation within a complete control cycle meets the preset accuracy requirements, thereby improving the operational stability and hardware service life of computing equipment in complex distributed industrial environments. Attached Figure Description

[0017] Figure 1 This is a flowchart of the integrated circuit thermal field sensing and instruction interleaving scheduling process of the present invention; Figure 2 This is a state evolution diagram of the dynamic adjustment of computing power quota under the physical thermal constraint of the present invention.

[0018] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0020] A method for scheduling remote control commands with integrated circuit power consumption awareness includes the following steps: Step S1: The junction temperature data of the integrated circuit is obtained in real time using the on-chip temperature sensing unit. Based on the deviation between the junction temperature data and the preset frequency reduction critical temperature, the evolution trend of the underlying physical thermal field of the chip and the real-time mapping relationship between the scheduler's configurable computing power space are established using the preset proportional-differential conversion rule, so as to calculate the instantaneous power consumption quota characterizing the computing power scheduling constraint dimension. Step S2: Identify the thermal power consumption attributes of each instruction in the instruction sequence to be processed based on the preset instruction power consumption feature library, mark state polling instructions with power consumption weight coefficients lower than the preset threshold as low thermal power consumption instructions, and mark floating-point arithmetic instructions with power consumption weight coefficients higher than the preset threshold as high thermal power consumption instructions. Step S3: Maintain a sliding observation window for the instruction sequence to be processed. By accumulating the power consumption weight coefficients of all instructions to be dispatched within the sliding observation window, obtain the expected total heat load of the instruction stream within the sliding observation window, and calculate the heat increment overflow value of the expected total heat load relative to the instantaneous power consumption quota. Step S4: When the thermal increment overflow value exceeds the preset safety threshold, while keeping the instruction pipeline continuously advancing, the timing of the high thermal dissipation instruction and the low thermal dissipation instruction are arranged. By precisely interspersing the low thermal dissipation instruction in the interval between the high thermal dissipation instructions, the internal thermal field distribution of the integrated circuit is controlled by the low toggle operation corresponding to the low thermal dissipation instruction.

[0021] Preferably, the instruction power consumption feature library is constructed in the following way: during the offline calibration stage, single-quantity assignment tests are performed on each original instruction in the instruction set; the instantaneous current increment and the temperature rise slope of the hot spot area of ​​each original instruction before and after assignment are measured; the product of the instantaneous current increment and the temperature rise slope is defined as the power consumption weight coefficient of the corresponding instruction; and a mapping between the instruction identifier and the power consumption weight coefficient is established.

[0022] Preferably, step S3 includes: setting the step size of the sliding observation window according to the deterministic delay requirements of the industrial control task; retrieving the power weight coefficient corresponding to the newly added instruction entering the window from the instruction power consumption feature library during the shifting process of the sliding observation window with the sequence of instructions to be processed; accumulating the sum of the power weight coefficients of each instruction in the sliding observation window, and comparing the sum with the instantaneous power consumption quota.

[0023] Preferably, low-heat-dissipation instructions include status register polling instructions, watchdog feed instructions, and low-frequency input / output interaction instructions; high-heat-dissipation instructions include matrix operation instructions, complex floating-point transformation instructions, and high-frequency bus toggle instructions; by identifying the opcode field and operand type of the instruction code, the corresponding power consumption weight coefficient is matched from the instruction power consumption feature library to complete the instruction attribute calibration.

[0024] Preferably, step S4 includes: when the thermal increment overflow value exceeds a preset safety threshold, suspending the currently assigned high thermal power instruction, and retrieving the low thermal power instruction with low power consumption attribute from the instruction sequence to be processed for pre-assignment; by dynamically adjusting the assignment ratio of the high thermal power instruction and the low thermal power instruction, the average power consumption intensity of the pipeline is converged to the threshold range defined by the instantaneous power consumption quota.

[0025] Preferably, the method further includes a timing deviation compensation step: calculating the delay time of the high thermal power instruction caused by the pre-dispatch of the low thermal power instruction; after the integrated circuit enters the physical cooling cycle, the processor frequency is increased using a clock stepping compensation rule to compensate for the delay time, so that the average instruction dispatch time deviation within a control cycle is within the accuracy range of 10μs, ensuring the deterministic timing of industrial control tasks.

[0026] Preferably, the update frequency of the instantaneous power consumption quota is consistent with the acquisition cycle of the real-time junction temperature data, and the shift cycle of the sliding observation window is synchronized with the instruction pipeline clock cycle of the integrated circuit to achieve nanosecond-level real-time sensing of thermal shock; when the instantaneous power consumption quota is dynamically reduced, the instruction assignment priority in the sliding observation window is adjusted in real time.

[0027] Preferably, the method further includes a heat dissipation environment correction step: real-time acquisition of external heat dissipation parameters of the edge device on which the integrated circuit is deployed; dynamic correction of the power consumption weight coefficient of each instruction in the instruction power consumption feature library based on the external heat dissipation parameters, so as to offset the nonlinear superposition effect of the temperature rise of the external heat dissipation environment on the internal thermal field distribution of the integrated circuit, and improve the accuracy of power consumption perception under different industrial site environments.

[0028] Preferably, the timing of the high thermal power consumption instruction and the low thermal power consumption instruction is arranged as follows: when the instantaneous power consumption quota is dynamically reduced, the interleaving density of the low thermal power consumption instruction between the high thermal power consumption instruction is increased, and the physical cooling time is converted into the task advancement time represented by the low thermal power consumption instruction, so that the integrated circuit can maintain the instruction throughput of the logic pipeline without exceeding the 85°C thermal safety boundary.

[0029] Example 1: In a remote edge control scenario deployed on a multi-axis linkage servo assembly line, the computing power equipment needs to continuously process high-heat-consuming instruction streams involving complex floating-point transformations and large-scale matrix operations. Because servo motors have extremely high requirements for the timing determinism of control signals, the instruction dispatch time deviation within the control closed loop must be maintained within a 10μs accuracy range. Any random protective frequency reduction caused by a sharp increase in the chip's internal current density will generate uncontrollable logic delays, leading to loss of synchronization between axes and deterioration of physical assembly accuracy. In this system application, the scheduler pre-assigns power weight coefficients to each original instruction in the instruction sequence to be processed based on the instruction power consumption feature library. Opcode fields such as status register polling and watchdog timer feeding correspond to low-power weights, while complex floating-point transformation opcodes correspond to high-power weights. During system operation, the on-chip temperature sensing unit collects real-time junction temperature data of the integrated circuit. The scheduler calculates the instantaneous power consumption quota, representing the current computing power scheduling constraint dimension, based on the deviation between this real-time junction temperature data and the preset frequency reduction critical temperature. Determined according to the following formula: ,in, For instantaneous power consumption quota, This is a preset proportional coefficient. The preset critical temperature for frequency reduction. For real-time junction temperature data, The preset differential coefficients, The junction temperature change rate is determined by the thermodynamic law of conservation of energy. The physical temperature rise of an integrated circuit is positively correlated with the integral of the input thermal power. The instantaneous power consumption quota is then calculated using the offline calibrated thermal impedance coefficient. The equivalent heating power benchmark is converted to dimensionally aligned with the expected total heat load. Since the expected total heat load is a composite dimensional exponent derived from the product of the operating current and the temperature rise slope, the system extracts the standard rated value of the chip's supply voltage during the dimensional alignment conversion. This value is then multiplied by the current increment component separated from the aforementioned product to restore the true power base. This thermal impedance coefficient is substituted into the steady-state approximate solution of the thermal conduction Fourier differential equation to physically calibrate the aforementioned temperature rise slope component, and the boundary heat flux required to generate this temperature rise trend is calculated. Density; Finally, the system uses an internal dimensional normalization algorithm to arithmetically merge the electrical power base and boundary heat flux density into a single equivalent watt reference. This dimensionality reduction rule based on the joint mapping of Ohm's law and the conduction thermodynamic equation ensures that multidimensional composite instruction-level parameters can be accurately and rigorously projected onto a single physical power domain. A preset threshold upper limit is set for low heat dissipation instructions. The upper limit value is limited to less than the minimum background passive heat dissipation power of the edge device where the integrated circuit is located at an ambient temperature of 85°C, thus establishing the objective premise for physical cooling generated by low flip-flop operation.

[0030] The scheduler maintains a sliding observation window for the sequence of instructions to be dispatched, with a step size set to a microsecond-level span matching the servo control cycle. The expected total heat load is obtained by accumulating the power consumption weight coefficients of the instructions within the sliding observation window. When the expected total heat load within the sliding observation window generates a heat increment overflow value relative to the instantaneous power consumption quota and exceeds a preset safety threshold, the scheduler automatically triggers a heterogeneous phase interleaving mechanism. This breaks down task priority barriers and extracts low-heat-consumption instructions from the background queue. The scheduler modifies the instruction launch pointer, interleaving the extracted low-heat-consumption instructions into the launch gaps of high-heat-consumption control instructions. It utilizes the low-flip-rate operation during the processing of low-heat-consumption instructions to regulate the local thermal field distribution within the integrated circuit, thus controlling the pre-dispatch and randomization of instructions. During heterogeneous interleaving, the scheduler hardware reads the source and destination register addresses of the low-thermal-power instruction to be extracted and compares them with the register allocation table of high-thermal-power instructions that have been issued but not yet written back in the current pipeline. If an address overlap is detected (e.g., read-after-write, read-after-write, or write-after-write), a data dependency conflict is determined, and the scheduler will immediately skip the low-thermal-power instruction and traverse the queue to find an unrelated independent instruction. At the same time, the scheduler temporarily saves the execution results of the preceding instructions by renaming the register mapping in hardware. The actual architecture state is committed only after the timing conditions of the original control logic are met. This ensures that the heterogeneous interleaving operation does not cause any damage to the data consistency and logical timing of the core control flow while avoiding data hazards and structural conflicts.

[0031] By dynamically adjusting the dispatch ratio of high-thermal-power instructions to low-thermal-power instructions, the average power consumption intensity of the processor pipeline converges to the threshold range defined by the instantaneous power consumption quota. The chip junction temperature is always maintained below the 85°C thermal safety boundary. Since the time required for physical cooling is converted into the advancement time of low-power auxiliary tasks, the logic pipeline maintains continuous and uninterrupted operation throughout the thermal offset process, eliminating the logic gaps caused by traditional frequency reduction mechanisms. The system uses clock stepping compensation rules to correct the slight delay caused by instruction redirection, ensuring that the average instruction dispatch time deviation within the complete control cycle meets the preset accuracy of 10μs, and achieving lossless throughput and time-determined industrial control output.

[0032] Example 2: In an edge computing controller hardware platform deployed with a 14nm integrated circuit processor, the test environment uses an internally integrated thermal diode to monitor the physical temperature of the on-chip hotspot area in real time. The thermal diode has a measurement accuracy of 0.5℃ and a sampling frequency of 1kHz. To simulate real industrial electromagnetic interference, Gaussian white noise with a signal-to-noise ratio of 25dB is superimposed on the temperature sensing signal using an algorithm to verify the stability of the instruction scheduling scheme under non-ideal sensing conditions. The experiment uses a scaling factor... With differential coefficients Establish instantaneous power consumption quota ,in The setting needs to balance the sensitivity of the thermal response with the stability of the system control loop. When the spatiotemporal evolution characteristics of the monitored thermal field are in a high-frequency fluctuation state, in order to ensure that the instantaneous power consumption quota can cover the peak value of the thermal surge in a timely manner, The value tends towards the upper limit of its range of 2.5 to 3.5. This test targets a processor with a clock speed of 2.0 GHz and a typical thermal resistance of 0.15℃ / W for the heat dissipation module. The applied logic rules will... The anchoring value is 3.2, while the differential coefficient is... Based on the junction temperature change rate The second derivative sign is dynamically compensated and set to 0.8 to suppress power consumption quota overshoot caused by a sharp rise in junction temperature. The experimental group uses the power consumption-aware remote control instruction scheduling method of this invention, while the control group uses a priority preemptive scheduling method combined with a dynamic voltage and frequency adjustment mechanism (DVFS) at the hardware layer. Under this comparative architecture, the original input instruction sequence consists of 500 high-thermal-power instructions containing 64-bit floating-point matrix multiplications and 300 low-thermal-power instructions polled by the status register. The single-quantity power consumption weight coefficient of the high-thermal-power instructions is statically calibrated to 12.4, and the single-quantity power consumption weight coefficient of the low-thermal-power instructions is calibrated to 1.2. At the start of the experiment, initial junction temperature data is collected. The preset critical temperature for frequency reduction is 76.2℃. The initial instantaneous power consumption quota is calculated based on the formula at 80.0℃. The value is 295.6 units. At this time, the total expected heat load accumulation within the sliding observation window is 342.5 units, and the heat increment overflow value is 46.9 units. In order to bridge the physical time scale gap from millisecond-level temperature sampling to nanosecond-level instruction stream perception, the system introduces a feedforward prediction mechanism based on the processor clock cycle within the millisecond-level physical temperature measurement interval. The scheduler uses the processor pipeline clock frequency as the nanosecond-level driving source, takes the actual junction temperature measured in the previous millisecond cycle as the reference initial value, and reads the power consumption weight coefficient of the newly issued instruction in each subsequent nanosecond-level clock cycle and performs arithmetic accumulation. Using the accumulated value of the instruction-level heat load and the chip's physical thermal constant, a linear extrapolation is performed to calculate the predicted junction temperature at the current nanosecond moment. Through this alternating advancement of overall physical sampling and surface logic prediction, the system can complete the nanosecond-level prediction of instantaneous hot spot accumulation before the next millisecond-level thermal diode actual sampling signal arrives.

[0033] During the core derivation phase, the test group scheduler detected that the thermal overflow value exceeded the preset safety threshold of 15.0 units, and then triggered the heterogeneous phase interleaving logic. After continuously dispatching three high thermally demanding instructions, it interspersed two low thermally demanding instructions, suppressing current density in real time by reducing the pipeline toggle rate. Monitoring data showed that after 100ms of interleaving scheduling, the real-time junction temperature of the test group processor stabilized at 78.4℃, without reaching the frequency reduction threshold, and the logic pipeline maintained a frequency of 2.0GHz. In contrast, the control group, unable to predict the thermal effect of instructions, saw its junction temperature climb to 80.2℃ within 45ms, triggering hardware frequency reduction protection, leading to processor overheating. The operating frequency was forcibly reduced to 1.2GHz. Verification data showed that the average instruction dispatch time deviation of the experimental group within a complete control cycle was 8.4μs, meeting the industrial control accuracy requirement of 10μs. In contrast, the control group experienced an increased dispatch deviation of 142.5μs due to logic execution delay caused by frequency reduction, resulting in timing jitter. Gradient verification of instruction load intensity revealed a clear logical correlation between the junction temperature control margin and instruction dispatch accuracy as the proportion of high-thermal-power instructions in the instruction sequence increased from 20% to 80%. When the proportion of high-thermal-power instructions was between 40% and 70% in the operating window, the chip junction temperature remained at [value missing]. Within a temperature range of 1.5℃ to 2.0℃, and with control accuracy consistently maintained below 10μs, when the load intensity continues to increase and exceeds the 75% performance inflection point, the thermal offset mechanism enters the saturation region due to a lack of sufficient low-flip-rate instructions in the instruction sequence to be assigned to fill the launch gap. The junction temperature begins to slowly cross 80.0℃, proving that the instruction interleaving ratio and quota calculation range are determined based on the thermodynamic equilibrium law. For extreme continuous heavy-load conditions where low-heat-consuming instructions are exhausted in the instruction sequence to be processed, a degradation and disaster recovery procedure is set up, periodically checking the low-heat-consuming instructions in the background task queue. When the remaining quantity is less than 10% of the sliding observation window capacity, and the heat increment overflow value continues to exceed the preset safety threshold for more than ten instruction dispatch cycles, the heterogeneous phase interleaving mechanism is terminated, and no-operation instructions are directly injected into the pipeline to force the extension of the physical cooling window, maintaining the system's thermal safety baseline. Finally, this experiment confirms through quantitative data that this invention, by converting the junction temperature fluctuation of the physical layer into instruction phase constraints of the scheduling layer, eliminates the negative impact of temperature control frequency reduction on the real-time performance of remote control without changing the hardware heat dissipation configuration, and achieves deep synergy between logic throughput and physical thermal safety.

[0034] Example 3: In an integrated circuit processing environment deployed in an industrial robot joint controller, the scheduler establishes power consumption weighting coefficients for each raw instruction in the instruction set. The calibration procedure involves the following steps during the offline calibration phase: the test platform loads the raw instruction under test into the processor's arithmetic unit and maintains a constant transmit frequency of 1.0MHz. On-chip current probes collect the instantaneous current increments of the pipeline during the processing of the raw instruction. Simultaneously, the temperature rise slope of the calculation core area is obtained using temperature sensors. The slope of the temperature rise The scheduler uses the absolute value of the derivative of the junction temperature change per unit time to calculate the instantaneous current increment. With temperature rise slope The product is determined as the power consumption weighting coefficient for the corresponding instruction. In this calibration procedure, the instantaneous current increment represents the severity of the charge flip caused by the command, while the temperature rise slope characterizes the thermal congestion rate of the local heat dissipation channel. Their product is physically defined as a dimensionless empirical penalty exponent, rather than a direct heating power. To complete the physical logic loop, the system integrates a preset physical calibration reference constant at the back end of the computational pipeline. This scaling factor is derived by measuring the actual Joule heat under standard load conditions using a micro calorimeter. After calculating the product of the current and temperature rise slope, the scheduler multiplies it by this physical calibration reference constant, thus forcibly canceling the unit deviation of the empirical penalty exponent. This ultimately maps to an equivalent Joule heat release rate that obeys the first law of thermodynamics, ensuring that subsequent energy calculations within the sliding window do not violate fundamental electrical and thermal principles. To address the interference of increased leakage current on the power consumption sensing logic during long-term operation of the integrated circuit, the system introduces a service life compensation mechanism in the computational logic. The scheduler calculates the service life compensation based on real-time junction temperature data. With preset frequency reduction critical temperature Determine instantaneous power consumption quota The calculation formula is as follows: ,in, For instantaneous power consumption quota, This is the proportionality coefficient. The preset critical temperature for frequency reduction. For real-time junction temperature data, These are the differential coefficients. The junction temperature change rate, This is the leakage current attenuation factor. This represents the cumulative number of hours the integrated circuit has been in operation. The estimated lifetime hours for the hardware design are compensated by this logic, along with the instantaneous power consumption quota. It adapts and adjusts as the hardware service life increases, offsetting the impact of the increased leakage current ratio.

[0035] During the process of dispatching instruction sequences, the sliding observation window shifts in microsecond increments along with the instruction issuance pointer. The scheduler accumulates the power consumption weighting coefficients of all instructions to be dispatched within the sliding observation window. Obtain the expected total heat load, when this expected total heat load is equal to the instantaneous power consumption quota. When the residual value between them exceeds the preset safety deviation threshold, the heterogeneous phase interleaving mechanism is triggered and the command transmission sequence is rearranged. The scheduler retrieves the attributes of high heat dissipation commands and low heat dissipation commands in the command sequence to be processed, and calculates the interleaving ratio factor to maintain thermal field stability. Based on the principle of steady-state thermal balance, the total heat generation within a specific observation period matches the heat dissipation of the physical environment, according to the formula... Determine the interleaving ratio factor ,in, The weighting factor representing the average power consumption of high thermally demanding floating-point instructions. The average power consumption weighting coefficient for low-flip-rate state polling instructions. Interleaving ratio factor represents the equivalent heat dissipation weight parameter of the current physical heat dissipation channel within a single command transmission cycle. The benchmark for the number of low-heat-consumption commands that need to be interleaved after a single high-heat-consumption command is continuously assigned, and based on this interleaving ratio factor. By interspersing low-flip-rate state polling instructions within the issue cycle of high-heat-dissipation floating-point instructions, the duty cycle of the pipeline switching activity rate is adjusted to suppress localized hotspot accumulation. Through these constraints, when processing high-intensity trajectory interpolation tasks involving six axes, the standard deviation of the processor's core junction temperature fluctuation is reduced by 15.6% compared to the state without compensation mechanisms, and this reduction is achieved within a certain number of system operating hours. Under 50,000 hours of operation, the real-time junction temperature is still controlled at 82.5℃ and does not trigger hardware frequency reduction. The time deviation of instruction dispatch is locked between 8.2μs and 9.5μs. The time consumed by physical cooling is converted into the advancement time of low-power auxiliary tasks, realizing the control of the underlying computing resources by the industrial control software and eliminating the impact of changes in the physical state of hardware on the real-time performance of remote control.

[0036] Example 4: In a scenario where processor instruction power consumption is statically calibrated, the system initiates the construction of an instruction power consumption feature library based on the complete set of opcodes for the instruction sequence to be processed. The processor is connected to a constant temperature plate maintained at 25.0°C via a heat-conducting medium. The on-chip current sampling circuit collects the instantaneous current of the core power rail at a frequency of 100MHz. The scheduler distributes each raw command one by one through the transmission interface and cyclically distributes them 1000 times to eliminate measurement errors. The calculation unit calculates based on the instantaneous current. The integration result within the execution cycle determines the average power consumption of a single allocation corresponding to the opcode. The scheduler then calculates the ratio of the average power consumption of a single allocation to the processor's thermal design power limit to obtain the power consumption weighting coefficient. When the system faces changes in the heat dissipation environment, the scheduler initiates a field parameter calibration procedure to correct physical deviations in junction temperature sensing. The on-chip temperature sensor continuously collects the average value of 100 sampling points under zero-load conditions as a thermal balance reference value. The scheduler dispatches a calibration sequence containing 500 high-heat-dissipation floating-point instructions to the computing pipeline and monitors real-time junction temperature data. Rise to the preset critical temperature for frequency reduction The system calculates the ratio between the temperature rise duration and the preset reference duration to obtain the environmental correction factor. Corrected instantaneous power consumption quota The calculation formula is as follows: ,in, This is the corrected instantaneous power consumption quota. As an environmental correction factor, This is the proportionality coefficient. The preset critical temperature for frequency reduction. For real-time junction temperature data, These are the differential coefficients. The scheduler utilizes an environmental correction factor to determine the junction temperature change rate. Adjust the gain of the feedback control loop to compensate for the differences in thermal conductivity at different physical deployment locations, and lock the time deviation of command dispatch within a preset range of 10μs.

[0037] Example 5: In applications involving the synchronous control of precision industrial robotic arm clusters, the system executes instruction interleaving scaling factors for processor nodes at different physical topology locations. The pre-adaptive calibration procedure involves the scheduler assigning a high-heat-dissipation instruction stream with increasing duty cycles to the target integrated circuit during the deployment phase. On-chip thermal sensors are used to acquire junction temperature data at the temperature rise saturation point under different instruction toggle rates. The scheduler calculates the interleaving ratio factor based on the balance point between the real-time measured temperature rise slope and heat dissipation efficiency. Its value is determined by matching the instantaneous heat generated by the high-flip-rate command with the energy removed by the current heat dissipation channel per unit cycle, thereby establishing the command interleaving density to maintain thermal balance in this specific physical deployment environment.

[0038] When the system detects the accumulated logic offset caused by instruction phase redirection during operation, it initiates a timing correction process based on clock step compensation rules. The on-chip high-precision timer quantifies in real time the nanosecond-level deviation between the actual completion time and the dispatch timestamp of each set of heterogeneous instructions after interleaving execution. The scheduler will set the deviation value The instruction issue delay compensation amount is converted into the instruction issue delay compensation amount for the next servo control cycle. As a feedback input, it fine-tunes the issue timing of the instruction pipeline. The processor compensates for the local delay caused by thermal management actions without reducing the average instruction throughput by performing an equivalent clock phase pre-offset in the subsequent control cycle. This makes the dispatch time deviation of remote control instructions stably converge within the range of 7.4μs to 8.6μs.

[0039] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for scheduling remote control commands based on integrated circuit power consumption awareness, characterized in that, Includes the following steps: Step S1: The junction temperature data of the integrated circuit is obtained in real time using the on-chip temperature sensing unit. Based on the deviation between the junction temperature data and the preset frequency reduction critical temperature, the evolution trend of the underlying physical thermal field of the chip and the real-time mapping relationship between the scheduler's configurable computing power space are established using the preset proportional-differential conversion rule, so as to calculate the instantaneous power consumption quota characterizing the computing power scheduling constraint dimension. Step S2: Identify the thermal power consumption attributes of each instruction in the instruction sequence to be processed based on the preset instruction power consumption feature library, mark state polling instructions with power consumption weight coefficients lower than the preset threshold as low thermal power consumption instructions, and mark floating-point arithmetic instructions with power consumption weight coefficients higher than the preset threshold as high thermal power consumption instructions. Step S3: Maintain a sliding observation window for the instruction sequence to be processed. By accumulating the power consumption weight coefficients of all instructions to be dispatched within the sliding observation window, obtain the expected total heat load of the instruction stream within the sliding observation window, and calculate the heat increment overflow value of the expected total heat load relative to the instantaneous power consumption quota. Step S4: When the thermal increment overflow value exceeds the preset safety threshold, while keeping the instruction pipeline continuously advancing, the timing of the high thermal dissipation instruction and the low thermal dissipation instruction are arranged. By precisely interspersing the low thermal dissipation instruction in the interval between the high thermal dissipation instructions, the internal thermal field distribution of the integrated circuit is controlled by the low toggle operation corresponding to the low thermal dissipation instruction.

2. The integrated circuit power consumption-aware remote control command scheduling method according to claim 1, characterized in that, The instruction power consumption feature library is constructed in the following way: During the offline calibration stage, single-quantity assignment tests are performed on each original instruction in the instruction set; the instantaneous current increment and the temperature rise slope of the hot spot area are measured before and after the assignment of each original instruction; the product of the instantaneous current increment and the temperature rise slope is defined as the power consumption weight coefficient of the corresponding instruction; and a mapping between the instruction identifier and the power consumption weight coefficient is established.

3. The integrated circuit power consumption-aware remote control command scheduling method according to claim 1, characterized in that, Step S3 includes: setting the step size of the sliding observation window according to the deterministic delay requirements of the industrial control task; retrieving the power weight coefficient corresponding to the newly added instruction entering the window from the instruction power consumption feature library during the shifting process of the sliding observation window with the sequence of instructions to be processed; accumulating the sum of the power weight coefficients of each instruction in the sliding observation window, and comparing the sum with the instantaneous power consumption quota.

4. The integrated circuit power consumption-aware remote control command scheduling method according to claim 1, characterized in that, Low-heat-consuming instructions include status register polling instructions, watchdog feed instructions, and low-frequency input / output interaction instructions; high-heat-consuming instructions include matrix operation instructions, complex floating-point transformation instructions, and high-frequency bus toggle instructions; by identifying the opcode field and operand type of the instruction code, the corresponding power consumption weight coefficient is matched from the instruction power consumption feature library to complete the instruction attribute calibration.

5. The integrated circuit power consumption-aware remote control command scheduling method according to claim 1, characterized in that, Step S4 includes: when the thermal increment overflow value exceeds a preset safety threshold, suspending the currently pending high thermal power instruction and retrieving the low thermal power instruction with low power consumption attribute from the instruction sequence to be processed for pre-assignment; by dynamically adjusting the assignment ratio of the high thermal power instruction and the low thermal power instruction, the average power consumption intensity of the pipeline converges to the threshold range defined by the instantaneous power consumption quota.

6. The integrated circuit power consumption-aware remote control command scheduling method according to claim 5, characterized in that, It also includes a timing deviation compensation step: calculating the delay time of the high thermal power instruction caused by the pre-dispatch of the low thermal power instruction; after the integrated circuit enters the physical cooling cycle, the processor frequency is increased using the clock stepping compensation rule to compensate for the delay time, so that the average instruction dispatch time deviation within a control cycle is within the accuracy range of 10μs, ensuring the deterministic timing of industrial control tasks.

7. The integrated circuit power consumption-aware remote control command scheduling method according to claim 1, characterized in that, The update frequency of the instantaneous power consumption quota is consistent with the acquisition cycle of the real-time junction temperature data, and the shift cycle of the sliding observation window is synchronized with the instruction pipeline clock cycle of the integrated circuit to achieve nanosecond-level real-time sensing of thermal shock; when the instantaneous power consumption quota shrinks dynamically, the instruction assignment priority within the sliding observation window is adjusted in real time.

8. The integrated circuit power consumption-aware remote control command scheduling method according to claim 1, characterized in that, It also includes a heat dissipation environment correction step: real-time acquisition of external heat dissipation parameters of edge devices deploying integrated circuits; dynamic correction of the power consumption weight coefficient of each instruction in the instruction power consumption feature library based on the external heat dissipation parameters, so as to offset the nonlinear superposition effect of the temperature rise of the external heat dissipation environment on the internal thermal field distribution of the integrated circuit, and improve the accuracy of power consumption perception under different industrial site environments.

9. The integrated circuit power consumption-aware remote control command scheduling method according to claim 1, characterized in that, The timing arrangement of the high thermal power consumption instruction and the low thermal power consumption instruction includes: increasing the interleaving density of the low thermal power consumption instruction between the high thermal power consumption instruction when the instantaneous power consumption quota is dynamically reduced, converting the physical cooling time into the task advancement time represented by the low thermal power consumption instruction, so that the integrated circuit can maintain the instruction throughput of the logic pipeline without exceeding the 85°C thermal safety boundary.

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