Adaptive bias low-dropout regulator with fast transient response
Patent Information
- Application Number
- CN202610539565.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-22
- Publication Date
- 2026-08-07
AI Technical Summary
为此，本发明提出了一种快速瞬态响应的自适应偏置低压差稳压器，能够在实现自适应偏置降低功耗的同时，改善瞬态响应慢和相位裕度恶化的问题
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Figure CN122526360A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of low dropout voltage regulator technology, and in particular to an adaptive bias low dropout voltage regulator with fast transient response. Background Technology
[0002] As we become increasingly reliant on smart wearables, Bluetooth headsets, and other electronic products, the demand for longer battery life is growing to meet the ever-increasing need for uninterrupted use. This has driven the continuous development of low-power chips and circuits, including low-dropout regulators (LDOs). As a crucial module in the power management unit (PMU), the LDO delivers a stable, low-noise, low-ripple voltage, powering other circuits. The lower quiescent power consumption of LDOs significantly contributes to longer battery life in consumer electronics, prompting researchers to continuously explore ways to achieve both low power consumption and low cost.
[0003] High-load LDOs require greater power consumption to operate, and even with fixed bias, high power consumption occurs under no-load or light-load conditions. Currently, adaptive biasing is commonly used to address this issue. However, a drawback of adaptive biasing is that it worsens the LDO's load transient response. Poor load transient response results in slow response and larger undershoot and overshoot voltages at the output. Another challenge with adaptive biasing is the difficulty in improving the deterioration of the phase margin (PM). Therefore, it is necessary to address the issues of slow transient response and phase margin degradation. Summary of the Invention
[0004] This invention aims to address at least one of the technical problems existing in the prior art. To this end, this invention proposes an adaptive bias low-dropout regulator with fast transient response, which can improve the problems of slow transient response and deteriorated phase margin while achieving adaptive bias to reduce power consumption.
[0005] According to an embodiment of the present invention, a fast transient response adaptive bias low dropout regulator includes: An error amplifier, wherein the inverting input terminal of the error amplifier is connected to a reference voltage, and the non-inverting input terminal of the error amplifier is connected to the output feedback voltage of a low dropout regulator; The main power transistor has its source connected to the input power supply and its drain connected to the output load of the low dropout regulator. A secondary power transistor, the source of which is connected to the input power supply, the drain of which is connected to the output load, and the gate of which is connected to the output terminal of the error amplifier; The first adaptive bias module is used to replicate the current of the main power transistor; The second adaptive bias module is used to replicate the current of the sub-power transistor. The current replicated by the first adaptive bias module and the current replicated by the second adaptive bias module are combined and flow into the error amplifier. The dynamic bias module is used to increase the bias current of the error amplifier when the low dropout regulator experiences overshoot or undershoot. The power transistor splitting module is used to control the on / off state of the main power transistor according to the load current of the low dropout regulator. The zero-point tracking module is used to dynamically change the zero-point position of the low-dropout regulator based on the changes in the load current of the low-dropout regulator.
[0006] According to some embodiments of the present invention, the first adaptive bias module includes: The first PMOS transistor has its source connected to the input power supply, its gate connected to the gate of the main power transistor, and its gate also connected to a first bias current source. The first NMOS transistor has its drain connected to the drain of the first PMOS transistor, and its source is grounded. The second NMOS transistor has its gate connected to the gate of the first NMOS transistor, its drain connected to the bias current input terminal of the error amplifier, and its source grounded. The gate of the first NMOS transistor is also connected to the drain of the first NMOS transistor.
[0007] According to some embodiments of the present invention, the second adaptive bias module includes: The gate of the second PMOS transistor is connected to the output terminal of the error amplifier and the gate of the sub-power transistor, respectively. The third NMOS transistor has its drain connected to the drain of the second PMOS transistor, and its source is grounded. The fourth NMOS transistor has its source grounded, its gate connected to the gate of the third NMOS transistor, and its gate also connected to the drain of the third NMOS transistor. The drain of the fourth NMOS transistor is connected to the bias current input terminal of the error amplifier.
[0008] According to some embodiments of the present invention, the bias current input terminal of the error amplifier is provided with: The third PMOS transistor has its source connected to the input power supply, its drain connected to the drain of the fourth NMOS transistor, and its gate connected to the drain of the third PMOS transistor. The fourth PMOS transistor has its gate connected to the gate of the third POS transistor, its source connected to the input power supply, and its drain connected to the error amplifier.
[0009] According to some embodiments of the present invention, the power transistor splitting module includes a fifth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first bias current source, a main power transistor, a secondary power transistor, a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source of the fifth PMOS transistor is connected to the input power supply, the gate of the fifth PMOS transistor is electrically connected to the gate of the secondary power transistor, the drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor, the source of the fifth NMOS transistor is grounded, the gate of the sixth NMOS transistor is connected to the gate of the fifth NMOS transistor, the source of the sixth NMOS transistor is grounded, and the drain of the sixth NMOS transistor is connected to the gate of the first PMOS transistor.
[0010] According to some embodiments of the present invention, the zero-point tracking module includes a second PMOS transistor, a third NMOS transistor, a seventh NMOS transistor, and a first capacitor. The gate of the seventh NMOS transistor is connected to the gate of the third NMOS transistor, the source of the seventh NMOS transistor is grounded, the drain of the seventh NMOS transistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the output terminal of the error amplifier.
[0011] According to some embodiments of the present invention, the zero-point tracking module further includes: The second capacitor has one end connected to the drain of the sub-power transistor and the other end connected to the non-inverting input of the error amplifier. An adjustable resistor, one end of which is connected to the drain of the sub-power transistor, and the other end of which is connected to the non-inverting input of the error amplifier; A first resistor, one end of which is connected to the other end of the adjustable resistor, and the other end of the first resistor is grounded.
[0012] According to some embodiments of the present invention, the dynamic bias module includes: The sixth PMOS transistor has its source connected to the input power supply and its drain connected to the error amplifier. The seventh PMOS transistor has its gate connected to the gate of the sixth PMOS transistor, its source connected to the input power supply, and its drain connected to the gate of the seventh PMOS transistor. The eighth NMOS transistor has its drain connected to the drain of the seventh PMOS transistor, and its source is grounded. The ninth NMOS transistor has its drain connected to the gate of the eighth NMOS transistor, and its source grounded. The tenth NMOS transistor has its gate connected to the gate of the ninth NMOS transistor, and its source is grounded. The eleventh NMOS transistor has its gate connected to the gate of the tenth NMOS transistor via a second resistor. The source of the eleventh NMOS transistor is grounded, and its drain is connected to a second bias current source. The gate of the eleventh NMOS transistor is also connected to the drain of the eleventh NMOS transistor Mn1. The third capacitor has one end connected to the gate of the tenth NMOS transistor and the other end connected to the output load of the low dropout regulator. The eighth PMOS transistor has its source connected to the input power supply and its drain connected to the drain of the eighth NMOS transistor. The ninth PMOS transistor has its gate connected to the gate of the eighth PMOS transistor via a third resistor, its source connected to the input power supply, and its drain connected to a third bias current source. The fourth capacitor has one end connected to the gate of the eighth PMOS transistor and the other end connected to the output load of the low dropout regulator. The tenth PMOS transistor has its source connected to the input power supply and its drain connected to the drain of the tenth NMOS transistor. The eleventh PMOS transistor has its gate connected to the gate of the tenth PMOS transistor, its source connected to the input power supply, and its drain connected to the fourth bias current source. The gate of the eleventh PMOS transistor is also connected to the drain of the eleventh PMOS transistor. The twelfth PMOS transistor has its gate connected to the drain of the tenth PMOS transistor, its source connected to the input power supply, and its drain connected to the error amplifier.
[0013] According to some embodiments of the present invention, the dynamic bias module includes: The thirteenth PMOS transistor has its source connected to the input power supply and its drain connected to the error amplifier. The fourteenth PMOS transistor has its gate connected to the gate of the thirteenth PMOS transistor, its source connected to the input power supply, and its drain connected to the gate of the fourteenth PMOS transistor. The twelfth NMOS transistor has its drain connected to the drain of the fourteenth PMOS transistor, and its source is grounded. The thirteenth NMOS transistor has its drain connected to the gate of the twelfth NMOS transistor, and its source grounded. The fourteenth NMOS transistor, the gate of which is connected to the gate of the thirteenth NMOS transistor, and the source of which is grounded; The fifteenth NMOS transistor has its gate connected to the gate of the fourteenth NMOS transistor through a fourth resistor, its source grounded, and its drain connected to a fourth bias current source. The fifth capacitor has one end connected to the gate of the fourteenth NMOS transistor, and the other end connected to the output load of the low dropout regulator. The fifteenth PMOS transistor, the source of which is connected to the input power supply, and the drain of which is connected to the gate of the twelfth NMOS transistor; The sixteenth PMOS transistor has its gate connected to the gate of the fifteenth PMOS transistor via a fifth resistor, its source connected to the input power supply, and its drain connected to a second bias current source. The sixth capacitor has one end connected to the gate of the fifteenth PMOS transistor and the other end connected to the output load of the low dropout regulator. The seventeenth PMOS transistor, the source of which is connected to the input power supply, and the drain of which is connected to the drain of the fourteenth NMOS transistor; The eighteenth PMOS transistor has its gate connected to the gate of the seventeenth PMOS transistor, its source connected to the input power supply, and its drain connected to the gate of the main power transistor.
[0014] According to some embodiments of the present invention, the output load of the low-dropout regulator includes: A load resistor, one end of which is connected to the drain of the main power transistor and the secondary power transistor; A load capacitor, one end of which is connected to the other end of the load resistor, and the other end of the load capacitor is grounded.
[0015] The fast transient response adaptive bias low-dropout regulator according to embodiments of the present invention has at least the following beneficial effects: by setting a first adaptive bias module and a second adaptive bias module, the bias current of the error amplifier can be adjusted according to the magnitude of the load current, thereby reducing the power consumption of the LDO. Furthermore, the dynamic bias module, power transistor splitting module, and zero-point tracking module can improve the transient response and phase margin problems caused by adaptive bias technology, thus achieving a low-power, fast transient response, and loop-stable LDO.
[0016] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0017] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a circuit diagram of an adaptive bias low-dropout regulator with fast transient response according to an embodiment of the present invention. Figure 2 The PM scan simulation results are shown when the load current is 0~300mA. Figure 3 This is a circuit schematic diagram of the dynamic bias module according to an embodiment of the present invention; Figure 4 This is a circuit schematic diagram of a dynamic bias module according to another embodiment of the present invention; Figure 5 This is a complete circuit diagram of an adaptive bias low-dropout regulator with fast transient response, according to an embodiment of the present invention. Detailed Implementation
[0018] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.
[0019] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.
[0020] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.
[0021] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0022] As we become increasingly reliant on smart wearables, Bluetooth headsets, and other electronic products, the demand for longer battery life is growing to meet the ever-increasing need for uninterrupted use. This has driven the continuous development of low-power chips and circuits, including low-dropout regulators (LDOs). As a crucial module in the power management unit (PMU), the LDO delivers a stable, low-noise, low-ripple voltage, powering other circuits. The lower quiescent power consumption of LDOs significantly contributes to longer battery life in consumer electronics, prompting researchers to continuously explore ways to achieve both low power consumption and low cost.
[0023] High-load LDOs require greater power consumption to operate, and even with fixed bias, high power consumption occurs under no-load or light-load conditions. Currently, adaptive biasing is commonly used to address this issue. However, a drawback of adaptive biasing is that it worsens the LDO's load transient response. Poor load transient response results in slow response and larger undershoot and overshoot voltages at the output. Another challenge with adaptive biasing is the difficulty in improving the deterioration of the phase margin (PM). Therefore, it is necessary to address the issues of slow transient response and phase margin degradation.
[0024] To address this issue, this application proposes an LDO with an adaptive biasing circuit (ABC) capable of achieving fast transient response, aiming to reduce power consumption. It comprises a traditional LDO architecture, an adaptive biasing module, a dynamic biasing module, a power transistor splitting module, and a zero-point tracking module. The adaptive biasing technology replicates the power transistor current back to the error amplifier (EA). When the LDO load current is large (small), the EA has more (less) bias current. This allows power consumption to automatically adjust according to different application scenarios, achieving lower static power consumption under no-load conditions. Previously, LDOs required significant power consumption to meet high load current requirements, even under light load or no-load conditions, which negatively impacted product endurance. The adaptive biasing technology solves this problem. The dynamic biasing module, power transistor splitting module, and zero-point tracking module improve the transient response and phase margin issues introduced by the adaptive biasing technology, thus achieving a low-power, fast-transient-response, and loop-stable LDO.
[0025] The following describes in detail, with reference to the accompanying drawings, an adaptive bias low-dropout regulator with fast transient response according to an embodiment of the present invention.
[0026] On the one hand, embodiments of the present invention propose an adaptive bias low-dropout regulator with fast transient response, such as... Figure 1As shown, the low dropout regulator includes an error amplifier (EA), a main power transistor Mpp2, a secondary power transistor Mpp1, a first adaptive bias module, a second adaptive bias module, a dynamic bias module, a power transistor splitting module, and a zero-point tracking module. The inverting input of the error amplifier is connected to the reference voltage (VREF), and the non-inverting input is connected to the output feedback voltage of the low dropout regulator. The source of the main power transistor Mpp2 is connected to the input power supply (LDOIN), and the drain of the main power transistor Mpp2 is connected to the output load of the low dropout regulator. The source of the secondary power transistor Mpp1 is connected to the input power supply, and the drain of the secondary power transistor Mpp1 is connected to the output load. The gate is connected to the output of the error amplifier; the first adaptive bias module is used to replicate the current of the main power transistor Mpp2, and the second adaptive bias module is used to replicate the current of the secondary power transistor Mpp1. The current replicated by the first adaptive bias module and the current replicated by the second adaptive bias module are combined and flow into the error amplifier; the dynamic bias module is used to increase the bias current of the error amplifier when the low dropout regulator overshoots or undershoots; the power transistor splitting module is used to control the on / off state of the main power transistor Mpp2 according to the load current of the low dropout regulator; the zero-point tracking module is used to dynamically change the zero-point position of the low dropout regulator according to the change of the load current of the low dropout regulator.
[0027] Specifically, such as Figure 1 As shown, in some embodiments of this application, the first adaptive bias module includes: a first PMOS transistor Mp20, a first NMOS transistor Mn19, and a second NMOS transistor Mn18. The source of the first PMOS transistor Mp20 is connected to the input power supply, and the gate of the first PMOS transistor Mp20 is connected to the gate of the main power transistor Mpp2. The gate of the first PMOS transistor Mp20 is also connected to a first bias current source I3. The drain of the first NMOS transistor Mn19 is connected to the drain of the first PMOS transistor Mp20, the source of the first NMOS transistor Mn19 is grounded (AGND), the gate of the first NMOS transistor Mn19 is connected to the gate of the second NMOS transistor Mn18, the drain of the second NMOS transistor Mn18 is connected to the bias current input terminal of the error amplifier, the source of the second NMOS transistor Mn18 is grounded, and the gate of the first NMOS transistor Mn19 is also connected to the drain of the first NMOS transistor Mn19. The current of the main power transistor Mpp2 can be replicated by Mp20, Mn18 and Mn19. The ratio of Mp20 to Mpp2 is 1:13248 (other ratios can also be set according to actual needs).
[0028] like Figure 1As shown, in some embodiments of this application, the second adaptive bias module includes a second PMOS transistor Mp18, a third NMOS transistor Mn13, and a fourth NMOS transistor Mn12. The gate of the second PMOS transistor Mp18 is connected to the output terminal of the error amplifier and the gate of the sub-power transistor Mpp1, respectively. The drain of the second PMOS transistor Mp18 is connected to the drain of the third NMOS transistor Mn13, the source of the third NMOS transistor Mn13 is grounded, the gate of the third NMOS transistor Mn13 is connected to the gate of the fourth NMOS transistor Mn12, the source of the fourth NMOS transistor Mn12 is grounded, the gate of the third NMOS transistor Mn13 is also connected to its drain, and the drain of the fourth NMOS transistor Mn12 is connected to the bias current input terminal of the error amplifier. Through Mp18, Mn12, and Mn13, the current of the sub-power transistor Mpp1 can be replicated. The ratio of Mp18 to Mpp1 is 1:16352 (other ratios can also be set according to actual needs). The first and second adaptive bias modules, respectively, measure the currents of the main power transistor Mpp2 and the auxiliary power transistor Mpp1 according to preset proportional amplitudes, and then the replicated currents are fed back to the error amplifier. In simple terms, adaptive bias technology replicates and reduces the current flowing through the power transistors using a current mirror according to a set ratio, and then feeds it back to the tail current source of the amplifier (EA). This allows the bias current of EA to change according to variations in the load current, achieving low power consumption under no-load or low-load conditions. However, the key challenge is overcoming the resulting load transient response and deterioration in loop stability.
[0029] like Figure 1 As shown, in some embodiments of this application, the bias current input terminal of the error amplifier is provided with a third PMOS transistor Mp11 and a fourth PMOS transistor Mp10. The source of the third PMOS transistor Mp11 is connected to the input power supply, the drain of the third PMOS transistor Mp11 is connected to the drain of the fourth NMOS transistor Mn12, and the gate of the third PMOS transistor Mp11 is connected to the drain of the third PMOS transistor Mp11. The gate of the fourth PMOS transistor Mp10 is connected to the gate of the third PMOS transistor Mp11, the source of the fourth PMOS transistor Mp10 is connected to the input power supply, and the drain of the fourth PMOS transistor Mp10 is connected to the error amplifier. After the first adaptive bias module and the second adaptive bias module respectively control the current of the main power transistor Mpp2 and the secondary power transistor Mpp1 according to the preset proportional amplitude, the two currents converge and flow into the error amplifier through the third PMOS transistor Mp11 and the fourth PMOS transistor Mp10.
[0030] like Figure 1As shown, in some embodiments of this application, the power transistor splitting module includes a fifth PMOS transistor Mp19, a fifth NMOS transistor Mn16, a sixth NMOS transistor Mn17, a first bias current source I3, a main power transistor Mpp2, a secondary power transistor Mpp1, a first PMOS transistor Mp20, a first NMOS transistor Mn19, and a second NMOS transistor Mn18. The source of the fifth PMOS transistor Mp19 is connected to the input power supply, and the gate of the fifth PMOS transistor Mp19 is electrically connected to the gate of the secondary power transistor Mpp1. The drain of the fifth NMOS transistor Mn16 is connected to the drain of the fifth PMOS transistor Mp19, and the source of the fifth NMOS transistor Mn16 is grounded. The gate of the sixth NMOS transistor Mn17 is connected to the gate of the fifth NMOS transistor Mn16, and the source of the sixth NMOS transistor Mn17 is grounded. The drain of the sixth NMOS transistor Mn17 is connected to the gate of the first PMOS transistor Mp20.
[0031] It should be noted that zero-point tracking and adaptive power transistor splitting techniques are employed to improve the loop stability of the LDO. The adaptive power transistor splitting technique uses a power transistor splitting module composed of Mp19, Mn16, Mn17, I3, Mpp1, Mpp2, Mp20, Mn18, and Mn19. I3 has a fixed bias current, and Mpp2 and Mpp1 are the primary and secondary power transistors, respectively. Both have the same W / L (channel width, channel length) per finger (single transistor), and their ratio is 368:112. Assume the load current that turns on the primary power transistor Mpp3 is I. ON In this application, I ON Take 70mA, I ON The size satisfies the following relationship: ; Mp19 detects load current I load After passing through current mirrors Mn16 and Mn17, the current is compared with I3. load As it gradually increases, it is less than I ON When only Mpp1 is conducting, the current of Mn17 is much smaller than I3, so the gate voltage of Mpp2 is high and Mpp2 is not conducting; when I... load Greater than I ON At that time, with I Ioad As the voltage increases, the gate voltage of Mpp2 gradually decreases, causing the conduction level of Mpp2 to gradually increase, providing sufficient load current. Controlled by the loop, Mpp2 can adaptively adjust its conduction level.
[0032] The zero-point tracking module has two components. One component includes a second PMOS transistor Mp18, a third NMOS transistor Mn13, a seventh NMOS transistor Mn11, and a first capacitor C1. The gate of the seventh NMOS transistor Mn11 is connected to the gate of the third NMOS transistor Mn13. The source of the seventh NMOS transistor Mn11 is grounded. The drain of the seventh NMOS transistor Mn11 is connected to one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the output of the error amplifier.
[0033] This zero-point tracking module can track changes in load current and dynamically change the zero-point position. Because the first capacitor C1 blocks DC, no current flows through the Mn11 transistor, which operates in the deep linear region. Its on-resistance Ron satisfies the following relationship: ; Where μn is the electron mobility, Cox is the gate oxide capacitance per unit area, and W, L, VGS, and VTH are the gate width, gate length, gate-source voltage, and threshold voltage of the Mn11 transistor, respectively.
[0034] When the load current I load When the gate-source voltage V of Mn11 increases or decreases, GS This will also increase or decrease, causing the on-resistance of Mn11 to decrease or increase accordingly. The zero-point value is 1 / (RonC1), and the zero-point position also shifts towards higher or lower frequencies. As mentioned earlier, at low (high) load currents, both the dominant and secondary poles shift towards lower (higher) frequencies. Therefore, after introducing zero-point tracking, it can also follow the load current in the same direction, but the degree of change is difficult to guarantee is the same because the load current has been significantly reduced and transformed by the Ron formula, and the degree of change of the dominant and secondary poles with the load current is not the same. Therefore, it can only achieve a phase margin optimization effect to a certain extent. It should be noted that the zero-point tracking module here only tracks the current of the secondary power transistor Mpp1. If I load >I ON Since the current of the secondary power transistor Mpp1 no longer changes, the zero-point position also no longer changes. Moreover, this zero-point tracking technology is only applicable at low load currents, the reason for which will be explained in the subsequent analysis. This is very consistent with the system structure of this application.
[0035] like Figure 1As shown, another part of the zero - tracking module includes: a second capacitor C4, a variable resistor Rf1, and a first resistor Rf2. One end of the second capacitor C4 is connected to the drain of the auxiliary power transistor Mpp1, and the other end of the second capacitor C4 is connected to the non - inverting input terminal of the error amplifier; one end of the variable resistor Rf1 is connected to the drain of the auxiliary power transistor Mpp2, the other end of the variable resistor Rf1 is connected to the non - inverting input terminal of the error amplifier, one end of the first resistor Rf2 is connected to the other end of the variable resistor Rf1, and the other end of the first resistor Rf2 is grounded. Another zero of the zero - tracking module is composed of C4, Rf1, and Rf2, which will generate a (left - half - plane) zero - pole pair. Among them, Rf1 is adjustable and can be used to calibrate the output voltage of the LDO. The generated zero - pole expression is as follows: , ; Calculate the loop transfer function expressions for two cases of the conduction of the main and auxiliary power transistors: (1) When I load <ION, only the auxiliary power transistor Mpp1 is conducting. Disconnect the loop between the output of the LDO and the feedback resistor string, and apply a test small - signal V t , and calculate the ratio of the output voltage to V t , which is the loop - gain transfer function expression at this time: ; Among them, s is the complex - frequency variable.
[0036] The output - terminal voltage of the error amplifier is: ; Among them, g m，EA is the equivalent transconductance of the EA, R EA is the equivalent output impedance of the EA, C EA is the equivalent output capacitance of the EA, and Ron is the on - resistance of Mn11. After passing through the auxiliary power transistor Mpp1, the LDO output is: ; Among them, is the equivalent transconductance of the auxiliary power transistor Mpp1, , is the output impedance of the auxiliary power transistor Mpp1, R L is the load resistance, is the equivalent impedance of the auxiliary power transistor Mpp1. So, the loop - gain transfer function of the main loop is: ; When only the auxiliary power transistor Mpp1 is conducting, C EA >>C1 does not hold. For example, under a 50 - mA load, C EA= 53.5p, C1=12p, then it will not make Simplified to ,lead to The zeros are canceled out in the numerator and denominator, explaining that this zero-point tracking only applies to low-load conditions. Therefore, the loop has 3 zeros and 4 poles, with the zeros generated by the load capacitance occurring at higher frequencies.
[0037] equation It is easy to generate complex roots, so we convert them to:
[0038] We can obtain:
[0039] in, The resonant angular frequency is a complex root, which significantly degrades loop stability. The condition for no complex root is that Q < 1 / 2, but since C in the above equation... EA R EA Ron, etc., all vary with the load current, so it is difficult to calculate over the entire load range. Taking a 50mA load as an example, C EA =53.5p, R EA =21M, Ron=1.17M, C1=12p, and we can calculate Q≈0.113, so there are no complex roots.
[0040] right To find the poles, taking a 50mA load as an example, the two poles are at 735.7Hz and 87.7kHz, one of which is located at a negligible high frequency. The pole was found to be at 141.7Hz. Clearly, without splitting the power transistor, the pole... To achieve lower voltage, the secondary pole is further away from the primary pole after splitting the power transistor and introducing a zero, which improves the phase margin.
[0041] (2) When I load >I ON At this time, both the main power transistor Mpp2 and the auxiliary power transistor Mpp1 are turned on. Calculate the loop transfer function expression at this time: The loop gain transfer function of the main power transistor loop is:
[0042] ; Where gmc is the equivalent transconductance of the current comparison section of Mp19, Mn16, Mn17, I3, etc., Rc is the equivalent resistance of the gate terminal of the main power transistor Mpp2, and Cc is the equivalent capacitance of the gate terminal of the main power transistor Mpp2. The equivalent transconductance of the main power transistor Mpp2 is... , The output impedance of the secondary power transistor Mpp1 is... Given the output impedance of the main power transistor Mpp2, and since both the main and auxiliary power transistors are conducting, Ro1 of Vout1 needs to be changed to Ro. Therefore, the overall loop gain transfer function is: ; As can be seen from the equation, when both the main and auxiliary power transistors are turned on, an additional zero and pole are added, making theoretical analysis difficult. A direct sweep simulation of the load from 0 to 300mA yields the following results for loop gain and phase margin: Figure 4 .
[0043] To overcome the impact of load transient response degradation, a dynamic bias module is proposed, such as... Figure 3 As shown, the dynamic bias module includes: the sixth PMOS transistor Mp7, the seventh PMOS transistor Mp6, the eighth NMOS transistor Mn4, the ninth NMOS transistor Mn3, the tenth NMOS transistor Mn2, the eleventh NMOS transistor Mn1, the third capacitor C3, the eighth PMOS transistor Mp5, the ninth PMOS transistor Mp4, the fourth capacitor C2, the tenth PMOS transistor Mp3, the eleventh PMOS transistor Mp1, and the twelfth PMOS transistor Mp2. In this configuration, the source of the sixth PMOS transistor Mp7 is connected to the input power supply, and the drain of the sixth PMOS transistor Mp7 is connected to the error amplifier (I2); the gate of the seventh PMOS transistor Mp6 is connected to the gate of the sixth PMOS transistor Mp7, the source of the seventh PMOS transistor Mp6 is connected to the input power supply, and the drain of the seventh PMOS transistor Mp6 is connected to the gate of the seventh PMOS transistor Mp6; the drain of the eighth NMOS transistor Mn4 is connected to the drain of the seventh PMOS transistor Mp6, and the source of the eighth NMOS transistor Mn4 is grounded; the drain of the ninth NMOS transistor Mn3 is connected to the gate of the eighth NMOS transistor Mn4, and the source of the ninth NMOS transistor Mn3 is grounded. Grounded; the gate of the tenth NMOS transistor Mn2 is connected to the gate of the ninth NMOS transistor Mn3, and the source of the tenth NMOS transistor Mn2 is grounded; the gate of the eleventh NMOS transistor Mn1 is connected to the gate of the tenth NMOS transistor Mn2 through the second resistor R1, the gate of the eleventh NMOS transistor Mn1 is also connected to the drain of the eleventh NMOS transistor Mn1, the source of the eleventh NMOS transistor Mn1 is grounded, and the drain of the eleventh NMOS transistor Mn1 is connected to the second bias current source Ibias2; one end of the third capacitor C3 is connected to the gate of the tenth NMOS transistor Mn2, and the other end of the third capacitor C3 is connected to the output load (V) of the low dropout regulator. OUTThe connections are as follows: The source of the eighth PMOS transistor Mp5 is connected to the input power supply, and the drain of the eighth PMOS transistor Mp5 is connected to the drain of the eighth NMOS transistor Mn4; The gate of the ninth PMOS transistor Mp4 is connected to the gate of the eighth PMOS transistor Mp5 through the third resistor R2, the source of the ninth PMOS transistor Mp4 is connected to the input power supply, and the drain of the ninth PMOS transistor Mp4 is connected to the third bias current source Ibias3; One end of the fourth capacitor C2 is connected to the gate of the eighth PMOS transistor Mp5, and the other end of the fourth capacitor C2 is connected to the output load of the low dropout regulator; The source of the tenth PMOS transistor Mp3 is connected to the input power supply, and the tenth P... The drain of MOSFET Mp3 is connected to the drain of the tenth NMOS transistor Mn2; the gate of the eleventh PMOS transistor Mp1 is connected to the gate of the tenth PMOS transistor Mp3, the source of the eleventh PMOS transistor Mp1 is connected to the input power supply, the drain of the eleventh PMOS transistor Mp1 is connected to the fourth bias current source Ibias1, and the gate of the eleventh PMOS transistor Mp1 is also connected to the drain of the eleventh PMOS transistor Mp1; the gate of the twelfth PMOS transistor Mp2 is connected to the drain of the tenth PMOS transistor Mp3, the source of the twelfth PMOS transistor Mp2 is connected to the input power supply, and the drain of the twelfth PMOS transistor Mp2 is connected to the error amplifier.
[0044] The idea behind this dynamic biasing method to improve the transient response of the load is as follows: Two current sources, A and B, are compared, with one current source being significantly larger than the other. The comparison result controls the magnitude of the other current source, C. When there is no load change, the current comparison result makes current source C zero, and the dynamic biasing circuit does not operate. When there is a load change, overshoot or undershoot is detected through capacitive coupling, causing one of the A and B current sources to increase its current. The resulting large voltage change is compared and output, causing current source C to increase rapidly. This increased current is then fed into the tail current of EA, improving the bandwidth of EA.
[0045] exist Figure 3 In this circuit, the current in Mp3 is much greater than that in Mn2, and the current in Mn3 is much greater than that in Mp5. Therefore, when the load does not change abruptly, both Mp2 and Mn4 are turned off, and this part of the circuit does not work. During overshoot, the Vo of Mn2... GS Increasing I3 causes a sudden drop in the gate voltage of Mp2, and increasing I3 increases the tail current of EA; during undershoot, the |V of Mp5 GS The increase in I2 causes a sudden rise in the gate voltage of Mn4, and the increase in I2 causes a sudden increase in the tail current of EA. Both of these factors cause a sudden increase in the bias current of EA during large undershoots or overshoots, thereby increasing the loop bandwidth and accelerating the response to sudden load changes.
[0046] The charging and discharging rate of the gate parasitic capacitance of the power transistor is also a factor affecting the transient response speed. Since the power transistor is split in this invention, and both I3 and Ibias3 are relatively small, while the gate parasitic capacitance of the main power transistor Mpp2 is relatively large, the gate voltage cannot change rapidly. Furthermore, overshoot is less degraded by adaptive bias than undershoot; therefore, [the following is omitted as the original text is incomplete and cannot be translated]. Figure 3 The dynamic bias module was modified to suit the actual situation. Figure 4 .
[0047] like Figure 4 As shown, in this example, the dynamic bias module includes: the thirteenth PMOS transistor Mp17, the fourteenth PMOS transistor Mp16, the twelfth NMOS transistor Mn15, the thirteenth NMOS transistor Mn14, the fourteenth NMOS transistor Mn9, the fifteenth NMOS transistor Mn8, the fifth capacitor C5, the fifteenth PMOS transistor Mp15, the sixteenth PMOS transistor Mp14, the sixth capacitor C6, the seventeenth PMOS transistor Mp13, and the eighteenth PMOS transistor Mp12. The source of the thirteenth PMOS transistor Mp17 is connected to the input power supply. The drain of the three PMOS transistors Mp17 is connected to the error amplifier; the gate of the fourteenth PMOS transistor Mp16 is connected to the gate of the thirteenth PMOS transistor Mp17, the source of the fourteenth PMOS transistor Mp16 is connected to the input power supply, and the drain of the fourteenth PMOS transistor Mp16 is connected to its gate; the drain of the twelfth NMOS transistor Mn15 is connected to the drain of the fourteenth PMOS transistor Mp16, the source of the twelfth NMOS transistor Mn15 is grounded, and the gate of the twelfth NMOS transistor Mn15 is connected to the gate of the thirteenth NMOS transistor Mp17. The drain of the S-MOSFET Mn14 is connected, and the source of the thirteenth NMOS transistor Mn14 is grounded; the gate of the thirteenth NMOS transistor Mn14 is connected to the gate of the fourteenth NMOS transistor Mn9, and the source of the fourteenth NMOS transistor Mn9 is grounded; the gate of the fifteenth NMOS transistor Mn8 is connected to the gate of the fourteenth NMOS transistor Mn9 through the fourth resistor R1, the source of the fifteenth NMOS transistor Mn8 is grounded, and the drain of the fifteenth NMOS transistor Mn8 is connected to the fourth bias current source Ibias1; one end of the fifth capacitor C5 is connected to the fourteenth NMOS transistor... The gate of Mn9 is connected, and the other end of the fifth capacitor C5 is connected to the output load of the low dropout regulator; the source of the fifteenth PMOS transistor Mp15 is connected to the input power supply, the drain of the fifteenth PMOS transistor Mp15 is connected to the gate of the twelfth NMOS transistor Mn15, the gate of the sixteenth PMOS transistor Mp14 is connected to the gate of the fifteenth PMOS transistor Mp15 through the fifth resistor R2, the source of the sixteenth PMOS transistor Mp14 is connected to the input power supply, and the drain of the sixteenth PMOS transistor Mp14 is connected to the second bias current source Ibias2; One end of the sixth capacitor C6 is connected to the gate of the fifteenth PMOS transistor Mp15, and the other end of the sixth capacitor C6 is connected to the output load of the low dropout regulator; the source of the seventeenth PMOS transistor Mp13 is connected to the input power supply, the drain of the seventeenth PMOS transistor Mp13 is connected to the drain of the fourteenth NMOS transistor Mn9, the gate of the eighteenth PMOS transistor Mp12 is connected to the gate of the seventeenth PMOS transistor Mp13, the source of the eighteenth PMOS transistor Mp12 is connected to the input power supply, and the drain of the eighteenth PMOS transistor Mp12 is connected to the gate of the main power transistor Mpp2.
[0048] This dynamic bias module consists of PMOS transistors Mp12~Mp17, NMOS transistors Mn8~Mn9 and Mn14~Mn15, capacitors C5~C6, and resistors R1~R2. During overshoot, I3 increases, causing the gate voltage of Mpp2 to rise instantaneously, thus reducing the response to sudden changes in load current. During undershoot, I3 decreases, causing the gate voltage of Mpp2 to drop instantaneously, responding to sudden increases in load current. Assuming the settling time of the load transient response is t1, which represents the time from the onset of a sudden load change to the LDO making an effective adjustment, and also signifies that the overshoot or undershoot voltage reaches its maximum value at this time, its expression is as follows: ; in, This represents the gate-source variation of the power transistor. The change in load current is given by BW, where BW is the loop bandwidth of the LDO, and t is the value of t. SR+ This represents the forward slew rate time of the power transistor, Cmp is the gate parasitic capacitance of the power transistor, and I... SR+ Let t1 be the forward current of the power transistor slew, and gmp be the equivalent transconductance of the power transistor. The value of t1 is inversely proportional to the system bandwidth and directly proportional to the power transistor's slew rate. Therefore, t1 can be reduced by increasing the LDO system bandwidth and using larger-sized power transistors with strong current drive capability, thereby improving the LDO's load transient response. The expression for the resulting overshoot or undershoot voltage is as follows:
[0049] It can be seen that the generated overshoot or undershoot voltage is inversely proportional to the load capacitance CL and the maximum load current I. load，maxThe transient response is proportional to the settling time t1. Since the maximum load current of the LDO in this invention can reach 300mA, it will generate significant undershoot and overshoot. Therefore, a 1uF external capacitor is used. However, after using adaptive biasing technology, the decrease in the bias current EA reduces the bias current BW, leading to a longer settling time t1 and increased undershoot and overshoot voltages. Therefore, measures must be taken to improve the load transient response. This application mainly improves the response by increasing BW. By detecting overshoot or undershoot in the output voltage, the bias current EA is briefly increased to quickly respond to sudden load changes. The complete circuit of the fast transient response adaptive bias low-dropout regulator is as follows: Figure 5 As shown.
[0050] like Figure 4 As shown, if the output voltage LDOOUT overshoots, it will couple to the gates of Mn9 and Mn14 through C2, causing V of Mn9 and Mn14 to... GS As the voltage increases, the current flowing through Mn9 and Mn14 will increase instantaneously. Simultaneously, the overshoot voltage will couple to the gate of Mp15 through C3, causing |V| of Mp15 to... GS The current flowing through Mp15 decreases because the current of Mn14 is much larger than that of Mp15, preventing Mn15 from conducting. Now, with the increase in the current of Mn14 and the decrease in the current of Mp15, Mn15 is even less likely to conduct. The main reason for overshoot or undershoot is that the parasitic capacitance at the gate of the power transistor cannot be charged and discharged quickly, i.e., the gate voltage cannot rise or fall quickly. This invention takes measures at the gate of the main power transistor. Because the current of Mn9 increases, the current of I3 increases. Since the other end is a fixed current source, it will drive the gate voltage of Mpp2 to rise rapidly, reducing the load current to respond to I. load The abrupt change from large to small reduces overshoot.
[0051] like Figure 4 As shown, if the LDO output produces undershoot, it will couple to the gates of Mn9 and Mn14 through C2, reducing their current. Simultaneously, coupling through C3 increases the current of Mp15. Therefore, the V of Mn15... GS The current will increase rapidly, causing the current I2 to increase, the tail current source of EA to increase, and expanding the entire loop bandwidth. Because the current of Mn9 decreases, the current I3 decreases, causing the gate voltage of the main power transistor Mpp2 to drop rapidly, increasing the load current to respond to I. load A dramatic shift from small to large. These two measures have greatly optimized the undershoot improvement.
[0052] The transient response simulation results with and without the dynamic bias module were compared. Without the dynamic bias module, the overshoot and undershoot voltages were 349mV and 1.582V, respectively. After using the dynamic bias module, the overshoot and undershoot voltages were 145mV and 160mV, respectively, and the transient response was significantly improved.
[0053] In some embodiments of this application, the output load of the low-dropout regulator includes a load resistor R. ESR and load capacitance CL, load resistance R ESR One end of the capacitor CL is connected to the drain of the main power transistor Mpp2 and the auxiliary power transistor Mpp1; one end of the load capacitor CL is connected to the load resistor R. ESR The other end of the capacitor is connected, and the other end of the load capacitor CL is grounded. The load resistor R... ESR Together with the load capacitor CL, they form the output load network of the LDO, which plays a decisive role in the system's stability, transient response, and noise performance.
[0054] It's important to note that deterioration in load transient response is a significant drawback of adaptive biasing technology. Because adaptive biasing reduces the EA bias current, a smaller EA bias current leads to a smaller bandwidth. The bandwidth of the EA affects the entire LDO loop bandwidth. A smaller bandwidth means the LDO cannot respond quickly to load changes, resulting in significant overshoot or undershoot in the output voltage, especially undershoot. For example, when the load current changes abruptly from 100µA to 300mA, the EA bias remains at 100µA because the LDO hasn't responded yet. In this case, the bias current drawn back to the EA by the adaptive biasing technology is very small, relying solely on its own tail current source for biasing. Therefore, the bandwidth is small, and the response after load switching is very slow. Larger load currents can only be powered by external load capacitors, leading to significant undershoot voltage. However, if the load switches from 300mA to 100µA, the initial state is 300mA, with a larger bandwidth response, so the overshoot deterioration is relatively less severe. To address this issue, a dynamic biasing module must be used to improve the situation.
[0055] In this application, the LDO's maximum load current can reach 300mA, using an external 1uF load capacitor, so the dominant pole is located at the output terminal. A large load current requires a very large power transistor, resulting in a very large gate-side parasitic capacitance, and the secondary pole is relatively close to the dominant pole, which degrades the power transistor's performance characteristics (PM). Especially at low loads, due to the reduced current flowing through the power transistor, the equivalent resistance rop of the power transistor increases, the dominant pole shifts to lower frequencies, and the equivalent gate-side capacitance Cgs+gmpropCgd also increases. Here, gmp is the power transistor's transconductance, and Cgs and Cgd are the gate-source and gate-drain parasitic capacitances, respectively. Furthermore, due to the adaptive biasing technology, the bias current at the EA output terminal is small, increasing the equivalent resistance ro,amp at the output terminal, and the secondary pole also shifts to lower frequencies. Their respective relationships with the load current are as follows: , , ,
[0056] Where N is the load current I load The scaling factor, reduced by the adaptive bias circuit, is very small, but it still causes the secondary pole to shift to lower frequencies more significantly under low load, resulting in poor PM at low load. Because of the adaptive bias, the output impedance of EA also varies with I. load The change causes the secondary pole to change with I. load As the degree of change increases, PM is exacerbated. Therefore, this invention mainly employs a power transistor adaptive splitting technique, which splits the power transistor into a primary and a secondary power transistor. This technique can automatically detect a set load current, and only conduct the secondary power transistor below the set current, while conducting all power transistors only when the current exceeds the set current. In this way, under low load conditions, because there are fewer secondary power transistors and the parasitic capacitance at the secondary pole is smaller, it can effectively improve PM.
[0057] The fast transient response adaptive bias low-dropout regulator according to this application can withstand a large load current of 300mA, and the power consumption changes with the load current, which greatly reduces the power consumption under light load or no load. The load transient response is well suppressed by adopting a dynamic bias module, a power transistor splitting module and a zero-point tracking module. The power transistor splitting technology is used to make the LDO have good stability under all process corners, -40℃~100℃, 2.5V~6.3V combinations, and Monte Carlo simulation.
[0058] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.
Claims
1. A fast transient response adaptive bias low dropout voltage regulator, characterized in that, include: An error amplifier, wherein the inverting input terminal of the error amplifier is connected to a reference voltage, and the non-inverting input terminal of the error amplifier is connected to the output feedback voltage of a low dropout regulator; The main power transistor has its source connected to the input power supply and its drain connected to the output load of the low dropout regulator. A secondary power transistor, the source of which is connected to the input power supply, the drain of which is connected to the output load, and the gate of which is connected to the output terminal of the error amplifier; The first adaptive bias module is used to replicate the current of the main power transistor; The second adaptive bias module is used to replicate the current of the sub-power transistor. The current replicated by the first adaptive bias module and the current replicated by the second adaptive bias module are combined and flow into the error amplifier. The dynamic bias module is used to increase the bias current of the error amplifier when the low dropout regulator experiences overshoot or undershoot. The power transistor splitting module is used to control the on / off state of the main power transistor according to the load current of the low dropout regulator. The zero-point tracking module is used to dynamically change the zero-point position of the low-dropout regulator based on the changes in the load current of the low-dropout regulator.
2. The fast transient response adaptive bias low dropout regulator according to claim 1, characterized in that, The first adaptive bias module includes: The first PMOS transistor has its source connected to the input power supply, its gate connected to the gate of the main power transistor, and its gate also connected to a first bias current source. The first NMOS transistor has its drain connected to the drain of the first PMOS transistor, and its source is grounded. The second NMOS transistor has its gate connected to the gate of the first NMOS transistor, its drain connected to the bias current input terminal of the error amplifier, and its source grounded. The gate of the first NMOS transistor is also connected to the drain of the first NMOS transistor.
3. The fast transient response adaptive bias low dropout regulator according to claim 2, characterized in that, The second adaptive bias module includes: The gate of the second PMOS transistor is connected to the output terminal of the error amplifier and the gate of the sub-power transistor, respectively. The third NMOS transistor has its drain connected to the drain of the second PMOS transistor, and its source is grounded. The fourth NMOS transistor has its source grounded, its gate connected to the gate of the third NMOS transistor, and its gate also connected to the drain of the third NMOS transistor. The drain of the fourth NMOS transistor is connected to the bias current input terminal of the error amplifier.
4. The fast transient response adaptive bias low dropout regulator according to claim 3, characterized in that, The bias current input terminal of the error amplifier is provided with: The third PMOS transistor has its source connected to the input power supply, its drain connected to the drain of the fourth NMOS transistor, and its gate connected to the drain of the third PMOS transistor. The fourth PMOS transistor has its gate connected to the gate of the third POS transistor, its source connected to the input power supply, and its drain connected to the error amplifier.
5. The fast transient response adaptive bias low dropout regulator according to claim 3, characterized in that, The power transistor splitting module includes a fifth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first bias current source, a main power transistor, a secondary power transistor, a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source of the fifth PMOS transistor is connected to the input power supply, the gate of the fifth PMOS transistor is electrically connected to the gate of the secondary power transistor, the drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor, and the source of the fifth NMOS transistor is grounded. The gate of the sixth NMOS transistor is connected to the gate of the fifth NMOS transistor, the source of the sixth NMOS transistor is grounded, and the drain of the sixth NMOS transistor is connected to the gate of the first PMOS transistor.
6. The fast transient response adaptive bias low dropout regulator according to claim 5, characterized in that, The zero-point tracking module includes a second PMOS transistor, a third NMOS transistor, a seventh NMOS transistor, and a first capacitor. The gate of the seventh NMOS transistor is connected to the gate of the third NMOS transistor, the source of the seventh NMOS transistor is grounded, the drain of the seventh NMOS transistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the output terminal of the error amplifier.
7. The fast transient response adaptive bias low dropout regulator according to claim 6, characterized in that, The zero-point tracking module also includes: The second capacitor has one end connected to the drain of the sub-power transistor and the other end connected to the non-inverting input of the error amplifier. An adjustable resistor, one end of which is connected to the drain of the sub-power transistor, and the other end of which is connected to the non-inverting input of the error amplifier; A first resistor, one end of which is connected to the other end of the adjustable resistor, and the other end of the first resistor is grounded.
8. The fast transient response adaptive bias low dropout regulator according to claim 5, characterized in that, The dynamic bias module includes: The sixth PMOS transistor has its source connected to the input power supply and its drain connected to the error amplifier. The seventh PMOS transistor has its gate connected to the gate of the sixth PMOS transistor, its source connected to the input power supply, and its drain connected to the gate of the seventh PMOS transistor. The eighth NMOS transistor has its drain connected to the drain of the seventh PMOS transistor, and its source is grounded. The ninth NMOS transistor has its drain connected to the gate of the eighth NMOS transistor, and its source grounded. The tenth NMOS transistor has its gate connected to the gate of the ninth NMOS transistor, and its source is grounded. The eleventh NMOS transistor has its gate connected to the gate of the tenth NMOS transistor via a second resistor. The source of the eleventh NMOS transistor is grounded, and its drain is connected to a second bias current source. The gate of the eleventh NMOS transistor is also connected to the drain of the eleventh NMOS transistor Mn1. The third capacitor has one end connected to the gate of the tenth NMOS transistor and the other end connected to the output load of the low dropout regulator. The eighth PMOS transistor has its source connected to the input power supply and its drain connected to the drain of the eighth NMOS transistor. The ninth PMOS transistor has its gate connected to the gate of the eighth PMOS transistor via a third resistor, its source connected to the input power supply, and its drain connected to a third bias current source. The fourth capacitor has one end connected to the gate of the eighth PMOS transistor and the other end connected to the output load of the low dropout regulator. The tenth PMOS transistor has its source connected to the input power supply and its drain connected to the drain of the tenth NMOS transistor. The eleventh PMOS transistor has its gate connected to the gate of the tenth PMOS transistor, its source connected to the input power supply, and its drain connected to the fourth bias current source. The gate of the eleventh PMOS transistor is also connected to the drain of the eleventh PMOS transistor. The twelfth PMOS transistor has its gate connected to the drain of the tenth PMOS transistor, its source connected to the input power supply, and its drain connected to the error amplifier.
9. The fast transient response adaptive bias low dropout regulator according to claim 5, characterized in that, The dynamic bias module includes: The thirteenth PMOS transistor has its source connected to the input power supply and its drain connected to the error amplifier. The fourteenth PMOS transistor has its gate connected to the gate of the thirteenth PMOS transistor, its source connected to the input power supply, and its drain connected to the gate of the fourteenth PMOS transistor. The twelfth NMOS transistor has its drain connected to the drain of the fourteenth PMOS transistor, and its source is grounded. The thirteenth NMOS transistor has its drain connected to the gate of the twelfth NMOS transistor, and its source grounded. The fourteenth NMOS transistor, the gate of which is connected to the gate of the thirteenth NMOS transistor, and the source of which is grounded; The fifteenth NMOS transistor has its gate connected to the gate of the fourteenth NMOS transistor through a fourth resistor, its source grounded, and its drain connected to a fourth bias current source. The fifth capacitor has one end connected to the gate of the fourteenth NMOS transistor, and the other end connected to the output load of the low dropout regulator. The fifteenth PMOS transistor, the source of which is connected to the input power supply, and the drain of which is connected to the gate of the twelfth NMOS transistor; The sixteenth PMOS transistor has its gate connected to the gate of the fifteenth PMOS transistor via a fifth resistor, its source connected to the input power supply, and its drain connected to a second bias current source. The sixth capacitor has one end connected to the gate of the fifteenth PMOS transistor and the other end connected to the output load of the low dropout regulator. The seventeenth PMOS transistor, the source of which is connected to the input power supply, and the drain of which is connected to the drain of the fourteenth NMOS transistor; The eighteenth PMOS transistor has its gate connected to the gate of the seventeenth PMOS transistor, its source connected to the input power supply, and its drain connected to the gate of the main power transistor.
10. The fast transient response adaptive bias low dropout regulator according to claim 6, characterized in that, The output load of the low-dropout regulator includes: A load resistor, one end of which is connected to the drain of the main power transistor and the secondary power transistor; A load capacitor, one end of which is connected to the other end of the load resistor, and the other end of the load capacitor is grounded.