Linear voltage stabilizing circuit, linear voltage stabilizer, power supply device, and electronic device for enhancing middle and low frequency power supply rejection ratio

Abstract

The application belongs to the field of electronic circuits, and provides a linear voltage stabilizing circuit for enhancing middle-low frequency power supply rejection ratio, a linear voltage stabilizer, a power supply device and an electronic device. The linear voltage stabilizing circuit comprises an error amplification module, a power module, a resistance module and a voltage control voltage module. When the power supply voltage is disturbed, the disturbance will have an impact on the output voltage through two paths: on the one hand, the disturbance of the power supply voltage will pass through the error amplification module and the power module to generate a disturbance on the output voltage, i.e. a first disturbance; on the other hand, the disturbance of the power supply voltage will pass through the voltage control voltage module to generate a disturbance, which is transmitted through two paths, and finally generates another disturbance on the output voltage, i.e. a second disturbance. The second disturbance is opposite to the first disturbance, and by reasonably controlling the voltage coefficient of the voltage control voltage module, the two disturbances are offset, thereby effectively suppressing the influence of the power supply voltage noise on the output voltage and realizing excellent middle-low frequency PSR performance.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and particularly relates to a linear voltage regulator circuit, linear regulator, power supply device and electronic equipment that enhances the power supply rejection ratio in low and medium frequencies. Background Technology

[0002] With the development of LDO (Low Dropout Regulator) technology, high power supply rejection ratio (PSR) LDOs are mainly used in fields with high requirements for power supply purity. They function like filters, blocking noise and ripple from upstream stages (such as DC-DC converters) to provide a more ideal power supply for downstream circuits. The radio frequency (RF) and wireless communication fields are also the core application markets for high PSR LDOs, as RF transmitters, power amplifiers, and phase-locked loops are highly susceptible to power supply noise. Noise from the power supply degrades phase noise and signal-to-noise ratio, directly affecting communication quality and data transmission rates. In base stations, mobile phones, and GPS (Global Positioning System) transceivers, high PSR LDOs provide clean power to these sensitive devices. Furthermore, in the field of image sensors, such as high-end security monitoring, machine vision, and mobile phone cameras, if the image sensor's power supply is noisy, it will directly manifest in the image, producing phenomena such as screen stripes or "snowflakes." Given the importance of high PSR LDO, research on it has always been a hot topic, with many excellent methods for enhancing PSR emerging in various articles and patents.

[0003] However, current research on enhancing LDO PSR faces the following problems: First, most articles and patents discuss enhancing the high-frequency PSR of LDOs, while there is less research on enhancing the mid-to-low frequency PSR. Second, the solutions provided in most studies are relatively complex and often consume a large chip area and power consumption, which is a problem that needs to be solved. Summary of the Invention

[0004] This application provides a linear voltage regulator circuit, linear regulator, power supply device, and electronic device that enhances the power supply rejection ratio (PSR) of low and medium frequencies. It can solve the problem that traditional low and medium frequency PSR enhancement schemes are complex in structure, resulting in large chip area and power consumption.

[0005] In a first aspect, embodiments of this application provide a linear voltage regulator circuit for enhancing the power supply rejection ratio in low and medium frequencies, including an error amplification module, a power module, a resistor module, and a voltage-controlled voltage module. The first input terminal of the error amplification module is used to receive a reference voltage. The second input terminal of the error amplification module is connected to the output terminal of the resistor module. The output terminal of the error amplification module is connected to the control terminal of the power module. The first terminal of the power module, the power supply terminal of the error amplification module, and the control terminal of the voltage-controlled voltage module all receive power supply voltage. The second terminal of the power module is connected to the first terminal of the resistor module, the first terminal of the output capacitor, and the first terminal of the load, respectively. The second terminal of the resistor module is connected to the first terminal of the voltage-controlled voltage module. The ground terminal of the error amplification module, the second terminal of the voltage-controlled voltage module, the second terminal of the output capacitor, and the second terminal of the load are all grounded. The error amplification module is used to receive feedback voltage and output error voltage based on the feedback voltage and the reference voltage; the power module is used to turn on according to the error voltage and output a first current, the first current flowing through the load to generate an output voltage; the voltage-controlled voltage module is used to output a first voltage based on the power supply voltage; the resistor module is used to output a feedback voltage based on the output voltage and the first voltage.

[0006] In one possible implementation of the first aspect, the error amplification module includes an error amplifier, a first input terminal of the error amplifier for receiving a reference voltage, a second input terminal of the error amplifier connected to the output terminal of the resistor module, an output terminal of the error amplifier connected to the control terminal of the power module, a power supply terminal of the error amplifier for receiving a power supply voltage, and a ground terminal of the error amplifier for grounding.

[0007] In one possible implementation of the first aspect, the power module includes a power transistor, the gate of which is connected to the output terminal of the error amplifier module, the source of which receives a power supply voltage, and the drain of which is connected to a first terminal of the resistor module, a first terminal of the output capacitor, and a first terminal of the load.

[0008] In one possible implementation of the first aspect, the resistor module includes a first resistor and a second resistor, a first terminal of the first resistor is connected to a second terminal of the power module, a first terminal of the output capacitor and a first terminal of the load, a second terminal of the first resistor is connected to a first terminal of the second resistor and a second input terminal of the error amplifier module, and a second terminal of the second resistor is grounded.

[0009] In one possible implementation of the first aspect, the voltage-controlled module includes a first transistor, a second transistor, a third transistor, and a third resistor. The gate of the first transistor receives an enable signal. The drain of the first transistor is connected to the drain of the third transistor and the second terminal of the resistor module. The gate of the third transistor is connected to the gate of the second transistor, the drain of the second transistor, and the first terminal of the third resistor. The sources of the second transistor and the third transistor both receive a power supply voltage. The source of the first transistor and the second terminal of the third resistor are both grounded.

[0010] In one possible implementation of the first aspect, the first transistor is turned on when the enable signal is high and turned off when the enable signal is low.

[0011] In one possible implementation of the first aspect, the voltage-controlled voltage module includes a second transistor, a third transistor, a third resistor, and a fourth resistor. The first terminal of the fourth resistor is connected to the drain of the third transistor and the second terminal of the resistor module. The gate of the third transistor is connected to the gate of the second transistor, the drain of the second transistor, and the first terminal of the third resistor. The sources of the second transistor and the third transistor both receive a power supply voltage. The second terminals of the third resistor and the fourth resistor are both grounded.

[0012] Secondly, embodiments of this application provide a linear regulator, including the linear regulator circuit with enhanced low-to-medium frequency power supply rejection ratio as described in any one of the first aspects.

[0013] Thirdly, embodiments of this application provide a power supply device including the linear regulator described in any one of the second aspects.

[0014] Fourthly, embodiments of this application provide an electronic device including the power supply device described in any one of the third aspects.

[0015] The beneficial effects of the embodiments in this application compared with the prior art are: This application provides a linear voltage regulator circuit for enhancing the low-to-medium frequency power supply rejection ratio, including an error amplifier module, a power module, a resistor module, and a voltage-controlled voltage module. The first input terminal of the error amplifier module is used to receive a reference voltage. The second input terminal of the error amplifier module is connected to the output terminal of the resistor module. The output terminal of the error amplifier module is connected to the control terminal of the power module. The first terminal of the power module, the power supply terminal of the error amplifier module, and the control terminal of the voltage-controlled voltage module all receive the power supply voltage. The second terminal of the power module is connected to the first terminal of the resistor module, the first terminal of the output capacitor, and the first terminal of the load, respectively. The second terminal of the resistor module is connected to the first terminal of the voltage-controlled voltage module. The ground terminal of the error amplifier module, the second terminal of the voltage-controlled voltage module, the second terminal of the output capacitor, and the second terminal of the load are all grounded.

[0016] The error amplifier module receives the feedback voltage and outputs an error voltage based on the feedback voltage and the reference voltage. The power module turns on based on the error voltage and outputs a first current, which flows through the load to generate the output voltage. The voltage-controlled voltage module outputs a first voltage based on the power supply voltage. The resistor module outputs a feedback voltage based on the output voltage and the first voltage.

[0017] When the power supply voltage experiences a disturbance (i.e., noise), this disturbance affects the output voltage through two paths: First, the power supply voltage disturbance passes through the error amplification module and the power module, generating a disturbance in the output voltage, referred to as the first disturbance. Second, the power supply voltage disturbance passes through the voltage-controlled voltage module, generating another disturbance, which is then transmitted through two paths: one through the resistor module to the output voltage, and the other through the error amplification module and the power module, ultimately generating another disturbance in the output voltage, referred to as the second disturbance. The second disturbance is opposite in direction to the first disturbance. This application, by reasonably controlling the voltage coefficient of the voltage-controlled voltage module, can make the two disturbances cancel each other out, thereby effectively suppressing the influence of power supply voltage noise on the output voltage and achieving excellent mid-to-low frequency PSR performance. With appropriate parameter design, the mid-to-low frequency PSR performance can typically be improved by 10dB~20dB. Furthermore, the linear voltage regulator circuit provided in this application has a simple structure, effectively saving chip area and reducing chip power consumption, and has strong practical value.

[0018] In summary, the linear voltage regulator circuit provided in this application solves the problem that the traditional medium- and low-frequency PSR enhancement schemes are complex in structure, resulting in large chip area and power consumption.

[0019] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a structural diagram of a traditional LDO PSR enhancement scheme; Figure 2 This is a schematic diagram of a linear voltage regulator circuit with enhanced low-to-medium frequency power supply rejection ratio provided in an embodiment of this application; Figure 3 This is a circuit connection diagram of a linear voltage regulator circuit for enhancing low-frequency power supply rejection ratio provided in an embodiment of this application; Figure 4 This is a circuit connection diagram of a linear voltage regulator circuit with enhanced low-to-medium frequency power supply rejection ratio provided in another embodiment of this application. Figure 1 ; Figure 5 This is a circuit connection diagram of a linear voltage regulator circuit with enhanced low-to-medium frequency power supply rejection ratio provided in another embodiment of this application. Figure 2 .

[0022] In the diagram: 10, error amplification module; 20, power module; 30, resistor module; 40, voltage-controlled voltage module. Detailed Implementation

[0023] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0024] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0025] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0026] As used in the specification of this application and the appended claims, the term "if" may be construed contextually as "when" or "once" or "in response to determining" or "in response to detecting". Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be construed contextually to mean "once determined" or "in response to determining" or "once [the described condition or event] is detected" or "in response to detecting [the described condition or event]".

[0027] In addition, in the description of the specification of this application and the appended claims, the terms "first", "second", "third", etc. are only used for differential description and cannot be construed as indicating or implying relative importance.

[0028] Reference to "one embodiment" or "some embodiments" or the like described in the specification of this application means that a specific feature, structure, or characteristic described in connection with that embodiment is included in one or more embodiments of this application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized.

[0029] Figure 1 The structure of a conventional LDO PSR enhancement scheme is shown. Assume that there is a perturbation (i.e., noise) Δ on the power supply voltage VDD. , the error amplifier EA itself will have a certain suppression effect on the noise of the power supply voltage VDD. Therefore, the node A1 will also generate a perturbation on the noise of the power supply voltage VDD, and its value is V_A1 = Δ. , where m represents the suppression of the error amplifier EA on the noise of the power supply voltage VDD, and the range of m is generally 0 < m < 1. Since the device PM3 acts as a source follower here, the voltage gain from the gate to the source of PM3 is approximately 1. Therefore, the perturbation amplitude of the node A2 is equal to the perturbation amplitude of the node A1, approximately V_A2_1 = Δ. . For the power transistor PM0, the change in its gate voltage (i.e., node A2) is less than the change in its source voltage (i.e., the power supply voltage VDD), that is, the voltage difference between the gate and the source of the power transistor PM0 has changed. Therefore, the output voltage VOUT will also change, and it can also be stated that the PSR performance of this LDO becomes worse. It can also be seen from this that no matter what kind of noise the power supply voltage VDD brings, as long as the voltage difference between the gate and the source of the power transistor PM0 remains unchanged, the output voltage VOUT can be made relatively stable, that is, good PSR performance can be obtained.

[0030] Therefore, it was proposed Figure 1 The core idea of ​​the structure within the dashed box is to introduce a large resistance R. LPF and capacitor C LPF A low-pass filter is formed, so that the voltage at node A3 is outside the filter bandwidth and unaffected by power supply voltage VDD disturbances. In this case, for device PM1, its gate voltage (i.e., node A3) does not change with the power supply voltage VDD. The change in the source voltage of device PM1 is equal to the change in the power supply voltage VDD, i.e. =△ .in, This represents the voltage difference between the gate and source of device PM1. Therefore, the voltage expression for node A2 is: V_A2_2= =△ ,in, Indicates the transconductance of device PM1. This represents the transconductance of device PM3. As described above, V_A2_1 + V_A2_2 = Δ When, i.e., m=1- When the gate-source voltage difference of device PMO remains constant, the output voltage VOUT remains stable and is not affected by power supply voltage VDD noise, resulting in high PSR performance.

[0031] but, Figure 1 The structure in this design has two drawbacks: firstly, because of the resistance R... LPF and capacitor C LPF The value of cannot be infinitely large, so it can only filter out noise interference outside a certain frequency, and is powerless for lower frequency PSR performance. Secondly, this structure often requires a very large capacitor C. LPF (It usually reaches hundreds of pF or more), which wastes a lot of chip area and is not conducive to the application of small-volume sensors.

[0032] To address the aforementioned issues, this application provides a linear voltage regulator circuit for enhancing the mid-to-low frequency power supply rejection ratio (PSR), comprising an error amplification module, a power module, a resistor module, and a voltage-controlled voltage (VCC) module. When the power supply voltage experiences a disturbance, this disturbance affects the output voltage through two paths: firstly, the disturbance passes through the error amplification module and the power module, generating a disturbance on the output voltage, referred to as the first disturbance; secondly, the disturbance passes through the VCC module, generating another disturbance, which is then transmitted through two paths: one through the resistor module to the output voltage, and the other through the error amplification module and the power module, ultimately generating another disturbance on the output voltage, referred to as the second disturbance. The second disturbance is opposite in direction to the first disturbance. By appropriately controlling the voltage coefficient of the VCC module, this application can cancel out the two disturbances, effectively suppressing the influence of power supply voltage noise on the output voltage and achieving excellent mid-to-low frequency PSR performance. With appropriate parameter design, the mid-to-low frequency PSR performance can typically be improved by 10dB to 20dB. Furthermore, the linear voltage regulator circuit provided in this application has a simple structure, which can effectively save chip area and reduce chip power consumption, and has strong practical value.

[0033] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0034] Figure 2 A schematic diagram of a linear voltage regulator circuit with enhanced low-to-medium frequency power supply rejection ratio according to an embodiment of this application is shown. Figure 2 As shown, the linear voltage regulator circuit for enhancing the low-to-medium frequency power supply rejection ratio includes an error amplifier module 10, a power module 20, a resistor module 30, and a voltage-controlled voltage module 40. The first input terminal of the error amplifier module 10 is used to receive the reference voltage VREF. The second input terminal of the error amplifier module 10 is connected to the output terminal of the resistor module 30. The output terminal of the error amplifier module 10 is connected to the control terminal of the power module 20. The first terminal of the power module 20, the power supply terminal of the error amplifier module 10, and the control terminal of the voltage-controlled voltage module 40 all receive the power supply voltage VDD. The second terminal of the power module 20 is connected to the first terminal of the resistor module 30, the first terminal of the output capacitor COUT, and the first terminal of the load RLOAD, respectively. The second terminal of the resistor module 30 is connected to the first terminal of the voltage-controlled voltage module 40. The ground terminal of the error amplifier module 10, the second terminal of the voltage-controlled voltage module 40, the second terminal of the output capacitor COUT, and the second terminal of the load RLOAD are all grounded to GND.

[0035] Specifically, the error amplifier module 10 receives the feedback voltage VFB and outputs an error voltage based on VFB and the reference voltage VREF. The power module 20 is turned on based on the error voltage and outputs a first current, which flows through the load RLOAD to generate an output voltage VOUT. The voltage-controlled voltage module 40 outputs a first voltage based on the power supply voltage VDD. The resistor module 30 outputs the feedback voltage VFB based on the output voltage VOUT and the first voltage.

[0036] When the power supply voltage VDD is disturbed, the disturbance will affect the output voltage VOUT through two paths: Firstly, the disturbance in the power supply voltage VDD will pass through the error amplification module 10 and the power module 20, generating a disturbance in the output voltage VOUT, which is called the first disturbance Δ. On the other hand, disturbances in the power supply voltage VDD will generate a disturbance through the voltage-controlled voltage module 40. This disturbance will then be transmitted through two paths: one through the resistor module 30 to the output voltage VOUT, and the other through the error amplifier module 10 and the power module 20 to the output voltage VOUT. Ultimately, another disturbance will be generated on the output voltage VOUT, which is called the second disturbance Δ. Among them, the second disturbance △ With the first disturbance △ Conversely, by rationally controlling the voltage coefficient of the voltage-controlled voltage module 40, this application can cancel out the two disturbances, thereby effectively suppressing the influence of power supply voltage VDD noise on the output voltage VOUT and achieving excellent mid-to-low frequency PSR performance. With appropriate parameter design, the mid-to-low frequency PSR performance can typically be improved by 10dB~20dB. Furthermore, the linear voltage regulator circuit provided in this application has a simple structure, effectively saving chip area and reducing chip power consumption, and has strong practical value.

[0037] In summary, the linear voltage regulator circuit provided in this application solves the problem that the traditional medium- and low-frequency PSR enhancement schemes are complex in structure, resulting in large chip area and power consumption.

[0038] In one embodiment of this application, such as Figure 3 As shown, the error amplification module 10 includes an error amplifier EA. The first input terminal of the error amplifier EA receives the reference voltage VREF. The second input terminal of the error amplifier EA is connected to the output terminal of the resistor module 30. The output terminal of the error amplifier EA is connected to the control terminal of the power module 20. The power supply terminal of the error amplifier EA receives the power supply voltage VDD, and the ground terminal of the error amplifier EA is grounded to GND. In this embodiment, the first input terminal of the error amplifier EA is a non-inverting input terminal, and the second input terminal is an inverting input terminal. Specifically, the error amplifier EA outputs an error voltage based on the feedback voltage VFB and the reference voltage VREF.

[0039] As shown in Figure 3 , the power module 20 includes a power transistor PM0. The gate of the power transistor PM0 is connected to the output terminal of the error amplification module 10. The source of the power transistor PM0 receives the power supply voltage VDD. The drain of the power transistor PM0 is respectively connected to the first terminal of the resistor module 30, the first terminal of the output capacitor COUT, and the first terminal of the load RLOAD. Specifically, the power transistor PM0 conducts according to the error voltage and outputs a first current. The first current flows through the load RLOAD to generate the output voltage VOUT.

[0040] As shown in Figure 3 , the resistor module 30 includes a first resistor R1 and a second resistor R2. The first terminal of the first resistor R1 is respectively connected to the second terminal of the power module 20, the first terminal of the output capacitor COUT, and the first terminal of the load RLOAD. The second terminal of the first resistor R1 is respectively connected to the first terminal of the second resistor R2 and the second input terminal of the error amplification module 10. The second terminal of the second resistor R2 is grounded to GND. Specifically, the first resistor R1 and the second resistor R2 form a voltage dividing network to output a feedback voltage according to the output voltage VOUT and the first voltage output by the voltage-controlled voltage module 40.

[0041] The core of this application is to introduce a voltage-controlled voltage module 40 between the second resistor R2 and the ground GND. As shown in Figure 3 , the function of the voltage-controlled voltage module 40 is to generate a voltage (i.e., the node B1 in , that is, the first voltage) that changes in the same direction as the noise △ of the power supply voltage VDD and has a very small amplitude. Its expression is V_B1 = N * △ Figure 3 , where the range of N is 0 < N < 1. Also, because the feedback voltage VFB (i.e., the node B2 in ) and the node B1 are in a voltage dividing relationship, the voltages of the node B1 and the node B2 change in the same direction, V_B2 = K * V_B1 = K * N * △ Figure 3 , where the value of K can be adjusted through circuit parameters. Because the feedback voltage VFB (i.e., the node B2 in ) is the inverting input terminal of the entire circuit, the expression from the feedback voltage VFB to the output voltage VOUT is VOUT = -VFB * Av, where Av is the loop gain of the entire circuit. The negative sign indicates the opposite direction of change. In a three-stage or higher-order linear voltage regulation circuit system, the value of Av is very large, at least above 60 dB. To sum up, when the power supply voltage VDD introduces noise △ Figure 3 , the change in the output voltage VOUT mainly consists of two parts. One part is the change in the output voltage VOUT caused by the change in the voltage of the node B1 due to resistor voltage division, and its value is VOUT_1 = M * K * N * △ , where M = ​ The other part is caused by the feedback voltage VFB at node B2 being transmitted to the output voltage VOUT through the loop, and its value is VOUT_2 = -VFB*Av = -Av*K*N*△ These two effects are ultimately added together at the output voltage VOUT, so the total change introduced into the output voltage VOUT through the voltage-controlled voltage module 40 of this application is Δ. =VOUT_1+VOUT_2=M*K*N*△ +(-Av*K*N*△ =K*N*△ *(M-Av), because the value of M is generally small, usually between 1 and 10, while the value of Av is generally large (at least 1000 or more), so M in the expression can be ignored, hence △ -Av*K*N*△ As analyzed above, since the error amplifier EA itself has a certain suppression effect on the noise of the power supply voltage VDD, the noise Δ on the power supply voltage VDD is... It will be transferred to the output voltage VOUT at a certain multiple Z, which can be expressed as △ Z*△ , △ +△ =-Av*K*N*△ +Z*△ =△ *(Z-Av*K*N), where parameters K and N are variables generated by the voltage-controlled voltage module 40 introduced in this application, and their values ​​can be flexibly changed according to the specific design. Therefore, as long as the values ​​of K and N are designed so that Z-Av*K*N=0, the noise of the power supply voltage VDD can be canceled at the output voltage VOUT, so that the output voltage VOUT will not be disturbed and change, thus obtaining good PSR performance.

[0042] In one embodiment of this application, such as Figure 4As shown, the voltage-controlled voltage module 40 includes a first transistor M1, a second transistor M2, a third transistor M3, and a third resistor R3. The gate of the first transistor M1 receives an enable signal EN. The drain of the first transistor M1 is connected to the drain of the third transistor M3 and the second terminal of the resistor module 30. The gate of the third transistor M3 is connected to the gate of the second transistor M2, the drain of the second transistor M2, and the first terminal of the third resistor R3. The sources of the second transistor M2 and the third transistor M3 both receive the power supply voltage VDD. The source of the first transistor M1 and the second terminal of the third resistor R3 are both grounded to GND. When the enable signal EN is high (e.g., equal to the power supply voltage VDD), the first transistor M1 is turned on; when the enable signal EN is low (e.g., equal to ground GND), the first transistor M1 is turned off.

[0043] Specifically, the voltage-controlled voltage module 40 is the PSR enhancement circuit, and the current flowing through the second transistor M2 is expressed as follows: ,in, This is the gate-source voltage difference of the second transistor M2. Because the second transistor M2 and the third transistor M3 have the same dimensions and act as a current mirror, the current flowing into node B1 is equal to... Therefore, the voltage at node B1, V_B1 = Where Rs is the on-resistance of the first transistor M1, expressed as Rs ,in, It is the aspect ratio of the first transistor M1. It is the gate-source voltage difference of the first transistor M1. It is the threshold voltage of the first transistor M1. Represents the surface mobility of an n-channel semiconductor device. This represents the gate oxide capacitance per unit area of ​​the semiconductor. As can be seen from the formula, V_B1 is a voltage controlled by the power supply voltage VDD; that is, a changing power supply voltage VDD will generate a voltage V_B1 (i.e., the first voltage) that changes in the same direction. Its expression is: .make =K*N*△ Substituting this into the formula △ derived earlier +△ =-Av*K*N*△ +Z*△ =△ From *(Z-Av*K*N), we can obtain Z*△ -Av* When VDD = 0, the noise of the power supply voltage VDD is exactly canceled out, so it can be adjusted... , The optimal PSR performance is obtained by considering the values ​​of the first transistor M1 and the dimensions of the second transistor M2.

[0044] In summary, this application generates a disturbance voltage controlled by the power supply voltage VDD noise using a simple current and a very small resistance. Then, by controlling the voltage coefficient of the voltage-controlled voltage module 40, the influence of the power supply voltage VDD noise on the output voltage VOUT is offset, thereby achieving excellent mid-to-low frequency PSR performance.

[0045] It should be noted that the first transistor M1 is a component inherent in the linear voltage regulator circuit. By reusing this component, the circuit area is further reduced. Since the first transistor M1 acts as a resistor when it is turned on, it can be replaced by a resistor. Figure 5 The structure shown is as follows: Figure 5 As shown, the voltage-controlled voltage module 40 includes a second transistor M2, a third transistor M3, a third resistor R3, and a fourth resistor R4. The first terminal of the fourth resistor R4 is connected to the drain of the third transistor M3 and the second terminal of the resistor module 30. The gate of the third transistor M3 is connected to the gate of the second transistor M2, the drain of the second transistor M2, and the first terminal of the third resistor R3. The sources of both the second transistor M2 and the third transistor M3 receive the power supply voltage VDD. The second terminals of the third resistor R3 and the fourth resistor R4 are both grounded to GND. It should be noted that the second transistor M2 and the third resistor R3 are used to generate a bias current that can vary with the power supply voltage VDD. This application does not limit this to a single function; any device with equivalent functionality is applicable.

[0046] This application, through appropriate parameter design, can improve the performance of low-to-medium frequency PSR by 10dB to 20dB, while requiring only a small chip area and power consumption.

[0047] This application also provides a linear regulator, including the linear regulator circuit described above that enhances the low-to-medium frequency power supply rejection ratio. Since the linear regulator provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated upon further here.

[0048] This application also provides a power supply device, including the linear voltage regulator described above. Since the power supply device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0049] This application also provides an electronic device, including the power supply device described above. Since this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0050] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0051] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A linear voltage regulator circuit with enhanced low-to-medium frequency power supply rejection ratio, characterized in that, The system includes an error amplifier module, a power module, a resistor module, and a voltage-controlled voltage module. The first input terminal of the error amplifier module is used to receive a reference voltage. The second input terminal of the error amplifier module is connected to the output terminal of the resistor module. The output terminal of the error amplifier module is connected to the control terminal of the power module. The first terminal of the power module, the power supply terminal of the error amplifier module, and the control terminal of the voltage-controlled voltage module all receive power supply voltage. The second terminal of the power module is connected to the first terminal of the resistor module, the first terminal of the output capacitor, and the first terminal of the load, respectively. The second terminal of the resistor module is connected to the first terminal of the voltage-controlled voltage module. The ground terminal of the error amplifier module, the second terminal of the voltage-controlled voltage module, the second terminal of the output capacitor, and the second terminal of the load are all grounded. The error amplification module is used to receive feedback voltage and output error voltage based on the feedback voltage and the reference voltage; the power module is used to turn on according to the error voltage and output a first current, the first current flowing through the load to generate an output voltage; the voltage-controlled voltage module is used to output a first voltage based on the power supply voltage; the resistor module is used to output a feedback voltage based on the output voltage and the first voltage.

2. The linear voltage regulator circuit with enhanced low-to-medium frequency power supply rejection ratio according to claim 1, characterized in that, The error amplification module includes an error amplifier. The first input terminal of the error amplifier is used to receive a reference voltage. The second input terminal of the error amplifier is connected to the output terminal of the resistor module. The output terminal of the error amplifier is connected to the control terminal of the power module. The power supply terminal of the error amplifier receives the power supply voltage. The ground terminal of the error amplifier is grounded.

3. The linear voltage regulator circuit with enhanced low-to-medium frequency power supply rejection ratio according to claim 1 or 2, characterized in that, The power module includes a power transistor, the gate of which is connected to the output terminal of the error amplifier module, the source of which receives the power supply voltage, and the drain of which is connected to the first terminal of the resistor module, the first terminal of the output capacitor, and the first terminal of the load.

4. The linear voltage regulator circuit with enhanced low-to-medium frequency power supply rejection ratio according to claim 1 or 2, characterized in that, The resistor module includes a first resistor and a second resistor. The first end of the first resistor is connected to the second end of the power module, the first end of the output capacitor, and the first end of the load, respectively. The second end of the first resistor is connected to the first end of the second resistor and the second input end of the error amplifier module, respectively. The second end of the second resistor is grounded.

5. The linear voltage regulator circuit with enhanced low-to-medium frequency power supply rejection ratio according to claim 1 or 2, characterized in that, The voltage-controlled module includes a first transistor, a second transistor, a third transistor, and a third resistor. The gate of the first transistor receives an enable signal. The drain of the first transistor is connected to the drain of the third transistor and the second terminal of the resistor module. The gate of the third transistor is connected to the gate of the second transistor, the drain of the second transistor, and the first terminal of the third resistor. The sources of the second transistor and the third transistor both receive a power supply voltage. The source of the first transistor and the second terminal of the third resistor are both grounded.

6. The linear voltage regulator circuit with enhanced low-to-medium frequency power supply rejection ratio according to claim 5, characterized in that, When the enable signal is high, the first transistor is turned on; when the enable signal is low, the first transistor is turned off.

7. The linear voltage regulator circuit with enhanced low-to-medium frequency power supply rejection ratio according to claim 1 or 2, characterized in that, The voltage-controlled module includes a second transistor, a third transistor, a third resistor, and a fourth resistor. The first terminal of the fourth resistor is connected to the drain of the third transistor and the second terminal of the resistor module. The gate of the third transistor is connected to the gate of the second transistor, the drain of the second transistor, and the first terminal of the third resistor. The sources of the second transistor and the third transistor both receive power supply voltage. The second terminals of the third resistor and the fourth resistor are both grounded.

8. A linear voltage regulator, characterized in that, The linear voltage regulator circuit with enhanced low-to-medium frequency power supply rejection ratio as described in any one of claims 1-7.

9. A power supply device, characterized in that, Includes the linear regulator as described in claim 8.

10. An electronic device, characterized in that, Includes the power supply device as described in claim 9.

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