Overcurrent protection circuit for txldo and radio frequency transceiver
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING TSINGTENG MICROSYSTEM CO LTD
- Filing Date
- 2026-05-06
- Publication Date
- 2026-08-07
AI Technical Summary
镜像电流检测和比较器响应需要一定时间，在出现快速负载跳变的情况下，电路的过流保护响应较慢
本公开实施例中，电流传感模块能够通过镜像复制生成与输出电流精确对应的目标镜像电流，然后通过比较与放大模块将目标镜像电流与参考电流进行比较，获得比较信号，动态钳位反馈模块能够根据比较信号输出TXLDO的动态介入电流，从而实现对TXLDO输出电流过流状态的持续、即时调节，进而实现快速的过流响应，提高了过流保护的响应速度。此外，通过动态钳位反馈模块的实时动态介入，能够减少输出电流的剧烈震荡，提供平滑的限流特性，在全工艺角、电压、温度变化下，精确地设定和限制输出电流，并提升系统稳定性。
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Figure CN122526367A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit design technology, for example to an overcurrent protection circuit and radio frequency transceiver for a TXLDO. Background Technology
[0002] In RF transmitter circuits, TXLDOs (Transmitter Low-Dropout Regulators) provide stable voltages for core components such as power amplifiers. For TXLDOs with a wide output voltage range (e.g., 2.1V to 5.7V), traditional current mirror protection circuits face an additional significant challenge: the large variation in the power transistor drain voltage (i.e., the TXLDO output voltage) greatly affects the mirror accuracy through channel length modulation, causing the current limiting threshold to drift with changes in output voltage, making accurate protection impossible. Furthermore, to achieve efficiency under light loads, TXLDOs need to operate within a wide load current range of 0-1A. Traditional fixed-ratio current mirrors produce very small mirror currents when detecting small currents, which complicates the design of subsequent comparison circuits. Using excessively large sensing resistor values introduces additional errors and noise, while using amplifiers to detect weak signals faces challenges in gain, bandwidth, and stability, making it difficult to achieve fast and accurate overcurrent detection.
[0003] In related technologies, the TXLDO overcurrent protection scheme uses a mirror transistor proportional to the power transistor to replicate a portion of the current, and overcurrent protection is achieved by detecting this mirror current.
[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art: The mirror current detection and comparator response take a certain amount of time, resulting in a slow overcurrent protection response in the event of rapid load changes.
[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.
[0007] This disclosure provides an overcurrent protection circuit and RF transceiver for a TXLDO to improve the response speed of overcurrent protection.
[0008] In some embodiments, the overcurrent protection circuit for the TXLDO includes: a current sensing module configured to mirror the output current of the TXLDO and output a target mirror current; a comparison and amplification module configured to compare the target mirror current with a reference current and output a comparison signal; and a dynamic clamping feedback module configured to output a dynamic intervention current of the TXLDO based on the comparison signal to limit the output current of the TXLDO to near a threshold current.
[0009] Optionally, the TXLDO includes: an error amplifier, a first PMOS transistor, a first resistor, and a second resistor; the negative input terminal of the error amplifier is connected to a reference voltage, the positive input terminal is connected to the first end of the second resistor, and the output terminal is connected to the gate of the first PMOS transistor; the source of the first PMOS transistor is connected to a power supply, and the drain is connected to the first end of the first resistor; the second end of the first resistor is connected to the first end of the second resistor; the second end of the second resistor is grounded; wherein, the drain of the first PMOS transistor is the output terminal of the TXLDO, generating an output current and an output voltage; both the drain and gate of the first PMOS transistor are connected to a current sensing module; the gate of the first PMOS transistor is also connected to a dynamic clamping feedback module.
[0010] Optionally, the current sensing module includes: a mirror unit configured to mirror the output current of the TXLDO and output an initial mirror current; a bias current compensation unit configured to provide bias current compensation to the initial mirror current and output a compensated mirror current; and a current output unit configured to subtract the bias current from the compensated mirror current and output a target mirror current.
[0011] Optionally, the mirror unit includes: a second PMOS transistor, an operational amplifier, a first NMOS transistor, and a second NMOS transistor; the source of the second PMOS transistor is connected to a power supply, its gate is connected to the gate of the first PMOS transistor, and its drain is connected to the drain of the first NMOS transistor and the positive input terminal of the operational amplifier, respectively; the negative input terminal of the operational amplifier is connected to the drain of the first PMOS transistor, and its output terminal is connected to the gate of the second NMOS transistor; the gate of the first NMOS transistor is connected to a first bias voltage, and its source is connected to the drain of the second NMOS transistor; the source of the second NMOS transistor is grounded; wherein an initial mirror current is generated at the drain of the second PMOS transistor.
[0012] Optionally, the bias current compensation unit includes: a third PMOS transistor; the source of the third PMOS transistor is connected to the power supply, the gate is connected to the second bias voltage, and the drain is connected to the drain of the first NMOS transistor; wherein, a bias current is generated at the drain of the third PMOS transistor, and the bias current and the initial mirror current flow together to the drain of the first NMOS transistor to form a compensation mirror current.
[0013] Optionally, the current output unit includes: a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the source of the fourth PMOS transistor is connected to the power supply, the gate is connected to the second bias voltage, and the drain is connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor is connected to the first bias voltage, and the source is connected to the drain of the fourth NMOS transistor; the gate of the fourth NMOS transistor is connected to the output terminal of the operational amplifier, and the source is grounded; wherein, an output terminal of the current output unit is provided at the connection between the drain of the fourth PMOS transistor and the drain of the third NMOS transistor to output the target mirror current.
[0014] Optionally, the comparison and amplification module includes: a fifth PMOS transistor, a sixth PMOS transistor, a third resistor, and a transconductance amplifier; the source of the fifth PMOS transistor is connected to the power supply, and its gate is connected to the gate of the sixth PMOS transistor, the drain of the fifth PMOS transistor, and the output terminal of the current output unit; the source of the sixth PMOS transistor is connected to the power supply, and its drain is connected to the first terminal of the third resistor and the positive input terminal of the transconductance amplifier; the second terminal of the third resistor is grounded; the negative input terminal of the transconductance amplifier is connected to the reference voltage and receives the reference current; wherein, a comparison signal is generated at the output terminal of the transconductance amplifier.
[0015] Optionally, the dynamic clamping feedback module includes: a fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to the output terminal of the transconductance amplifier, the source is grounded, and the drain is connected to the gate of the first PMOS transistor; wherein, a dynamic intervention current is generated at the drain of the fifth NMOS transistor.
[0016] Optionally, the width-to-length ratio of the second PMOS transistor is proportional to the width-to-length ratio of the first PMOS transistor by 1:K; and / or, the width-to-length ratio of the second NMOS transistor is proportional to the width-to-length ratio of the fourth NMOS transistor by 1:1; and / or, the reference current at the negative input terminal of the transconductance amplifier is proportional to the threshold current by 1:K.
[0017] In some embodiments, the radio frequency transceiver includes an overcurrent protection circuit for a TXLDO as described above.
[0018] The overcurrent protection circuit and RF transceiver for TXLDO provided in this disclosure can achieve the following technical effects: In this embodiment, the current sensing module generates a target mirror current that precisely corresponds to the output current through mirror replication. Then, the comparison and amplification module compares the target mirror current with a reference current to obtain a comparison signal. The dynamic clamping feedback module outputs the dynamic intervention current of the TXLDO based on the comparison signal, thereby achieving continuous and real-time adjustment of the overcurrent state of the TXLDO output current. This results in a rapid overcurrent response and improves the response speed of overcurrent protection. Furthermore, the real-time dynamic intervention of the dynamic clamping feedback module reduces severe oscillations in the output current, provides smooth current limiting characteristics, and accurately sets and limits the output current under various process angles, voltage, and temperature changes, thus improving system stability.
[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description
[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of an overcurrent protection circuit for a TXLDO provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of another overcurrent protection circuit for a TXLDO provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of another overcurrent protection circuit for a TXLDO provided in an embodiment of this disclosure; Figure 4 This is a circuit diagram of a current sensing module in an overcurrent protection circuit for a TXLDO provided in an embodiment of this disclosure; Figure 5 This is a circuit diagram of a comparison and amplification module in an overcurrent protection circuit for a TXLDO provided in an embodiment of this disclosure; Figure 6 This is a circuit diagram of an overcurrent protection circuit for a TXLDO provided in an embodiment of this disclosure.
[0021] Reference numerals: 100, Current sensing module; 101, Mirror unit; 102, Bias current compensation unit; 103, Current output unit; 200, Comparison and amplification module; 300, Dynamic clamping feedback module; 400, TXLDO; EA, Error amplifier; PM1, First PMOS transistor; R1, First resistor; R2, Second resistor; VREF, Reference voltage; VDD, Power supply; PM2, Second PMOS transistor; A1, Operational amplifier; NM1, First NMOS transistor; NM2, Second NMOS transistor; vb1, First bias voltage; PM3, Third PMOS transistor; vb2, Second bias voltage; PM4, Fourth PMOS transistor; NM3, Third NMOS transistor; NM4, Fourth NMOS transistor; PM5, Fifth PMOS transistor; PM6, Sixth PMOS transistor; R3, Third resistor; OTA, Transconductance amplifier; V_ref, Reference voltage; NM5, Fifth NMOS transistor. Detailed Implementation
[0022] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.
[0023] The terms "first," "second," etc., used in the technical solutions described in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.
[0024] Unless otherwise stated, the term "multiple" means two or more.
[0025] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.
[0026] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.
[0027] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.
[0028] Combination Figure 1 As shown, this disclosure provides an overcurrent protection circuit for a TXLDO, including a current sensing module 100, a comparison and amplification module 200, and a dynamic clamping feedback module 300. The current sensing module 100 is configured to mirror the output current of the TXLDO 400 and output a target mirror current. The comparison and amplification module 200 is configured to compare the target mirror current with a reference current and output a comparison signal. The dynamic clamping feedback module 300 is configured to output a dynamic intervention current of the TXLDO 400 based on the comparison signal, thereby limiting the output current of the TXLDO 400 to near a threshold current.
[0029] In this embodiment, the current sensing module 100 generates a target mirror current that precisely corresponds to the output current through mirror replication. Then, the comparison and amplification module 200 compares the target mirror current with a reference current to obtain a comparison signal. The dynamic clamping feedback module 300 outputs a dynamic intervention current for the TXLDO400 based on the comparison signal, thereby achieving continuous and real-time adjustment of the overcurrent state of the TXLDO400 output current. This results in a rapid overcurrent response and improves the response speed of overcurrent protection. Furthermore, the real-time dynamic intervention of the dynamic clamping feedback module 300 reduces severe oscillations in the output current, providing smooth current limiting characteristics. It accurately sets and limits the output current under various process angles, voltage, and temperature changes, improving system stability.
[0030] Optionally, combined Figure 2 As shown, the TXLDO400 includes: an error amplifier EA, a first PMOS transistor PM1, a first resistor R1, and a second resistor R2. The negative input terminal of the error amplifier EA is connected to the reference voltage VREF, the positive input terminal is connected to the first end of the second resistor R2, and the output terminal is connected to the gate of the first PMOS transistor PM1. The source of the first PMOS transistor PM1 is connected to the power supply VDD, and the drain is connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the first end of the second resistor R2. The second end of the second resistor R2 is grounded. The drain of the first PMOS transistor PM1 is the output terminal of the TXLDO400, generating the output current and output voltage. Both the drain and gate of the first PMOS transistor PM1 are connected to the current sensing module 100. The gate of the first PMOS transistor PM1 is also connected to the dynamic clamping feedback module 300.
[0031] In this embodiment, the first resistor R1 and the second resistor R2 form a feedback resistor network. The error amplifier EA can adjust the gate voltage of the first PMOS transistor PM1 by comparing the reference voltage VREF with the feedback voltage of the feedback resistor network, thereby stabilizing the output current and output voltage. The drain of the first PMOS transistor PM1 is the output node of the TXLDO400. Connecting this node to the current sensing module 100 allows the current sensing module 100 to directly sense the voltage and current operating status of the power stage. The gate of the first PMOS transistor PM1 is the output node of the error amplifier EA. Providing this node to the current sensing module 100 helps the current sensing module 100 to more accurately track the operating region of the power transistor and improve the mirror accuracy. The gate of the first PMOS transistor PM1 directly determines its on-resistance and output current capability. Connecting the dynamic clamping feedback module 300 to this node can directly and quickly affect the core control signal of the power stage of the TXLDO400, thereby intervening in the main control loop of the TXLDO400.
[0032] Optionally, combined Figure 3 As shown, the current sensing module 100 includes: a mirror unit 101 configured to mirror the output current of the TXLDO400 and output an initial mirror current; a bias current compensation unit 102 configured to provide bias current compensation to the initial mirror current and output a compensated mirror current; and a current output unit 103 configured to subtract the bias current from the compensated mirror current and output a target mirror current.
[0033] In this embodiment, the mirror unit 101 can eliminate mirroring errors caused by large variations in output voltage, achieving high-precision current replication. The bias current compensation unit 102 can provide bias current compensation when the initial mirror current is small, ensuring that the compensated mirror current is large enough, expanding the dynamic range of current detection, and enabling small current detection. The current output unit 103 can eliminate the introduced bias current, ensuring the accuracy of subsequent current detection. Therefore, the current sensing module 100 can solve the defects in wide output voltage range and small current detection, achieving high-precision current sensing under all operating conditions (wide voltage, wide current).
[0034] Optionally, combined Figure 4 and Figure 6As shown, the mirror unit 101 includes: a second PMOS transistor PM2, an operational amplifier A1, a first NMOS transistor NM1, and a second NMOS transistor NM2; the source of the second PMOS transistor PM2 is connected to the power supply VDD, the gate is connected to the gate of the first PMOS transistor PM1, and the drain is connected to the drain of the first NMOS transistor NM1 and the positive input terminal of the operational amplifier A1; the negative input terminal of the operational amplifier A1 is connected to the drain of the first PMOS transistor PM1, and the output terminal is connected to the gate of the second NMOS transistor NM2; the gate of the first NMOS transistor NM1 is connected to the first bias voltage vb1, and the source is connected to the drain of the second NMOS transistor NM2; the source of the second NMOS transistor NM2 is grounded; wherein, an initial mirror current is generated at the drain of the second PMOS transistor PM2.
[0035] In this embodiment, the virtual short characteristic of operational amplifier A1 forces its positive and negative input voltages to be equal, that is, forces the drain voltage of the second PMOS transistor PM2 to strictly track and equal the drain voltage of the first PMOS transistor PM1 (i.e., the output voltage of TXLDO400). Since the gate voltages of the first PMOS transistor PM1 and the second PMOS transistor PM2 are the same, under the condition that the drain voltages are forced to be equal, the channel currents of the two transistors will be strictly proportional, thereby eliminating the current mirror error (channel length modulation effect) caused by the output voltage change, and realizing high-precision current replication sampling that does not change with the output voltage. The drain of the first NMOS transistor NM1 is connected to the drain of the second PMOS transistor PM2, forming a high-impedance node, which can effectively isolate the sensing branch from the subsequent circuits and reduce the interference and errors caused by the load effects of the subsequent circuits (such as bias current injection and voltage fluctuations) to the precision sensing node.
[0036] Optionally, the width-to-length ratio of the second PMOS transistor PM2 is proportional to the width-to-length ratio of the first PMOS transistor PM1, which is 1:K. This ensures that the drain current I2 of the second PMOS transistor PM2 is strictly proportional to the drain current I1 of the first PMOS transistor PM1, i.e., I2≈I1 / K.
[0037] Optionally, combined Figure 4 and Figure 6 As shown, the bias current compensation unit 102 includes: a third PMOS transistor PM3; the source of the third PMOS transistor PM3 is connected to the power supply VDD, the gate is connected to the second bias voltage vb2, and the drain is connected to the drain of the first NMOS transistor NM1; wherein, a bias current is generated at the drain of the third PMOS transistor PM3, and the bias current and the initial mirror current flow together to the drain of the first NMOS transistor NM1 to form a compensation mirror current.
[0038] In this embodiment, when the TXLDO400 operates under light load or low current, the initial mirror current I2 generated by the second PMOS transistor PM2 is very weak. If this tiny current is processed directly, the subsequent operational amplifier A1 and circuitry may operate outside the linear region due to the excessively small signal amplitude, leading to decreased gain, slow response, or even increased error. By adding a constant bias current Ib through the third PMOS transistor PM3, even under extreme light load conditions where the initial mirror current I2 is close to zero, the compensation mirror current I3 can be maintained at a sufficiently large minimum value, I3 = I2 + Ib. This ensures that the signal amplitude of the sensing branch is not too small across the entire load range, providing a stable operating point for the subsequent signal processing circuitry.
[0039] Optionally, combined Figure 4 and Figure 6 As shown, the current output unit 103 includes: a fourth PMOS transistor PM4, a third NMOS transistor NM3, and a fourth NMOS transistor NM4; the source of the fourth PMOS transistor PM4 is connected to the power supply VDD, the gate is connected to the second bias voltage vb2, and the drain is connected to the drain of the third NMOS transistor NM3; the gate of the third NMOS transistor NM3 is connected to the first bias voltage vb1, and the source is connected to the drain of the fourth NMOS transistor NM4; the gate of the fourth NMOS transistor NM4 is connected to the output terminal of the operational amplifier A1, and the source is grounded; wherein, the output terminal of the current output unit 103 is provided at the connection between the drain of the fourth PMOS transistor PM4 and the drain of the third NMOS transistor NM3 to output the target mirror current.
[0040] In this embodiment, the fourth PMOS transistor PM4 and the third PMOS transistor PM3, the third NMOS transistor NM3 and the first NMOS transistor NM1, and the fourth NMOS transistor NM4 and the second NMOS transistor NM2 all have the same gate connection, forming a symmetrical mirror structure. The third NMOS transistor NM3 and the fourth NMOS transistor NM4 can accurately replicate the compensation mirror current I3, forming current I3', while the fourth PMOS transistor PM4 can generate the same bias current Ib' as the third PMOS transistor PM3. By setting the output terminal of the current output unit 103 at the connection between the drain of the fourth PMOS transistor PM4 and the drain of the third NMOS transistor NM3, the current value I4 of the target mirror current output at the output terminal can be made equal to the current value of the compensation mirror current minus the current value of the bias current, I4=I3'-Ib', realizing the current subtraction operation. From the compensation mirror current after bias compensation, the pure target mirror current that is strictly proportional to the output current of TXLDO400 is restored, I4=I2≈I1 / K, providing a high-precision and high-consistency input signal for overcurrent protection decision.
[0041] Optionally, the width-to-length ratio of the second NMOS transistor NM2 is proportional to the width-to-length ratio of the fourth NMOS transistor NM4 at a ratio of 1:1.
[0042] Optionally, combined Figure 5 and Figure 6 As shown, the comparison and amplification module 200 includes: a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a third resistor R3, and a transconductance amplifier OTA; the source of the fifth PMOS transistor PM5 is connected to the power supply VDD, and its gate is connected to the gate of the sixth PMOS transistor PM6, the drain of the fifth PMOS transistor PM5, and the output terminal of the current output unit 103; the source of the sixth PMOS transistor PM6 is connected to the power supply VDD, and its drain is connected to the first terminal of the third resistor R3 and the positive input terminal of the transconductance amplifier OTA; the second terminal of the third resistor R3 is grounded; the negative input terminal of the transconductance amplifier OTA is connected to the reference voltage V_ref and receives the reference current; wherein, a comparison signal is generated at the output terminal of the transconductance amplifier OTA.
[0043] In this embodiment, the sixth PMOS transistor PM6 and the fifth PMOS transistor PM5 form a current mirror, which can copy the target mirror current at the output terminal of the current output unit 103 to the drain of the sixth PMOS transistor PM6. The drain current I5 of the sixth PMOS transistor PM6 flows through the third resistor R3 and forms a voltage signal at the positive input terminal of the transconductance amplifier OTA, where I5=I4=I2. The transconductance amplifier OTA has the characteristics of high gain and high bandwidth. The negative input terminal of the transconductance amplifier OTA is connected to the reference voltage V_ref and receives the reference current Ir, thereby realizing the comparison between the target mirror current and the reference current, and thus determining whether the output current of TXLDO400 exceeds the safety threshold. When the target mirror current is greater than the reference current, it indicates that the output current of TXLDO400 has exceeded the threshold, and the transconductance amplifier OTA will quickly flip from high level to low level, generating an overcurrent flag signal.
[0044] Optionally, the reference current at the negative input of the transconductance amplifier OTA is proportional to the threshold current at a ratio of 1:K.
[0045] Optionally, combined Figure 6 As shown, the dynamic clamping feedback module 300 includes: a fifth NMOS transistor NM5; the gate of the fifth NMOS transistor NM5 is connected to the output terminal of the transconductance amplifier OTA, the source is grounded, and the drain is connected to the gate of the first PMOS transistor PM1; wherein, a dynamic intervention current is generated at the drain of the fifth NMOS transistor NM5.
[0046] In this embodiment, the conduction state of the fifth NMOS transistor NM5 is controlled by the comparison signal output by the transconductance amplifier OTA. The dynamic intervention current generated at the drain can directly act on the gate of the first PMOS transistor PM1, constructing a fast, direct, and analog continuous control path. During normal operation, the transconductance amplifier OTA outputs a high level, and the fifth NMOS transistor NM5 is turned off, without affecting the TXLDO400 main loop. When an overcurrent occurs, the transconductance amplifier OTA outputs a low level, and the fifth NMOS transistor NM5 is turned on, pulling the gate voltage of the first PMOS transistor PM1 to ground through the fifth NMOS transistor NM5. At this time, the gate-source voltage of the first PMOS transistor PM1 will increase, and its conduction capability will weaken, thereby reducing the output current of the TXLDO400 and clamping it near the threshold current. The fifth NMOS transistor NM5 can convert the comparison signal output by the transconductance amplifier OTA into a dynamic intervention current injected into the TXLDO400 main control loop (the gate of the first PMOS transistor PM1) in real time and continuously. The dynamic intervention current is proportional to the overcurrent level, forming a high-speed local negative feedback that rapidly pulls down the gate voltage of the first PMOS transistor PM1, thereby reducing the conduction level of PM1 and dynamically clamping the TXLDO400 output current near the threshold current. This dynamic clamping is an analog feedback, with a response speed much faster than traditional digital shutdown logic. It can seamlessly work in conjunction with the high-speed main loop of the TXLDO400 to achieve soft limiting of transient overcurrent and avoid severe voltage oscillations.
[0047] The overcurrent protection circuit for a TXLDO provided in this embodiment eliminates the impact of large-range output voltage variations on current mirror accuracy by forcibly balancing the drain voltage through negative feedback of operational amplifier A1, achieving high stability of the current limiting threshold within a preset voltage range. The introduction of a bias current compensation mechanism ensures that the current sensing module 100 always operates at its optimal state across the entire range from microamp-level light loads to milliamp-level heavy loads, solving the bottleneck of low-current detection and achieving wide-range, high-precision protection. The combination of transconductance amplifier OTA and dynamic clamping feedback module 300 provides a response time in the nanosecond range, effectively suppressing current spikes caused by rapid load changes in the TXLDO400 and matching its high-speed characteristics. The entire detection and protection process does not rely on the sensing resistor connected in series in the main path, thus avoiding additional voltage drops and power consumption and ensuring the overall efficiency of the TXLDO400. Dynamic clamping provides smooth current limiting characteristics, preventing voltage drops or restarts caused by protection actions, and improving system stability and reliability. The entire circuit is composed of standard CMOS devices, making it suitable for integration into a SoC.
[0048] This disclosure also provides an RF transceiver that includes the overcurrent protection circuit for a TXLDO as described above. Therefore, the RF transceiver possesses all the technical advantages of the overcurrent protection circuit, which will not be elaborated further here.
[0049] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the technical solutions described herein. As used in the technical solutions described herein, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used herein refers to any and all possible combinations of one or more of the associated listed elements. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.
Claims
1. An overcurrent protection circuit for a TXLDO, characterized in that, include: The current sensing module is configured to mirror the output current of the TXLDO and output the target mirror current. The comparison and amplification module is configured to compare the target mirror current with the reference current and output a comparison signal; The dynamic clamping feedback module is configured to output the dynamic intervention current of the TXLDO based on the comparison signal, so as to limit the output current of the TXLDO to near the threshold current.
2. The overcurrent protection circuit according to claim 1, characterized in that, The TXLDO includes: an error amplifier, a first PMOS transistor, a first resistor, and a second resistor; The negative input terminal of the error amplifier is connected to the reference voltage, the positive input terminal is connected to the first end of the second resistor, and the output terminal is connected to the gate of the first PMOS transistor; the source of the first PMOS transistor is connected to the power supply, and the drain is connected to the first end of the first resistor; the second end of the first resistor is connected to the first end of the second resistor; the second end of the second resistor is grounded. The drain of the first PMOS transistor is the output terminal of the TXLDO, generating output current and output voltage; both the drain and gate of the first PMOS transistor are connected to the current sensing module; the gate of the first PMOS transistor is also connected to the dynamic clamping feedback module.
3. The overcurrent protection circuit according to claim 2, characterized in that, The current sensing module includes: The mirror unit is configured to mirror the output current of the TXLDO and output the initial mirror current. The bias current compensation unit is configured to provide bias current compensation for the initial mirror current and output a compensated mirror current. The current output unit is configured to subtract the bias current from the compensated mirror current and output the target mirror current.
4. The overcurrent protection circuit according to claim 3, characterized in that, The mirror unit includes: a second PMOS transistor, an operational amplifier, a first NMOS transistor, and a second NMOS transistor; The source of the second PMOS transistor is connected to the power supply, its gate is connected to the gate of the first PMOS transistor, and its drain is connected to the drain of the first NMOS transistor and the positive input terminal of the operational amplifier. The negative input terminal of the operational amplifier is connected to the drain of the first PMOS transistor, and its output terminal is connected to the gate of the second NMOS transistor. The gate of the first NMOS transistor is connected to the first bias voltage, and its source is connected to the drain of the second NMOS transistor. The source of the second NMOS transistor is grounded. In this process, an initial mirror current is generated at the drain of the second PMOS transistor.
5. The overcurrent protection circuit according to claim 4, characterized in that, The bias current compensation unit includes: a third PMOS transistor; The source of the third PMOS transistor is connected to the power supply, the gate is connected to the second bias voltage, and the drain is connected to the drain of the first NMOS transistor. In this process, a bias current is generated at the drain of the third PMOS transistor. This bias current and the initial mirror current flow together to the drain of the first NMOS transistor, forming a compensation mirror current.
6. The overcurrent protection circuit according to claim 5, characterized in that, The current output unit includes: a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The source of the fourth PMOS transistor is connected to the power supply, the gate is connected to the second bias voltage, and the drain is connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor is connected to the first bias voltage, and the source is connected to the drain of the fourth NMOS transistor; the gate of the fourth NMOS transistor is connected to the output terminal of the operational amplifier, and the source is grounded. The output terminal of the current output unit is provided at the connection between the drain of the fourth PMOS transistor and the drain of the third NMOS transistor to output the target mirror current.
7. The overcurrent protection circuit according to claim 6, characterized in that, The comparison and amplification module includes: a fifth PMOS transistor, a sixth PMOS transistor, a third resistor, and a transconductance amplifier; The source of the fifth PMOS transistor is connected to the power supply, and its gate is connected to the gate of the sixth PMOS transistor, the drain of the fifth PMOS transistor, and the output terminal of the current output unit, respectively. The source of the sixth PMOS transistor is connected to the power supply, and its drain is connected to the first terminal of the third resistor and the positive input terminal of the transconductance amplifier, respectively. The second terminal of the third resistor is grounded. The negative input terminal of the transconductance amplifier is connected to the reference voltage and receives the reference current. A comparison signal is generated at the output of the transconductance amplifier.
8. The overcurrent protection circuit according to claim 7, characterized in that, The dynamic clamping feedback module includes: a fifth NMOS transistor; The gate of the fifth NMOS transistor is connected to the output of the transconductance amplifier, its source is grounded, and its drain is connected to the gate of the first PMOS transistor. In this process, a dynamic intervention current is generated at the drain of the fifth NMOS transistor.
9. The overcurrent protection circuit according to claim 7, characterized in that, The width-to-length ratio of the second PMOS transistor is proportional to the width-to-length ratio of the first PMOS transistor at a ratio of 1:K; and / or, The width-to-length ratio of the second NMOS transistor is proportional to the width-to-length ratio of the fourth NMOS transistor at a ratio of 1:1; and / or, The reference current at the negative input of the transconductance amplifier is proportional to the threshold current by a ratio of 1:K.
10. A radio frequency transceiver, characterized in that, include: The overcurrent protection circuit for TXLDO as described in any one of claims 1 to 9.