High-frequency digital carrier signal generation method based on multiphase parallel structure

Abstract

The application discloses a high-frequency digital carrier signal generation method based on a multi-phase parallel structure, comprising the following steps: determining the number of parallel phases P, the system sampling clock frequency and the target carrier frequency; calculating the Nyquist zone number and determining the low-frequency fundamental wave frequency; calculating the p-phase fixed phase factor; generating a low-frequency complex fundamental wave signal; respectively carrying out complex multiplication operation on the low-frequency complex fundamental wave signal and the p-phase fixed phase factor to obtain the p-phase output; and sequentially and serially converting the P-phase output to obtain a high-frequency digital carrier signal with an equivalent sampling rate of and a frequency of The high-frequency digital carrier signal generation method based on the multi-phase parallel structure provided by the application decomposes the high-frequency carrier generation task into two sub-tasks of shared low-frequency fundamental wave generation and multi-phase fixed phase rotation through the multi-phase parallel structure, and realizes P times frequency expansion without improving the system working clock frequency.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing and digital front-end technology, specifically relating to a high-frequency digital carrier signal generation method based on a multi-phase parallel structure. In particular, it relates to a stream processing architecture that breaks through the limitations of single-channel Nyquist sampling, significantly reduces the storage area of ​​lookup tables (LUTs), and broadens the range of digital carrier frequency generation. It can be applied to fields such as digital upconversion (DUC), software radio, phased array radar, distributed phased coherent signal sources, and broadband test and measurement. Background Technology

[0002] In modern wireless communication, radar, satellite navigation, software radio, and high-performance test and measurement systems, digital up-conversion (DUC) is the core component connecting baseband processing and RF transceiver in the digital front end. The generation of high-frequency digital carrier signals determines the upper limit of the RF output frequency, spectral purity (spurious noise and phase noise), hardware area, power consumption, and cost of the entire system. Currently, common methods for generating digital carrier signals on FPGA, SoC, and ASIC platforms mainly include: (1) Direct Digital Synthesizer (DDS) based on lookup table (LUT), which achieves high-precision carrier output by using a phase accumulator in conjunction with a sine / cosine lookup table; (2) Iterative rotation method based on the CORDIC (Coordinate Rotation Digital Computer) algorithm, which approximates the sine / cosine values ​​by using addition and shift iteration; and (3) A combination of the above two methods.

[0003] The methods described above are all constrained by the Nyquist sampling theorem when generating high-frequency carriers. This is based on the FPGA's internal logic clock. As the system sampling clock, the range of digital carrier frequencies that a single DDS can output is limited to the interval [range 1]. Taking the DDS Compiler IP core provided by Xilinx as an example, the frequency range of the carrier it generates is also limited to this range. For application scenarios where the carrier frequency is much higher than the digital processing clock frequency, such as S / C / X / Ku band radar, 5G / 6G millimeter-wave communication, broadband electronic countermeasures, and high-speed data converter front-ends, a single-channel DDS can hardly directly generate the required high-frequency carrier. As shown in Figure 1, when sampling high-frequency analog signals at a sampling rate lower than the Nyquist rate, obvious phase information loss (spectral aliasing) will occur in the time domain.

[0004] To address the aforementioned frequency limitation issue, existing solutions typically employ two approaches: first, using a phase-locked loop (MMCM / PLL) within the FPGA to multiply the system clock to a higher frequency before running the DDS; second, offloading the carrier generation task directly to the digital up-converter within the high-speed DAC chip. The former significantly increases the FPGA's dynamic power consumption and timing convergence pressure, and is limited by device technology and the maximum achievable clock frequency; the latter sacrifices system flexibility, reconfigurability, and observability, making it unsuitable for collaborative design of multi-channel, distributed coherent systems.

[0005] On the other hand, LUT-based DDS requires high precision in both phase bit width and amplitude bit width to ensure frequency resolution and spurious-free dynamic range (SFDR), which increases the ROM / BRAM storage area. Considerable; even with improvements like CORDIC optimizing the storage area to... For multi-channel parallel upconversion links, the overall storage and routing overhead remains significant. Furthermore, the traditional single-channel DDS lacks collaborative optimization space with the subsequent multiphase interpolation filter architecture, making it impossible to utilize the parallel sub-channels of the multiphase interpolation filter to absorb the phase rotation calculations required for carrier generation, resulting in resource redundancy.

[0006] Therefore, on FPGA processing platforms with limited clock frequencies, designing a high-frequency digital carrier generation method that significantly expands the digital carrier frequency generation range without increasing the system operating clock frequency or significantly increasing storage resources, and that can be synergistically optimized with a multiphase interpolation filtering architecture, has significant engineering and industrial value. To address the above problems, this invention proposes a high-frequency digital carrier signal generation method based on a multiphase parallel structure and its stream processing hardware architecture. Summary of the Invention

[0007] This invention provides a high-frequency digital carrier signal generation method based on a multiphase parallel structure to solve the technical problems of existing single-channel DDS being limited by Nyquist sampling, having a limited range of digital carrier frequency generation, and having a large LUT / ROM storage area that is difficult to coordinate with multiphase interpolation filtering architecture. The specific technical solution adopted is as follows:

[0008] A method for generating high-frequency digital carrier signals based on a multiphase parallel structure includes the following steps:

[0009] Determine the number of parallel phases P and the system sampling clock frequency. and target carrier frequency ,in ;

[0010] Calculate the Nyquist zone number And determine the low-frequency fundamental frequency. ;

[0011] Calculate the fixed phase factor of phase p. ,in ;

[0012] based on Generate low-frequency complex fundamental signal ;

[0013] Will respectively with Perform complex multiplication to obtain the p-th phase output. When p=0 Direct output ;

[0014] The P-phase outputs are sequentially converted from parallel to serial to obtain an equivalent sampling rate of , frequency is High-frequency digital carrier signal.

[0015] Furthermore, the Nyquist zone number K satisfies:

[0016]

[0017] in, This is for rounding up to the nearest integer.

[0018] Furthermore, the complex analytic expression for the p-th phase is:

[0019]

[0020] Where n is an integer, and p∈[0,P-1].

[0021] Furthermore, the low-frequency complex fundamental signal Generated by a single-channel direct digital frequency synthesizer or a coordinate-rotating digital computer algorithm, running in At the rate.

[0022] Furthermore, the P-phase output is according to The order of each P samples are output in parallel within a period, and then converted to digital-to-analog conversion via a high-speed digital-to-analog converter interface. The data rate completes the digital-to-analog conversion.

[0023] Furthermore, when used in conjunction with a multiphase interpolation filter, a fixed phase factor will be used. The coefficients absorbed into the p-th phase of the polyphase interpolation filter form the complex filter coefficients with phase compensation:

[0024]

[0025] in is the p-th phase coefficient of the original multiphase interpolation filter.

[0026] Furthermore, the coefficients of the complex filter with phase compensation The calculation and quantization are performed offline on the processor side, and then downloaded to the multiphase interpolation filter coefficient memory on the programmable logic side via the configuration interface.

[0027] Furthermore, the fixed phase factor The calculation is performed offline on the processor and quantized into a fixed-point number that matches the bit width of the multiplier on the programmable logic side. The result is then downloaded to the phase factor register or memory via a configuration interface.

[0028] Furthermore, the parallel phase number P and the target carrier frequency The Nyquist zone number K can be dynamically modified via a configuration interface to support carrier frequency agility and multi-channel coherent signal source applications.

[0029] Furthermore, the method can be applied to digital upconversion links, software-defined radio systems, phased array radar signal sources, or distributed phased coherent signal sources to generate frequencies higher than [the specified frequency] without increasing the system's operating clock frequency. / 2 high-frequency digital carrier signal.

[0030] The high-frequency digital carrier signal generation method based on a multiphase parallel structure provided by this invention decomposes the high-frequency carrier generation task into two sub-tasks: shared low-frequency fundamental wave generation and multiphase fixed phase rotation. Without increasing the system's operating clock frequency, this expands the digital carrier frequency generation range from that of a single-channel DDS. Expand to This achieves P-fold frequency expansion while reducing the LUT storage area required by DDS from S to S / P, significantly lowering hardware resource overhead. The system operating clock f... clk It is equal to the working rate of each phase fs (i.e., fclk=fs), and the equivalent sampling rate after P-path parallelization is P·fs. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is due to aliasing in the time domain caused by undersampling;

[0033] Figure 2This is a schematic diagram of the multiphase method for acquiring / generating high-speed signals (P=4 in the diagram).

[0034] Figure 3 The spectrum correspondence from the high Nyquist region to the low Nyquist region is shown, where: (a) part represents the distribution of target frequency points in the high Nyquist region, (b) part represents the folding of the spectrum after sampling according to the sampling frequency period, and (c) part represents the mapping of high frequency points corresponding to different k to the same low frequency fundamental wave;

[0035] Figure 4 This is a schematic diagram of a high-frequency carrier stream processing unit generated by the multiphase method. Detailed Implementation

[0036] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0037] The core idea of ​​this invention is: utilizing The multi-phase parallel structure ensures that the clock speed of each operation is only a low value. The equivalent sampling rate is expressed jointly. The high-frequency digital carrier signal is described below. The complete mathematical derivation and architectural method from Nyquist sampling / aliasing analysis to hardware mapping are presented below.

[0038] (1) Signal model.

[0039] Suppose the sampling rate of the complex digital carrier signal to be generated is The frequency is Its discrete sequence is:

[0040]

[0041] (2) Multiphase splitting.

[0042] In-phase components For example, the entire sequence is split into multiphase structures. Phase, defining the phase number , For integers, each phase is... To operate at the working rate, the sample expression for each phase is obtained:

[0043]

[0044] This is equivalent to extracting P subsequences from the original sequence of length N according to the subsampling points numbered p, with the sampling rate of each subsequence being p. Figure 2 illustrates the temporal correspondence between multiphase acquisition and multiphase generation.

[0045] (3) Phase decomposition.

[0046] right phase Expanding on this, we get:

[0047]

[0048] Further utilization ( It is an integer. The in-phase fraction can be simplified as follows:

[0049]

[0050] Therefore, the equivalent frequency of each phase output is... Only the initial phase With phase number Linear correlation. The range of values ​​and the unique integer solution are:

[0051]

[0052] in This represents rounding. Correspondingly, the fundamental frequency of each phase. and the first meeting It is given by the following formula:

[0053]

[0054] Figure 3 shows the Nyquist zone mapping relationship of complex carrier signals under undersampling / oversampling conditions. The high-frequency points under different integer K will be uniformly mapped to the fundamental frequency fa of the first Nyquist zone. This is the core basis of the low-frequency fundamental frequency multiplexing and multiphase phase reconstruction of the present invention.

[0055] (4) Plural expression.

[0056] right , Processing both paths simultaneously, the first The complex analytic expression for a phase is:

[0057]

[0058] Further rewritten as a product of "low-frequency fundamental frequency × phase factor":

[0059]

[0060] That is, the first The phase can be decomposed into the product of two parts: one working in Low-frequency complex carrier term at rate and a numbered by phase number Determined fixed phase factor .

[0061] (5) Maximum possible carrier frequency.

[0062] According to the Nyquist criterion Phase parallel, sampling rate per phase The highest carrier frequency that the system can express satisfies:

[0063]

[0064] (6) Hardware mapping

[0065] Based on the above derivation, this invention maps the high-frequency digital carrier generation hardware to the following stream processing unit (e.g., Figure 4 As shown): ① Use a working... Single-channel low-frequency DDS (or CORDIC) at a certain speed generates low-frequency complex basis signals. ; ② will Simultaneously sent in There are 3 parallel branches, each branch is connected to its corresponding fixed phase factor. Perform complex multiplication to obtain the first... Phase output ;③ The branch has a phase factor of The complex multiplier can be omitted; ④ The output of each branch is then fed into a multi-channel DAC via parallel-to-serial conversion or alternately in the subsequent stage, thus forming an equivalent sampling rate of [missing information]. , frequency is High-frequency carrier signals. The entire link requires... A complex number multiplier.

[0066] (7) Co-optimization with multiphase interpolation filter architecture.

[0067] When this method is used in conjunction with a multiphase interpolation filtering architecture (e.g., a multiphase DUC link), Fixed phase factor of the phase It can be directly absorbed into the multiphase interpolation filter. The phase coefficients are modified as follows:

[0068]

[0069] At this point, the entire link does not add extra multiplier resources compared to the "single-channel DDS + multiphase interpolation" scheme. It only needs to pre-calculate and load the multiphase filter coefficients with phase compensation offline at the PS end.

[0070] Based on the foregoing derivation, this application discloses a method for generating high-frequency digital carrier signals based on a multiphase parallel structure, comprising the following steps:

[0071] S1: Determine the number of parallel phases P and the system sampling clock frequency. and target carrier frequency ,in .

[0072] S2: Calculate the Nyquist zone number And determine the low-frequency fundamental frequency. .

[0073] S3: Calculate the fixed phase factor of phase p. ,in .

[0074] S4: Based on Generate low-frequency complex fundamental signal .

[0075] S5: Will respectively with Perform complex multiplication to obtain the p-th phase output. When p=0 Direct output .

[0076] S6: Convert the P-phase outputs sequentially from parallel to serial to obtain an equivalent sampling rate of , frequency is High-frequency digital carrier signal.

[0077] In the embodiments of this application, the Nyquist zone number K satisfies:

[0078]

[0079] in, This is for rounding up to the nearest integer.

[0080] In the embodiments of this application, the complex analytic expression of the p-th phase is:

[0081]

[0082] Where n is an integer, and p∈[0,P-1].

[0083] In the embodiments of this application, the low-frequency complex fundamental signal Generated by a single-channel direct digital frequency synthesizer or a coordinate-rotating digital computer algorithm, running in At the rate.

[0084] In the embodiments of this application, the P-phase output is... The order of each P samples are output in parallel within a period, and then converted to digital-to-analog conversion via a high-speed digital-to-analog converter interface. The data rate completes the digital-to-analog conversion.

[0085] In embodiments of this application, when used in conjunction with a multiphase interpolation filter, a fixed phase factor is used. The coefficients absorbed into the p-th phase of the polyphase interpolation filter form the complex filter coefficients with phase compensation:

[0086]

[0087] in is the p-th phase coefficient of the original multiphase interpolation filter.

[0088] In the embodiments of this application, the complex filter coefficients with phase compensation The calculation and quantization are performed offline on the processor side, and then downloaded to the multiphase interpolation filter coefficient memory on the programmable logic side via the configuration interface.

[0089] In the embodiments of this application, a fixed phase factor is used. The calculation is performed offline on the processor and quantized into a fixed-point number that matches the bit width of the multiplier on the programmable logic side. The result is then downloaded to the phase factor register or memory via a configuration interface.

[0090] In the embodiments of this application, the parallel phase number P and the target carrier frequency The Nyquist zone number K can be dynamically modified via a configuration interface to support carrier frequency agility and multi-channel coherent signal source applications.

[0091] In the embodiments of this application, the method is applied to digital upconversion links, software radio systems, phased array radar signal sources, or distributed phased coherent signal sources, generating frequencies higher than [the specified frequency] without increasing the system's operating clock frequency. / 2 high-frequency digital carrier signal.

[0092] The high-frequency digital carrier signal generation method based on a multiphase parallel structure proposed in this application has the following advantages:

[0093] Carrier frequency range expanded: from traditional single-channel DDS Expand to It breaks through the Nyquist sampling limit without increasing the system operating clock frequency, and can directly generate medium / high frequency digital carriers under a relatively low FPGA logic clock.

[0094] Significant savings in LUT / ROM storage resources: from the storage area required by the original single-channel DDS Compress to If the original solution uses a CORDIC or CORDIC+LUT hybrid solution to optimize the storage area to... This method can be further compressed to This is particularly advantageous for multi-channel, multi-link systems.

[0095] Hardware costs are controllable: to increase Complex multipliers and In exchange for a fixed phase factor constant, the carrier frequency range is increased. This extends the filter by a factor of two; when used in conjunction with a polyphase interpolation filter, this... Each multiplier can be directly absorbed into the filter coefficients, achieving zero additional multiplier addition.

[0096] The production line has strong processing capabilities. The branches are fully parallel and have a regular structure, making them suitable for FPGA / ASIC pipeline mapping and high-parallel data path design, with a throughput per unit clock cycle. Each sample point is naturally matched with the subsequent high-speed DAC (such as the JESD204B / C interface).

[0097] Reduce clock stress and power consumption: Avoid multiplying the FPGA's internal clock frequency. This generates high-frequency carriers, significantly reducing dynamic power consumption, timing convergence risk, and PLL / MMCM resource consumption.

[0098] High system flexibility: carrier frequency Nyquist District Number , phase number All parameters can be dynamically modified through PS terminal configuration, supporting application scenarios such as frequency agility and multi-frequency coherent signal sources.

[0099] The following describes the specific implementation of this invention using a distributed coherent signal source based on a CPU+FPGA heterogeneous embedded system (such as Xilinx Zynq UltraScale+ MPSoC, Intel SoC FPGA, etc.) as an example. The entire link consists of three parts: parameter configuration and offline calculation at the PS end (ARM), multiphase parallel stream processing calculation at the PL end (FPGA), and transmission from the JESD204B / C interface to the high-speed DAC.

[0100] (1) System parameter determination. Based on the target transmission carrier frequency. With FPGA internal system clock Determine the degree of parallelism Make ;according to Calculate the Nyquist zone number, and then obtain the low-frequency fundamental frequency. .

[0101] (2) Offline computation on the PS side. Computation is performed on the ARM side. A fixed phase factor , And quantized into a fixed-point number matching the bit width of the FPGA multiplier; if a multiphase interpolation filter exists in the link. Then, the coefficients of the complex filter with phase compensation are further calculated. All constants / coefficients are downloaded to the coefficient register or BRAM at the PL end via AXI-Lite or DMA.

[0102] (3) Generation of low-frequency fundamental frequency at the PL terminal. Instantiate a working channel at the PL terminal. DDS / CORDIC modules at certain speeds, according to frequency Generate low-frequency complex fundamental signal The phase accumulator and sine / cosine meter of this module are both powered by a low-speed clock. Running at this speed, the storage area is approximately [amount missing] of a traditional single-socket solution. .

[0103] (4) Parallel phase rotation of phase P. Broadcast to Parallel branch, the first A branch road connects it with By performing complex multiplication, we can obtain ; branch road due to The multiplier can be omitted and the output can be directly processed. The entire supply chain requires shared resources. A complex multiplier (each complex multiplier consists of 3 or 4 real multipliers).

[0104] (5) Output in parallel to the DAC. The output of each branch is according to The order of each Parallel output within a cycle Each point is fed into a high-speed DAC via a JESD204B / C or LVDS interface. The data rate completes the digital-to-analog conversion and generates a frequency of The analog carrier.

[0105] (6) Co-implementation with a multiphase interpolation filter (optional). The complex coefficients with phase compensation calculated in step (2) are... Loading to the In the coefficient memory of the phase filter, The phase factor multiplications are merged into the convolution multiplication-addition operation of the filter, eliminating the need for a separate phase rotation multiplier in the link.

[0106] (7) Dynamic switching of frequency and phase. Dynamically updated via the AXI-Lite interface. and (or It can switch carrier frequencies during runtime to achieve functions such as frequency agility and phase synchronization; this process does not interrupt the pipeline and can be completed within a few clock cycles.

[0107] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any way, and all technical solutions obtained by equivalent substitution or equivalent transformation fall within the protection scope of the present invention.

Claims

1. A method for generating high-frequency digital carrier signals based on a multiphase parallel structure, characterized in that, Includes the following steps: Determine the number of parallel phases P and the system sampling clock frequency. and target carrier frequency ,in ; Calculate the Nyquist zone number And determine the low-frequency fundamental frequency. ; Calculate the fixed phase factor of phase p. ,in ; based on Generate low-frequency complex fundamental signal ; Will respectively with Perform complex multiplication to obtain the p-th phase output. When p=0 Direct output ; The P-phase outputs are sequentially converted from parallel to serial to obtain an equivalent sampling rate of , frequency is High-frequency digital carrier signal; The Nyquist zone number K satisfies: in, This is for rounding up to the nearest integer.

2. The high-frequency digital carrier signal generation method based on a multiphase parallel structure according to claim 1, characterized in that, The complex analytic expression for the p-th phase is: Where n is an integer, and p∈[0,P-1].

3. The high-frequency digital carrier signal generation method based on a multiphase parallel structure according to claim 1, characterized in that, The low-frequency complex fundamental signal Generated by a single-channel direct digital frequency synthesizer or a coordinate-rotating digital computer algorithm, running in At the rate.

4. The high-frequency digital carrier signal generation method based on a multiphase parallel structure according to claim 1, characterized in that, The P-phase output is according to The order of each P samples are output in parallel within a period, and then converted to digital-to-analog conversion via a high-speed digital-to-analog converter interface. The data rate completes the digital-to-analog conversion.

5. The high-frequency digital carrier signal generation method based on a multiphase parallel structure according to claim 1, characterized in that, When used in conjunction with a multiphase interpolation filter, the phase factor will be fixed. The coefficients absorbed into the p-th phase of the polyphase interpolation filter form the complex filter coefficients with phase compensation: in is the p-th phase coefficient of the original multiphase interpolation filter.

6. The high-frequency digital carrier signal generation method based on a multiphase parallel structure according to claim 5, characterized in that, The complex filter coefficients with phase compensation The calculation and quantization are performed offline on the processor side, and then downloaded to the multiphase interpolation filter coefficient memory on the programmable logic side via the configuration interface.

7. The high-frequency digital carrier signal generation method based on a multiphase parallel structure according to claim 1, characterized in that, The fixed phase factor The calculation is performed offline on the processor and quantized into a fixed-point number that matches the bit width of the multiplier on the programmable logic side. The result is then downloaded to the phase factor register or memory via a configuration interface.

8. The high-frequency digital carrier signal generation method based on a multiphase parallel structure according to claim 1, characterized in that, The parallel phase number P and the target carrier frequency The Nyquist zone number K can be dynamically modified via a configuration interface to support carrier frequency agility and multi-channel coherent signal source applications.

9. The high-frequency digital carrier signal generation method based on a multiphase parallel structure according to claim 1, characterized in that, The method is applied to digital upconversion links, software-defined radio systems, phased array radar signal sources, or distributed phased coherent signal sources to generate frequencies higher than [the specified frequency] without increasing the system's operating clock frequency. / 2 high-frequency digital carrier signal.

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