Scheduling apparatus and operating method for a memory device using multiple clock commands

Abstract

The present disclosure relates to a memory system including a memory device and a memory controller. The memory device includes at least one data storage area. The memory controller is coupled to the memory device and configured to transmit at least one command scheduled to be transmitted within a preset clock range to the memory device. The memory controller is configured to transmit an activate command to be included in the at least one command to the memory device when a command to be transmitted after the activate command is not a data input / output (I / O) command.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2025-0015001, filed on February 6, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure described herein relate to a memory device, and more specifically, to a scheduling apparatus and operating method for a memory device using multi-clock commands. Background Technology

[0004] Data processing systems that include memory systems or data storage devices have been developed to store larger volumes of data and have faster rates of inputting (or writing) data to and outputting (or reading) data from the data storage device. The data storage device may include non-volatile memory cells and / or volatile memory cells for storing data.

[0005] The development of a data processing system can include improving computing power and data processing speed according to user needs. The memory system within the data processing system can respond to requests from external devices such as the host computer, performing input and output data operations. The memory system can receive data input / output requests from at least one external device and can schedule multiple tasks or operations corresponding to the data input / output requests to achieve efficient management or processing of these requests. Summary of the Invention

[0006] Embodiments of this disclosure may provide an apparatus and a method of operation for improving the data input and output (input / output) performance of a memory device comprising multiple memory regions capable of independently performing data input / output operations by adjusting the command execution order of related multi-clock commands or scheduling multi-clock commands.

[0007] Additionally, embodiments of this disclosure can perform scheduling such that data input / output commands or multi-clock commands among multiple commands sent to a memory device comprising multiple memory regions capable of independently performing data input / output operations can be sent before other commands, thereby reducing the time spent executing multiple data input / output commands.

[0008] Furthermore, embodiments of this disclosure can prevent or avoid execution delays of data input / output commands by allowing the scheduling device or memory controller to send other commands later than the data input / output commands within the minimum (and sometimes necessary) time period that should be ensured between data input / output commands, thereby enabling the memory device to maintain the operational state of executing data input / output commands.

[0009] Embodiments of this disclosure may provide a memory system comprising: a memory device including at least one data storage area; and a memory controller coupled to the memory device and configured to send at least one command scheduled to be sent within a preset clock range to the memory device. The memory controller may be configured to send the activation command to the memory device when a command to be sent after an activation command to be included in the at least one command is not a data input / output (input / output) command.

[0010] Data input / output commands may include at least one of read commands and write commands. The memory controller may be configured to send a data input / output command to the memory device before the activation command when the command to be sent after the activation command is a data input / output command.

[0011] Activation commands and data input / output commands can be multi-clock commands that are sent over multiple clock cycles.

[0012] The preset clock range can include at least four clock cycles.

[0013] At least one command may include a precharge command, which is a single-clock command to be sent within a single clock cycle. The controller can be configured to send the precharge command to the memory device regardless of the order in which the data input / output commands are sent.

[0014] The memory controller can be configured to send the data input / output command to the memory device before the activation command when the command to be sent after the data input / output command is an activation command.

[0015] At least one data storage area may include multiple memory banks. Activation commands and data input / output commands can be sent to different memory banks.

[0016] Data input / output commands can have a minimum burst period or minimum column command delay period that is longer than the preset clock range.

[0017] The minimum column command delay period can include eight clock cycles.

[0018] In another embodiment, a method of operating a memory system may include: determining at least one command scheduled to be sent to a memory device including at least one data storage area within a preset clock range; and sending the activation command to the memory device when the command to be sent after the activation command to be included in the at least one command is not a data input and output (input / output) command.

[0019] The method may further include sending the data input / output command to the memory device before the activation command when the command to be sent after the activation command is a data input / output command included in at least one command.

[0020] Data input / output commands may include at least one of read commands and write commands.

[0021] Activation commands and data input / output commands can be multi-clock commands that are sent over multiple clock cycles.

[0022] The preset clock range can include at least four clock cycles.

[0023] At least one command may include a precharge command, which is a single-clock command to be sent within a single clock cycle. The method may further include sending the precharge command to the memory device regardless of the order in which the data input / output commands are sent.

[0024] At least one data storage area may include multiple storage banks. Activation commands and data input / output commands can be sent to different storage banks among the multiple storage banks.

[0025] Data input / output commands can have a minimum burst period or minimum column command delay period that is longer than the preset clock range.

[0026] The minimum column command delay period can include eight clock cycles.

[0027] In another embodiment, a command scheduler is coupled to a memory device including at least one data storage area and is configured to determine the transmission timing of at least one command scheduled to be transmitted within a preset clock range. The command scheduler may be configured to send an activation command to the memory device when a command to be transmitted after an activation command to be included in at least one command is not a data input / output (I / O) command.

[0028] Activation commands and data input / output commands can be multi-clock commands to be sent over multiple clock cycles. Data input / output commands can include at least one of read commands and write commands.

[0029] These and other features and advantages of the invention will become apparent from the detailed description of the embodiments of this disclosure and the accompanying drawings. Attached Figure Description

[0030] This document is described with reference to the accompanying drawings, in which the same reference numerals refer to the same parts throughout the drawings.

[0031] Figure 1 A memory system according to an embodiment of the present disclosure is shown.

[0032] Figure 2 A memory device according to an embodiment of the present disclosure is shown.

[0033] Figure 3 The operation performed in a memory system according to an embodiment of the present disclosure is illustrated.

[0034] Figure 4 Examples of multiple commands sent to a memory device in a memory system according to embodiments of the present disclosure are shown.

[0035] Figure 5 A scheduling method according to an embodiment of the present disclosure is shown.

[0036] Figure 6 The scheduling effect according to an embodiment of this disclosure is shown.

[0037] Figure 7 A data processing apparatus according to an embodiment of the present disclosure is shown.

[0038] Figure 8 Another data processing apparatus according to an embodiment of the present disclosure is shown. Detailed Implementation

[0039] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0040] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “optional embodiments,” etc., are intended to indicate that any of these features are included in one or more embodiments of this disclosure, but may or may not be combined in the same embodiments.

[0041] In this disclosure, the terms “comprising,” “including,” “including,” and “comprising” are open-ended. As used in the appended claims, these terms specify the presence of the said element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the device from including additional components, such as interface units, circuitry, etc.

[0042] In this disclosure, various units, circuits, or other components may be described or declared as "configured to" perform one or more tasks. In this context, "configured to" is used to indicate a structure by indicating that the block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, even when the block / unit / circuit / component is not currently running (e.g., not turned on or not activated), it can be said that the specified block / unit / circuit / component is configured to perform a task. Examples of blocks / units / circuits used with the "configured to" language include hardware, circuits, memory storing program instructions that can be executed to perform operations, etc. Additionally, "configured to" may include general structures (e.g., general circuits) manipulated by software and / or firmware (e.g., FPGAs or general-purpose processors running software) to operate in a manner capable of performing the relevant tasks(s). "Configured to" may also include means (e.g., integrated circuits) that adapt a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture devices suitable for performing or carrying out one or more tasks.

[0043] As used in this disclosure, the terms “machine,” “circuit,” or “logic” refer to all of the following: (a) a purely hardware circuit implementation (e.g., an implementation in analog and / or digital circuitry only); and (b) a combination of circuitry with software and / or firmware, such as (if applicable): (i) a combination of (multiple) processors or (ii) multiple processors / software working together to enable a device such as a mobile phone or server to perform various functions, including portions of (multiple) digital signal processors, software, and (multiple) memories; and (c) circuitry that requires software or firmware to operate even if the software or firmware is not physically present, such as (multiple) microprocessors or portions of (multiple) microprocessors. This definition of “machine,” “circuit,” or “logic” applies to all uses of the term in this application (including any claim). As another example, as used in this application, the terms “machine,” “circuit,” or “logic” also cover an implementation of a processor or multiple processors or portions of a processor and its (or their) accompanying software and / or firmware. For example, if applicable to a particular claim element, the terms “machine,” “circuit,” or “logic” also cover an integrated circuit of a storage device.

[0044] As used herein, the terms “first,” “second,” “third,” etc., serve as labels for the nouns preceding them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily mean that the first value must precede the second value. Furthermore, while these terms can be used herein to identify various components, these components are not limited by these terms. These terms are used to distinguish one component from another that would otherwise have the same or similar names. For example, a first circuit can be distinguished from a second circuit.

[0045] Furthermore, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude other factors that may influence the determination. The determination may be based solely on those factors or at least partially on them. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, this expression does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely on B.

[0046] Embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals refer to the same elements.

[0047] Figure 1 A memory system 110 according to an embodiment of the present disclosure is shown.

[0048] Reference Figure 1 The data processing system 100 may include a host 102 and a memory system 110. The memory system 110 may be coupled to the host 102 as an external device. According to an embodiment, the data processing system 100 may further include additional components for coupling the host 102 and the memory system 110.

[0049] Host 102 and memory system 110 can communicate via at least one component (e.g., a data bus, network, or root hub). Data communication between host 102 and memory system 110 can be performed via a host interface (e.g., host I / F). The host interface (e.g., host I / F) between host 102 and memory system 110 can include mutually agreed-upon data transmission and reception standards. These standards can include various interface protocols for transmitting and receiving data, such as: Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), High-Speed ​​Peripheral Component Interconnect (PCIe), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), and Mobile Industry Processor Interface (MIPI). According to an embodiment, host 102 and memory system 110 can be connected via Universal Serial Bus (USB). Universal Serial Bus (USB) can include scalable, hot-pluggable, plug-and-play serial interfaces to ensure cost-effective connections to peripherals such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, and video conferencing cameras.

[0050] According to embodiments, the memory system 110 can be implemented as one of a variety of storage devices such as: solid-state drive (SSD), MMC, embedded MMC (eMMC), small form factor MMC (RS-MMC), multimedia card (MMC) in the form of micro MMC, secure digital card (SD) in the form of SD, mini SD or micro SD, universal serial bus (USB) storage device, universal flash memory (UFS) device, compact flash memory (CF) card, smart media card or memory stick.

[0051] The memory system 110 may include a memory controller 150 and a memory device 180. The memory controller 150 may be configured to receive commands from a host 102, which is an external device, and send a response to the command to the host 102. For example, the command may be used to check the operational status of the memory system 110, store data in the memory system 110, or read data stored in the memory system 110. According to embodiments, the host 102 may send various commands to the memory system 110 as needed. The memory system 110 may be configured to perform internal operations in response to commands from the host 102 and send a response to the host 102 based on agreed-upon standards or rules.

[0052] Memory controller 150 may include a read buffer (RD buffer) 152 and a write buffer (WR buffer) 154. Read buffer 152 is a component for processing read commands, and write buffer 154 is a component for processing write commands. According to an embodiment, memory controller 150 may process both read and write commands through a single buffer. However, in this case, the operating mode may frequently change from read mode to write mode, or vice versa. Frequent changes in operating mode may reduce the throughput of the memory system. To address this issue, memory system 110 may separate the read buffer 152 for processing read commands and the write buffer 154 for processing write commands, and process read and write commands through separate processes (e.g., separate pipelines).

[0053] Read buffer 152 and write buffer 154 may have a fixed size corresponding to internal resources and internal configuration. However, according to embodiments of this disclosure, the sizes of read buffer 152 and write buffer 154 may vary based on the operating environment or conditions. Furthermore, the sizes of read buffer 152 and write buffer 154 may be different. Depending on the operating environment of the memory system, when a large number of read commands need to be processed, the memory system 110 may use more internal resources to process read commands than to process write commands. Conversely, when a large number of write commands need to be processed, the memory system 110 may use more internal resources to process write commands than to process read commands.

[0054] The memory controller 150 may include a command scheduler 160. The command scheduler 160 may include a request storage unit 162 configured to temporarily store multiple commands, including commands sent from read buffer 152 and write buffer 154, and commands for checking or controlling the operational state of the memory device 180. The request storage unit 162 can be understood as space temporarily storing multiple commands scheduled to be sent to the memory device 180. According to embodiments, the request storage unit 162 may include content-addressable memory (CAM) or a queue.

[0055] For example, Content-Addressable Memory (CAM) can be a special type of memory configured to access data in storage space by addressing the actual data content. CAM can also be called associative memory and can be used in search applications that require high speed. CAM can be more powerful and faster than general-purpose digital address memory and can be very useful for information retrieval because it can access information stored in memory by searching for the location of the desired information using a portion of the stored content (rather than the address).

[0056] Queues can have a First-In-First-Out (FIFO) data structure. A queue is a list structure where insertion occurs at one end and deletion at the other. For example, a queue processes only one piece of data at a time, and data input and output can only occur at fixed positions. That is, adding (inserting, inputting) data to the queue can only happen at the end of the queue (e.g., the tail), while returning (deleting, outputting) data can only happen at the beginning of the queue (e.g., the head). Queues can also have a linear data structure where the head and tail are in a 1:1 ratio. Implementing the request storage unit 162 as a queue has the advantage of reducing the complexity of command processing.

[0057] Command scheduler 160 may include a current stage request candidate unit 164 and a next stage request candidate unit 166. The current stage request candidate unit 164 and the next stage request candidate unit 166 may sequentially store commands scheduled to be sent to memory device 180 within a preset clock range from a plurality of commands stored in request storage unit 162. For example, if the preset clock range includes four clock cycles, commands to be sent to memory device 180 within these four clock cycles may be sequentially stored in the current stage request candidate unit 164 and the next stage request candidate unit 166. The following will refer to... Figure 4 Describes the commands stored in the current stage request candidate unit 164 and the next stage request candidate unit 166.

[0058] Command scheduler 160 may include a no-request unit 168. Request memory unit 162 may not include commands sent to memory device 180 within a preset clock range. That is, the current stage request candidate unit 164 and the next stage request candidate unit 166 may not include any commands. If no command is sent to memory device 180 within the preset clock range, the no-request unit 168 can be activated.

[0059] Command scheduler 160 may include selector 170 (e.g., selection unit) configured to determine the command (e.g., dynamic random access memory (DRAM) command) to be sent to memory device 180 in response to input / instructions from current stage request candidate 164, next stage request candidate 166, and no-request unit 168. If no-request unit 168 is active, selector 170 may not send any command to memory device 180. If current stage request candidate 164 includes a data input / output command (e.g., a read command or a write command), selector 170 may send the corresponding data input / output command to memory device 180. If current stage request candidate 164 includes a command other than a data input / output command (e.g., a read command or a write command), selector 170 may check the commands included in next stage request candidate 166 before sending the command to memory device 180.

[0060] In response to a command included in the next stage request candidate 166, selector 170 may output one of the commands included in the current stage request candidate 164 or the next stage request candidate 166 to memory device 180. For example, if the current stage request candidate 164 includes an activation command and the next stage request candidate 166 includes a data input / output command (e.g., a read command or a write command), selector 170 may output the data input / output command (e.g., a read command or a write command) included in the next stage request candidate 166 to memory device 180 instead of the activation command included in the current stage request candidate 164. Conversely, if the current stage request candidate 164 includes a data input / output command (e.g., a read command or a write command) and the next stage request candidate 166 includes an activation command, selector 170 may send the data input / output command to memory device 180 first, and then send the activation command to memory device 180.

[0061] According to an embodiment, activation commands and data input / output commands (e.g., read commands or write commands) can be multi-clock commands. Multi-clock commands include commands that the memory controller 150 promises (i.e., reserves, holds, schedules, indicates) to be sent to the memory device 180 over multiple (or several) clock cycles. The memory controller 150 can be configured to send various types of commands to the memory device 180, some of which can be multi-clock commands and others can be single-clock commands. Single-clock commands include commands that the memory controller 150 promises (indicates) to be sent to the memory device 180 over a single clock cycle. For example, a precharge command can be a single-clock command. On the other hand, for data input / output commands (e.g., read commands or write commands), a minimum interval or period of time between commands can be required based on the burst length (BL). The minimum interval between data input / output commands can be set to a minimum burst period or a minimum column command delay period (e.g., column-to-column delay, tCCD).

[0062] According to an embodiment, the burst length (BL) can be increased to improve the data input / output performance of the memory system 110. For example, the burst length (BL) of DDR5 can be doubled from 8 to 16 compared to DDR4. In this case, the minimum interval or period between commands can be doubled in clock cycles. For example, when considering DDR data transmission using both rising and falling edges of the clock, the time required to transmit data with a burst length of 8 (BL=8) is 4 clock cycles, while the time required to transmit data with a burst length of 16 (BL=16) is 8 clock cycles. Therefore, the minimum interval or period between commands can be increased from 4 clock cycles to 8 clock cycles to avoid overlap in burst length (BL) units when sequentially issuing read or write commands. However, if the reference clock speed for the operation of the memory system is doubled, the minimum interval between commands may not substantially or physically increase.

[0063] Multi-clock commands can be considered slower than single-clock commands (e.g., based on multiple separate commands), but there is no difference in actual or physical time. Furthermore, even with an increase in the number of clock cycles for command or data transmission, the number of pins or pads used to transmit commands and addresses can be reduced. For example, a command or address (command / address) transmitted in a single clock cycle (i.e., 1 cycle) in DDR4 may require multiple clock cycles (e.g., 2 cycles) to transmit in DDR5. On the other hand, DDR4 has 26 pins or pads for transmitting commands or addresses, while DDR5 has 14 pins or pads. Reducing the number of pins or pads can reduce the package size or number of solder balls of the memory device 180, thereby reducing the manufacturing cost of the substrate or board (e.g., printed circuit board (PCB)) included in the memory system 110 and facilitating its design.

[0064] Additionally, in DDR4, Data Bus Inversion (DBI) can be applied to pins or pads that transmit data. Bus Inversion (BI) is an input / output (I / O) signaling technique designed to reduce DC power consumption by selectively inverting the power consumption asymmetry of the system's data bus between alternating signaling states. On the other hand, DDR5 can apply bus inversion to pins or pads that transmit commands or addresses, but not to pins or pads that transmit data.

[0065] As described above, the command scheduler 160 in the memory system 110 can change the transmission order of multi-clock commands to increase the number of commands and data sent and received between the memory controller 150 and the memory device 180 within a preset time period. The following will refer to... Figure 6 Describe the effects of Command Scheduler 160.

[0066] Figure 2 A memory device 180A according to an embodiment of the present disclosure is shown.

[0067] Reference Figure 2 The memory device 180A may include multiple data storage areas. The memory device 180A is... Figure 1 An example of the memory device 180 described herein. The memory device 180A can be configured in various forms.

[0068] Memory device 180A may include multiple memory banks (for ease of description, memory bank 0 and memory bank 1 are illustrated as a non-limiting example). Here, memory banks are logically independent regions, data in memory banks can be accessed simultaneously, and each memory bank can be operated independently. Word lines may have row addresses, and bit lines to which sense amplifiers are connected may have column addresses. Memory banks can perform read or write operations independently and simultaneously. However, since the circuitry and paths from the pins or pads of the memory device 180A package to each memory bank are shared with other memory banks, a certain time interval or period, such as a minimum column command delay period (column-to-column delay, tCCD), should be ensured between read or write commands sent to other memory banks. Each memory bank (memory bank 0, memory bank 1) may include multiple pages. Pages may indicate the number of memory cells (i.e., the number of bits) connected to word lines. For example, the page size may be 1KB, 2KB, or 4KB. The page size may be the same as the number of sense amplifiers turned on at one time. Smaller page sizes are beneficial for reducing power consumption because fewer sense amplifiers need to be operated.

[0069] As the number of memory banks in the memory device 180A increases, memory bank groups (units for grouping multiple memory banks) can be set up to efficiently implement, manage, and control a large number of memory banks. (See reference...) Figure 2 A memory bank group (e.g., group 0, group 1) may include a group of memory banks (e.g., two or four memory banks). When memory bank groups are configured, the portion of shared circuitry and paths between memory banks belonging to different memory bank groups can be reduced, allowing the minimum interval or time period between commands to be reduced more significantly than between memory banks within the same memory bank group. For example, the time interval or time period between commands from memory banks belonging to different memory bank groups can be defined as a first minimum column command delay period (e.g., short column-to-column delay, tCCD_S), while the time interval or time period between commands from memory banks belonging to the same memory bank group can be defined as a second minimum column command delay period (e.g., long column-to-column delay, tCCD_L). The first minimum column command delay period (e.g., tCCD_S) is shorter than the second minimum column command delay period (e.g., tCCD_L). Therefore, since the memory bank groups are divided into multiple groups, the memory controller 150 can send read commands or write commands to the memory device 180A with shorter intervals or time periods.

[0070] Additionally, the memory device 180A can be divided into multiple memory rank groups, which indicate physical groups of memory chips. Each memory rank can be accessed in parallel. Each memory rank can have an independent structure. However, each memory rank can share a channel for exchanging data with the memory controller 150. (See reference...) Figure 2 The memory device 180A can be divided into multiple physical memory rows (e.g., physical memory row 0, physical memory row 1), and each physical memory row (e.g., physical memory row 0, physical memory row 1) can include multiple logical memory rows (e.g., logical memory row 0, logical memory row 1). Each logical memory row (e.g., logical memory row 0, logical memory row 1) can include multiple memory bank groups (e.g., group 0, group 1).

[0071] According to an embodiment, the memory device 180A may employ a hierarchical design, and the data input / output performance of the memory system 110 may be improved by means of a means and method of operation for allocating and storing large amounts of data in hierarchical units by different settings of the shortest time between commands corresponding to each layer, or for reducing power consumption or preventing data errors.

[0072] Figure 3 Operations performed in a memory system according to embodiments of the present disclosure are described. Specifically, Figure 3 Described Figure 1 The operating modes of the memory device 180 described herein, and the changes in the operating modes of the memory device 180 in response to commands sent to the memory device 180 by the memory controller 150. Figure 3The operating modes of the memory device 180 described herein and the variations thereof may vary depending on the embodiments.

[0073] Reference Figure 3 The memory controller 150 can execute an initialization sequence on the memory device 180. The initialization sequence may include operations such as supplying power and adjusting settings to enable data communication between the memory controller 150 and the memory device 180. After the initialization sequence, all memory cells in the memory device 180 can be pre-charged in an idle state 230.

[0074] When the memory controller 150 sends a refresh command REF to a memory bank in idle state 230, the memory bank can be in refresh state (e.g., refresh, perform refresh operation) 232. After the refresh operation is completed, the memory bank can automatically switch back to idle state 230. Here, switching operation states by command can be represented by solid arrows, while automatic switching without command can be represented by dashed arrows.

[0075] When memory controller 150 sends an activation command (e.g., activation command) ACT to a specific memory bank in memory device 180, the memory bank can switch from an idle state 230 to an activation operation state (e.g., activation) 234, and then back to an active state (e.g., memory bank activation) 236. The activation operation state 234 can vary depending on the embodiment. For example, each memory bank can be activated simultaneously (e.g., concurrently), or only some of the multiple memory banks can be activated. The activation operation may include precharging an open page corresponding to a row address in the memory bank being activated. The instruction Precharge[All] can close any memory bank with open pages (e.g., rows).

[0076] Memory device 180 should (e.g., be configured to) open the memory bank before it is ready to respond to a read command or write command (e.g., an activation operation). Memory controller 150 may send an activation command ACT to specify the memory row, bank, and page (e.g., row) to be accessed, so that memory device 180 performs the activation operation. The time required to activate the memory bank is called the row-to-column (or command) latency and is denoted by tRCD. This variable can indicate the minimum time required to latch commands in the command interface, program the control logic, and read data from the memory array into the sense amplifier to prepare for column-level access.

[0077] When a particular memory bank is in an active state 236 and a precharging command (e.g., precharging[All], PR[A]) is sent to that memory bank, the memory bank can switch to a precharging state 242.

[0078] When a specific memory bank is in active state 236, its operating state can change according to data input / output commands. For example, when a write command (WRI) is sent for the corresponding memory bank, the corresponding memory bank can switch from active state 236 to writing state 244. When a write command (Write(WRI)) is sent in writing state 244, the corresponding memory bank can remain in writing state 244. When the write operation is complete, the corresponding memory bank can automatically switch from writing state 244 to active state 236.

[0079] When a specific memory bank is in write state 244 and a write and auto-precharge command (WRA) is sent to that memory bank, the memory bank can switch from write state 244 to write and auto-precharge state (e.g., write with auto-precharge) 246. When the precharge operation terminates in write and auto-precharge state 246, the memory bank can automatically switch to precharge state 242. Alternatively, if a precharge command (PR[A]) 244 is sent to that specific memory bank while it is in write state, the memory bank can switch to precharge state 242. Afterward, the memory bank can automatically switch from precharge state 242 to idle state 230.

[0080] Similar to the state transition of write commands, when a specific memory bank is in active state 236, a read command (READ) can be sent for that memory bank. When a read command (READ) is sent for that memory bank, the memory bank switches from active state 236 to read state (e.g., reading) 238. When a read command (READ) is sent in read state 238, the memory bank can remain in read state 238. When the read operation is complete, the memory bank can automatically switch back from read state 238 to active state 236.

[0081] When a specific memory bank is in read state 238 and a read and auto precharge command (e.g., read with auto precharge) RDA is sent to that memory bank, the memory bank can switch from read state 238 to read and auto precharge state 240. When the precharge operation is terminated in read and auto precharge state 240, the memory bank can automatically switch to precharge state 242. Additionally, when a specific memory bank is in read state 238 and a precharge command PR[A] is sent, the memory bank can switch to precharge state 242. Afterward, the memory bank can automatically switch from precharge state 242 to idle state 230.

[0082] When a specific memory bank is in read state 238, a write command WRI can be entered. In this case, the memory bank can switch from read state 238 to write state 244. Conversely, when a specific memory bank is in write state 244, a read command READ can be entered. In this case, the memory bank can switch from write state 244 to read state 238. Additionally, when a write and auto-precharge command WRA or a read and auto-precharge command RDA is sent to a specific memory bank, the memory bank can switch from write state 244 or read state 238 to write and auto-precharge state 246 or read and auto-precharge state 240.

[0083] As described above, following the activation operation of the memory bank, the open memory bank can perform operations in response to at least one read command (READ) and at least one write command (WRI). This operation can specify the starting column address to be accessed and set the time required to read data bytes from the open page as the column address strobe (CAS) delay (e.g., CL or tCAS). This variable can indicate the shortest time required to latch commands in the command interface, program the control logic, prefetch the requested data from the sense amplifier into the input / output (I / O) buffer, and place the first data from the requested data onto the memory bus.

[0084] According to an embodiment, the memory controller 150 can open one page of each memory bank at a time. The memory controller 150 should first close (or can be configured to close) the open page, and then access another page in the same memory bank. If a page is open (or remains open, is open), the memory controller 150 can issue a combination of a read command (READ) and a write command (WRI), and in some cases, switch back and forth between the two commands (e.g., READ, WRI). This can continue until the open page is no longer needed, or until pending requests to read data from another page in the same memory bank and write data to another page in the same memory bank require closing the current page in order to access other pages. This can be achieved by the memory controller 150 issuing a precharge command (PR) to close only the specified memory bank, or issuing a precharge command (e.g., precharge[All], (PR[A])) to close all open memory banks in the memory bank.

[0085] As described above, the memory controller 150 can send a Write and Automatic Precharge Command (WRA) or a Read and Automatic Precharge Command (RDA) as a precharge command, instead of sending the last read command among multiple read commands or the last write command among multiple write commands. In this case, the last read or write operation of the corresponding memory bank can be efficiently combined with the precharge operation. This allows the control logic within the memory device 180 to automatically close open pages immediately after certain conditions are met. The specific conditions may be that the shortest row access strobe (RAS) activation time (tRAS) has elapsed since the activation command (ACT) was issued, and the shortest read-to-precharge delay (tRTP) has elapsed since the most recent read command (REA) was issued.

[0086] The precharge operation prepares the data lines and sensing circuitry to transfer the charge stored in the sensing amplifier back to the open pages of a single memory cell to reverse a previous destructive read and prepares the memory device 180 to sample the next memory page to be accessed. The precharge time for an open memory bank can be set as the RAS precharge delay (tRP). The minimum time interval or period between consecutive activation commands (ACT) for the same memory bank can be determined by the row cycle time (tRC) of the memory device 180. According to an embodiment, the row cycle time (tRC) can be determined by simply adding the RAS activation time (tRAS) and the RAS precharge delay (tRP). The minimum time interval or period between activation commands (ACT) for different memory banks can be set as the read-to-read delay (tRRD).

[0087] Figure 4Examples of multiple commands sent to a memory device in a memory system according to embodiments of the present disclosure are shown. Figure 4 An example is shown where the burst length (BL) of DDR5 is 16 (i.e., BL=16) and the minimum time interval or period of read commands (e.g., RD ​​command interval) is 8 clock cycles (i.e., 8 Clk).

[0088] Reference Figure 4 The memory controller 150 may send a first activation command ACT#1 to the memory device 180 at any given time within multiple clock cycles (e.g., clock cycle 285 P0 and clock cycle 286 P1) (e.g., in cycle 284). The first activation command ACT#1 is a multi-clock command. In the following two clock cycles (e.g., P2 to P3, i.e., clock cycles 287 to 288), the memory controller 150 may not send any commands to the memory device 180.

[0089] Subsequently, the memory controller 150 may send a first precharge command PR#1 to the memory device 180 in the 289th clock cycle. Here, the precharge command is a single-clock command.

[0090] Subsequently, the memory controller 150 may send a first read command RD#1 to the memory device 180 during clock cycles 290 to 291 (e.g., P1, P2). The first read command RD#1, which is a data input / output command, is a multi-clock command.

[0091] Subsequently, the memory controller 150 may send a second activation command ACT#2 to the memory device 180 during two clock cycles (e.g., P3, P0). Then, the memory controller 150 may send a second precharge command PR#2 to the memory device 180 during the 294th clock cycle.

[0092] As described above, there is a minimum interval or time period between activation commands and data input / output commands (e.g., read commands or write commands). The memory controller 150 may send multiple activation commands and data input / output commands to the memory device 180 at minimum intervals or time periods.

[0093] Reference Figure 4The second read command RD#2 can be sent to memory device 180 in the 298th clock cycle (P1), which is the minimum interval (e.g., the RD command interval, 8 cl) after the time point when the first read command RD#1 was sent (i.e., the 290th clock cycle P1). However, due to the third activation command ACT#3, the second read command RD#2 is sent to memory device 180 in the 299th clock cycle (P2) instead of the 298th clock cycle (P1). That is, in Figure 4 In the example described, sending multiple read commands RD#1, RD#2, RD#3 to memory device 180 at a minimum interval of 8 Clk can improve the data input / output performance of memory system 110. However, if memory controller 150 fails to adjust the order or sequence of multiple commands sent to memory device 180, memory controller 150 may send data input / output commands to memory device 180 after a longer time interval or period than the minimum interval.

[0094] like Figure 1 and Figure 4 As described above, when the command scheduler 160 in the memory controller 150 is able to compare or check commands to be sent to the memory device 180 within a preset time range, in order to improve data input / output performance, the command scheduler 160 may send the second read command RD#2 to the memory device 180 in the 298th to 299th clock cycles (P1, P2), and sequentially send the third activation command ACT#3, the fourth precharge command PR#3, and the fourth activation command ACT#4 in the 300th to 304th clock cycles (P3, P0, P1, P2, P3).

[0095] Furthermore, when the transmission time of the second read command RD#2 is accelerated by one clock cycle, the transmission time of the third read command RD#3 can also be accelerated by one clock cycle. This process improves the data input / output operation of the memory system 110.

[0096] Figure 5 A scheduling method according to embodiments of the present disclosure is described. Figure 5 It is a description Figures 1 to 4 An example of the operation method of the command scheduler 160 described herein. According to an embodiment, the operation method of the command scheduler 160 in the memory system 110 may vary.

[0097] Reference Figure 5 The memory system 110 can schedule multiple commands at a specific operation point (stage n) (operation 210).

[0098] First, the memory system 110 can check whether there is a data input / output command to be issued (e.g., a read command or a write command, RD / WR) at the corresponding operating point, for example, the command that the memory controller 150 is about to send to the memory device 180 (i.e., is there an RD / WR that can be issued?) (Operation 212).

[0099] When a data input / output command exists at the corresponding operation point (Y in operation 212), the memory controller 150 may send the corresponding data input / output command to the memory device 180 (e.g., issue an RD / WR command) (operation 222). Afterwards, command scheduling at the corresponding operation point may be terminated (in stage n) (operation 220).

[0100] When no data input / output command is present at the corresponding operation time ("No (N)" in operation 212), the memory controller 150 may check whether there is an activation command ACT to be sent to the memory device 180 at the corresponding operation time (i.e., is there an ACT that can be issued?) (operation 214).

[0101] When an activation command exists at the corresponding operation time (Y in operation 214), the memory controller 150 can check whether there is a data input / output command (e.g., RD / WR) to be sent to the memory device 180 at the next operation time after the corresponding operation time (i.e., is there an RD / WR that can be issued in the next stage?) (operation 216).

[0102] If no data input / output command (e.g., RD / WR) is available to be sent to memory device 180 at the next operation time ("No (N)" in operation 216), memory controller 150 may send an activation command ACT to memory device 180 at the corresponding operation time (operation 218). Afterwards, command scheduling for the corresponding operation time may be terminated (operation 220).

[0103] When there is no activation command at the corresponding operation time ("No (N)" in operation 214), or when there is a data input / output command (e.g., RD / WR) to be sent to memory device 180 at the next operation time ("Yes (Y)" in operation 216), memory controller 150 may not send an activation command to memory device 180 at the corresponding operation time (but may send a precharge command (e.g., PRE) etc.) (operation 224).

[0104] When the activation command is not sent to memory device 180 at the corresponding operation time (operation 224), memory controller 150 may change the order of commands to be sent to memory device 180 in response to the type of command, the minimum interval between commands, or the time period, such as... Figure 1 and Figure 4 As described in [the text]. For example, as [the text is incomplete]. Figure 4 As described above, the memory controller 150 can postpone the order of commands other than data input / output commands, so that data input / output commands can be sent to the memory device 180 earlier.

[0105] Figure 6 The scheduling effect according to an embodiment of the present disclosure is illustrated. As an example, Figure 6 The data input / output performance of memory system 110 is shown to vary with... Figures 1 to 5 The operation method of the memory system 110 described herein varies. Figure 4 similar, Figure 6 An example is shown where the burst length (BL) of DDR5 is 16 and the minimum time interval or period of read commands (RD command interval) is 8 clock cycles (i.e. 8 Clk).

[0106] First, in the case of a conventional memory system that does not perform scheduling of multiple commands (i.e., the conventional case), the first read command RD1 can be sent to the memory device 180 at the first and second clock points (e.g., CK0-CK1). Subsequently, the first activation command ACT1 can be sent to the memory device 180 at the eighth and ninth clock points (e.g., CK7-CK8). Figure 6 During the interval, the activation command is represented by AT), and the second read command RD2 can be sent to the memory device 180 at the tenth and eleventh clock points (e.g., CK9-CK10). Multiple activation commands ACT1, ACT2, ACT3, ACT4 and multiple read commands RD1, RD2, RD3, RD4, RD5 can be sent to the memory device 180 sequentially. The fifth read command RD5 can be sent to the memory device at the 37th to 38th clock points (e.g., CK36-CK37).

[0107] Conversely, according to an embodiment of this disclosure (i.e., the embodiment scenario), when a data input / output command is scheduled to be sent after an activation command, the memory controller 150 may send the data input / output command to the memory device 180 before the activation command. The memory controller 150 may send a first read command RD1 to the memory device 180 at a first to second clock point (e.g., CK0-CK1). Thereafter, the memory controller 150 may send a second read command RD2 to the memory device 180 at a ninth to tenth clock point (e.g., CK8-CK9) corresponding to the minimum interval or period of the read command, instead of sending the first activation command ACT1 to the memory device 180 at an eighth to ninth clock point (e.g., CK7-CK8). After sending the second read command RD2 to the memory device 180, the memory controller 150 may send the first activation command ACT1, scheduled to be sent to the memory device 180 at an eleventh to twelfth clock point (e.g., CK10-CK11), to the memory device 180. The memory controller 150 can change the order in which multiple activation commands ACT1, ACT2, ACT3, ACT4 and multiple read commands RD2, RD3, RD4, RD5 are sent to the memory device 180. Through this process, the memory controller 150 can send the fifth read command RD5 to the memory device 180 at clock points 33 to 34 (e.g., CK32-CK33).

[0108] Compared to conventional memory systems, the memory system 110 according to embodiments of this disclosure can advance the timing of sending the fifth read command RD5 from clock points 37-38 (e.g., CK36-CK37) to clock points 33-34 (e.g., CK32-CK33) (i.e., a difference of 4 clock cycles). This difference may become more significant as the memory system 110 processes multiple data input / output commands. Furthermore, various simulations can be performed to check (or confirm) that the memory system 110 can introduce at least a 2% difference in command transmission timing. This improvement becomes more pronounced as the computational load of the memory system 110 increases.

[0109] Figure 7 A data processing apparatus 400 according to an embodiment of the present disclosure is shown.

[0110] Reference Figure 7 The data processing device 400 can be implemented using a multi-chip package comprising multiple semiconductor devices or multiple semiconductor chips. According to an embodiment, the data processing device 400 may include a high-bandwidth memory (HBM) module 410. The HBM module 410 may correspond to... Figure 1 The memory system 110 described herein.

[0111] The data processing device 400 may include an interposer 406 disposed on a package substrate 408. The interposer 406 can provide a path for data communication between multiple devices or components. The interposer 406 can be used to simplify the manufacturing process of multi-chip packages supporting high-speed data communication and improve the signal quality of high-speed data communication. The HBM module 410 disposed on the interposer 406 may include multiple memory dies 414A to 414D and logic dies 412. Figure 7 The HBM module 410 described herein may include four memory dies 414A to 414D, but the number of memory dies may be 8, 12, 16, etc., depending on the performance required by the HBM module 410. According to an embodiment, each of the memory dies 414A to 414D may include a data storage region comprising volatile memory cells (e.g., DRAM, SRAM, etc.). According to an embodiment, multiple memory dies 414A to 414D may include data storage regions comprising different types of memory cells (e.g., volatile memory cells and non-volatile memory cells). For example, some of the memory dies 414A to 414D may be DRAM memory dies, while others may be NAND memory dies.

[0112] Multiple memory dies 414A to 414D can be stacked vertically and can correspond to multiple memory devices (e.g., Figure 1 (180 shown in the figure). Multiple memory dies 414A to 414D can transmit and receive data or signals via through-silicon vias (TSVs), thereby enabling vertical electrical connections between memory dies. Additionally, each of the multiple memory dies 414A to 414D may include microbumps for maintaining a gap with adjacent dies and ensuring electrical contact.

[0113] A host 402, connected to the HBM module 410 and configured to process data, can be placed (deployed or connected) on the intermediary layer 406. The host 402 may include a central processing unit (CPU), a graphics processing unit (GPU), or a system-on-a-chip (SoC). The host 402 may correspond to a connection to... Figure 1The external device (i.e., host 102) of the memory system 100 described herein. According to an embodiment, the HBM module 410 can be directly connected to the host 402 (e.g., CPU or GPU) and can increase bandwidth to bypass the memory controller. This architecture can reduce data transmission latency and improve system performance. For example, the host 402 (e.g., CPU or GPU) can send a data read / write request to the HBM module 410. The HBM controller included in the logic die 412 can analyze the request input from the host 402 and send the request to a specific memory bank included in a plurality of memory dies 414A to 414D. The specific memory bank included in the plurality of memory dies 414A to 414D can read or write the requested data via TSV and send the read data to the host 402, such as the CPU or GPU, via an intermediary layer 406. Additionally, the host 402 (e.g., CPU or GPU) can process the data output from the HBM module 410 and return the result (e.g., data) to the HBM module 410.

[0114] According to an embodiment, the HBM controller included in the logic die 412 may include Figure 1 The controller 150 and buffers 152 and 154 described herein. The HBM controller included in the logic die 412 can efficiently control the memory banks included in multiple memory dies 414A to 414D and manage data transmission based on the priority assigned to multiple data input / output requests.

[0115] In addition, the logic die 412 and the host 402 may include at least one component corresponding to the physical layer PHY, which is responsible for sending and receiving data or signals between the logic die 412 and the host 402.

[0116] Figure 8 Another data processing apparatus according to an embodiment of the present disclosure is shown.

[0117] Reference Figure 8 The data processing device may include a host 302 and a memory system (e.g., a computing high-speed link (CXL)). TM Device 310. The host 302 and memory system 310 can be connected via a computer memory link (e.g., CXL). TM The controller 312 within the memory system 310 may include a protocol or interface for data communication. Figure 1 The controller 150 and buffers 152 and 154 are described herein. Controller 312 can manage and control the memory device (or CXL) based on the priority assigned to multiple data I / O requests. TM Data I / O operations performed in memory device 314.

[0118] The memory system 310 can be designed to support memory-centric computing technologies. Memory-centric computing technologies can provide dynamically scalable shared memory, overcoming the limitations of large-capacity data processing performance and capacity inherent in CPU-centric systems, and meeting the needs or requirements of memory-decomposed systems. Therefore, system scalability can be flexibly maintained according to the requirements of data processing devices. Due to the explosive growth in data volume from emerging applications such as big data and artificial intelligence (AI), data processing devices, including at least one computing unit, can be designed or built to meet the demands of large-capacity, high-bandwidth memory or innovative architectural changes. The number of servers and memory devices may continue to increase to meet the corresponding growth in memory demand. Protocols or interfaces based on computer memory links can be provided to support large-capacity, high-bandwidth memory.

[0119] Memory decomposition can be an architectural solution that separates memory (e.g., memory devices) from compute nodes (e.g., compute devices), allowing system designers to flexibly expand additional memory capacity independently of each compute server while meeting the memory requirements of user applications. For example, compute servers with high memory utilization can use memory devices located further away from other nodes included in the decomposition group. Therefore, this decomposition scheme can manage or utilize resources more efficiently than a previously proposed dedicated CPU and memory architecture.

[0120] It can provide computer memory links (e.g., high-speed computing links, CXL) TM This accelerates the transition to a memory-decomposed architecture. Computer memory links (CCIs) are industry-supported cache-coherent interconnects (CCIs) for various processors, designed to efficiently expand memory capacity via memory semantic protocols. Unlike host memory 306, which is entirely dependent on the host central processing unit (e.g., CPU) 304, memory devices 314, connected to the host 302 via handshake communication through CXL-based protocols or interfaces, can include additional data or values ​​such as data processing engines, as memory.

[0121] The host 302 may include a host CPU 304 and a host memory 306. The number and configuration of the host CPU 304 and host memory 306 can vary depending on the performance, operational requirements, operating speed, and data I / O speed of the host 302. The host CPU 304 and host memory 306 can send and receive data through a mutually agreed-upon communication interface protocol. This can be achieved using various communication standards or interfaces, such as those mentioned above. Figure 1According to an embodiment, host 302 and host memory 306 can be connected via a Universal Serial Bus (USB), which includes a scalable, hot-pluggable plug-and-play serial interface to provide connectivity to peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, and video conferencing cameras.

[0122] exist Figure 8 In this context, host 302 can utilize protocols or interfaces based on computer memory links (e.g., CXL). TM Protocol or CXL TM The interface communicates with the memory system 310. (CXL) TM Both CXL (Computing High-Speed ​​Link) and PCIe (PCIe High-Speed ​​Peripheral Component Interconnect) are standard interfaces used to connect peripheral devices and the CPU in a computer system. However, CXL TM There are several differences between CXL and PCIe. First, PCIe is designed as a standard for general-purpose input / output devices, while CXL... TM It is an interface specifically designed for memory access and high-speed data transmission in high-performance computing environments. Therefore, CXL TM Designed to allow the CPU direct access to the device's memory, PCIe may have limited such functionality. Furthermore, PCIe uses a unidirectional communication method, while CXL... TM It can support bidirectional communication. For example, CXL TM The device can simultaneously support sending and receiving data. Due to the CXL... TM The design aims to maintain backward compatibility with PCIe, thus allowing the use of a proposed PCIe infrastructure for the design or implementation of CXL. TM Device.

[0123] According to an embodiment, the memory device 314 (e.g., CXL) allocated to the host central processing unit (CPU) 304 is different from the host memory 306. TM Data communication in memory devices may have limited interface bandwidth. For example, when using DDR4 and DDR5 DIMMs as host memory 306, the DIMM has a 64-bit (i.e., 8-byte) data width. For DDR4, the maximum bandwidth can be 25.6 GB / s (= 3.2 Gbps × 8 bytes), and for DDR5, the maximum bandwidth can be 38.4 GB / s (= 4.8 Gbps × 8 bytes) or 51.2 GB / s (= 6.4 Gbps × 8 bytes). Therefore, when the storage capacity of each chip is 64 Gb, the interface bandwidth can be 0.4 s. -1 (=25.6GB / s / 64GB) and 0.6s -1(=38.4GB / s / 64GB) or 0.8s -1 (=51.2GB / s / 64GB). On the other hand, the interface bandwidth of the memory system 310 may be very limited, at 0.0625s. -1 (=32GB / s (@PCIe 5.0 x 8) / 512GB). This bandwidth difference limits the input / output performance of data processing devices.

[0124] To overcome the above problems, the memory system 310 may include a controller 312 (e.g., CXL). TM A kernel is designed and used for near data processing (NDP). Near data processing (NDP) is a computing scheme that improves or enhances the efficiency of data processing. Near data processing (NDP) can be based on a configuration in which a controller 312 (e.g., at least one processor or core that processes data) is arranged or located near a data storage device or memory (e.g., memory device 314).

[0125] In one proposed computing model, the host CPU 304 retrieves data from a memory device 314 connected to expand the host memory 306, processes the data, and stores the results back to the memory device 314. However, in applications requiring the processing of large amounts of data, this approach can lead to a bandwidth bottleneck between the memory device 314 and the host CPU 304. To address this issue, near-data processing (NDP) can be designed to place the controller 312 (e.g., a processor that processes data) near the memory device 314 where the processed data is stored. That is, instead of moving data from the memory device 314 to the host CPU 304, the processor performing the data processing, i.e., the controller 312, is included within the memory system 310, which serves as the data location. This configuration can significantly reduce or avoid latency and energy consumption caused by data movement.

[0126] Unlike memory system 310, host memory 306 can be used for in-memory processing of the host CPU 304. In-memory processing allows as much data as possible to be stored in host memory 306 and reduces latency caused by disk I / O (e.g., memory system I / O). In this configuration, host memory 306 can provide excellent performance for database work, real-time analytics, and other applications. However, host memory 306 is expensive and has limited capacity, which can limit its ability to process very large datasets. Therefore, data processing devices can overcome some of the operational and performance limitations of host memory 306 by using memory system 310, which includes controller 312 for near-data processing (NDP).

[0127] As described above, according to embodiments of the present disclosure, a memory device or memory system can improve the data input / output performance of a memory device or memory system by scheduling to efficiently send multiple multi-clock commands while satisfying the minimum burst period or minimum column command delay period (e.g., column-to-column delay, tCCD).

[0128] Furthermore, according to embodiments of the present invention, the data input / output performance of a memory device or memory system can be improved by a scheduling device and operation method that changes the transmission order of multiple adjacent commands based on the command type. This scheduling device and operation method has the advantages of low scheduling resource consumption and low operation latency caused by scheduling.

[0129] The methods, processes, and / or operations described herein can be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. This computer, processor, controller, or other signal processing device can be the apparatus described herein or elements other than those described herein. Because the algorithms that form the basis of the methods or the operation of the computer, processor, controller, or other signal processing device are described in detail, the code or instructions used to implement the operations of embodiments of the method can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0130] Alternatively, another embodiment may include a computer-readable medium for storing the aforementioned code or instructions, such as a non-transitory computer-readable medium. The computer-readable medium may be a volatile or non-volatile memory or other storage device that may be removably or permanently coupled to a computer, processor, controller, or other signal processing device that is to execute the code or instructions for performing the operations of the method or apparatus embodiments described herein.

[0131] For example, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features disclosed herein can be implemented with non-transient logic that may include hardware, software, or both. For example, when implemented at least partially in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features can be any of a variety of integrated circuits, including but not limited to application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), combinations of logic gates, systems-on-a-chip (SoCs), microprocessors, or other types of processing or control circuits.

[0132] For example, when implemented at least partially in software, controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may include memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be the device described herein or may be elements other than those described herein. Because the algorithms that form the basis of the methods or operations of the computer, processor, microprocessor, controller, or other signal processing device are described in detail, the code or instructions for implementing the operations of embodiments of the method can transform the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods described herein.

[0133] Although the invention has been described and illustrated with reference to specific embodiments, it will be apparent to those skilled in the art, based on this disclosure, that various changes and modifications may be made without departing from the spirit and scope defined in the appended claims. Furthermore, these embodiments may be combined to form other embodiments.

Claims

1. A memory system, comprising: A memory device, including at least one data storage area; as well as A memory controller, coupled to the memory device, sends at least one command scheduled to be sent within a preset clock range to the memory device. Wherein, when the command to be sent after the activation command to be included in the at least one command is not a data input and output command, i.e., a data input / output command, the memory controller sends the activation command to the memory device.

2. The memory system according to claim 1, wherein, The data input / output commands include at least one of read commands and write commands, and When the command to be sent after the activation command is the data input / output command, the memory controller sends the data input / output command to the memory device before the activation command.

3. The memory system according to claim 1, wherein, The activation command and the data input / output command are multi-clock commands to be sent over multiple clock cycles.

4. The memory system according to claim 1, wherein, The preset clock range includes at least four clock cycles.

5. The memory system according to claim 1, wherein, The at least one command includes a precharge command, which is a single-clock command to be sent within a single clock cycle, and Regardless of the order in which the data input / output commands are sent, the controller sends the precharge command to the memory device.

6. The memory system according to claim 1, wherein, When the activation command is the command to be sent after the data input / output command, the memory controller sends the data input / output command to the memory device before the activation command.

7. The memory system according to claim 1, wherein, The at least one data storage area includes multiple storage units, and The activation command and the data input / output command are sent to different storage units among the plurality of storage units.

8. The memory system according to claim 1, wherein, The data input / output commands have a minimum burst period or minimum column command delay period that is longer than the preset clock range.

9. The memory system according to claim 8, wherein, The minimum column command delay period comprises eight clock cycles.

10. A method of operating a memory system, comprising: Determine at least one command to be scheduled to be sent to a memory device within a preset clock range, the memory device including at least one data storage area; as well as The activation command is sent to the memory device when the command to be sent after the activation command to be included in the at least one command is not a data input and output command, i.e., a data input / output command.

11. The method of claim 10, further comprising: When the command to be sent after the activation command is a data input / output command included in at least one of the commands, the data input / output command is sent to the memory device before the activation command.

12. The method according to claim 10, wherein, The data input / output commands include at least one of a read command and a write command.

13. The method according to claim 10, wherein, The activation command and the data input / output command are multi-clock commands to be sent over multiple clock cycles.

14. The method of claim 10, wherein, The preset clock range includes at least four clock cycles.

15. The method according to claim 10, wherein, The at least one command includes a precharge command, which is a single-clock command to be sent within a single clock cycle, and The method further includes sending the precharge command to the memory device regardless of the order in which the data input / output commands are sent.

16. The method of claim 10, wherein, The at least one data storage area includes multiple storage units, and The activation command and the data input / output command are sent to different storage units among the plurality of storage units.

17. The method according to claim 10, wherein, The data input / output commands have a minimum burst period or minimum column command delay period that is longer than the preset clock range.

18. The method according to claim 17, wherein, The minimum column command delay period comprises eight clock cycles.

19. A command scheduler coupled to a memory device, the memory device including at least one data storage area, wherein, The command scheduler determines the transmission timing of at least one command scheduled to be sent within a preset clock range. When the command to be sent after the activation command included in the at least one command is not a data input / output command, the command scheduler sends the activation command to the memory device.

20. The command scheduler according to claim 19, wherein, The activation command and the data input / output command are multi-clock commands to be sent over multiple clock cycles, and The data input / output commands include at least one of a read command and a write command.

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