A solid state disk data writing method

Abstract

The application discloses a solid state disk data writing method. The method comprises the following steps: intercepting a plurality of read-write I / O requests issued by an application layer, reconstructing a history action state transition sequence according to a logical data container identifier, compressing the read-write instruction into a fixed length, adding a label, injecting a storage bus protocol instruction control block, and delivering the storage bus protocol instruction control block to a storage device; the storage device extracts the label and maps it to a physical address continuous linear storage space to assemble a scheduling descriptor, executes a priority rearrangement on the scheduling descriptor by using a microprocessor to execute a hardware parallel instruction, and converts the scheduling descriptor into a physical operation signal; quantifying the edge queuing cost scalar value of each bottom layer physical channel in real time, determining the routing destination by a formal logic isolation equation according to the label attribute; extracting the physical telemetry characteristic value of the physical operation signal by a hardware probe and calculating the deviation, and implementing physical level interception before programming voltage is applied. The data writing efficiency and safety are improved.

Description

Technical Field

[0001] This application relates to the field of solid-state storage device technology, and specifically to a method for writing data to a solid-state drive. Background Technology

[0002] Solid-state drives (SSDs) use NAND flash memory as their storage medium, offering advantages such as low latency and high throughput. A unified data placement framework maps strictly ordered data to sequentially isolated physical regions and randomly updated data to tag-based isolated random write streams, aiming to eliminate garbage collection overhead.

[0003] However, in high-concurrency production environments, severe congestion in the static random access memory (SRAM) within the storage device controller can cause instruction pipeline stalls. Traditional firmware uses pointer-based dynamic data structures to manage the mapping state of logical data containers, frequently allocating and releasing nodes in the limited SRAM capacity. This leads to physical memory fragmentation and frequent cache misses in the microprocessor's L1 cache, causing tail latency to deteriorate from microseconds to milliseconds. Furthermore, static hashing or round-robin routing algorithms cannot detect the dynamic congestion state of physical channels, easily causing uneven load distribution. When host software crashes or suffers malicious attacks, unauthorized write commands may disrupt the sequential physical isolation area, triggering time-consuming garbage collection and affecting system stability. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a solid-state drive (SSD) data writing method, aiming to solve the problems of controller internal scheduling congestion, uneven physical channel load, and difficulty in isolating abnormal writes in the prior art.

[0005] The method described in this application includes the following steps: Intercept multiple read / write I / O requests issued by the application layer, and reconstruct the basic action states corresponding to the multiple read / write I / O requests into a historical action state transition sequence based on the logical data container identifier; The historical action state transition sequence is compressed into a fixed-length read / write instruction with an attached tag, and injected into the storage bus protocol instruction control block and sent to the storage device. The storage device extracts the instruction control block carrying the additional tags of the read and write instructions, maps it to a linear memory space with contiguous physical addresses to assemble a scheduling descriptor, uses the microprocessor to execute hardware parallel instructions to perform priority rearrangement on the scheduling descriptor, and converts it into physical operation signals for the flash memory medium. The edge queuing cost scalar value of each underlying physical channel is quantified in real time, and the route destination is determined by formal logical isolation equation based on the tag attribute attached to the read and write instructions, so as to transmit the physical operation signal to the route destination to perform the programmed solidification operation. The target logic block address and related timing characteristics carried in the physical operation signal entering the route destination are extracted by hardware probes and used as physical telemetry feature values. Based on the deviation between the physical telemetry feature values ​​and the static security reference point constant, the physical operation signal is physically intercepted before the programming voltage required to perform the programming and solidification operation at the route destination is applied.

[0006] Furthermore, the reconstruction into a historical action state transition sequence includes: recording the timestamp of each action state occurrence; and concatenating all basic action states belonging to the same logical data container identifier in chronological order to form the historical action state transition sequence.

[0007] Furthermore, the step of compressing the historical action state transition sequence into a fixed-length read / write instruction additional tag includes: performing statistical analysis on the historical action state transition sequence using a probabilistic finite state machine to synthesize a rule path matcher; and aligning the rule path matcher to an 8-byte fixed-length space using a hash mapping and dimensionality reduction algorithm to generate the read / write instruction additional tag.

[0008] Furthermore, the step of mapping it to a linear memory space with contiguous physical addresses to assemble the scheduling descriptor includes: pre-allocating a global memory region with absolutely contiguous physical addresses in the static random access memory of the memory controller as the linear memory space; padding the read and write instructions with tags combined with the global hardware clock cycle to form a 16-byte address-aligned scheduling descriptor and storing it in the linear memory space.

[0009] Furthermore, the step of using the microprocessor to execute hardware parallel instructions to prioritize the scheduling descriptors and convert them into physical operation signals for the flash memory medium includes: using the microprocessor's vectorized registers to load the priority fields of multiple scheduling descriptors in parallel and executing arithmetic comparison instructions; executing vector permutation instructions to batch shift and rearrange the scheduling descriptors that meet the conditions based on the comparison results; and when it is detected that the number of scheduling descriptors in the linear storage space is lower than a preset number threshold, switching to the microprocessor's data cache linear scan mode to locate the target descriptor and output the physical operation signal.

[0010] Furthermore, the real-time quantization of the edge queuing cost scalar value of each underlying physical channel includes: obtaining the number of physical operation signals in the suspended state within the physical channel, and calculating the corresponding expected queuing waiting time based on the number; obtaining the health index of the physical channel to calculate the physical loss delay, and linearly weighting the expected queuing waiting time and the physical loss delay to obtain the edge queuing cost scalar value.

[0011] Furthermore, the real-time quantification of the edge queuing cost scalar value of each underlying physical channel also includes: periodically sampling the average write duration of the physical channel, and dynamically adjusting the weight of the expected queuing wait time in the edge queuing cost scalar value based on the average write duration.

[0012] Further, the step of extracting the target logical block address and related timing features carried in the physical operation signal entering the routing destination through the hardware probe as a physical telemetry feature value includes: capturing the target logical block address of the current physical operation signal and the target logical block address of the previous physical operation signal through the hardware probe, calculating the absolute address jump span between the two; and recording the absolute clock cycle difference of adjacent physical operation signals arriving at the designated physical channel as the physical telemetry feature value.

[0013] Furthermore, the deviation between the physical telemetry feature value and the static safety reference point constant includes: inputting the physical telemetry feature value into a pre-compiled tree-like mathematical discrimination formula with a nesting depth of no more than six layers to perform a combination operation to output a judgment scalar; and calculating the arithmetic difference between the judgment scalar and the static safety reference point constant to obtain the deviation.

[0014] Furthermore, the implementation of physical-level interception includes: when the deviation exceeds a preset hardware tolerance threshold, forcibly cutting off the programming instruction writing timing of the target 3D flash memory chip to prevent the application of programming high voltage; and reporting an asynchronous event notification to the host to indicate that the access corresponding to the logical data container identifier has caused a logical out-of-bounds violation of physical channel attributes. Attached Figure Description

[0015] To more clearly illustrate the solution of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart illustrating a solid-state drive data writing method according to an embodiment of this application.

[0017] Figure 2 This is a schematic diagram of continuous memory scheduling and parallel priority rearrangement in step 30.

[0018] Figure 3 for Figure 1 A flowchart of step 40.

[0019] Figure 4 for Figure 1 A flowchart of step 50. Detailed Implementation

[0020] The technical solutions in this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0021] The method described in this application is applied to a system including a host computer and a solid-state drive (SSD). The host computer runs an operating system, which includes block device drivers. The SSD comprises a controller, static random access memory (SRAM), multiple physical flash memory channels, and a three-dimensional flash memory medium coupled to each channel. In high-concurrency mixed read / write scenarios, traditional firmware uses pointer-based dynamic data structures (such as linked lists and red-black trees) to manage logical data containers, leading to SRAM fragmentation and frequent cache misses in the microprocessor's L1 cache, with tail latency deteriorating from microseconds to milliseconds. Static routing algorithms cannot detect physical channel congestion and lack hardware-level protection against unauthorized writes. Once an anomaly occurs, time-consuming garbage collection is triggered, causing severe fluctuations in system performance.

[0022] To address the aforementioned technical problems, this application provides a method for writing solid-state drive (SSD) data from host-side semantic recognition to storage device-side physical isolation. For example... Figure 1 As shown, the method includes five steps executed sequentially: step 10, step 20, step 30, step 40, and step 50. Each step is described in detail below with reference to the accompanying drawings.

[0023] Step 10: Intercept multiple read / write I / O requests issued by the application layer, and reconstruct the basic action states corresponding to the multiple read / write I / O requests into a historical action state transition sequence based on the logical data container identifier.

[0024] This step aims to categorize and sort the unordered read / write I / O requests issued by the application layer according to logical data containers, forming a predictable historical action sequence, and providing the raw data foundation for subsequent semantic compression.

[0025] Specifically, the block device driver within the host operating system intercepts multiple read / write I / O requests issued by the application layer in real time. Each read / write I / O request corresponds to a logical data container, which is distinguished by a unique logical data container identifier (ID). The driver categorizes each I / O request into four basic action states based on the request type: container creation, append write, status read, and container destruction.

[0026] To form predictable time series, this step further includes: Record the timestamp of each action state occurrence; All basic action states belonging to the same logical data container identifier are concatenated in chronological order to form the historical action state transition sequence.

[0027] For example, the lifecycle of a typical log data container might look like this: "Creation" → "Four consecutive append writes" → "Long period of inactivity" → "Single status read" → "Container destruction". This sequence fully preserves the temporal characteristics of data access, providing raw material for subsequent semantic compression.

[0028] Step 20: Compress the historical action state transition sequence into a fixed-length read / write instruction with an attached tag, and inject it into the storage bus protocol instruction control block to send it to the storage device.

[0029] This step aims to compress the variable-length historical action state transition sequence into an 8-byte fixed-length tag, enabling it to be embedded in the instruction control block of the standard storage protocol and sent to the storage device. This allows the storage device to anticipate the lifecycle attributes of the data without increasing bus overhead.

[0030] Specifically, in a low-priority thread in the host's background, a probabilistic finite state machine (PFSM) statistical analysis is performed on massive historical action state transition sequences. Specifically, the frequency percentage of transitions between any two basic action states is calculated, constructing a directed graph with transition probability attributes. To eliminate abnormal noise, a transition probability threshold (e.g., 5%) is set, and transition branches below this threshold are forcibly pruned. The pruned high-confidence state machine can be transformed into a deterministic rule path matcher (i.e., a regular expression). For example, for the aforementioned log data container, its rule expression can be expressed as: (append write)^{3,6} → (state read) → (container destruction).

[0031] Because the length of the rule path matcher is not fixed, it cannot be directly embedded into a fixed-length storage protocol instruction block. Therefore, this step uses a two-stage feature extraction process to compress it into an 8-byte fixed-length tag: The first stage (high-dimensional mapping) involves establishing a global feature dictionary that maps all possible generated rule path expressions into a high-dimensional feature vector, thus fully preserving the data lifecycle evolution relationship.

[0032] The second stage (dimensionality reduction and alignment): using hash mapping and dimensionality reduction statistical algorithms (such as locality-sensitive hashing), the high-dimensional feature vector is aligned to a 64-bit (8-byte) low-dimensional space to generate the final read and write instruction append tags.

[0033] This compression process allows the host to accurately characterize the future access trajectory of data with minimal space overhead by simply performing a table lookup operation.

[0034] The block device driver directly injects this 8-byte fixed-length tag into the "Extended Payload" reserved field of the instruction control block of a standardized storage bus protocol (such as NVMe). Subsequently, read / write instructions carrying this tag are written to the shared commit queue between the host and the storage device, and the doorbell register is set to notify the storage device controller to retrieve and execute them. Because the tag is fixed at 8 bytes, no additional data transfer cycles are added, and it is fully compatible with existing protocol stacks.

[0035] Step 30: The storage device extracts the instruction control block carrying the additional tag of the read and write instructions, maps it to a linear memory space with contiguous physical addresses to assemble a scheduling descriptor, uses the microprocessor to execute hardware parallel instructions to perform priority rearrangement on the scheduling descriptor, and converts it into physical operation signals for the flash memory medium.

[0036] This step aims to completely eliminate pointer jumps and dynamic memory allocation in traditional firmware, map instructions to a linear memory space with contiguous physical addresses, and use the microprocessor's SIMD instructions for hardware-level parallel sorting, fundamentally eliminating memory fragmentation and cache misses, and achieving microsecond-level deterministic scheduling.

[0037] like Figure 2 As shown, this step performs lock-free concurrent scheduling within the SRAM of the storage device controller.

[0038] First, the scheduling descriptor is assembled: the controller's front-end Direct Memory Access (DMA) engine fetches the instruction control block from the shared commit queue using zero-copy, parsing out the 8-byte read / write instruction appended tag. Simultaneously, the controller reads the current global hardware clock cycle value and extracts its lower 32 bits as a timestamp. The 8-byte tag is then combined with the 4-byte timestamp to form a scheduling descriptor strictly aligned to 16-byte addresses. This descriptor also contains the data's lifecycle attributes and arrival timing information.

[0039] In the SRAM of the storage controller, this step pre-allocates a contiguous global memory region as a linear storage space. Scheduling descriptors are then appended compactly to this linear storage space in arrival order, such as... Figure 2 As shown. The entire process does not involve any malloc / free or linked list node insertion operations, thus fundamentally eliminating the generation of memory fragmentation.

[0040] By recording the start and end offsets of different priority segments in the linear memory space using a set of preset reference tag registers (i.e., reference tag register group), multiple priority buckets are implicitly divided on the physically contiguous linear memory space. This partitioning method does not rely on any pointers and can be located solely through physical offsets, enabling the microprocessor to maintain excellent spatial locality during access.

[0041] Then, SIMD parallel comparison and vector permutation are performed: the microprocessor uses its built-in 128-bit SIMD registers to perform the following operations: Vectorized register bulk loading: Using a single hardware load instruction, the priority fields (32 bits each) of four scheduler descriptors are read from the linear memory space at once and filled into the 128-bit SIMD register.

[0042] Hardware-level parallel arithmetic comparison: The microprocessor issues a parallel comparison instruction to the arithmetic logic unit (ALU) to simultaneously compare the four priority fields with the baseline threshold of the current scheduling cycle. This operation produces four Boolean comparison results within one clock cycle.

[0043] Vector permutation and batch shift: Based on the comparison results, the vector permutation instruction is executed to extract the descriptors that meet the high priority conditions through register shift operations, and then use contiguous memory block copy instructions (instead of changing the pointers) to move them in batches to the physical front of the high priority bucket.

[0044] Figure 2 The diagram illustrates the change in the order of elements in the linear storage space before and after rearrangement: After the above operation, the originally messy Desc1 to Desc6 elements are moved to the front of the linear storage space by the higher priority Desc3, Desc1, and Desc6, thus achieving lock-free priority sorting.

[0045] Finally, a degraded linear scan is performed: the firmware monitors the actual fill depth of each priority bucket in the linear storage space in real time. When the number of scheduling descriptors in a high-priority bucket is lower than a preset threshold (set to 16 elements in this embodiment), the microprocessor stops executing complex parallel rearrangement logic and switches to a direct linear scan of the linear storage space region where the bucket is located.

[0046] In this mode, because the data addresses are absolutely contiguous and the bucket size is much smaller than the capacity of the L1 data cache, the cache miss rate during the scan is zero, and the L1 data cache hit rate of the microprocessor reaches 100%. After the scan locates the descriptor with the most urgent timestamp, it is immediately converted into physical operation signals for the flash memory medium, including timing signals such as chip select enable, command latch enable, and address latch enable, which are then executed by the back-end flash interface controller.

[0047] Step 40: Quantify the edge queuing cost scalar value of each underlying physical channel in real time, and determine the route destination through formal logical isolation equations based on the tag attributes attached to the read and write instructions, so as to transmit the physical operation signal to the route destination to perform the programming solidification operation.

[0048] This step aims to quantify the dynamic congestion level of each physical channel in real time, and select the channel with the least latency for writing while ensuring physical isolation between sequential and random data, thus achieving the dual goals of load balancing and semantic isolation.

[0049] like Figure 3 As shown, this step integrates dynamic congestion quantization and formal isolation constraints in the physical channel selection process to achieve deterministic low-latency routing.

[0050] First, there is the real-time quantification of edge queuing costs: the hardware status polling module inside the controller periodically (e.g., every few clock cycles) directly reads the depth of the "physical operation signal in a suspended state" register for each physical flash channel.

[0051] 1. Estimated queuing time: Multiply the number of currently pending instructions read by the factory-calibrated average clock cycles required to execute this type of instruction on the underlying physical medium to obtain the absolute queuing time T. wait =N pending ×T cycle_avg .

[0052] 2. Physical Wear Delay Calculation: The controller detects the wear (number of erases) and remaining capacity of the physical blocks currently being written to the physical channel, and estimates the block erase delay penalty T that may be triggered soon. erase_penalty This value increases with increasing wear.

[0053] 3. Linear Weighting: The absolute queuing waiting time and the erase delay penalty are linearly weighted and summed to obtain the edge queuing cost Cost = T. wait +α⋅T erase_penalty , where α is a configurable weighting coefficient.

[0054] Furthermore, to adapt to dynamic changes in load, in some embodiments, this step may also include: periodically sampling the average write duration of the physical channel and dynamically adjusting the weight of the estimated queuing wait time in the edge queuing cost based on the average duration. For example, when the recent write latency of a channel is significantly higher than the factory calibration value, the weight of its queuing wait time is automatically increased, making it easier to avoid.

[0055] Then, a formal logical isolation equation is performed: before pursuing the lowest latency, it is essential to ensure that the physical placement of data conforms to the absolute isolation requirements of the upper-layer storage semantics. This step transforms the data placement rules into Boolean logic inequalities and quickly solves for the candidate channel mask using bitwise AND operations.

[0056] Specifically, the controller embeds a compile-time determined logic solver that takes attribute bits of the attached label as input and outputs a bitmap mask. For example: 1. If the additional tag indicates the "long lifespan read-only" or "sequential append" attribute, the Boolean inequality requires that the candidate physical channel must belong to the channel set that is pre-initialized as "sequential physical isolation zone".

[0057] 2. If the additional label indicates the "Random Update" attribute, the Boolean inequality requires that the candidate physical channel must belong to the channel set that is pre-initialized as "Multi-stream Random Physical Isolation Zone".

[0058] In actual hardware implementation, the solver only needs to perform a few parallel bitwise AND operations: performing an AND operation between the full-channel state bitmap and a pre-stored sequential isolation mask (or random isolation mask) yields the candidate channel mask that meets the isolation conditions. The entire process does not consume any additional software instruction cycles.

[0059] Finally, optimal channel determination and physical drive are performed: the real-time calculated global edge queuing cost table is logically ANDed with the above candidate mask (i.e., unqualified channels are masked), resulting in a cost list containing only valid channels. Subsequently, the controller uses a hardware-level comparator tree to perform a single fast traversal of this list, directly selecting the physical channel with the lowest edge queuing cost as the sole optimal route destination for the current read / write request.

[0060] Once the determination is complete, the controller skips all intermediate software state updates and directly drives the underlying circuitry: triggering the chip select enable, command latch enable, and address latch enable signals of the selected physical channel, and using direct memory access (DMA) to load the data to be written into the page cache inside the target flash memory chip at the highest frequency of the physical bus, immediately executing the programming and hardening operation.

[0061] Step 50: Extract the target logic block address and related timing features carried in the physical operation signal entering the route destination using a hardware probe, and use them as physical telemetry feature values; and based on the deviation between the physical telemetry feature values ​​and the static security reference point constant, perform physical-level interception on the physical operation signal before the programming voltage required to perform the programming and solidification operation at the route destination is applied.

[0062] This step, as the last line of defense, does not rely on any upper-layer software tags. It identifies and intercepts illegal write commands based solely on physical layer write characteristics (address jump span and time interval) before the high pressure of programming is applied, fundamentally avoiding the triggering of garbage collection and ensuring the physical security of data isolation.

[0063] Specifically, such as Figure 4 As shown, this step involves setting up an independent hardware probe at the physical channel entrance to achieve nanosecond-level interception of unauthorized writes.

[0064] First, physical telemetry feature values ​​are extracted: a hardware probe is set up in bypass mode of the direct memory access (DMA) controller. This probe monitors write commands entering each physical channel in real time and extracts the following two features: 1. Absolute Address Jump Span: Capture the target logical block address (LBA) of the current instruction and the target logical block address (LBA) of the previous instruction, and directly calculate the difference between the two using a hardware subtractor. This value reflects the spatial continuity of the write stream: the jump span of sequential writes is stable within a small range, while random writes exhibit large-scale, irregular jumps.

[0065] 2. Absolute Clock Cycle Difference: This value records the absolute clock cycle difference between two adjacent write commands arriving at the same physical channel using the controller's internal hardware timer. This value reflects the temporal density of the write stream.

[0066] These two characteristic values ​​are latched into a dedicated monitoring register in real time as physical telemetry characteristic values ​​of the current I / O stream, without interrupting the main data path.

[0067] Then, a pre-compiled tree-structured formula is used for dimensionality reduction: the controller loads a pre-compiled tree-structured mathematical discriminant formula from read-only memory. This formula consists of cascaded basic arithmetic operators (addition, subtraction, multiplication) and comparison operators (greater than, less than). Its nesting depth is strictly limited to no more than 6 levels during compilation to ensure that any combination of input variables can output a deterministic result within 50 hardware clock cycles.

[0068] like Figure 4 As shown, the address jump span and clock cycle difference captured in step 50 are substituted into the tree formula as leaf node variables to perform combined operations (e.g., calculating the moving variance of the address jump span within a specific time window). After pipelined operation for a fixed clock cycle, the root node of the tree formula outputs a scalar value, which is a dimensionality-reduced scalar representing the "random disorder" of the current data stream.

[0069] Then, a static safety baseline deviation comparison is performed: the controller reads the static safety baseline constant, which is derived from a large number of standard tests and statistics before leaving the factory, from its firmware parameter table. This constant typically includes two values: 1. A sequential write reference point constant representing the "standard strict sequential write" characteristic distribution (e.g., the address jump span is stable within 1 to 8 logical block addresses (LBA), and the clock cycle difference is a fixed period value).

[0070] 2. Random write reference point constants representing the "standard multi-stream independent random write" characteristic distribution (e.g., address jump spans are evenly distributed throughout the address space).

[0071] The hardware subtractor performs arithmetic subtraction on the real-time output of the dimensionality-reduced scalar and the corresponding baseline constant (selected according to the expected write type of the current instruction) to obtain the absolute deviation value Δ=∣Sreal−Sbase∣.

[0072] Finally, hard threshold judgment and physical-level interception are performed: the above absolute deviation value is compared with the preset hardware tolerance threshold (i.e., the configurable threshold register value set at the factory based on the physical characteristics of flash memory): If the deviation is less than the threshold, the current instruction is deemed valid and allowed to proceed. The flash memory interface logic applies programming voltage normally to complete data persistence.

[0073] If the deviation value is greater than or equal to the threshold, the current instruction is determined to be an illegal write (e.g., an attempt to send a drastically random overwrite instruction to a sequential physical isolation zone), and the bypass interception trigger level is immediately raised.

[0074] Upon detecting a high interception level, the flash interface logic forcibly cuts off the programming instruction write timing before the high voltage for programming the 3D flash memory chip is applied. Even if data has already been loaded into the flash page cache by DMA, the system will silently discard the data, absolutely prohibiting the application of high voltage for programming to the flash memory cell. After the interception action is completed, the controller writes the identifier of the abnormal read / write instruction to the hardware exception status register and immediately pushes an asynchronous event notification to the shared completion queue between the host and the storage device, informing the host that the logical data container has experienced a logical out-of-bounds violation of the physical channel attributes and has been forcibly isolated by the underlying hardware. The normal write path then directly completes the programming and hardening process.

[0075] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0076] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0077] In this application, unless otherwise stated, directional terms such as "up" and "down" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction; similarly, for ease of understanding and description, "left" and "right" are generally used in relation to the left and right shown in the accompanying drawings; "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit this application.

[0078] The above description is merely an exemplary embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope described in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for writing data to a solid-state drive, characterized in that, include: Intercept multiple read / write I / O requests issued by the application layer, and reconstruct the basic action states corresponding to the multiple read / write I / O requests into a historical action state transition sequence based on the logical data container identifier; The historical action state transition sequence is compressed into a fixed-length read / write instruction with an attached tag, and injected into the storage bus protocol instruction control block and sent to the storage device. The storage device extracts the instruction control block carrying the additional tags of the read and write instructions, maps it to a linear memory space with contiguous physical addresses to assemble a scheduling descriptor, uses the microprocessor to execute hardware parallel instructions to perform priority rearrangement on the scheduling descriptor, and converts it into physical operation signals for the flash memory medium. The edge queuing cost scalar value of each underlying physical channel is quantified in real time, and the route destination is determined by formal logical isolation equation based on the tag attribute attached to the read and write instructions, so as to transmit the physical operation signal to the route destination to perform the programmed solidification operation. The target logical block address and related timing features carried in the physical operation signal entering the route destination are extracted by hardware probes and used as physical telemetry feature values. Based on the deviation between the physical telemetry characteristic value and the static security reference point constant, the physical operation signal is physically intercepted before the programming voltage required to perform the programming and solidification operation at the route destination is applied.

2. The method according to claim 1, characterized in that, The reconstruction is a historical action state transition sequence, including: Record the timestamp of each action state occurrence; All basic action states belonging to the same logical data container identifier are concatenated in chronological order to form the historical action state transition sequence.

3. The method according to claim 2, characterized in that, The step of compressing the historical action state transition sequence into a fixed-length read / write instruction with an attached tag includes: The historical action state transition sequence is statistically analyzed using a probabilistic finite state machine to synthesize a rule path matching symbol; The rule path matcher is aligned to an 8-byte fixed-length space using hash mapping and dimensionality reduction algorithms to generate the additional tag for the read / write instruction.

4. The method according to claim 1, characterized in that, The process of mapping these to a linear memory space with contiguous physical addresses to assemble a scheduling descriptor includes: A globally contiguous area of ​​physical addresses is pre-allocated in the static random access memory of the storage controller as the linear storage space; The read / write instructions are padded with tags and combined with the global hardware clock cycle to form a 16-byte address-aligned scheduling descriptor, which is then stored in the linear storage space.

5. The method according to claim 4, characterized in that, The step of using a microprocessor to execute hardware parallel instructions to prioritize the scheduling descriptor and convert it into physical operation signals for the flash memory medium includes: The priority fields of multiple scheduling descriptors are loaded in parallel using the vectorized registers of the microprocessor, and arithmetic comparison instructions are executed. Based on the comparison results, a vector permutation instruction is executed to perform a batch shift and rearrangement of the scheduling descriptors that meet the conditions; When the number of scheduling descriptors in the linear storage space is detected to be lower than a preset threshold, the microprocessor switches to the data cache linear scan mode to locate the target descriptor and output the physical operation signal.

6. The method according to claim 1, characterized in that, The real-time quantization of the edge queuing cost scalar value for each underlying physical channel includes: The number of physical operation signals that are in a suspended state within the physical channel is obtained, and the corresponding estimated queuing waiting time is calculated based on the number. The health index of the physical channel is obtained to calculate the physical loss delay, and the expected queuing waiting time is linearly weighted and summed with the physical loss delay to obtain the scalar value of the edge queuing cost.

7. The method according to claim 6, characterized in that, The real-time quantization of the edge queuing cost scalar value of each underlying physical channel also includes: periodically sampling the average write duration of the physical channel, and dynamically adjusting the weight of the expected queuing wait time in the edge queuing cost scalar value based on the average write duration.

8. The method according to claim 1, characterized in that, The step of extracting the target logical block address and related timing features carried in the physical operation signal entering the route destination through a hardware probe, and using them as physical telemetry feature values, includes: The hardware probe captures the target logic block address of the current physical operation signal and the target logic block address of the previous physical operation signal, and calculates the absolute address jump span between the two. The absolute clock cycle difference between adjacent physical operation signals arriving at the designated physical channel is recorded as the physical telemetry characteristic value.

9. The method according to claim 1, characterized in that, The deviation between the physical telemetry feature value and the static safety reference point constant includes: The physical telemetry feature values ​​are input into a pre-compiled tree-structured mathematical discrimination formula with a nesting depth of no more than six layers to perform a combination operation, and a judgment scalar is output. The deviation is obtained by calculating the arithmetic difference between the determination scalar and the static safety reference point constant.

10. The method according to claim 1, characterized in that, The implementation of physical-level interception includes: When the deviation exceeds a preset hardware tolerance threshold, the programming instruction writing timing of the target 3D flash memory chip is forcibly cut off to prevent the application of high programming voltage; An asynchronous event notification is reported to the host to indicate that a logical out-of-bounds violation of physical channel attributes has occurred during the access corresponding to the logical data container identifier.

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