A memory, control method, and electronic device

Abstract

The present disclosure provides a memory, a control method and an electronic device, the memory comprising: a first external data port configured to receive data from outside the memory; or, send data stored by the memory to the outside; an external data selector configured to, when the memory is in a second mode, enable a data transmission path between a first data processing module and a shadow register to obtain data from the shadow register or write data to the shadow register; and when the memory is in a first mode, enable a data transmission path between the first data processing module and a first storage array coupled thereto to obtain data from the first storage array or write data to the first storage array; and the first data processing module coupled between the first external data port and a first end of the external data selector, configured to perform data check processing and / or data inversion processing on data transmitted therethrough.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory, control method, and electronic device. Background Technology

[0002] With the rapid development of large models, traditional computing architectures are facing fundamental bottlenecks. On the one hand, large models with billions of data points require large-capacity storage devices for storage; on the other hand, in the traditional von Neumann architecture, a large amount of energy and latency is consumed in data transfer, resulting in the storage wall problem. Even with advanced packaging technology, it is difficult to meet the development requirements of power consumption, cost, and size.

[0003] In recent years, near-memory computing has received considerable attention as a solution to the aforementioned memory wall problem. This technology integrates computing units with storage devices, significantly reducing data transmission paths and thus substantially improving computing power and reducing energy efficiency. However, near-memory computing still faces many unresolved issues, such as how to achieve efficient and low-cost information exchange between the memory controller and computing circuitry. Summary of the Invention

[0004] This disclosure provides a memory, a control method, and an electronic device.

[0005] The technical solution of this disclosure embodiment is implemented as follows: In a first aspect, embodiments of this disclosure provide a memory, the memory including a first external data port, a first data processing module, an external data selector, a shadow register, and a plurality of first storage arrays; The first external data port is configured to receive data from outside the memory; or to send data stored in the memory to an external source. The external data selector has a first terminal, a first strobe terminal, and a second strobe terminal, respectively coupled to the first data processing module, the shadow register, and the first storage array; the external data selector is configured to, when the memory is in a second mode, select a data transmission path between the first data processing module and the shadow register to obtain data from or write data to the shadow register; and when the memory is in a first mode, select a data transmission path between the first data processing module and the coupled first storage array to obtain data from or write data to the first storage array. The first data processing module is coupled between the first external data port and the first end of the external data selector, and is configured to perform data verification processing and / or data flipping processing on the data transmitted therethrough.

[0006] In some embodiments, the first data processing module includes a data error correction module; The first external data port is configured to receive initial data from external input; The data error correction module is coupled to the first external data port and is further configured to, in the first mode, encode the first data corresponding to the initial data based on the on-chip verification algorithm to generate a first error correction code, and output the first data and the first error correction code; The first storage array is further configured to receive and store the first data and the first error correction code in response to a regular write signal in the first mode; The regular write signal indicates that the data input via the first external data port will be stored in the first storage array.

[0007] In some embodiments, the data error correction module is further configured to output only the first data in the second mode; The shadow register is also configured to, in the second mode, receive and store at least a portion of the bits in the first data as a first calculation configuration parameter in response to a special write signal; The special write signal indicates that the data input via the first external data port will be stored in the shadow register.

[0008] In some embodiments, the data error correction module is further configured to be in a disabled or bypassed state in the second mode, and the input first data is output directly without processing.

[0009] In some embodiments, the data error correction module is further configured to encode the first data based on an on-chip verification algorithm to generate the first error correction code in a second mode, and output only the first data; wherein the first error correction code is discarded.

[0010] In some embodiments, the memory further includes a computing controller; The computing controller is connected to the shadow register and configured to write the second computing configuration parameter to the shadow register; wherein the storage locations of the first computing configuration parameter and the second computing configuration parameter in the shadow register are independent of each other. The external data selector is further configured to, in the second mode, transmit the second data from the shadow register to the data error correction module in response to a special read signal; wherein the second data includes the first in-memory calculation parameters and / or the second calculation configuration parameters; The data error correction module is further configured to, in the second mode, directly output the second data as the third data in response to the special read signal; The special read signal indicates that the data stored in the shadow register should be output via the first external data port.

[0011] In some embodiments, the data error correction module includes an encoding submodule and a verification submodule; The encoding submodule is configured to encode the received second data and output the error correction code to be compared. The verification submodule is configured to receive an enable control signal and, when the enable control signal indicates that it is in the second mode, directly output the second data.

[0012] In some embodiments, the memory further includes a computing controller and an error correction code computing module; The computing controller is further configured to, in the second mode, read the first computing configuration parameter from the shadow register in response to a special read signal, and output the current values ​​of the first computing configuration parameter and the second computing configuration parameter as the data to be calculated; The error correction code calculation module is coupled to the calculation controller and is configured to receive and calculate the data to be calculated, generate and output a second error correction code. The computing controller is further configured to store the current value of the second computing configuration parameter and the second error correction code into the shadow register; The external data selector is further configured to, in the second mode, transmit the second data from the shadow register and the second error correction code to the data error correction module in response to a special read signal; The data error correction module is further configured to receive second data and the second error correction code output from the shadow register; based on the on-chip verification algorithm, the second error correction code is used to perform error correction processing on the second data to generate and output third data.

[0013] In some embodiments, the memory further includes a computing controller and a plurality of computing arrays; The computing array is configured to perform in-memory computations on the received data; The computing controller, connected to multiple computing arrays, is further configured to, in response to a special read signal, read the first computing configuration parameter from the shadow register and determine the current values ​​of the first computing configuration parameter and the second computing configuration parameter as the data to be computed; and to obtain the second error correction code generated after the data to be computed is computed by a preset programming algorithm, and store the current value of the second computing configuration parameter and the second error correction code in the shadow register. The external data selector is further configured to, in the second mode, transmit the second data from the shadow register and the second error correction code to the data error correction module in response to a special read signal; The data error correction module is further configured to receive second data and the second error correction code output from the shadow register; based on the on-chip verification algorithm, the second error correction code is used to perform error correction processing on the second data to generate and output third data; The preset programming algorithm is implemented based on the computing units in the computing array.

[0014] In some embodiments, the first data processing module further includes a data flipping module; The first external data port is also configured to receive a first flip flag and the initial data from an external input; The data flipping module is coupled between the first external data port and the data error correction module, and is further configured to determine whether to perform level flipping processing on the initial data based on the first flipping flag in the first mode, and generate and output the first data; wherein the first data is the initial data or the inverse data of the initial data.

[0015] In some embodiments, the data flipping module performs the same data processing procedure in the second mode and the first mode.

[0016] In some embodiments, the data error correction module is further configured to be disabled in a second mode, where the input initial data is output directly without processing.

[0017] In some embodiments, the memory is further configured to receive and, in response to a data processing function shutdown command, disable the data processing function provided by the first data processing module before decoding an externally sent operation command and generating a special write signal or a special read signal; the data processing function includes: the data error detection / correction function of the data error correction module and the data flipping function of the data flipping module; The memory is further configured to receive and respond to a data processing function enable command after the read / write operation of the shadow register indicated by the special write signal or the special read signal is completed, and enable the data processing function provided by the first data processing module.

[0018] In some embodiments, the first external data port is further configured to receive an initial link error correction code from an external input; The data flipping module is further configured to determine whether to perform level flipping processing on the initial link error correction code based on the first flipping flag, and generate and output the first link error correction code; wherein, the first link error correction code is the initial link error correction code or the inverse data of the initial link error correction code; The data error correction module is further configured to correct the first data using the first link error correction code based on the link verification algorithm before encoding the first data based on the on-chip verification algorithm. The data error correction module is further configured to encode the third data based on the link verification algorithm and output a second link error correction code; The data flipping module is specifically configured to perform statistics on the target level data in the third data and the second link error correction code to generate a second flip flag, determine whether to invert the third data and the second link error correction code according to the second flip flag, and output the third data or its inverted data, the second link error correction code or its inverted data, and the second flip flag together to the first external data port.

[0019] In some embodiments, the memory further includes a plurality of second storage arrays; The external data selector also has a third strobe terminal, which is coupled to a plurality of the second storage arrays; The external data selector, specifically configured in the second mode, selects the data transmission path between the first data processing module and the shadow register to obtain data from the shadow register or to write data to the shadow register. Alternatively, in the first mode, the data transmission path between the first data processing module and the first storage array is selected to obtain data from the first storage array or to write data to the first storage array. Alternatively, in the first mode, the data transmission path between the first data processing module and the second storage array is selected to obtain data from the second storage array or to write data to the second storage array.

[0020] In a second aspect, embodiments of this disclosure provide a control method applied to a memory, the memory including a plurality of first memory arrays, a shadow register, and a data error correction module; the method includes: In the first mode, the data error correction module is controlled to be in working state, the first input data is encoded, the first check code is output, and the first data and the first check code are stored in the first storage array; In the second mode, the data error correction module is controlled to be in a disabled or bypassed state, so that the input first data is not processed and is directly output, and at least a portion of the bits of the first data are stored as the first calculation configuration parameter in the shadow register.

[0021] Thirdly, embodiments of this disclosure provide a control method applied to a memory, the memory including a computing controller, a shadow register, and a data error correction module; the method includes: During the read operation of the shadow register, the first calculation configuration parameter stored in the shadow register is obtained, and the current value of the second calculation configuration parameter is obtained from the calculation controller; The current values ​​of the first calculation configuration parameter and the second calculation configuration parameter are determined as the data to be calculated. The data to be calculated is encoded based on the on-chip verification algorithm, and the second error correction code is output. Store the current value of the second calculation configuration parameter and the second error correction code into the shadow register.

[0022] Thirdly, embodiments of this disclosure provide an electronic device, which includes the memory described in the first aspect.

[0023] This disclosure provides a memory, a control method, and an electronic device. The memory supports in-memory computing and introduces a shadow register as an information intermediary between the memory controller and the computing circuit. Since the shadow register can be written to or read from data via the data port, the number of bits written or read at one time is relatively large, resulting in high efficiency of information exchange. The data in the shadow register is incorporated into the data transmission bus via an external data selector. This external data selector can reuse existing selection devices in the circuit, requiring minimal circuit modification and is located close to the external data port, thus requiring less driving capability. At the same time, the memory has been adapted to the first data processing module originally present on the data transmission bus, enabling it to process not only data for the first storage array but also data for the shadow register, ensuring the normal operation of the memory. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the in-memory computing system provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the first internal structure of the memory provided in this embodiment of the disclosure; Figure 3 This is a schematic diagram of writing data from the first external data port to the first storage array; Figure 4 This is a schematic diagram of reading data from the first storage array through the first external data port; Figure 5This is a schematic diagram of writing data from the first external data port to the shadow register; Figure 6 This is a schematic diagram of reading the data from the shadow register through the first external data port; Figure 7 This is a schematic diagram of a special write signal in memory; Figure 8 This is a schematic diagram of a special read signal in a memory. Figure 9 This is a schematic diagram of the first type of data readout under different modes provided in the embodiments of this disclosure; Figure 10 This is a schematic diagram of the signals for the data processing function shutdown command and the data processing function startup command provided in the embodiments of this disclosure; Figure 11 This is a schematic diagram of a second internal structure of the memory provided in an embodiment of this disclosure; Figure 12 This is a schematic diagram of the first type of data readout under different modes provided in the embodiments of this disclosure; Figure 13 This is a schematic diagram illustrating the working process of the data flipping module and data error correction module provided in this embodiment of the present disclosure for the first storage array; Figure 14 This is a schematic diagram illustrating the working process of the data flipping module and data error correction module provided in this embodiment for the shadow register; Figure 15 This is a schematic diagram illustrating the complete process of transferring data to the first storage array according to an embodiment of this disclosure; Figure 16 This is a schematic diagram illustrating the complete process of transferring data to the shadow register from the memory according to an embodiment of this disclosure; Figure 17 This is a schematic diagram of the first sub-channel and the second sub-channel provided in the embodiments of this disclosure; Figure 18 This is a schematic diagram of the shadow register data provided in an embodiment of this disclosure; Figure 19 This is a schematic diagram illustrating the working process of the data flipping module provided in this embodiment for the first storage array; Figure 20 This is a schematic diagram illustrating the working process of the data flipping module for the shadow register provided in this embodiment of the disclosure. Detailed Implementation

[0025] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0027] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0029] Embodiments are described and illustrated in the accompanying drawings by functional blocks, circuits, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based fabrication techniques or other manufacturing techniques. Where functional blocks, circuits, units, and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuit systems) for performing other functions. Furthermore, without departing from the scope of the technical concept of this disclosure, each functional block, circuit, unit and / or module of the embodiments may be physically divided into two or more interactive and separate functional blocks, circuits, units and / or modules of the embodiments, and each functional block, circuit, unit and / or module may be physically combined into more complex functional blocks, circuits, units and / or modules.

[0030] First, the nouns and terms used in the embodiments of this disclosure will be explained: Dynamic Random Access Memory (DRAM); Synchronous Dynamic Random Access Memory (SDRAM); Double Data Rate SDRAM (DDR); Low-power DDR (LPDDR); Fifth generation DDR (DDR5); Specification (SPEC); Mode register (MR); Mode register read command (MRR); Mode register write (MRW); Wafer on wafer (WOW); Processing-in-Memory (PIM); Hybrid bonding (HB); Through-Silicon Via (TSV); System on a Chip (SoC); Error checking and correction (ECC); Wordline (WL); Bitline (BL); Command address (Command / Address, CA); Chip Select (CS); Processing-Using-Memory (PUM) direct computation; Processing-Near-Memory (PNM).

[0031] Please see Figure 1The in-memory computing system 10 may include a memory controller 100 and a memory 200. The memory controller 100 can control the memory 200 according to requests from a processor that supports various applications, such as server applications, personal computer applications, and mobile applications. The memory controller 100 may be set up independently of the processor core or integrated with the processor core on the same chip (i.e., a system-on-a-chip, SoC).

[0032] Specifically, the memory controller 100 instructs the memory 200 to perform actions by sending a command address signal CA, a clock signal CK, and a chip select signal CS to the memory 200. At the same time, the memory controller 100 and the memory 200 exchange data through the data signal DQ. The above are only some examples of signals and not all of them.

[0033] like Figure 1 As shown, the memory 200 includes multiple first memory arrays BK and computing circuitry 22; The first storage array BK is configured to transmit data to the computing circuit 22 via the first data path D1 when in in-memory computing mode. The computing circuit 22 is configured to perform calculations on the received data when in in-memory computing mode, and the calculated data is either stored back into the first storage array BK or output to the memory controller 100.

[0034] The first storage array BK is also configured to, in storage mode, respond to the chip select CS and command address CA sent by the memory controller 100 to write data to or read data from the first storage array BK via the second data path D2.

[0035] In some embodiments, such as Figure 1 As shown, the memory 200 also includes a plurality of internal data selectors 24. The first end of each internal data selector 24 is connected to the corresponding first memory array BK. The first strobe end of each internal data selector 24 is coupled to the first external data port 25 via the second data path D2. The second strobe end of each internal data selector 24 is coupled to the computing circuit 22 via the first data path D1.

[0036] The internal data selector 24 is configured to select the first data path D1 and the computing circuit 22 when the coupled first storage array BK is in in-memory computing mode, so as to realize the data transmission between the first storage array BK and the computing circuit 22 through the first data path D1. Alternatively, when the coupled first storage array BK is in storage mode, the second data path D2 and the first external data port 25 are selected to realize data transmission between the first storage array BK and the first external data port 25 through the second data path D2.

[0037] In one example, in in-memory computing mode, various operations of the first memory array BK (such as activation operation, read operation, write operation, refresh operation, precharge operation, power-down operation, etc.) are executed in response to internal commands or internal signals of computing circuit 22.

[0038] In another example, in in-memory computing mode, various operations of the first storage array BK (such as activation, read, write, refresh, precharge, power-down, etc.) still respond to external commands executed by the memory controller 100.

[0039] Here, the first storage array BK includes multiple storage cells, multiple word lines (WL), and multiple bit lines (BL). Each word line connects multiple storage cells, and storage cells connected to the same word line are also called storage rows, and their addresses are called row addresses. Each bit line connects multiple storage cells, and storage cells connected to the same bit line are also called storage columns, and their addresses are called column addresses.

[0040] For ease of management, the memory 200 has multiple storage levels. For example, the memory 200 includes multiple bank groups (BG), each bank group includes multiple banks (BK), each bank includes multiple sections arranged along the bit line direction, each section includes multiple memory array pieces (MAT), each MAT includes multiple column planes (CP), and so on. The embodiments described below use the first memory array BK as an example of a bank, but the first memory array BK can also be a bank group, a section, or a column plane… Overall, for memory 200, at least a portion of the first memory array BK has a storage mode and an in-memory computing mode: (1) Storage mode: The first storage array BK performs normal data storage function, and in response to the command address CA, clock CK and chip select CS signals sent by the memory controller 100, it stores the data from the memory controller 100 or reads the stored data to the outside of the chip; and in this mode, the first storage array BK and the computing circuit 22 are isolated from each other.

[0041] (2) In-memory computing mode: The data stored in the first storage array BK is provided to the computing circuit 22 for computing, or the first storage array BK stores the computing results output by the computing circuit 22; and, in this mode, the first storage array BK is isolated from the memory controller 100.

[0042] It should be understood that different first memory arrays (BKs) may operate in different modes. For example, some first memory arrays (BKs) may operate in storage mode, while others may operate in in-memory compute mode.

[0043] Please see Figure 1 The computing circuit 22 includes a computing controller 221 and multiple computing arrays (PUs). The computing controller 221 mainly integrates some control logic for controlling data transmission between the first storage array BK and the corresponding computing array PU, as well as controlling the computing operations of the computing array PU. The computing array PU contains computing units for performing computing tasks, which can be either Processing-Using-Memory (PUM) units or Processing-Near-Memory (PNM) units.

[0044] The signal transmission between the memory 200 and the memory controller 100 can follow any of the following protocols: (1) DDR protocol: such as DDR4, DDR5, DDR6, DDR7, etc.; (2) LPDDR protocol: such as LPDDR4, LPDDR5, LPDDR6, LPDDR7, etc.

[0045] In some embodiments, see Figure 1 The memory 200 also includes a shadow register 21. Both the computing circuit 22 and the memory controller 100 can read from or write to the shadow register 21. Thus, the memory controller 100 and the computing circuit 22 can interact via the shadow register 21 to coordinate the switching process between in-memory computing mode and storage mode, ensuring that the in-memory computing function and storage function are compatible and can work stably.

[0046] In some embodiments, to improve information transmission efficiency, the shadow register 21 transmits data via the first external data port 25 (originally intended for data transmission in the first memory array BK). See also... Figure 1 The memory 200 also includes an external data selector 23. For example... Figure 1 As shown, the external data selector 23 is used to select the first external data port 25 and the shadow register 21, or to select the first external data port 25 and the first memory array BK.

[0047] Thus, although the shadow register 21 is a register, it is not read and written via the command address port like a regular mode register (i.e., the mode register can be written via information carried in the externally received register write command MRW and register read command MRR). Instead, it is read and written via the first external data port 25 (i.e., the DQ port for transmitting data signals), just like the first memory array BK. Since the amount of data carried by each register write command MRW / register read command MRR is only 8 bits (for example only), while the amount of data transmitted by each first external data port 25 can be 256 bits (for example only), the amount of data transmitted in one read / write operation through the data port is equivalent to the amount of data carried by 32 register write commands MRW / register read commands MRR. Therefore, the transmission efficiency of the technical solution disclosed in this invention is significantly improved.

[0048] It should be noted that, please refer to Figure 2 This illustrates a schematic diagram of the internal structure of the memory 200 provided in an embodiment of this disclosure. For example... Figure 2 As shown, each first memory array BK has its own independent local data bus Lbus. The local data buses Lbus of several first memory arrays BK are connected to the same secondary data bus Abus. The multiple secondary data buses Abus corresponding to all first memory arrays BK are connected to the first external data port 25 via the global data bus Dbus. In short, the local data bus Lbus is unique to each memory array, but the secondary data bus Abus may be shared by some memory arrays (e.g., all memory arrays included in memory bank group BG), and the global data bus Dbus is shared by all memory arrays. Specifically, if the memory 200 contains multiple sub-channels, all memory arrays in the same sub-channel share the same global data bus Dbus (see subsequent description).

[0049] The aforementioned external data selector 23 can be coupled to any of the following locations: (1) local data bus Lbus; (2) secondary data bus Abus; (3) global data bus Dbus; (4) between local data bus Lbus and secondary data bus Abus; (5) between secondary data bus Abus and global data bus Dbus; (6) between global data bus Dbus and first external data port 25; (7) between local data bus Lbus and first storage array BK.

[0050] Please see Figure 2The embodiments disclosed herein will be illustrated and described in the accompanying drawings as "an external data selector 23 coupled between the secondary data bus Abus and the global data bus Dbus". In this scenario, the external data selector 23 is located in the data path slicing control (DPSC). DPSC refers to a slice structure used to manage high-speed data channels to achieve more efficient data reading and writing.

[0051] like Figure 2 As shown, the first external data port 25 is configured to receive data from outside the memory 200; or to send data stored in the memory 200 to the outside.

[0052] like Figure 2 As shown, the memory 200 also includes a first data processing module 30. The first data processing module 30 is coupled between the first external data port 25 and the first end of the external data selector 23, and is configured to perform data verification processing (also known as error correcting code, ECC) and / or data bus inversion processing (DBI) on the data transmitted therethrough.

[0053] Please refer to Figure 2 The external data selector 23 has a first terminal, a first gating terminal and a second gating terminal. The first terminal of the external data selector 23 is coupled to the first data processing module 30, the first gating terminal of the external data selector 23 is coupled to the shadow register 21, and the second gating terminal of the external data selector 23 is coupled to the first storage array BK. External data selector 23 is configured to, when memory 200 is in the second mode, select the data transmission path Lsr between the first data processing module 30 and the shadow register 21 to obtain data from or write data to the shadow register 21; and when memory 200 is in the first mode, select the data transmission path between the first data processing module 30 and the coupled first storage array BK to obtain data from or write data to the first storage array BK.

[0054] It should be noted that the external data selector 23 also has a control terminal, which is used to receive a gating control signal, which is used to indicate the first mode or the second mode.

[0055] It should be noted that the external data selector 23 can be composed of multiple 2-to-1 data selectors (Mux), the specific number of which depends on the number of bits of the parallel data signal to be transmitted.

[0056] Thus, in the first mode, the memory controller 100 is instructed to access the first memory array BK through the first external data port 25, and the data transmitted through the first external data port 25 is either written to or read from the first memory array BK. In the second mode, the memory controller 100 is instructed to access the shadow register 21 through the first external data port 25, and the data transmitted through the first external data port 25 is either written to or read from the shadow register 21. Therefore, the shadow register 21 and the first memory array BK share the same first external data port 25 for data transmission, requiring minimal circuit modifications and achieving high signal transmission efficiency.

[0057] In some embodiments, certain signals in the memory 200 are used to indicate whether the memory 200 is in a first mode or a second mode, as detailed below.

[0058] In other embodiments, the mode register (MR) in the memory 200 stores mode parameters to indicate whether the memory 200 is in a first mode or a second mode, as detailed in the following description.

[0059] exist Figure 2 The diagram also shows multiple latch circuits and read / write control circuits, all used for temporary data storage and control transmission at different locations.

[0060] Thus, this embodiment of the present disclosure provides a memory 200. Since multiple secondary data buses Abus are coupled to the same global data bus Dbus, there may already be some data selectors between the secondary data buses Abus and the global data bus Dbus. Therefore, the aforementioned external data selector 23 can reuse existing data selectors or add pins of the selection terminals to existing data selectors (for example, the original data selector has 2 selection terminals, which are adjusted to 3 selection terminals in order to couple the shadow register 21), thereby reducing the circuit area. At the same time, compared with the scheme of "external data selector 23 is located on the secondary data bus Abus", the external data selector 23 is coupled between the secondary data bus Abus and the global data bus Dbus, which will not affect the timing control of data transmission of the first memory array BK, and can also reduce the required driving capability.

[0061] However, please refer to Figure 2Because the external data selector 23 is located between the secondary data bus Abus and the global data bus Dbus, the data for the shadow register 21 also needs to go through the first data processing module 30. However, the first data processing module 30 was originally designed for the first memory array BK, and the data of the shadow register 21 and the data of the first memory array BK are different in some aspects. This causes the first data processing module 30 to fail to work properly and report an error when transmitting the data of the shadow register 21, as explained in detail below.

[0062] In some embodiments, see Figure 2 The first data processing module 30 includes a data error correction module 31, also known as an ECC module, which is mainly used to implement the aforementioned data verification processing.

[0063] First, the working process of the data error correction module 31 in the first mode will be explained.

[0064] Please see Figure 3 This illustrates a schematic diagram of writing data from the first external data port 25 to the first storage array BK. (See diagram for example.) Figure 3 As shown: The first external data port 25 is configured to receive initial data Data0 from external input; The data error correction module 31 is coupled to the first external data port 25 and is also configured to encode the first data Data1 corresponding to the initial data Data0 based on the on-chip verification algorithm in the first mode to generate the first error correction code Ecode1, and output the first data Data1 and the first error correction code Ecode1. The first storage array BK is also configured to receive and store first data Data1 and first error correction code Ecode1 in response to the regular write signal Array_WR in the first mode.

[0065] It should be noted that the regular write signal Array_WR indicates that data input via the first external data port 25 will be stored in the first memory array BK. Here, the regular write signal Array_WR can be in response to the memory controller 100 (see reference). Figure 1 The write signal Array_WR is generated by sending a write command. The write command is specifically represented by a command address CA and a chip select CS with a specific encoding (or a specific waveform). The encoding rules conform to the DRAM protocol followed by the memory 200 (e.g., but not limited to: DDR4, DDR5, DDR6, LPDDR4, LPDDR5, or LPDDR6). In this case, the regular write signal Array_WR can be generated by decoding the write command sent by the memory controller 100.

[0066] Please see Figure 4 This illustrates a schematic diagram of reading data from the first storage array BK from the first external data port 25. For example... Figure 4 As shown: The first storage array BK is also configured to output target data Data_Array and target error correction code Ecode_Array in response to the regular read signal Array_RD in the first mode. The data error correction module 31 is coupled to the first external data port 25 and is also configured to, in the first mode, perform error correction on the target data Data_Array based on the on-chip verification algorithm and the target error correction code Ecode_Array, and output the read result data Darray_out. The read result data Darray_out is transmitted to the memory controller 100 via the first external data port 25.

[0067] It should be noted that the regular read signal Array_RD indicates that data input via the first external data port 25 will be stored in the first memory array BK. Here, the regular read signal Array_RD may be in response to the memory controller 100 (see reference...). Figure 1 The read signal Array_RD is generated by sending a read command. The read command is specifically represented by a command address CA and a chip select CS with a specific encoding (or a specific waveform). The encoding rules conform to the DRAM protocol followed by the memory 200 (e.g., but not limited to: DDR4, DDR5, DDR6, LPDDR4, LPDDR5, or LPDDR6). In this case, the regular read signal Array_RD can be generated by decoding the read command sent by the memory controller 100.

[0068] As can be seen from the above, in the first mode, the data error correction module 31 can encode the data written in the first storage array BK and verify it when this part of the data is read out, thereby correcting some errors that occur during the storage of this part of the data in the first storage array BK and improving the storage performance of the memory 200.

[0069] In some embodiments, the data processing procedures of the data error correction module 31 in the second mode and the first mode are different to match the data characteristics of the shadow register 21 and the first storage array BK.

[0070] In other embodiments, the data processing procedure of the data error correction module 31 is the same in both the second and first modes, reducing the complexity of control.

[0071] The two design approaches described above will be explained below.

[0072] First, the data processing of the data error correction module 31 differs between the first and second modes.

[0073] (a) Regarding the write process: Please see Figure 5 This illustrates a diagram of writing data from the first external data port 25 to the shadow register 21. (See diagram for example.) Figure 5 As shown: The first external data port 25 is configured to receive initial data Data0 from external input; The data error correction module 31 is also configured to output only the first data, Data1, in the second mode; Shadow register 21 is also configured in the second mode to receive and store at least a portion of the bits of the first data Data1 (e.g., 256 bits) as the first computed configuration parameter PIMdata1 (e.g., 128 bits) in response to the special write signal SR_WR.

[0074] It should be noted that the special write signal SR_WR indicates that the data input via the first external data port 25 will be stored in the shadow register 21, and can also be used to indicate that the memory 200 is in the second mode.

[0075] It should be noted that, please refer to Figure 5 The memory 200 also includes a computing controller 221; the computing controller 221 is connected to the shadow register 21 and is configured to write the second computing configuration parameter PIMdata2 (e.g., 128 bits) to the shadow register 21; wherein the storage locations of the first computing configuration parameter PIMdata1 and the second computing configuration parameter PIMdata2 in the shadow register 21 are independent of each other.

[0076] For example, shadow register 21 provides 256 bits of storage space for the calculation configuration parameters, of which 128 bits are used to store the first calculation configuration parameter PIMdata1 and the other 128 bits are used to store the second calculation configuration parameter PIMdata2.

[0077] It should be noted that the memory calculator 100 can read the first calculation configuration parameter PIMdata1 and / or the second calculation configuration parameter PIMdata2 stored in the shadow register 21, and the calculation controller 221 can also read the first calculation configuration parameter PIMdata1 and / or the second calculation configuration parameter PIMdata2 stored in the shadow register 21.

[0078] In a specific example, please see Figure 18 Assuming that memory 200 has 16 first external data ports DQ15~DQ0, and the amount of data transferred for each read command is 256 (for example only), the storage capacity of shadow register 21 can be designed to be 256 bits. Figure 18 The horizontal axis in the diagram represents the length of data continuously transmitted in a single read / write command (DQ) (the diagram illustrates 16 consecutive serial transmissions of data), also known as the burst length (BL). B0 represents the first data transmission, and B15 represents the sixteenth data transmission. Figure 18 The vertical axis in the diagram represents each external data port DQ, with a total of 16 external data ports DQ15~DQ0. Therefore, all data parameters stored in the shadow register 21 can be transmitted via the first external data ports DQ15~DQ0 within 16 transmission cycles B15~B0 (the number of transmission cycles corresponding to each read / write command).

[0079] Correspondingly, for write commands, although the first external data ports DQ15~DQ0 can also transmit 256 bits of data, only the first calculated configuration parameter PIMdata1 is stored in the shadow register 21. In other words, the number of bits in the first data Data1 may be greater than the number of bits in the first calculated configuration parameter PIMdata1 (the extra bits in the first data Data1 can be filled with preset level data, random data, or random data), so the shadow register 21 will only store the corresponding valid bits.

[0080] Only with Figure 18 For example, the first in-memory calculation parameter PIMdata1 is used to indicate at least one or more of the following: (1) PIM status: Whether to enter in-memory calculation mode; (2) PIM mode: All Bank mode (all storage arrays are used for computation), Half Bank mode (only half of the first storage array is used for computation), Part Bank mode (a more flexible way to select the target storage array, which requires information from other bits to determine which storage arrays are used for computation, and can be set by the user). (3) Input address: The storage address of the data to be calculated in the first storage array BK; (3) Output address: The expected storage address of the calculated data in the first storage array BK, that is, the address that the memory controller 100 wants to store; (4) First power supply status parameters: operating frequency, power supply voltage, etc. of the first storage array; (5) First error information encoding, error encoding information sent to computing controller 221; (6) User-defined, reserved space for user-defined space, also known as reserved code (Reserved for Future Use, RFU); (7) Data can be any information that the memory controller 100 needs to write to the shadow register 21, or even data to be calculated or other configuration information that instructs the computing circuit 22 to perform a computing operation.

[0081] Only with Figure 18 For example, the second in-memory calculation parameter PIMdata2 is used to indicate at least one or more of the following: (1) PU mode: Whether the calculation is complete, and whether it is possible to exit PIM mode; (2) PU state: The working state of the computing circuit, such as computing state, standby state, etc., which in turn indicates whether the computing task has been completed; (3) Output address: The actual storage address of the calculated data in the first storage array BK; (4) Second power supply status parameters: calculate the operating frequency, power supply voltage, and other statuses in the array; (5) Second error information encoding: Error encoding information reported to memory controller 100, including but not limited to: data error, data overflow, temperature abnormality, power abnormality, etc.; (6) User-defined, reserved space for user-defined space, also known as reserved code (Reserved for Future Use, RFU); (7) Data can be any information that the computation controller 221 needs to write to the shadow register 21, or even computation result data or related configuration information that instructs the memory controller 100 (or understands as SoC) how to read the computation result data, such as: reading data from the shadow register 21 or reading data from the first storage array, or reading the computation result in a specified order.

[0082] (b) Regarding the readout process: Please see Figure 6 This illustrates a diagram of reading data from the shadow register 21 from the first external data port 25. (See diagram for example.) Figure 6 As shown: External data selector 23 is also configured to, in the second mode, transmit the second data Data_SR from shadow register 21 to data error correction module 31 in response to a special read signal SR_RD; The data error correction module 31 is also configured to, in the second mode, directly output the second data Data_SR as the third data DSR_out in response to the special read signal SR_RD; The special read signal SR_RD indicates that the data stored in the shadow register 21 is output through the first external data port 25, and can also be used to indicate that the memory 200 is in the second mode.

[0083] In this way, neither writing data to nor reading data from the shadow register 21 requires any data verification processing, saving energy. It should be understood that the shadow register 21 is essentially a register, and its structure and storage principle are different from the storage units in the first storage array BK. Its data security is generally higher than that of the storage units. Therefore, in the second mode, the first data Data1 output by the data error correction module 31 does not need to undergo error correction; the shadow register 21 only stores the data and not the corresponding error correction code, resulting in higher storage space utilization.

[0084] It should be noted that there are multiple possibilities for the generation of the special write signal SR_WR and the special read signal SR_RD. The following is a specific example and does not constitute a limitation.

[0085] Example 1: Please see Figure 7 It shows a signal schematic diagram of a memory 200. Figure 7 In this context, CK refers to the clock, CA<3:0> refers to the command address (CMD refers to the instruction type corresponding to a specific CA<3:0> encoding, DQ<11:0> refers to the data signal, i.e. the signal transmitted by the first external data port 25), and SRcell<255:0> can be regarded as the data in the shadow register 21. The number of bits of the above signals is only an example and does not constitute any relevant limitation.

[0086] Please see Figure 7 The memory 200 is configured to output a special read / write status signal SRACT in an enabled state (e.g., high level 1) in response to an activation command Active for a target row address (a predefined dedicated row address); when the special read / write status signal SRACT is enabled, a special write signal SR_WR is generated and output in response to a received write command Write.

[0087] Please see Figure 8 The memory 200 is configured to generate and output a special read signal SR_RD in response to the received read command Read when the special read / write status signal SRACT is enabled.

[0088] Please see Figure 7 or Figure 8 The memory 200 is also configured to adjust the special read / write state signal SRACT to an enabled state (e.g., low level 0) in response to the precharge command PRE (Precharge).

[0089] It should be noted that the target row address is a pre-agreed row address. Although its format adopts the format of the storage row address in the first storage array BK, it will not be indexed to the corresponding storage row in the first storage array BK, but will be indexed to the shadow register 21.

[0090] Overall, the possible scenarios for activating the command are as follows: (1) Please see Figure 7 or Figure 8 For activation commands Active that are not the first target row address, the activation operation signal ACT will be generated in the command address decoder, thereby activating the corresponding storage row. (2) The activation command for the first target row address will trigger the generation of the activation operation signal ACT and the special read / write status signal SRACT in the energy state at the same time in the command address decoder. The special read / write status signal SRACT in the energy state will block the subsequent operation of the activation signal ACT and will no longer execute the activation operation for the memory array. At the same time, the special read / write status signal SRACT can be sent to the shadow register 21 and its related circuits, which will start some circuits related to the shadow register 21 that are closed by default (such as the transmission line Bus for the shadow register 21) to prepare for the subsequent read / write operation of the shadow register 21. Meanwhile, when the special read / write status signal SRACT is enabled, the subsequent read / write command is decoded into the special read signal SR_RD / special write signal SR_WR. The special read signal SR_RD / special write signal SR_WR is further sent to the shadow register 21 and the computing controller 221, thus completing the read / write operation for the shadow register 21 and controlling the computing controller to update the value of SR.

[0091] In addition, the decoding operation of the special read signal SR_RD / special write signal SR_WR also requires decoding the array address information to ensure that when part of the memory array enters the in-memory computing mode, the read command / write command is indeed aimed at the shadow register 21 and not the memory array that is still in memory mode, so as to ensure that the special read signal SR_RD / special write signal SR_WR will not be misdecoded.

[0092] It should be understood that, taking the first storage array BK as an example, each first storage array BK can be further divided into storage sections, storage array pieces, storage column planes (CP), etc., for management. Therefore, the target row address actually contains multiple fields, which are used to indicate the selected storage array, the selected storage section, the selected storage array piece, the selected storage column plane, etc. In a specific implementation, please refer to Figure 7 The memory 200 is configured to output a special write signal SR_WR in response to a write command for a target array address when the special read / write status signal SRACT is enabled.

[0093] In a specific implementation, please refer to Figure 8 The memory 200 is configured to output a special read signal SR_RD in response to a read command Read for a target array address when the special read / write status signal SRACT is enabled.

[0094] For example, the target row address could be RA<17:0>=0100111100001111, and the target array address could be the target storage array indicated by the target row address RA<17:0> with the field corresponding to the target storage array set to a preset value (e.g., RA<17:14>=BK<3:0>=0100). For example, the target array address could be the array address corresponding to the target storage array (BK<3:0>=0100).

[0095] Based on the foregoing embodiments, the working mechanism of the data error correction module 31 in the second mode can be implemented in the following ways.

[0096] (1.1) The data error correction module 31 in the second mode is prevented from performing related processing by means of hardware circuit.

[0097] Regarding the writing process: the data error correction module 31 is also configured to be in bypass mode in the second mode, and the first input data Data1 is not processed and is directly output.

[0098] Regarding the reading process: the data error correction module 31 is also configured to be in bypass mode in the second mode, and the input second data Data_SR is not processed and is directly output.

[0099] It should be noted that in the second mode, the data error correction module 31 can be partially or completely bypassed, which will be described separately below.

[0100] (1.1.1) In the second mode, some modules of the data error correction module 31 are bypassed.

[0101] It should be understood that the data error correction module 31 has two functions: encoding and verification. The lack of a corresponding checksum in the second data Data_SR only involves the verification function. Therefore, in the second mode, only the verification function of the data error correction module 31 can be bypassed.

[0102] For the writing process: please refer to Figure 5The data error correction module 31 is also configured to encode the first data Data1 based on the on-chip verification algorithm to generate the first error correction code Ecode1 in the second mode, and output only the first data Data1; wherein the first error correction code Ecode1 is discarded.

[0103] Regarding the readout process: please refer to Figure 6 The data error correction module 31 is also configured to encode the second data Data_SR based on the on-chip verification algorithm to generate the error correction code to be compared in the second mode; and to directly output the second data Data_SR as the third data DSR_out; wherein the error correction code to be compared is discarded.

[0104] In a specific example, please see Figure 9 The data error correction module 31 includes an encoding submodule 311 and a verification submodule 312.

[0105] Please see Figure 9 In (a), for the readout process in the first mode: The first storage array BK is configured to output target data Data_Array and target error correction code Ecode_Array in response to the regular read signal Array_RD (or in the first mode); Encoding submodule 311 is configured to encode the target data Data_Array from the first storage array BK and output the error correction code to be compared. The verification submodule 312 is configured to receive the enable control signal SR_en, and when the enable control signal SR_en indicates that it is in the first mode, compare the error correction code to be compared with the target error correction code Ecode_Array, and perform correction processing on the target data Data_Array according to the comparison result, and output the correction result as the read result data Darray_out.

[0106] It should be noted that, please refer to Figure 4 The verification submodule 312 specifically includes a pre-decoding unit 3121 and a correction unit 3122. The pre-decoding unit 3121 is configured to compare and pre-decode the error correction code to be compared and the target error correction code Ecode_Array, and output the correction code; the correction unit 3122 is configured to perform correction processing on the target data Data_Array based on the correction code, and output the correction result as the read result data Darray_out.

[0107] Please see Figure 9 In (b), regarding the readout process in the second mode: The first storage array BK is configured to output the second data Data_SR in response to a special read signal SR_RD (or described as in the second mode); Encoding submodule 311 is configured to encode the second data Data_SR and output the error correction code to be compared; Verification submodule 312 is configured to receive the enable control signal SR_en, and when the enable control signal SR_en indicates that it is in the second mode, directly output the second data Data_SR as the third data DSR_out (see reference). Figure 6 ).

[0108] In this way, only an enable control signal SR_en needs to be introduced in the verification submodule 312 to bypass the verification submodule 312 in the second mode, which can support different functions in the first mode / second mode with minimal circuit modification.

[0109] The above explanation uses read operations as an example. The same applies to write operations; please refer to the explanation for understanding.

[0110] (1.1.2) In the second mode, all modules of the data error correction module 31 are bypassed.

[0111] In other words, in the second mode, neither the encoding submodule 311 nor the verification submodule 312 will operate, maximizing power and energy savings.

[0112] (1.2) In the second mode, the data error detection / correction function is turned off by command.

[0113] In some embodiments, the data error correction module 31 is further configured to be disabled in the second mode, and the input first data Data1 is output directly without processing.

[0114] Please see Figure 10 This illustrates yet another signal timing diagram for memory 200. For example... Figure 10 As shown: Memory 200 is also configured to decode operation commands sent externally, generating a special write signal SR_WR. Figure 10 (As illustrated in this example) or before the special read signal SR_RD (i.e., before time tB), the data processing function provided by the first data processing module 30 is disabled in response to the data processing function shutdown command MRW2; the data processing function includes: the data error detection / correction function of the data error correction module 31, i.e. Figure 10 The enable signal ECC_En of the data error correction module 31 changes to the Off state; The memory 200 is also configured to receive and respond to the data processing function enable command MRW4 after the read / write operation of the shadow register 21 indicated by the special write signal SR_WR or the special read signal SR_RD is completed (i.e., after time tC), enabling the data processing function provided by the first data processing module 30. Figure 10 The enable signal ECC_En of the data error correction module 31 changes to the On state.

[0115] In one specific embodiment, it can also be designed as follows: The memory 200 is further configured to receive and respond to the data processing function shutdown command MRW2 before receiving the activation command Active for the target row address (i.e., before time tA), disabling the data processing functions provided by the first data processing module 30; the data processing functions include: the data error detection / correction function of the data error correction module 31, i.e. Figure 10 The enable signal ECC_En of the data error correction module 31 changes to the Off state; The memory 200 is further configured to, after receiving the activation command Active for the target row address and the precharge command PRE (i.e., after time tD), receive and respond to the data processing function enable command MRW4 to enable the data processing function provided by the first data processing module 30. Figure 10 The enable signal ECC_En of the data error correction module 31 changes to the On state.

[0116] It should be noted that, please refer to Figure 10 The value in the first mode register MR23 in memory 200 is used to indicate whether the data error detection / correction function is enabled. Therefore, the data processing function disable command MRW2 and the data processing function enable command MRW4 are both manifested as mode register write commands, which enable or disable the data error correction module 31 by modifying the corresponding value in the first mode register MR23.

[0117] In this scenario, the value of the first mode register MR23 can also be used to distinguish between the first mode and the second mode.

[0118] As can be seen from the above, this disclosure provides a control method applied to a memory 200. For writing data, the method includes: In the first mode, the control data error correction module 31 is in working state, encodes the input first data, outputs the first check code, and stores the first data and the first check code into the first storage array; In the second mode, the control data error correction module 31 is in a disabled or bypassed state, so that the input first data is not processed and is directly output, and at least a portion of the bits of the first data are stored as the first calculation configuration parameter in the shadow register 21.

[0119] For reading data, the method also includes: In the first mode, the working state of the control data error correction module 31 is controlled, the target data and target error correction code are received from the first storage array BK, the target data is verified using the target error correction code, and the read result data is output. In the second mode, the control data error correction module 31 is in a disabled or bypassed state, receives the second data from the shadow register 21, and outputs the input second data directly without processing.

[0120] As can be seen from the above, the data error correction module 31 operates differently in the first and second modes, thus adapting to the needs of different modes, ensuring not only data security but also power consumption.

[0121] Specifically, in the aforementioned embodiments, the shadow register 21 only stores data without corresponding error correction codes. This is the fundamental reason why the data error correction module 31 operates differently in the first and second modes. Therefore, in other scenarios, additional mechanisms can be added to ensure that the shadow register 21 also stores the corresponding error correction codes. In this case, the data error correction module 31 can operate in the same way in both the first and second modes, as detailed below.

[0122] Second, the data processing procedure of the data error correction module 31 in both the first and second modes is the same.

[0123] Because the data error correction module 31 processes the same data in the second mode and the first mode, the data error correction module 31 does not need to distinguish between the first mode and the second mode, and therefore does not need to respond to the aforementioned enable control signal SR_en to work.

[0124] (a) can still be referred to Figure 5 Regarding the write process: The first external data port 25 is configured to receive initial data Data0 from external input; The data error correction module 31 is coupled to the first external data port 25 and is also configured to, in the second mode, encode the first data Data1 corresponding to the initial data Data0 based on the on-chip verification algorithm to generate the first error correction code Ecode1, and output the first data Data1 and the first error correction code Ecode1.

[0125] However, the shadow register 21 not only stores the first computational configuration parameter PIMdata1 (which is essentially derived from the memory controller 100), but also stores the second computational configuration parameter PIMdata2 derived from the computational controller 221. Furthermore, the first computational configuration parameter PIMdata1 and the second computational configuration parameter PIMdata2 may need to be jointly encoded to generate the corresponding error correction code.

[0126] In this way, the shadow register 21 will also have a portion of space to store the error correction code (e.g., 16 bits) after the first calculation configuration parameter PIMdata1 and the second calculation configuration parameter PIMdata2 are encoded together.

[0127] However, as mentioned above, when the memory controller 100 writes to the shadow register 21, the data error correction module 31 encodes the first data (e.g., 256 bits) to generate a 16-bit first error correction code. However, since only 128 bits of the first calculation configuration parameter PIMdata1 in the first data will be written to the shadow register 21, and the error correction code required in the shadow register 21 corresponds to "the first calculation configuration parameter PIMdata1 and the second configuration parameter PIMdata2", in the second mode, the shadow register 21 cannot directly use the first error correction code Ecode1 output by the data error correction module 31, but needs to be calculated separately.

[0128] In one example, shadow register 21 is also configured to receive and store a portion of the bits in the first data Data1 as the first calculation configuration parameter PIMdata1 in response to a special write signal SR_WR in the second mode. Thus, although the data error correction module 31 still calculates the first error correction code Ecode1 in the second mode, it does not actually need to store it in shadow register 21.

[0129] In another example, shadow register 21 is also configured in a second mode to receive and store at least a portion of the bits in the first data Data1 as a first computed configuration parameter PIMdata1, and to store the first error correction code Ecode1, in response to a special write signal SR_WR. In this case, although shadow register 21 stores the first error correction code Ecode1, this portion of the error correction code will be overwritten during a read operation (see description below).

[0130] In another example, to save power consumption, the data error correction module 31 can also skip encoding during the writing process and directly output the first data Data1, as described above.

[0131] (b) Regarding the readout process: The error correction code in shadow register 21 can be generated in several ways. Two possible examples are provided below.

[0132] (b1) Please refer to Figure 11 The error correction code corresponding to shadow register 21 is calculated by adding a new hardware circuit.

[0133] The computing controller 221 is also configured to, in the second mode, read the first computing configuration parameter PIMdata1 from the shadow register 21 in response to the special read signal SR_RD, and output the current values ​​of the first computing configuration parameter PIMdata1 and the second computing configuration parameter PIMdata2 as the data to be computed; The error correction code calculation module, coupled to the calculation controller 221, is configured to receive and calculate the data to be calculated, generate and output the second error correction code Ecode_SR; The computing controller 221 is also configured to store the current value of the second computing configuration parameter PIMdata2 and the second error correction code Ecode_SR into the shadow register 21.

[0134] Please refer to Figure 11 The external data selector 23 is also configured to, in the second mode, transmit the second data Data_SR and the second error correction code Ecode_SR from the shadow register 21 to the data error correction module 31 in response to the special read signal SR_RD. The data error correction module 31 is also configured to receive the second data Data_SR and the second error correction code Ecode_SR output from the shadow register 21; based on the on-chip verification algorithm, the second error correction code Ecode_SR is used to perform error correction processing on the second data Data_SR, generate and output the third data DSR_out, and transmit the third data DSR_out to the first external data port 25 for output.

[0135] Here, the encoding method of the error correction code calculation module 40 is the same as that of the encoding submodule 311.

[0136] Thus, by adding a separate error correction code calculation module 40 to the computing circuit 22 (which only has the encoding function corresponding to the on-chip verification algorithm, see encoding submodule 311), the second error correction code Ecode_SR corresponding to the shadow register 21 is generated. Specifically, after receiving a read command for the shadow register 21 (which can be triggered by a special read signal SR_RD), the computing circuit 22 will read the first data Data1 already stored in the shadow register 21, and then send the first data Data1 and the current value of the second calculation configuration parameter PIMdata2 into the error correction code calculation module 40 for calculation. The generated second error correction code Ecode_SR and the current value of the second calculation configuration parameter PIMdata2 are then written into the shadow register 21.

[0137] Please refer to Figure 12 Regardless of whether it is the first mode or the second mode, the data error correction module 31 will receive 256 bits of data and 16 bits of error correction code, and can perform error detection and error correction processing normally, further improving the data stability of the shadow register 21.

[0138] (b2) Calculate the error correction code corresponding to shadow register 21 using a software algorithm.

[0139] As mentioned above, the memory 200 also includes a computing controller 221 and multiple computing arrays (PUs); the computing arrays (PUs) are configured to perform in-memory computations on the received data. In this way, the memory 200 can support large-scale model operations while reducing transport time and power consumption.

[0140] It should be noted that during the large model operation, the amount of data to be calculated will gradually decrease, so the computing power will be idle. Therefore, the computing power provided by the computing array PU can be used to calculate error correction codes at the software algorithm level.

[0141] The computing controller 221, connected to multiple computing arrays PU, is also configured to, in response to a special read signal SR_RD, read the first computing configuration parameter PIMdata1 from the shadow register 21 and determine the current values ​​of the first computing configuration parameter PIMdata1 and the second computing configuration parameter PIMdata2 as the data to be computed; and to obtain the second error correction code Ecode_SR generated after the data to be computed is computed by a preset programming algorithm, and store the current value of the second computing configuration parameter PIMdata2 and the second error correction code Ecode_SR in the shadow register 21.

[0142] Please refer to Figure 11 To perform adaptive understanding (but in this scenario there is no need to set up the error correction code calculation module 40), the external data selector 23 is also configured to, in the second mode, in response to the special read signal SR_RD, transmit the second data Data_SR and the second error correction code Ecode_SR from the shadow register 21 to the data error correction module 31. The data error correction module 31 is also configured to receive the second data Data_SR and the second error correction code Ecode_SR output from the shadow register 21; based on the on-chip verification algorithm, the second error correction code Ecode_SR is used to perform error correction processing on the second data Data_SR, and the third data DSR_out is generated and output.

[0143] The preset programming algorithm is implemented based on the computing units in the computing array PU and corresponds to the aforementioned on-chip verification algorithm. That is, the preset programming algorithm and the aforementioned encoding submodule 311 use the same algorithm. In addition, the computing controller 221 can determine which computing array PU (the relatively idle computing array PU) will execute the preset programming algorithm according to the execution status of the computing tasks corresponding to each computing array PU.

[0144] In this way, since the memory controller 100 reads the shadow register 21 at a low frequency, and the computing circuit 22 does not always run at full load during the computing process, such as during the data loading stage of the large model, the later stage of the operation, and the result write-back stage after the calculation is completed, the computing resources are idle, and the second error correction code Ecode_SR can be calculated.

[0145] As can be seen from the above, this disclosure provides a control method applied to a memory 200, the method comprising: During the read operation of the shadow register 21, the first computing configuration parameter PIMdata1 stored in the shadow register 21 is obtained, and the current value of the second computing configuration parameter PIMdata2 is obtained from the computing controller 221. The current values ​​of the first calculation configuration parameter PIMdata1 and the second calculation configuration parameter PIMdata2 are determined as the data to be calculated. The data to be calculated is encoded based on the on-chip verification algorithm, and the second error correction code Ecode_SR is output. Store the current value of the second calculation configuration parameter PIMdata2 and the second error correction code Ecode_SR into the shadow register 21.

[0146] In summary, the memory 200 provided in this embodiment enables the correct error correction code to be stored in the shadow register 21, allowing the data error correction module 31 to work normally in both the second and first modes. That is, reusing the same data error correction module 31 can make read and write operations compatible in both modes, ensuring the normal operation of the memory 200 while reducing the complexity of circuit design and the chip area occupied.

[0147] In another embodiment of this disclosure, please refer to Figure 19 and Figure 20 The first data processing module 30 includes a data flipping module 32. Here, the data flipping module 32 is used to provide data flipping functionality, also known as data bus flipping functionality.

[0148] It should be understood that for data transmitted between the memory controller 100 and the first external data port 25, data "0" consumes less energy than data "1". Therefore, taking a read command as an example, the data inversion module 32 will count the number of "0"s in the transmitted data. If the number of "0"s in the transmitted data is large, all the data can be inverted. In this case, the number of "1"s in the inverted data is large, and the energy consumption for transmission is less. At the same time, the data inversion module 32 will also output a toggle flag to inform the memory controller 100 whether the data transmitted this time has been inverted. Writing data is similar; please refer to the explanation for further understanding.

[0149] Please refer to Figure 19Figure (a) illustrates a schematic diagram of writing data from the first external data port 25 to the first storage array BK. Please refer to... Figure 20 (a) illustrates a schematic diagram of writing data from the first external data port 25 to the shadow register 21. Figure 19 (a) or Figure 20 As shown in (a): The first external data port 25 is also configured to receive the first flip flag DBIFlagin and initial data Data0 from external input; The data flipping module 32 is coupled between the first external data port 25 and the data error correction module 31, and is further configured to determine whether to perform level flipping processing on the initial data Data0 based on the first flipping flag DBIFlagin in the first mode, and generate and output the first data Data1; wherein the first data Data1 is the initial data Data0 or the inverse of the initial data Data0.

[0150] Specifically, if the first flip flag DBIFlagin is enabled, then the first data Data1 is the inverse of the initial data Data0; if the first flip flag DBIFlagin is disabled, then the first data Data1 can be regarded as the initial data Data0.

[0151] like Figure 19 As shown in (a), the first storage array BK is configured to store the first data Data1 in the first mode.

[0152] like Figure 20 As shown in (a), the shadow register 21, configured in the second mode, stores a portion of the bits in the first data Data1 as the first calculation configuration parameter PIMdata1.

[0153] Please refer to Figure 19 Figure (b) illustrates a schematic diagram of reading data from the first external data port 25 from the first storage array BK. Figure 13 As shown in (b): The data inversion module 32 is further configured to, in the first mode, receive target data Data_Array output from the first storage array BK, perform statistics on the target level (e.g., low level 0) data in the target data Data_Array to generate a read output inversion flag DBIFlagout_array, determine whether to invert the target data Data_Array based on the read output inversion flag DBIFlagout_array, output read output data Darray_output; and output the read output data Darray_output and the read output inversion flag DBIFlagout_array to the first external data port 25.

[0154] Here, if the read output toggle flag DBIFlagout_array is enabled, then the read output data Darray_output is the inverted data of the target data Data_Array; if the read output toggle flag DBIFlagout_array is disabled, then the read output data Darray_output can be considered as the target data Data_Array.

[0155] In some embodiments, the data flipping module 32 has the same data processing state in the second mode and the first mode.

[0156] Please refer to Figure 20 Figure (b) illustrates a schematic diagram of reading data from the shadow register 21 from the first external data port 25. Figure 20 As shown in (b): The data inversion module 32 is specifically configured to, in the second mode, statistically analyze the target level data in the second data Data_SR output by the shadow register 21 to generate a second inversion flag DBIFlagout_SR, and determine whether to invert the second data Data_SR based on the second inversion flag DBIFlagout_SR, outputting a fourth data DSR_output; and outputting the fourth data DSR_output and the second inversion flag DBIFlagout_SR to the first external data port 25.

[0157] Similarly, if the second toggle flag DBIFlagout_SR is enabled, then the fourth data DSR_output is the inverted data of the second data Data_SR; if the second toggle flag DBIFlagout_SR is disabled, then the fourth data DSR_output is the second data Data_SR.

[0158] In this way, whether it is data for the first storage array BK or data for the shadow register 21, the toggling can be determined during writing based on whether the first toggle flag is toggled, or during reading based on the number of target levels, thus saving power consumption.

[0159] In some embodiments, the first data processing module 30 includes a data error correction module 31 and a data flipping module 32.

[0160] Please refer to Figure 13 Figure (a) illustrates a schematic diagram of writing data from the first external data port 25 to the first storage array BK. Please refer to... Figure 14 (a) illustrates a schematic diagram of writing data from the first external data port 25 to the shadow register 21. Figure 13 (a) or Figure 14 As shown in (a): The first external data port 25 is also configured to receive the first flip flag DBIFlagin and initial data Data0 from external input; The data flipping module 32 is coupled between the first external data port 25 and the data error correction module 31, and is further configured to determine whether to perform level flipping processing on the initial data Data0 based on the first flipping flag DBIFlagin in the first mode, and generate and output the first data Data1; wherein the first data Data1 is the initial data Data0 or the inverse of the initial data Data0.

[0161] Specifically, if the first flip flag DBIFlagin is enabled, then the first data Data1 is the inverse of the initial data Data0; if the first flip flag DBIFlagin is disabled, then the first data Data1 can be regarded as the initial data Data0.

[0162] Here, the enabled state is either a high level 1 or a low level 0, and the disabled state is either a high level 1 or a low level 0.

[0163] Please refer to Figure 13 Figure (b) illustrates a schematic diagram of reading data from the first external data port 25 from the first storage array BK. Figure 13 As shown in (b): The data flipping module 32 is also configured to, in the first mode, receive the read result data Darray_out output by the data error correction module 31, perform statistics on the target level (e.g., low level 0) data in the read result data Darray_out to generate a read output flip flag, and determine whether to invert the read result data Darray_out based on the read output flip flag DBIFlagout_array, output the read output data Darray_output; and output the read output data Darray_output and the read output flip flag DBIFlagout_array to the first external data port 25.

[0164] Here, if the read output toggle flag DBIFlagout_array is enabled, then the read output data Darray_output is the inverted data of the read result data Darray_out; if the read output toggle flag DBIFlagout_array is disabled, then the read output data Darray_output can be considered as the read result data Darray_out.

[0165] In some embodiments, the data flipping module 32 has the same data processing state in the second mode and the first mode.

[0166] Please refer to Figure 14 Figure (b) illustrates a schematic diagram of reading data from the shadow register 21 from the first external data port 25. Figure 14 As shown in (b): The data inversion module 32 is specifically configured to, in the second mode, perform statistics on the target level data in the third data DSR_out to generate a second inversion flag DBIFlagout_SR, and determine whether to invert the third data DSR_out based on the second inversion flag DBIFlagout_SR to output the fourth data DSR_output; and output the fourth data DSR_output and the second inversion flag DBIFlagout_SR to the first external data port 25.

[0167] Similarly, if the second toggle flag DBIFlagout_SR is enabled, then the fourth data DSR_output is the inverted data of the third data DSR_out; if the second toggle flag DBIFlagout_SR is disabled, then the fourth data DSR_output is the third data DSR_out.

[0168] In this way, whether it is data for the first storage array BK or data for the shadow register 21, the toggling can be determined during writing based on whether the first toggle flag is toggled, or during reading based on the number of target levels, thus saving power consumption.

[0169] In other embodiments, the data error correction module 31 is also configured to be disabled in the second mode, and the input initial data Data0 is output directly without processing.

[0170] For details, please see Figure 10 The memory 200 is further configured to receive and, in response to the data processing function shutdown command MRW1, disable the data processing functions provided by the first data processing module 30 before decoding externally sent operation commands and generating a special write signal SR_WR or a special read signal SR_RD; the data processing functions include: the data flipping function of the data flipping module 32, i.e. Figure 10 The enable signal DBI_En of the data flipping module 32 changes to the Off state; The memory 200 is further configured to receive and respond to the data processing function enable command MRW3 after the read / write operation of the shadow register 21 indicated by the special write signal SR_WR or the special read signal SR_RD is completed, thereby enabling the data processing function provided by the first data processing module 30. Figure 10 The enable signal DBI_En of the data flipping module 32 changes to the On state.

[0171] It should be understood that both the data processing function disable command MRW1 and the data processing function enable command MRW3 are sent by the memory controller 100. Therefore, the memory controller 100 knows whether the memory 200 has enabled the data flipping function and thus takes corresponding actions. In other words, during the period when the data flipping module 32 is disabled, the data sent by the memory controller 100 is not subject to flipping processing.

[0172] It should be noted that, please refer to Figure 10 The value in the second mode register MR3 in memory 200 is used to indicate whether the data flipping function is enabled. Therefore, the data processing function disable command MRW1 and the data processing function enable command MRW3 are both manifested as mode register write commands, enabling or disabling the data flipping module 32 by modifying the corresponding value in the second mode register MR3. In this scenario, the value of the second mode register MR3 can also be used to distinguish between the first mode and the second mode.

[0173] In this way, the shadow register 21 will only be read and written after the data processing function provided by the first data processing module 30 is turned off, so as to avoid the first data processing module 30 being unable to handle the data in the shadow register 21 and reporting an error.

[0174] As mentioned above, the data error correction module 31 can protect the data stored in the memory 200. In some embodiments, the aforementioned data error correction module 31 can not only protect the data stored in the memory 200 (i.e., on-chip verification algorithm), but also jointly protect the data transmitted between the memory controller 100 and the memory 200 (i.e., link verification algorithm). The following is a detailed description.

[0175] Please refer to Figure 15 Figure (a) illustrates a schematic diagram of writing data from the first external data port 25 to the first storage array BK. Please refer to... Figure 16 (a) illustrates a schematic diagram of writing data from the first external data port 25 to the shadow register 21. Figure 15 (a) or Figure 16 As shown in (a): The first external data port 25 is also configured to receive the first flip flag DBIFlagin, initial data Data0 and initial link error correction code Ecodein0 from external input; The data flipping module 32 is specifically configured to determine whether to perform level flipping processing on the initial link error correction code Ecodein0 based on the first flipping flag DBIFlagin, and generate and output the first link error correction code Ecodein.

[0176] The data error correction module 31 is further configured to correct the first data Data1 using the first link error correction code Ecodein based on the link verification algorithm before encoding the first data Data1 based on the on-chip verification algorithm, and generate the corrected first data Data1'. Similarly, if the first flip flag DBIFlagin is enabled, the first link error correction code Ecodein is the inverse of the initial link error correction code Ecodein0; if the first flip flag DBIFlagin is disabled, the first link error correction code Ecodein is the initial link error correction code Ecodein0.

[0177] In some embodiments, the link verification algorithm differs from the on-chip verification algorithm.

[0178] In other embodiments, the link verification algorithm is the same as the on-chip verification algorithm.

[0179] The following explanation uses the example that "the data processing process of the data flipping module 32 is the same in the first mode and the second mode" as an example, but this does not constitute a limitation.

[0180] Please refer to Figure 15(b) shows a schematic diagram of reading data from the first external data port 25 from the first storage array BK. Figure 15 As shown in (b): The data error correction module 31 is also configured to, in the first mode, correct the target data Data_Array using the target error correction code Ecode_Array based on the on-chip verification algorithm and output the read result data Darray_out; and to encode the read result data Darray_out based on the link verification algorithm and output the read result link error correction code Earray_out. The data inversion module 32 is specifically configured to statistically analyze the target level data in the read result data Darray_out and the read result link error correction code Earray_out to generate a read output inversion flag DBIFlagout_array, and determine whether to invert the read result data Darray_out and the read result link error correction code Earray_out based on the read output inversion flag DBIFlagout_array, and output the read output data Darray_output and the read output link error correction code Earray_output; and output the read output inversion flag DBIFlagout_array, the read output data Darray_output, and the read output link error correction code Earray_output to the first external data port 25.

[0181] Similarly, if the read output toggle flag DBIFlagout_array is enabled, the read output data Darray_output is the inverted data of the read result data Darray_out, and the read output link error correction code Earray_output is the inverted data of the read result link error correction code Earray_out; if the read output toggle flag DBIFlagout_array is disabled, the read output data Darray_output is the read result data Darray_out, and the read output link error correction code Earray_output is the read result link error correction code Earray_out.

[0182] Please refer to Figure 16 (b) shows a schematic diagram of reading data from the shadow register 21 from the first external data port 25. Figure 16 As shown in (b): The data error correction module 31 is configured to, in the second mode, directly output the second data Data_SR as the third data DSR_out in response to the special read signal SR_RD; or, based on the on-chip verification algorithm, use the second error correction code Ecode_SR to perform error correction processing on the second data Data_SR, generate and output the third data DSR_out. The data error correction module 31 is also configured to encode the third data DSR_out based on the link verification algorithm and output the second link error correction code EcodeSR_out; The data inversion module 32 is specifically configured to perform statistics on the target level data in the third data DSR_out and the second link error correction code EcodeSR_out to generate a second inversion flag DBIFlagout_SR, and determine whether to invert the third data DSR_out and the second link error correction code EcodeSR_out based on the second inversion flag DBIFlagout_SR, and output the fourth data DSR_output and the third link error correction code EcodeSR_output; and output the fourth data DSR_output, the third link error correction code EcodeSR_output and the second inversion flag DBIFlagout_SR to the first external data port 25.

[0183] Similarly, if the second flip flag DBIFlagout_SR is enabled, then the fourth data DSR_output is the inverted data of the third data DSR_out, and the third link error correction code EcodeSR_output is the inverted data of the second link error correction code EcodeSR_out; if the second flip flag DBIFlagout_SR is disabled, then the fourth data DSR_output is the third data DSR_out, and the third link error correction code EcodeSR_output is the second link error correction code EcodeSR_out.

[0184] With the evolution of storage protocols, new-generation storage protocols (such as LP6) have introduced more storage arrays and multiple operating modes.

[0185] In some embodiments, see Figure 17 The memory 200 includes a first sub-channel and a second sub-channel. The first sub-channel includes the aforementioned first storage array BK, external data selector 23, first data processing module 30, and first external data port 25. The second sub-channel has a similar main structure to the first sub-channel but does not have a shadow register 21. The second sub-channel includes a second storage array, a data selector, a second data processing module, and a second external data port.

[0186] The memory 200 supports Dynamic Efficiency Mode (DEFF), Static Efficiency Mode (SEFF), and Normal Operating Mode.

[0187] It's important to note that static efficiency mode typically refers to memory operating in a fixed, preset low-power or low-performance state, unaffected by load changes. This is suitable for scenarios with relatively stable power consumption and latency requirements. Dynamic efficiency mode, on the other hand, dynamically adjusts voltage, frequency, or refresh strategies based on real-time memory bandwidth utilization, latency demands, and other load conditions. This provides higher performance when needed and further reduces power consumption during idle periods, achieving a better energy efficiency balance.

[0188] The memory 200 is configured to, in normal operating mode, transmit data for the first memory array BK using the first external data port 25, and transmit data for the second memory array using the second external data port; or, In either dynamic or static operating mode, data for the first storage array BK or the second storage array is transmitted using the first external data port 25.

[0189] Therefore, in some embodiments, such as Figure 17 As shown, the external data selector 23 also has a third strobe terminal, which is coupled to a plurality of second memory arrays. External data selector 23, specifically configured in the second mode, selects the data transmission path between the first data processing module 30 and the shadow register 21 to obtain data from the shadow register 21 or to write data to the shadow register 21. Alternatively, in the first mode, the data transmission path between the first data processing module 30 and the first storage array BK is selected to obtain data from the first storage array BK or to write data to the first storage array BK. Alternatively, in the first mode, the data transmission path between the first data processing module 30 and the second storage array is selected to obtain data from the second storage array or to write data to the second storage array.

[0190] In this way, the external data selector 23 actually reuses the data selector that originally existed between the first and second sub-channels in the memory 200. By adding a strobe terminal on it, the data of the shadow register 21 is finally incorporated.

[0191] It should be noted that the second storage array and the first storage array have the same structure and working principle. In normal mode, the second sub-channel operates similarly to the first sub-channel, the second external data port can be understood with reference to the first external data port, and the second data processing module can be understood with reference to the first data processing module.

[0192] In some embodiments, the memory 200 may be a single physical chip.

[0193] In other embodiments, the memory 200 may include a WOW structure comprising multiple chips stacked vertically (active plane). For example, computing circuitry 22 is located on one of the chips, and a first memory array and a second memory array are located on another chip.

[0194] In this application, the term 'memory 200' refers to any physical device or module used for storing data / in-memory computing, including but not limited to: memory chips, memory dies, multi-chip packages, ball grid array packaged memory 200, single in-line memory modules, dual in-line memory modules, small outline dual in-line memory modules, micro dual in-line memory modules, registered memory, low-load memory, high-bandwidth memory 200, solid-state drives, embedded multimedia cards, general-purpose flash memory, memory cards, and on-board packaged or integrated memory units.

[0195] In another embodiment of this disclosure, an electronic device is provided, which includes the aforementioned memory 200. The electronic device may be a user equipment (UE), a mobile device, a handheld device, a computing device, an in-vehicle device, a wearable device, etc.

[0196] Examples include: personal computers (PCs), mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), enterprise digital assistants (EDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, server computers, data centers, workstations, mobile phones, smartphones, and tablets.

[0197] The above description is merely an example embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0198] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0199] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0200] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or circuit embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or circuit embodiments without conflict. The above descriptions are merely specific embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the protection scope of this disclosure.

Claims

1. A memory, characterized in that, The memory includes a first external data port, a first data processing module, an external data selector, a shadow register, and multiple first storage arrays; The first external data port is configured to receive data from outside the memory; or to send data stored in the memory to an external source. The external data selector has a first terminal, a first strobe terminal, and a second strobe terminal, which are respectively coupled to the first data processing module, the shadow register, and the first storage array; the external data selector is configured to select the data transmission path between the first data processing module and the shadow register when the memory is in the second mode, so as to obtain data from the shadow register or write data to the shadow register. And when the memory is in the first mode, the data transmission path between the first data processing module and the coupled first storage array is selected to obtain data from the first storage array or to write data to the first storage array. The first data processing module is coupled between the first external data port and the first end of the external data selector, and is configured to perform data verification processing and / or data flipping processing on the data transmitted therethrough.

2. The memory according to claim 1, characterized in that, The first data processing module includes a data error correction module; The first external data port is configured to receive initial data from external input; The data error correction module is coupled to the first external data port and is further configured to, in the first mode, encode the first data corresponding to the initial data based on the on-chip verification algorithm to generate a first error correction code, and output the first data and the first error correction code; The first storage array is further configured to receive and store the first data and the first error correction code in response to a regular write signal in the first mode; The regular write signal indicates that the data input via the first external data port will be stored in the first storage array.

3. The memory according to claim 2, characterized in that, The data error correction module is further configured to output only the first data in the second mode; The shadow register is also configured to, in the second mode, receive and store at least a portion of the bits in the first data as a first calculation configuration parameter in response to a special write signal; The special write signal indicates that the data input via the first external data port will be stored in the shadow register.

4. The memory according to claim 3, characterized in that, The data error correction module is also configured to be disabled or bypassed in the second mode, and the input first data is not processed but directly output.

5. The memory according to claim 3, characterized in that, The data error correction module is further configured to encode the first data based on an on-chip verification algorithm to generate the first error correction code in the second mode, and output only the first data; wherein the first error correction code is discarded.

6. The memory according to claim 3, characterized in that, The memory also includes a computing controller; The computing controller is connected to the shadow register and configured to write the second computing configuration parameter to the shadow register; wherein the storage locations of the first computing configuration parameter and the second computing configuration parameter in the shadow register are independent of each other. The external data selector is further configured to, in the second mode, transmit the second data from the shadow register to the data error correction module in response to a special read signal; wherein the second data includes the first in-memory calculation parameters and / or the second calculation configuration parameters; The data error correction module is further configured to, in the second mode, directly output the second data as the third data in response to the special read signal; The special read signal indicates that the data stored in the shadow register should be output via the first external data port.

7. The memory according to claim 3 or 6, characterized in that, The data error correction module includes an encoding submodule and a verification submodule; The encoding submodule is configured to encode the received second data and output the error correction code to be compared. The verification submodule is configured to receive an enable control signal and, when the enable control signal indicates that it is in the second mode, directly output the second data.

8. The memory according to claim 2, characterized in that, The memory also includes a computing controller and an error correction code computing module; The computing controller is further configured to, in the second mode, read a first computing configuration parameter from the shadow register in response to a special read signal, and output the current values ​​of the first computing configuration parameter and the second computing configuration parameter as data to be computed; The error correction code calculation module is coupled to the calculation controller and is configured to receive and calculate the data to be calculated, generate and output a second error correction code. The computing controller is further configured to store the current value of the second computing configuration parameter and the second error correction code into the shadow register; The external data selector is further configured to, in the second mode, transmit the second data from the shadow register and the second error correction code to the data error correction module in response to a special read signal; The data error correction module is further configured to receive second data and the second error correction code output from the shadow register; based on the on-chip verification algorithm, the second error correction code is used to perform error correction processing on the second data to generate and output third data.

9. The memory according to claim 2, characterized in that, The memory also includes a computing controller and multiple computing arrays; The computing array is configured to perform in-memory computations on the received data; The computing controller, connected to multiple computing arrays, is further configured to read a first computing configuration parameter from the shadow register in response to a special read signal, and determine the current values ​​of the first computing configuration parameter and the second computing configuration parameter as the data to be computed; In addition, the second error correction code generated after the data to be calculated is processed by a preset programming algorithm is obtained, and the current value of the second calculation configuration parameter and the second error correction code are stored in the shadow register; The external data selector is further configured to, in the second mode, transmit the second data from the shadow register and the second error correction code to the data error correction module in response to a special read signal; The data error correction module is further configured to receive second data and the second error correction code output from the shadow register; based on the on-chip verification algorithm, the second error correction code is used to perform error correction processing on the second data to generate and output third data; The preset programming algorithm is implemented based on the computing units in the computing array.

10. The memory according to claim 8 or 9, characterized in that, The first data processing module further includes: a data flipping module; The first external data port is also configured to receive a first flip flag and the initial data from an external input; The data flipping module is coupled between the first external data port and the data error correction module, and is further configured to determine whether to perform level flipping processing on the initial data based on the first flipping flag in the first mode, and generate and output the first data; wherein the first data is the initial data or the inverse data of the initial data.

11. The memory according to claim 10, characterized in that, The data flipping module performs the same data processing procedure in the second mode as in the first mode.

12. The memory according to claim 10, characterized in that, The data error correction module is also configured to be disabled in the second mode, where the input initial data is output directly without processing.

13. The memory according to claim 10, characterized in that, The memory is further configured to receive and respond to a data processing function shutdown command before decoding an externally sent operation command and generating a special write signal or a special read signal, thereby disabling the data processing function provided by the first data processing module; the data processing function includes: the data error detection / correction function of the data error correction module and the data flipping function of the data flipping module; The memory is further configured to receive and respond to a data processing function enable command after the read / write operation of the shadow register indicated by the special write signal or the special read signal is completed, and enable the data processing function provided by the first data processing module.

14. The memory according to claim 10, characterized in that, The first external data port is also configured to receive an initial link error correction code from an external input; The data flipping module is further configured to determine whether to perform level flipping processing on the initial link error correction code based on the first flipping flag, and generate and output the first link error correction code; wherein, the first link error correction code is the initial link error correction code or the inverse data of the initial link error correction code; The data error correction module is further configured to correct the first data using the first link error correction code based on the link verification algorithm before encoding the first data based on the on-chip verification algorithm. The data error correction module is further configured to encode the third data based on the link verification algorithm and output a second link error correction code; The data flipping module is specifically configured to perform statistics on the target level data in the third data and the second link error correction code to generate a second flip flag, determine whether to invert the third data and the second link error correction code according to the second flip flag, and output the third data or its inverted data, the second link error correction code or its inverted data, and the second flip flag together to the first external data port.

15. The memory according to claim 1, characterized in that, The memory also includes multiple second memory arrays; The external data selector also has a third strobe terminal, which is coupled to a plurality of the second storage arrays; The external data selector, specifically configured in the second mode, selects the data transmission path between the first data processing module and the shadow register to obtain data from the shadow register or to write data to the shadow register. Alternatively, in the first mode, the data transmission path between the first data processing module and the first storage array is selected to obtain data from the first storage array or to write data to the first storage array. Alternatively, in the first mode, the data transmission path between the first data processing module and the second storage array is selected to obtain data from the second storage array or to write data to the second storage array.

16. A control method, characterized in that, The invention is applied to a memory, which includes multiple first memory arrays, a shadow register, an external data selector, a data error correction module, and a first external data port. The data error correction module is coupled between the first external data port and a first end of the external data selector. The external data selector also has a first strobe end and a second strobe end, which are respectively coupled to the shadow register and the first memory array. The method includes: In the first mode, the external data selector is used to select the data error correction module and the first storage array, and the data error correction module is controlled to be in working state, to encode the input first data, output the first check code, and store the first data and the first check code in the first storage array; In the second mode, the external data selector is used to select the data error correction module and the shadow register, and the data error correction module is controlled to be in a disabled or bypassed state, so that the input first data is directly output without processing, and at least a portion of the bits of the first data are stored as the first calculation configuration parameter in the shadow register.

17. A control method, characterized in that, The invention is applied to a memory, which includes a computing controller, a shadow register, multiple first memory arrays, an external data selector, a data error correction module, and a first external data port. The data error correction module is coupled between the first external data port and a first end of the external data selector. The external data selector also has a first strobe end and a second strobe end, which are respectively coupled to the shadow register and the first memory array. The method includes: In the first mode, the external data selector is used to select the data error correction module and the first storage array; In the second mode, the external data selector is used to select the data error correction module and the shadow register; and, during the read operation of the shadow register, the first calculation configuration parameter stored in the shadow register is obtained, and the current value of the second calculation configuration parameter is obtained from the calculation controller; the current values ​​of the first calculation configuration parameter and the second calculation configuration parameter are determined as the data to be calculated, the data to be calculated is encoded based on the on-chip verification algorithm, and a second error correction code is output; the current value of the second calculation configuration parameter and the second error correction code are stored in the shadow register.

18. An electronic device, characterized in that, The memory includes the memory as described in any one of claims 1-15.

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