A montgomery modular multiplication circuit and method

Abstract

The application discloses a Montgomery modular multiplication circuit and a Montgomery modular multiplication method, and aims at solving the problem that in the existing Montgomery modular multiplication hardware implementation scheme, the multiplier is in intermittent working state, which leads to obvious high-low fluctuation of power consumption in the whole operation process, and further easily causes local voltage sag. The Montgomery modular multiplication circuit comprises a multiplier, a summer, a state machine and a pseudo operation control unit. The multiplier is used for performing multiplication operation. The summer is connected with the output end of the multiplier and is used for performing accumulation operation on the multiplication result. The state machine is used for controlling the data flow direction of each operation unit in the Montgomery modular multiplication circuit. The pseudo operation control unit is used for increasing the number of non-zero bits of input data before the multiplier starts and decreasing the number of non-zero bits of input data after the operation of the multiplier ends. The state machine is configured to enable the multiplier continuously from the start of the multiplier to the end of the operation in the Montgomery modular multiplication operation process, so that the continuous operation of the multiplier is maintained in the Montgomery modular multiplication operation process through the summer.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a Montgomery modular multiplication circuit and a Montgomery modular multiplication method. Background Technology

[0002] Montgomery modular multiplication is a core computational module in public-key cryptography algorithms, widely used in Super SIM cards, eSIM cards, and other smart card chips. As process nodes continue to shrink and the demands for processing speed increase, the bit width of Montgomery modular multiplication operations is becoming larger (e.g., 64x64 bits), and its power consumption as a percentage of the overall chip power consumption is also rising, becoming a key factor affecting chip performance and stability.

[0003] In existing Montgomery modular multiplication hardware implementations, the design focus is typically on improving computational speed. However, in actual hardware execution, the core arithmetic units (such as multipliers) often operate intermittently, frequently switching between on and off. Because the power consumption of the arithmetic units rises sharply when on and falls sharply when off, the power consumption curve throughout the modular multiplication process exhibits significant fluctuations. These fluctuations can cause sudden drops in local voltage, potentially leading to logic level errors in digital circuits, and in severe cases, even causing chip reset.

[0004] Therefore, how to provide a hardware implementation method for Montgomery modular multiplication that can effectively suppress power consumption fluctuations and achieve smooth power consumption transition has become a technical problem that needs to be solved in the existing technology. Summary of the Invention

[0005] This application provides a Montgomery modular multiplication circuit to solve the problem that in existing Montgomery modular multiplication hardware implementations, the multiplier operates intermittently, causing the power consumption curve to fluctuate significantly throughout the modular multiplication process, which can easily lead to sudden drops in local voltage and cause errors in the logic level of the digital circuit.

[0006] This application also provides a Montgomery modular multiplication method to solve the problem that in existing Montgomery modular multiplication hardware implementations, the multiplier is in an intermittent working state, causing the power consumption curve to fluctuate significantly throughout the modular multiplication operation, which can easily lead to a sudden drop in local voltage and cause errors in the logic level of digital circuits.

[0007] The embodiments of this application adopt the following technical solutions: A Montgomery modular multiplication circuit includes: a multiplier for performing multiplication operations to obtain a multiplication result; an adder connected to the output of the multiplier for performing an accumulation operation on the multiplication result; a state machine for controlling the enabling and data flow of each arithmetic unit in the Montgomery modular multiplication circuit; and a pseudo-operation control unit for controlling the increase of non-zero bits in the input data before the multiplier is started and controlling the decrease of non-zero bits in the input data after the multiplication operation is completed; the state machine is configured to: continuously enable the multiplier from the start of the multiplier to the end of the operation during the Montgomery modular multiplication operation, so that the multiplier performs a multiplication operation in each clock cycle, and maintain the continuous operation of the multiplier during the Montgomery modular multiplication operation through the adder.

[0008] A Montgomery modular multiplication method includes: increasing the number of non-zero bits in the input data of the multiplier through a pseudo-operation control unit to increase the power consumption of the multiplier; maintaining continuous execution of multiplication operations by the multiplier during the Montgomery modular multiplication operation, and performing addition operations in parallel or pipelined manner during the execution of the multiplication operation to keep the multiplier running continuously; and reducing the number of non-zero bits in the input data of the multiplier through the pseudo-operation control unit after the multiplier completes the Montgomery modular multiplication operation to decrease the power consumption of the multiplier.

[0009] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects: The Montgomery modular multiplication circuit provided in this application includes: a multiplier for performing multiplication operations to obtain a multiplication result; an adder connected to the output of the multiplier for performing an accumulation operation on the multiplication result; a state machine for controlling the enabling and data flow of each operation unit in the Montgomery modular multiplication circuit; and a pseudo-operation control unit for controlling the increase of non-zero bits in the input data before the multiplier starts and controlling the decrease of non-zero bits in the input data after the multiplier operation ends; the state machine is configured to: continuously enable the multiplier from the start of the multiplier to the end of the operation during the Montgomery modular multiplication operation, so that the multiplier performs a multiplication operation in each clock cycle, and maintain the continuous operation of the multiplier during the Montgomery modular multiplication operation through the adder. The Montgomery modular multiplication circuit provided in this application uses a state machine to control the multiplier to remain continuously enabled throughout the entire Montgomery modular multiplication operation. Multiplication is performed in every clock cycle. Combined with the cooperative design of the adder, the multiplier operates without idle interruptions from its initial startup to the end of the last operation. This eliminates the power consumption fluctuations caused by frequent start-stop cycles during the operation. Due to the smooth power consumption curve, instantaneous power consumption fluctuations are significantly reduced, effectively suppressing local voltage drops caused by large current surges. This effectively avoids logic level errors in digital circuits caused by instantaneous voltage drops, ensuring the correct establishment and maintenance of internal signals during modular multiplication. Simultaneously, the pseudo-operation control unit gradually increases the number of non-zero bits in the input data before the multiplier starts and gradually decreases it after the multiplier ends, achieving a smooth rise and fall in power consumption. Therefore, the power consumption of the entire Montgomery modular multiplication operation is stabilized within a narrow range, avoiding voltage spikes and drops caused by power consumption surges, fundamentally preventing the risk of chip reset due to voltage anomalies. Attached Figure Description

[0010] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A schematic diagram of the specific structure of a Montgomery modular multiplication circuit provided in this application embodiment; Figure 2 A schematic diagram illustrating the specific process of a smooth power consumption Montgomery modular multiplication method provided in this application embodiment; Figure 3 This is a schematic diagram illustrating a state transition process provided in an embodiment of this application. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0012] This application provides a Montgomery modular multiplication circuit to solve the problem that in existing Montgomery modular multiplication hardware implementations, the multiplier operates intermittently, causing the power consumption curve to fluctuate significantly throughout the modular multiplication process, which can easily lead to sudden drops in local voltage and cause errors in the logic level of the digital circuit.

[0013] The specific structure of the Montgomery modular circuit provided in this application embodiment is as follows: Figure 1 As shown, it mainly includes: a multiplier (MUL), a first adder (ADD0), a second adder (ADD1), a subtractor (SUB), a state machine (FSM), and a pseudo-operation control unit.

[0014] The multiplier is primarily used to perform multiplication operations. In one implementation, to meet the performance requirements of public-key cryptography algorithms, the multiplier can be a 64-bit multiplier (i.e., a 64×64 multiplier), capable of performing the multiplication of two 64-bit data within one clock cycle and outputting a 128-bit product. The power consumption of this multiplier mainly comes from bit flipping of the input data, and its instantaneous power consumption is positively correlated with the number of non-zero bits in the input data.

[0015] An adder, connected to the output of the multiplier, is used to add the result of the multiplication operation to the accumulated value and the cached data. In one embodiment, the Montgomery modular multiplication circuit provided in this application includes two adders, as follows: 1. First adder (ADD0): Used to add the product output by the multiplier to the accumulated value and the carry value, corresponding to the accumulation operation in the algorithm.

[0016] 2. Second adder (ADD1): Used to handle boundary carry additions during modular multiplication, such as carry accumulation of the highest bit word.

[0017] In this embodiment, the addition process performed by the adder includes three steps: data reception, addition calculation, and result transmission. During the data reception stage, the adder receives input data from the multiplier, data buffer unit, and other related modules. This data may include the multiplier's output, the accumulated value from the previous addition operation, and carry signals that may need to be processed. Subsequently, during the addition calculation stage, the first adder performs bit-by-bit addition on the received data, generating a partial sum and a carry signal. Simultaneously, the second adder handles boundary carry, ensuring that carry information is not lost in multi-bit addition operations. Finally, the adder transmits the calculated result to subsequent modules, such as the multiplier or data buffer unit, to support the next round of calculations. The entire addition process is uniformly scheduled by a state machine to ensure smooth data flow and correct calculation. In one implementation, the first adder and the second adder are arranged in parallel, so that while the multiplier is performing continuous operations, boundary additions do not occupy additional clock cycles, ensuring that the multiplier operates uninterruptedly.

[0018] The subtractor (SUB) is used to perform the final reduction. Specifically, the subtractor first compares the modular multiplication result with the modulus to determine if the former is greater than the latter. If the modular multiplication result is greater than the modulus, the subtractor performs a conditional subtraction operation, subtracting the modulus from the modular multiplication result to obtain the final result that meets the requirements; otherwise, if the modular multiplication result is less than or equal to the modulus, the modular multiplication result is directly output as the final result.

[0019] It should be noted that the Montgomery modular multiplication circuit provided in this application embodiment does not employ pre-reduction to avoid inconsistent result storage locations and facilitate calls by higher-level operators.

[0020] State Machine (FSM): The state machine is the control center of the Montgomery modular multiplication circuit. Its main function is to coordinate the enable states of various arithmetic units and the flow of data, thereby ensuring that the circuit executes Montgomery modular multiplication operations in a predetermined order. Specifically, the state machine monitors the current operating state and computation progress of the circuit, dynamically adjusting the enable signals of modules such as multipliers, adders, and pseudo-operation control units to achieve efficient resource scheduling and data transmission. Furthermore, the state machine is also responsible for managing the switching between different computational stages, such as transitioning from the multiplication stage to the addition stage, or from the pseudo-operation control stage to the normal computation stage.

[0021] In this embodiment, the state machine is configured to continuously enable the multiplier during the Montgomery modular multiplication operation, from the start of the multiplier to the end of the operation, so that the multiplier performs a multiplication operation in every clock cycle. Through the parallel / pipelined coordination of the adder, the multiplier is kept running continuously during the addition operation without any idle cycles inserted in between.

[0022] In one implementation, the state machine's workflow can be divided into multiple discrete states, each corresponding to a specific computational task or control operation. For example, at the start of a Montgomery modular multiplication operation, the state machine first enters an initialization state, resetting and configuring the parameters of each computational unit. Subsequently, the state machine transitions to the multiplier-enabled state, initiating the multiplier to perform the multiplication operation, and continuously monitoring the multiplier's operating status during this period. After the multiplier completes one round of computation, the state machine switches to the adder-enabled state, triggering the adder to process the multiplication result. During this process, the state machine determines whether to proceed to the next iteration or end the computation based on preset transition conditions.

[0023] The pseudo-operation control unit is used to control the non-zero number of input data to gradually increase before the multiplier starts and to control the non-zero number of input data to gradually decrease after the multiplier ends.

[0024] In one implementation, the pseudo-operation control unit can consist of a data gradient register and other auxiliary logic circuits. Its main function is to dynamically adjust the number of non-zero bits in the input data before and after the multiplier starts, thereby optimizing power consumption. Specifically, the data gradient register gradually increases the number of non-zero bits in the input data before the multiplier starts and gradually decreases the number of non-zero bits after the multiplier ends. During several clock cycles before the multiplier starts, it sequentially outputs multiplier data with increasing non-zero bits (e.g., from 16-bit, 32-bit, 48-bit to 64-bit); during several clock cycles after the multiplier ends, it sequentially outputs multiplier data with decreasing non-zero bits (e.g., from 64-bit, 48-bit, 32-bit to 16-bit). This gradient process, by precisely controlling the change pattern of the input data, effectively smooths the power consumption curve of the multiplier, avoiding power spikes caused by sudden high loads. Furthermore, the auxiliary logic circuits are responsible for generating control signals to coordinate the operation of the data gradient register and other arithmetic units, ensuring the smooth implementation of the pseudo-operation control strategy.

[0025] Furthermore, the Montgomery modular multiplication circuit provided in this application embodiment also includes a data buffer unit, used to store the operation data corresponding to the multiplication operation before the multiplier performs the multiplication operation, and to ensure that this data is not overwritten before the multiplication operation is completed, thereby supporting continuous operation of the multiplier. Specifically, the data buffer unit is used to temporarily store the operands to be multiplied, intermediate results, and some accumulated values. This data usually comes from the output of the previous round of operation or external input. By pre-storing this key data, the data buffer unit can effectively reduce the idle time of the multiplier due to waiting for data input, thereby improving the overall operating efficiency of the circuit.

[0026] Based on the aforementioned Montgomery modular multiplication circuit, the schematic diagram of the specific implementation process of the Montgomery modular multiplication method with smooth power consumption provided in this application is shown below. Figure 2 As shown, the main steps include the following: Step 11: Increase the number of non-zero bits in the input data of the multiplier by using the pseudo-operation control unit, so as to increase the power consumption of the multiplier. During the startup phase of the Montgomery modular multiplication circuit, the pseudo-operation control unit can adjust the data input to the multiplier through the data gradient register to achieve the increment of non-zero bits.

[0027] It's important to note that, due to the circuit's operating characteristics, the power consumption of a multiplier is closely related to the number of significant bits in its input data. As the number of non-zero bits in the input data increases, the switching frequency of the logic gates inside the multiplier increases significantly, leading to a rise in dynamic power consumption. Therefore, in the Montgomery analog multiplication circuit, increasing the number of non-zero bits in the input data through a pseudo-operation control unit forces the multiplier into a high-load state, thereby increasing its overall power consumption. This power ramp-up design aims to optimize the circuit's energy distribution and avoid energy waste caused by the multiplier's instantaneous start and stop. Simultaneously, the power ramp-up process must be synchronized with the state machine's control signals to ensure that the multiplier reaches a stable high-power state before the operation begins.

[0028] Specifically, the data gradation register can gradually increase the number of significant bits of the input data according to preset logic before the multiplier starts. For example, in the initial state, the input data may be filled with zeros to reduce power consumption. However, at the moment the multiplier starts, the pseudo-operation control unit is triggered by the state machine signal to gradually fill the high-order bits of the input data with significant values. The control logic ensures that the number of non-zero bits of the input data increases linearly or exponentially, thereby supporting the power ramp-up of the multiplier. In addition, the design of the data gradation register must consider timing requirements and resource consumption to ensure its stable operation under high-frequency clocks.

[0029] Step 12: During the Montgomery modular multiplication operation, the multiplier is kept running continuously, and during the execution of the multiplication operation, the addition operation is completed in parallel or pipelined manner so that the multiplier keeps running continuously. In this embodiment, the Montgomery modular multiplication operation is divided into at least two iteration cycles to ensure continuous operation of the multiplier throughout the entire operation. Within each iteration cycle, the multiplier performs a scan multiplication operation between the input data and the multiplier, and a reduction multiplication operation between the intermediate result and the modulus. Specifically, the state machine first loads the input data and the multiplier into the multiplier and initiates the first multiplication operation; subsequently, the multiplier's output is passed to the adder for partial sum accumulation, while the state machine controls the multiplier to load the next set of data to perform the next multiplication operation. In this way, the multiplier can continuously perform multiplication operations within each clock cycle, thereby improving its utilization and reducing computational latency. Furthermore, the continuous operation of the multiplier also relies on the cooperation of the pseudo-operation control unit to ensure a stable supply of input data and timing consistency.

[0030] In this embodiment, addition can be implemented by setting up a first adder and a second adder in parallel to ensure the continuous operation of the multiplier. The first adder is responsible for adding the result of the multiplication operation to the accumulated value and the cached data to form a partial sum; while the second adder focuses on handling boundary carry additions during modular multiplication to ensure the accuracy of the operation result. Specifically, the first adder receives the output result of the multiplier and adds it to the accumulated value of the previous iteration and the temporary data in the data cache unit to generate a new partial sum. At the same time, the second adder detects and handles possible boundary carry situations to avoid errors caused by carry overflow. Through this parallel architecture, the adder can prepare for the next addition operation while the multiplier completes the current operation, thereby minimizing the idle time of the multiplier and improving the overall efficiency of the circuit.

[0031] Step 13: After the multiplier completes the Montgomery modular multiplication operation, the non-zero number of input data to the multiplier is reduced by the pseudo-operation control unit, so as to reduce the power consumption of the multiplier. After the multiplier completes the Montgomery modular multiplication operation, the pseudo-operation control unit can gradually reduce the number of non-zero bits in the input data to the multiplier through the data gradient register, thereby reducing power consumption.

[0032] Specifically, the pseudo-operation control unit is triggered by the end signal of the state machine and gradually clears the high-order bits of the input data to zero according to preset logic, thereby reducing the load on the multiplier. This process corresponds to the operation of increasing the non-zero bits during the multiplier startup phase, but in the opposite direction. In this way, the input data of the multiplier gradually returns to a low-power state, laying the foundation for energy consumption optimization in subsequent idle cycles.

[0033] Corresponding to the principle of power ramp-up, reducing the number of non-zero bits in the input data leads to a decrease in the switching frequency of the logic gates inside the multiplier, thereby significantly reducing dynamic power consumption. When the number of non-zero bits in the input data decreases, the number of logic gates participating in the operation in the multiplier decreases accordingly, and the node switching activity and load capacitance also decrease, thus achieving a reduction in power consumption.

[0034] After completing the Montgomery modular multiplication operation through the above steps, a subtractor can be used to perform modulus comparison and conditional subtraction on the result to ensure the correctness of the final result. Specifically, the subtractor first compares the modular multiplication result with a predefined modulus. If the modular multiplication result is greater than or equal to the modulus, a conditional subtraction operation is performed, that is, the modulus is subtracted from the modular multiplication result; otherwise, the modular multiplication result is directly output as the final result.

[0035] Based on the subtractor's processing results, the final result of Montgomery's modular multiplication can be obtained through simple logical judgment. If the subtractor does not perform a conditional subtraction operation, the modular multiplication result is directly output as the final result; if the subtractor performs a conditional subtraction operation, the result after subtraction is output as the final result.

[0036] In one implementation, the input and output of the Montgomery modular multiplication algorithm are defined as follows: Input: Large numbers a and b, constant n0, where the constant n0 can be determined according to the following formula [1]: n0= -n0^{-1} % w, w = 2^64 [1] Output: t = (a* b) mod n.

[0037] In one implementation, the Montgomery modular multiplication algorithm can employ a coarse integrated operand scan CIOS architecture, merging multiplication and reduction into two nested loops. The outer loop variable i iterates from 0 to s-1 (where s is the length in 64-bit word segments), and the inner loop contains two phases: the first phase is multiplication and accumulation, and the second phase is multiplication and reduction.

[0038] In this embodiment of the application, the specific processing flow of the above two stages is as follows, including: Phase 1, Multiplication and Accumulation Operations: For each fixed value i, the inner loop variable j iterates from 0 to s-1, performing the following operations in sequence: Read a[j] and b[i] from storage, and the multiplier calculates the product a[j]*b[i].

[0039] Simultaneously, the current accumulated intermediate result t[j] and the carry value C are read. The first adder adds the product a[j]* b[i] to t[j] and the carry C to obtain the result S and the carry C.

[0040] Write the result S back to t[j].

[0041] After the inner loop finishes, the carry of the most significant bit is processed: t[s] is added to the carry C, and the result is stored in t[s]. The resulting higher carry is stored in t[s+1]. This boundary addition is performed by the second adder and does not occupy the multiplier clock.

[0042] The second stage, multiplication, reduction, and subtraction operations: First, calculate the quotient m of the current iteration: read t[0] and constant n0, calculate the product t[0]* n0 through the multiplier, and take the lower 64 bits of the product as m, that is, m=t[0]*n0% w. Since w=2^64, the modulo operation is implemented by truncating the lower 64 bits.

[0043] Then, the inner loop variable j iterates from 1 to s-1, performing the following operations in sequence: The product m*n[j] is calculated using a multiplier; Simultaneously reading t[j] and carry C, the first adder adds the product m×n[j] to t[j] and carry C to obtain the result S and carry C.

[0044] Write the result S into t[j-1], which means shifting the result left by one word.

[0045] After the inner loop finishes, the boundary carry is processed: t[s] is added to the carry C, and the result is stored in t[s-1]; then t[s+1] is added to the previously stored carry, and the result is stored in t[s]. This boundary addition is also performed by the second adder.

[0046] After completing all outer loops (i=0 to s-1), perform the final reduction: compare the intermediate result t with the modulus n. If t≥n, the subtractor executes t = tn and outputs the final result; otherwise, output t directly.

[0047] In one implementation, the Montgomery modular multiplication operation mainly includes the following core states: initial idle state (IDLE), data acquisition state (GET_DATA), multiplication and accumulation state (AMULB), quotient calculation state (MCAL), multiplication and reduction state (MMULN), and comparison and reduction state (CMP_SUB). The transition conditions and execution actions between each state are as follows: Figure 3 As shown, it includes: 1. Initial Idle State (IDLE): After the system starts up, it first enters the IDLE state, waiting for the modular multiplication operation to start signal.

[0048] In IDLE state, all arithmetic units (multipliers, adders, subtractors) are disabled or in a low-power state, and the data cache is cleared.

[0049] Jump condition: When the external start signal Start is received, the state machine jumps to the "GET_DATA state".

[0050] 2. Data retrieval status (GET_DATA): Before the multiplier performs its actual operation, the input data for the modular multiplication operation is prefetched, and the pseudo-operation control unit starts the data gradient register to perform pseudo-operation ramping.

[0051] Specifically, large numbers a and b, along with the modulus n, can be read from memory and stored in the data buffer unit. Simultaneously, the pseudo-operation control unit activates the data gradient register, which sequentially outputs multiplier data with increasing non-zero bits: In the first clock cycle, it outputs 64 bits of data with the lower 16 bits non-zero and the higher 48 bits zero; in the second clock cycle, it outputs the lower 32 bits non-zero and the higher 32 bits zero; in the third clock cycle, it outputs the lower 48 bits non-zero and the higher 16 bits zero; and in the fourth clock cycle, it outputs all 64 bits of non-zero data. Each clock cycle, the multiplier performs one pseudo-multiplication operation, allowing the multiplier's power consumption to gradually increase.

[0052] Duration: Fixed at two clock cycles, used to complete the first stage of data prefetching and pseudo-computation ramp-up.

[0053] Jump condition: After two clock cycles, the state machine jumps to the multiply-accumulate state (AMULB).

[0054] 3. Multiply-accumulate state (AMULB): The state machine control circuit performs the multiplication and accumulation operation in the first stage of the outer loop, that is, calculates a[j] * b[i] and accumulates it to the intermediate result t[j].

[0055] Taking s=4 as an example, the specific timing sequence is as follows: First clock cycle: The multiplier calculates a[0]*b[0], while the data buffer unit pre-reads t[0] and the carry.

[0056] Second clock cycle: The first adder adds the product of the previous cycle to t[0] and the carry, and writes the result back to t[0]; at the same time, the multiplier calculates a[1]*b[0].

[0057] Third clock cycle: The first adder processes t[1]+a[1]*b[0]+C, while the multiplier calculates a[2]*b[0].

[0058] 4th clock cycle: The first adder processes t[2]+a[2]*b[0]+C, while the multiplier calculates a[3]*b[0].

[0059] In the 5th clock cycle: the first adder processes t[3]+a[3]*b[0]+C; at the same time, the second adder processes the boundary carry t[4]+C and stores the result in t[4] and t[5].

[0060] In this state, the multiplier is enabled every clock cycle, the first adder works in pipeline with the multiplier, and the second adder processes boundary additions in parallel, ensuring that the multiplier is never idle.

[0061] Jump condition: When the first inner loop ends, that is, after j completes all multiplication and accumulation operations from 0 to s-1, the state machine jumps to the MCAL state.

[0062] 4. Quotient Calculation Status (MCAL): In this MCAL state, the quotient m of the current iteration is calculated to prepare for the multiplication-reduction process in the next stage.

[0063] Specifically, in the 6th clock cycle: the multiplier calculates t[0]*n0, takes the lower 64 bits to get m; at the same time, it reads n[0].

[0064] This state lasts for only one clock cycle, during which the multiplier completes the multiplication, while the first adder is temporarily idle.

[0065] Jump condition: After one clock cycle, it automatically jumps to the MMULN state.

[0066] 5. Multiplication, reduction, and subtraction state (MMULN): In this MMULN state, multiplication, reduction and subtraction operations are performed, that is, m*n[j] is calculated and accumulated into the intermediate result, while word shifting is performed.

[0067] Read m and n[j] (j ranges from 1 to s-1), calculate the product, and the specific timing is as follows: 7th clock cycle: The multiplier calculates m*n[0], the first adder adds the product to t[0], and writes the result back to t[0].

[0068] In the 8th clock cycle: the multiplier calculates m*n[1], the first adder adds the product to t[1] and the carry, and writes the result back to t[j-1], thus achieving a right shift of one word.

[0069] 9th clock cycle: The multiplier calculates m*n[2], the first adder processes t[2]+ m*n[2]+C, and the result is written back to t[1].

[0070] 10th clock cycle: The multiplier calculates m*n[3], the first adder processes t[3]+m*n[3]+C, and the result is written back to t[2].

[0071] In the 11th clock cycle: the second adder processes the boundary carry t[4]+C, writes the result back to t[3], and adds t[5] to the carry and writes it back to t[4].

[0072] Jump conditions: When the second inner loop ends, that is, after j completes all multiplication, reduction, and subtraction operations from 1 to s-1, determine whether the outer loop has ended.

[0073] If the outer loop has not ended, i.e. i has not reached s-1, then jump back to the AMULB state and start the next iteration.

[0074] If the outer loop ends, that is, all iterations from i=0 to s-1 are completed, then jump to the CMP_SUB state.

[0075] After all formal iterations are completed, the pseudo-multiplication control unit initiates a fading transition. The data fading register outputs multiplier data with decreasing non-zero bits sequentially: all 64 bits are non-zero in the first clock cycle; the lower 48 bits are non-zero and the higher 16 bits are zero in the second clock cycle; the lower 32 bits are non-zero and the higher 32 bits are zero in the third clock cycle; and the lower 16 bits are non-zero and the higher 48 bits are zero in the fourth clock cycle. A pseudo-multiplication operation is performed once per clock cycle, and the multiplier power consumption smoothly decreases from full-scale to a lower value. After this state ends, the state machine transitions to the CMP_SUB state.

[0076] 6. Comparison and Reduction State (CMP_SUB): By enabling the subtractor, the intermediate result array t and the modulus n are read and compared: if t ≥ n, then t = tn is executed; otherwise, t remains unchanged. The final result t = (a*b) mod n is output. After completion, the state machine returns to the idle state.

[0077] Jump condition: After the reduction operation is completed, the state machine jumps back to the IDLE state and waits for the next start signal.

[0078] The Montgomery modular multiplication circuit provided in this application includes: a multiplier for performing multiplication operations to obtain a multiplication result; an adder connected to the output of the multiplier for performing an accumulation operation on the multiplication result; a state machine for controlling the enabling and data flow of each operation unit in the Montgomery modular multiplication circuit; and a pseudo-operation control unit for controlling the increase of non-zero bits in the input data before the multiplier starts and controlling the decrease of non-zero bits in the input data after the multiplier operation ends; the state machine is configured to: continuously enable the multiplier from the start of the multiplier to the end of the operation during the Montgomery modular multiplication operation, so that the multiplier performs a multiplication operation in each clock cycle, and maintain the continuous operation of the multiplier during the Montgomery modular multiplication operation through the adder. The Montgomery modular multiplication circuit provided in this application uses a state machine to control the multiplier to remain continuously enabled throughout the entire Montgomery modular multiplication operation. Multiplication is performed in every clock cycle. Combined with the cooperative design of the adder, the multiplier operates without idle interruptions from its initial startup to the end of the last operation. This eliminates the power consumption fluctuations caused by frequent start-stop cycles during the operation. Due to the smooth power consumption curve, instantaneous power consumption fluctuations are significantly reduced, effectively suppressing local voltage drops caused by large current surges. This effectively avoids logic level errors in digital circuits caused by instantaneous voltage drops, ensuring the correct establishment and maintenance of internal signals during modular multiplication. Simultaneously, the pseudo-operation control unit gradually increases the number of non-zero bits in the input data before the multiplier starts and gradually decreases it after the multiplier ends, achieving a smooth rise and fall in power consumption. Therefore, the power consumption of the entire Montgomery modular multiplication operation is stabilized within a narrow range, avoiding voltage spikes and drops caused by power consumption surges, fundamentally preventing the risk of chip reset due to voltage anomalies.

[0079] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0080] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0081] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0082] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0083] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0084] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0085] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0086] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0087] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0088] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A Montgomery modular multiplication circuit, characterized in that, include: A multiplier is used to perform multiplication operations and obtain the result of the multiplication operation; An adder, connected to the output of the multiplier, is used to perform an accumulation operation on the result of the multiplication operation; A state machine is used to control the enabling and data flow of each arithmetic unit in the Montgomery modular multiplication circuit; and A pseudo-operation control unit is used to control the increase of the non-zero number of the input data before the multiplier is started, and to control the decrease of the non-zero number of the input data after the multiplier operation is completed; The state machine is configured such that, during the Montgomery modular multiplication operation, from the start of the multiplier to the end of the operation, the multiplier is continuously enabled so that the multiplier performs a multiplication operation in each clock cycle, and the adder is used to ensure the continuous operation of the multiplier during the Montgomery modular multiplication operation.

2. The Montgomery modular multiplier circuit according to claim 1, characterized in that, The pseudo-operation control unit includes a data gradient register, which is used to output multiplier data with non-zero increments before the multiplier is started, and to output multiplier data with non-zero decrements after the multiplier operation is completed.

3. The Montgomery modular multiplication hardware circuit according to claim 1, characterized in that, It also includes a data caching unit for storing the operation data corresponding to the multiplication operation before the multiplier performs the multiplication operation.

4. The Montgomery modular multiplication hardware circuit according to claim 1, characterized in that, The adder includes a first adder and a second adder. The first adder is used to add the result of the multiplication operation to the cached data. The second adder is used to handle the boundary carry addition in the modular multiplication process. The first adder and the second adder are set in parallel.

5. The Montgomery modular multiplication hardware circuit according to claim 1, characterized in that, The multiplier module is a 64-bit multiplier.

6. The Montgomery modular multiplication hardware circuit according to claim 1, characterized in that, It also includes a subtractor, which is used to perform modular comparison and conditional subtraction after the operation of the multiplier is completed, so as to obtain the final modular multiplication result.

7. A Montgomery modular multiplication method, characterized in that, include: The non-zero number of bits in the input data of the multiplier is increased by the pseudo-operation control unit, thereby increasing the power consumption of the multiplier. During the Montgomery modular multiplication operation, the multiplier is kept running continuously, and during the execution of the multiplication operation, the addition operation is completed in parallel or pipelined manner so that the multiplier can keep running continuously. After the multiplier completes the Montgomery modular multiplication operation, the pseudo-operation control unit reduces the number of non-zero bits in the input data to the multiplier, thereby reducing the power consumption of the multiplier.

8. The method according to claim 7, characterized in that, During the Montgomery modular multiplication operation, maintaining the multiplier's continuous execution of multiplication operations specifically includes: The Montgomery modular multiplication operation is divided into at least two iteration cycles; For each iteration cycle, a scanning multiplication operation between the input data and the multiplier, and a reduction multiplication operation between the intermediate result and the modulus are performed respectively, so as to keep the multiplier continuously performing multiplication operations.

9. The method according to claim 7, characterized in that, The addition operation includes: a first addition operation, used to add the result of the multiplication operation to the accumulated value and the cached data; a second addition operation, used to handle boundary carry addition in the modular multiplication process; the first addition operation and the second addition operation are executed through a first adder and a second adder, and the first adder and the second adder are set in parallel.

10. The method according to claim 1, characterized in that, Also includes: After the multiplier completes its operation, the subtractor performs modular comparison and conditional subtraction to obtain the final modular multiplication result.

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