Data reading method and device, electronic equipment, and storage medium

Abstract

The present disclosure provides a data reading method and device, electronic equipment and storage medium. The method comprises: in the case that the destination addresses of a plurality of sub-instructions of a memory reading instruction are located in a scalar memory, merging, according to the source addresses and the destination addresses of the plurality of sub-instructions, the sub-instructions of the plurality of sub-instructions in which the source addresses are in the same cache line and the destination addresses are in the same data write line of the scalar memory, to obtain at least one first cache reading request; executing the at least one first cache reading request to obtain first target data corresponding to each first cache reading request; and storing the first target data corresponding to each first cache reading request to the scalar memory. According to the embodiments of the present disclosure, the plurality of sub-instructions in the memory reading instruction can be merged, thereby improving the execution efficiency of the memory reading instruction.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a data reading method and apparatus, electronic device, and storage medium. Background Technology

[0002] In related technologies, the total number of threads that a processor (such as a central processing unit, graphics processing unit, etc.) can process in parallel within one cycle is called a warp. For example, a warp may include M (M is an integer greater than 1) threads for performing memory read operations, and the memory read operations of these M threads can be processed in parallel.

[0003] Memory read operations by M threads have M memory addresses and a shared request length, meaning that the length of data read from memory by the M threads is the same. Typically, the data read by the M threads is stored in on-chip vector memory (e.g., vector registers) or scalar memory (e.g., scalar registers). For vector memory, the M threads share a single destination address; while for scalar memory, there is a unified addressing mode, and each of the M threads sets an independent and distinct destination address. Summary of the Invention

[0004] This disclosure provides a data reading method and apparatus, an electronic device, and a storage medium.

[0005] In a first aspect, this disclosure provides a data reading method, which includes: when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, merging the sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory according to the source addresses and destination addresses of the multiple sub-instructions to obtain at least one first cache read request; executing the at least one first cache read request to obtain first target data corresponding to each first cache read request; and storing the first target data corresponding to each first cache read request into the scalar memory.

[0006] Secondly, this disclosure provides a data reading device, comprising: a first merging module, configured to, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, merge sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory according to the source addresses and destination addresses of the multiple sub-instructions, to obtain at least one first cache read request; a first execution module, configured to execute the at least one first cache read request to obtain first target data corresponding to each first cache read request; and a first storage module, configured to store the first target data corresponding to each first cache read request into the scalar memory.

[0007] Thirdly, this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the data reading method described above.

[0008] Fourthly, this disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the above-described data reading method.

[0009] The embodiments provided in this disclosure, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, can merge sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory to obtain at least one first cache read request. Then, the at least one first cache read request is executed to read data from memory or cache, obtaining the first target data corresponding to each first cache read request, and storing the first target data in scalar memory. In this way, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, the merging of multiple sub-instructions in a memory read instruction can be achieved, reducing the number of cache read requests corresponding to the memory read instruction. This not only reduces the processor's cache resource usage but also improves the execution efficiency of the memory read instruction.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0011] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of detailed exemplary embodiments with reference to the accompanying drawings, which are described below.

[0012] Figure 1 This is a flowchart of a data reading method provided in an embodiment of the present disclosure.

[0013] Figure 2 This is a schematic diagram of a data reading method provided in an embodiment of the present disclosure.

[0014] Figure 3 This is a schematic diagram illustrating the position update of sub-data in a data reading method provided in an embodiment of this disclosure.

[0015] Figure 4 This is a schematic diagram illustrating the position update of sub-data in a data reading method provided in an embodiment of this disclosure.

[0016] Figure 5 This is a block diagram of a data reading device provided in an embodiment of the present disclosure.

[0017] Figure 6 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0019] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0020] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0022] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0023] In related technologies, when the destination addresses of M threads are all located in scalar memory, the memory read operations of these M threads cannot be merged; each thread's memory read operation must be processed as a single cache read request. For example, when M is 32, the memory read operations of 32 threads require 32 cache read requests to process. This not only consumes more cache resources, such as more cache requestlatency buffers, but also affects data read efficiency.

[0024] To address the aforementioned technical problems, embodiments of this disclosure provide a data reading method, which includes: when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, merging sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory according to the source addresses and destination addresses of the multiple sub-instructions to obtain at least one first cache read request; executing at least one first cache read request to obtain first target data corresponding to each first cache read request; and storing the first target data corresponding to each first cache read request into the scalar memory.

[0025] According to the data reading method of this disclosure, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory can be merged to obtain at least one first cache read request. Then, the at least one first cache read request is executed to read data from memory or cache, obtaining first target data corresponding to each first cache read request, and storing the first target data in scalar memory. In this way, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, the merging of multiple sub-instructions in a memory read instruction can be achieved, reducing the number of cache read requests corresponding to the memory read instruction. This not only reduces the occupation of cache resources in the processor but also improves the execution efficiency of the memory read instruction.

[0026] The data reading method according to embodiments of this disclosure can be executed by a processor (e.g., CPU, GPU, etc.) in an electronic device such as a terminal device or server. The terminal device can be an in-vehicle device, user equipment (UE), mobile device, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, wearable device, etc., and the method can be implemented by the processor calling computer-readable program instructions stored in memory.

[0027] Figure 1 A flowchart illustrating a data reading method provided in an embodiment of this disclosure. (Refer to...) Figure 1 The method includes steps S11-S13, which are described below.

[0028] In step S11, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, the sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory are merged according to the source addresses and destination addresses of the multiple sub-instructions to obtain at least one first cache read request.

[0029] In step S12, at least one first cache read request is executed to obtain the first target data corresponding to each first cache read request.

[0030] In step S13, the first target data corresponding to each first cache read request is stored in scalar memory.

[0031] In some possible implementations, a memory read instruction refers to an instruction issued by the processor of an electronic device to read data from the internal memory of the electronic device. For example, if the processor is a Central Processing Unit (CPU) in the electronic device, then the memory read instruction is an instruction issued by the CPU to read data from the memory of the electronic device. As another example, if the processor is a Graphics Processing Unit (GPU) in the electronic device, then the memory read instruction is an instruction issued by the GPU to read data from the video memory of the electronic device. It should be noted that the processor can also be a general-purpose graphics processing unit (GPGPU) or other processors; this disclosure does not limit the specific type of processor.

[0032] In some possible implementations, a memory read instruction may include multiple subinstructions. One subinstruction corresponds to a memory read operation (also called a read request) for one thread. Each subinstruction includes a source address and a destination address. The source address is the address in memory where the data to be read is located. The destination address is the address where the data read from memory is stored; it is located in scalar memory or vector memory. That is, the destination addresses of multiple subinstructions of a memory read instruction can all be located in scalar memory or all in vector memory. Both scalar memory and vector memory are located within the processor. Scalar memory is, for example, a scalar register set, and vector memory is, for example, a vector register set.

[0033] In some possible implementations, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, in step S11, sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of scalar memory can be coalesced based on the source and destination addresses of the multiple sub-instructions to obtain at least one first cache read request. Here, a cache line is the smallest unit of data transfer between the processor and memory. That is, data is read from memory line by line. Similarly, data is written to scalar memory line by line. The data write line in scalar memory can be seen as the alignment granularity when the processor writes data to scalar memory, specifically referring to the maximum amount of data written to scalar memory in one cycle.

[0034] When merging multiple sub-instructions of a memory read instruction, the cache line containing the source address of each sub-instruction and the data write line in scalar memory containing the destination address of each sub-instruction can be determined separately. Sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line in scalar memory are then merged into a single first cache read request, allowing data to be read or written within one cycle. Multiple sub-instructions of a memory read instruction can be merged into at least one first cache read request; that is, a memory read instruction corresponds to at least one first cache read request.

[0035] In some possible implementations, in step S12, at least one first cache read request may be executed to obtain the first target data corresponding to each first cache read request. For any first cache read request, when executing the first cache read request, the first starting address of the corresponding cache line of the first cache read request may be determined according to the source address of each sub-instruction in the first cache read request. Then, data is read from memory or cache according to the first starting address, and the first target data corresponding to the first cache read request is determined from the read data according to the source address of each sub-instruction in the first cache read request.

[0036] In some possible implementations, in step S13, the first target data corresponding to each first cache read request can be stored in scalar memory. Since the execution progress of each first cache read request may be different, the first target data can be stored in scalar memory immediately after any first cache read request completes and obtains the corresponding first target data, thus initiating the data storage process, without waiting for other first cache read requests to complete, thereby saving waiting time and improving processing efficiency.

[0037] The first target data read by the first cache read request is arranged in a way that facilitates reading from memory or cache. To facilitate writing the first target data into scalar memory, the first target data can be rearranged according to the source address and destination address of each sub-instruction in the first cache read request, and then the rearranged first target data can be written into scalar memory according to the destination address. The data rearrangement process can be regarded as a data packing process.

[0038] According to the data reading method of this disclosure, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory can be merged to obtain at least one first cache read request. Then, the at least one first cache read request is executed to read data from memory or cache, obtaining first target data corresponding to each first cache read request, and storing the first target data in scalar memory. In this way, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, the merging of multiple sub-instructions in a memory read instruction can be achieved, reducing the number of cache read requests corresponding to the memory read instruction. This not only reduces the consumption of processor cache resources but also improves the execution efficiency of the memory read instruction.

[0039] The data reading method according to embodiments of this disclosure will now be described in detail.

[0040] As mentioned above, in step S11, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, the sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory are merged according to the source addresses and destination addresses of the multiple sub-instructions to obtain at least one first cache read request. In some possible implementations, step S11 may include: determining a first address bit in the source address according to the first data length of the cache line; wherein the first address bit is the address bit in the source address corresponding to the alignment granularity of the first data length; determining a second address bit in the destination address according to the second data length of the data write line of the scalar memory; wherein the second address bit is the address bit in the destination address corresponding to the alignment granularity of the second data length; and merging the sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory into a single first cache read request based on the first address bit and the second address bit; wherein the source addresses with the same first address bit to the highest address bit are in the same cache line, and the destination addresses with the same second address bit to the highest address bit are in the same data write line of the scalar memory.

[0041] The first data length of a cache line refers to the number of bytes in a cache line, and its value can be a power of 2 (n is a positive integer), for example, the first data length is 128 bytes. The second data length of a scalar memory data write line refers to the number of bytes in a scalar memory data write line, and its value can be a power of 2 (k is a positive integer), for example, the second data length is 128 bytes. The first data length of a cache line and the second data length of a scalar memory data write line can be the same, for example, both the first data length and the second data length are 128 bytes. The first data length of a cache line and the second data length of a scalar memory data write line can also be different, for example, the first data length is 128 bytes and the second data length is 64 bytes. This disclosure does not impose any restrictions in this regard.

[0042] When merging multiple subinstructions within a memory read instruction, the first address bit in the source address is determined based on the first data length of the cache line. The first address bit is the lowest address bit in the source address that indicates the cache line containing the source address. Address bits below the first address bit in the source address are used to indicate address offsets within the cache line. In other words, the first address bit is the address bit in the source address corresponding to the alignment granularity of the first data length. The alignment granularity of the first data length refers to the smallest alignment unit of the cache line, which can be represented by a power of 2. The address bit in the source address corresponding to the alignment granularity of the first data length is the address bit corresponding to the exponent of the power of 2 of the first data length in the source address.

[0043] When determining the first address bit, the exponent of the power of two corresponding to the first data length can be determined first, and then the address bit corresponding to that exponent in the source address can be determined as the first address bit. When the first data length of the cache line is R bytes (R is a positive integer), the address bit corresponding to the value of log2(R) in the source address can be determined as the first address bit in the source address. In multiple sub-instructions, source addresses with the same first address bit to highest address bit are located in the same cache line. That is, in multiple sub-instructions, source addresses with the same [S_highbit:log2(R)] are located in the same cache line. Here, S_highbit represents the highest address bit of the source address. The S_highbit value differs depending on the length of the source address. For example, when the source address length is 48 bits, its highest address bit S_highbit is the 47th bit; when the source address length is 16 bits, its highest address bit S_highbit is the 15th bit. It should be noted that in the embodiments of this disclosure, the lowest address bit of both the source address and the destination address is bit 0. For example, assuming the source address length is 48 bits, the highest address bit is the 47th bit, the lowest address bit is the 0th bit, and the first data length R is 128, then the value of log2(R) is 7, which means the first address bit in the source address can be determined as the 7th bit. In the source addresses of multiple sub-instructions, source addresses with the same bits from the 7th to the 47th bit (i.e., [47:7]) are located in the same cache line.

[0044] Then, based on the second data length of the data write line in the scalar memory, the second address bit in the destination address can be determined. The second address bit is the lowest address bit in the destination address that indicates the data write line (in the scalar memory) where the destination address is located. Address bits in the destination address lower than the second address bit are used to indicate the address offset within the data write line. In other words, the second address bit is the address bit in the destination address corresponding to the alignment granularity of the second data length. The alignment granularity of the second data length refers to the smallest alignment unit of the data write line, which can be represented by an integer power of 2. The address bit in the destination address corresponding to the alignment granularity of the second data length is the address bit corresponding to the exponent of the power of two corresponding to the second data length in the destination address.

[0045] When determining the second address bit, first determine the exponent of the power of two corresponding to the second data length, and then determine the address bit corresponding to that exponent in the destination address as the second address bit. When the second data length of the data write line in scalar memory is Q bytes (Q is a positive integer), the address bit corresponding to the value of log2(Q) in the destination address can be determined as the second address bit in the destination address. In multiple subinstructions, destination addresses with the same second address bit to highest address bit are located in the same data write line of scalar memory. That is, in multiple subinstructions, destination addresses with the same [D_highbit:log2(Q)] are located in the same data write line of scalar memory. Here, D_highbit represents the highest address bit of the destination address. The length of the destination address varies, and its D_highbit also varies. For example, when the length of the destination address is 48 bits, its highest address bit D_highbit is the 47th bit; when the length of the destination address is 16 bits, its highest address bit D_highbit is the 15th bit. For example, if the destination address is 48 bits long, the highest address bit is the 47th bit, the lowest address bit is the 0th bit, and the second data length Q is 128, then log2(Q) is 7, and the second address bit in the destination address can be determined as the 7th bit. Among the destination addresses of multiple sub-instructions, the same destination addresses from the 7th to the 47th bit (i.e., [47:7]) are located in the same data write line of the scalar memory.

[0046] Subsequently, subinstructions whose source address is in the same cache line and whose destination address is in the same data write line in scalar memory can be merged into a single first cache read request. This means merging subinstructions with the same [S_highbit:log2(R)] in the source address and the same [D_highbit:log2(Q)] in the destination address into a single first cache read request. For example, if the first data length R and the second data length Q are both 128, the memory read instruction includes four subinstructions: subinstruction 0 (corresponding to thread 0), subinstruction 1 (corresponding to thread 1), subinstruction 2 (corresponding to thread 2), and subinstruction 3 (corresponding to thread 3). The source address (memory address) is 48 bits, and the destination address is 16 bits. The source addresses of these four sub-instructions are 0x1000010, 0x1000020, 0x1000030, and 0x1000040, respectively, and the destination addresses are 0xA20, 0xA30, 0xA40, and 0xA00, respectively. When merging these four sub-instructions into a first cache read request, since the source addresses [47:7] and destination addresses [15:7] of these four sub-instructions are the same, they can be merged into a single first cache read request. The number of first cache read requests obtained by merging the four sub-instructions of this memory read instruction is 1.

[0047] For example, if the first data length R and the second data length Q are both 128, the memory read instruction includes four sub-instructions: sub-instruction 0 (corresponding to thread 0), sub-instruction 1 (corresponding to thread 1), sub-instruction 2 (corresponding to thread 2), and sub-instruction 3 (corresponding to thread 3). The source address (i.e., the memory address) is 48 bits, and the destination address is 16 bits. The source addresses of these four sub-instructions are 0x1000010, 0x1000020, 0x1000030, and 0x1000040, respectively. The destination addresses of these four sub-instructions are 0xA20, 0xA30, 0xB40, and 0xB00, respectively. When merging these four sub-instructions into a first cache read request, since sub-instructions 0 and 1 share the same source address [47:7] and destination address [15:7], they can be merged into one first cache read request. Similarly, since sub-instructions 2 and 3 share the same source address [47:7] and destination address [15:7], they can be merged into one first cache read request. Therefore, the number of first cache read requests obtained by merging the four sub-instructions of this memory read instruction is 2.

[0048] In the embodiments of this disclosure, when merging multiple sub-instructions in a memory read instruction, firstly, the first address bit in the source address is determined based on the first data length of the cache line. Among the source addresses of multiple sub-instructions, those with the same first address bit to the highest address bit are located in the same cache line. Then, based on the second data length of the data write line in the scalar memory, the second address bit in the destination address is determined. Among the destination addresses of multiple sub-instructions, those with the same second address bit to the highest address bit are located in the same data write line in the scalar memory. Subsequently, sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line in the scalar memory can be merged into a single first cache read request. In this way, when merging multiple sub-instructions, not only the first data length of the cache line and the source address are considered, but also the second data length of the data write line in the scalar memory and the destination address are considered. This allows the merged first cache read request to complete the memory data read in one cycle and store the read data in the scalar memory in another cycle, thus improving data read efficiency.

[0049] In some possible implementations, step S12 may include: merging first cache read requests corresponding to the same cache line into a single target cache read request based on the source address and first address bit of the sub-instruction in at least one first cache read request; reading the second target data from the cache if the second target data corresponding to the target cache read request is located in the cache; and determining the first target data corresponding to the first cache read request included in the target cache read request from the second target data.

[0050] When executing at least one first cache read request, a cache hit test is first performed. During the cache hit test, first cache read requests corresponding to the same cache line can be merged into a single target cache read request based on the source address and first address bit of the sub-instruction in at least one first cache read request. First cache read requests corresponding to the same cache line, also known as first cache read requests falling within the same cache line, refer to the first cache read requests that read data from the same cache line. Source addresses with the same first address bit to the highest address bit are located in the same cache line. Therefore, the first cache read requests corresponding to the same cache line can be determined based on the first address bit to the highest address bit in the source address of each first cache read request, and these first cache read requests corresponding to the same cache line can be merged into a single target cache read request. The target cache read request includes at least one first cache read request.

[0051] After receiving the target cache read request, it can be determined whether the second target data corresponding to the target cache read request is in the cache. If it is in the cache, the cache hit test result is a hit. If it is not in the cache, the cache hit test result is a miss. If the cache hit test result is a hit, that is, if the second target data corresponding to the target cache read request is in the cache, the second target data can be read from the cache. If the cache hit test result is a miss, that is, if the second target data corresponding to the target cache read request is not in the cache, the second target data can be read from memory according to the source address of the sub-instruction in the target cache read request, and simultaneously written to the cache.

[0052] After obtaining the second target data, for any first cache read request included in the target cache read request, the first target data corresponding to the first cache read request can be determined from the second target data based on the source address of the sub-instruction in the first cache read request.

[0053] Therefore, in the data reading method of this embodiment, when merging multiple sub-instructions of a memory read instruction (i.e., the sub-instruction merging stage), sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory are merged into a single first cache read request. This process considers both the source and destination addresses. When executing at least one first cache read request, in the cache hit test stage, the source address of the sub-instruction and the first address bit in the source address are used to determine whether at least one first cache read request will fall into the same cache line. This process only considers the source address. Therefore, some sub-instructions that cannot be merged in the sub-instruction merging stage may still fall into the same cache line in the cache hit test stage, i.e., the cache hit test is performed using the same target cache read request. In this way, not only are the processing logics of the sub-instruction merging stage and the cache hit test stage independent and do not affect each other, but the execution efficiency of the first cache read request is also improved.

[0054] In some possible implementations, step S13 may include: for any first cache read request, determining a first address offset and a second address offset for each sub-instruction in the first cache read request; wherein the first address offset refers to the address offset of the source address in the cache line, and the second address offset refers to the address offset of the destination address in the data write line; and storing the first target data corresponding to the first cache read request into scalar memory according to the first address offset, the second address offset, and the destination address of each sub-instruction in the first cache read request.

[0055] For any first cache read request, the first address offset and the second address offset of each subinstruction in the first cache read request can be determined. The first address offset refers to the address offset of the source address within the cache line. To determine the first address offset, the first starting address of the corresponding cache line for the first cache read request can be determined based on the source address of any subinstruction in the first cache read request. Then, for any subinstruction in the first cache read request, the address offset between the source address of the subinstruction and the first starting address (i.e., the address offset of the source address of the subinstruction within the cache line) is determined as the first address offset of that subinstruction.

[0056] The second address offset refers to the address offset of the destination address within the data write line. When determining the second offset address, the second starting address of the data write line corresponding to the first cache read request can be determined based on the destination address of any sub-instruction in the first cache read request. Then, for any sub-instruction in the first cache read request, the address offset between the destination address of the sub-instruction and the second starting address (i.e., the address offset of the destination address of the sub-instruction within the data write line of the scalar memory) is determined as the second address offset of the sub-instruction.

[0057] Then, the first target data can be stored in scalar memory according to the first address offset, second address offset, and destination address of each sub-instruction in the first cache read request. The first target data corresponding to the first cache read request is arranged in a way that facilitates reading from memory or cache. In order to facilitate writing the first target data into scalar memory, the first target data can be rearranged according to the first address offset and second address offset of each sub-instruction in the first cache read request, and the rearranged first target data can be written into scalar memory according to the destination address.

[0058] In the embodiments of this disclosure, when storing the first target data corresponding to any first cache read request into the scalar memory, the first address offset and the second address offset of each sub-instruction in the first cache read request are first determined, and then the first target data corresponding to the first cache read request is stored into the scalar memory according to the first address offset, the second address offset and the destination address, thereby improving the processing efficiency when storing the first target data.

[0059] In some possible implementations, determining the first address offset and the second address offset of each sub-instruction in the first cache read request may include: for any sub-instruction in the first cache read request, determining the first address offset of the sub-instruction based on the lowest address bit in the source address of the sub-instruction to the address bit lower than the first address bit; and determining the second address offset of the sub-instruction based on the lowest address bit in the destination address of the sub-instruction to the address bit lower than the second address bit.

[0060] For any subinstruction in the first cache read request, the first address offset of the subinstruction can be determined based on the least significant bit in the source address of the subinstruction and the address bit below the first address (e.g., the 6th address bit and the 5th address bit below the first address). Since the first to the most significant bits in the source address are used to determine the cache line where the source address is located, the offset of the source address in the cache line, i.e., the first address offset of the subinstruction, can be determined based on the least significant bit in the source address of the subinstruction and the address bit below the first address. When the first data length of the cache line is R bytes, [log2(R)-1:0] in the source address of the subinstruction can be determined as the first address offset of the subinstruction. Here, log2(R) represents the first address bit, log2(R)-1 represents the address bit below the first address bit, and 0 represents the least significant bit.

[0061] The second address offset of the subinstruction can be determined by the distance from the lowest address bit to the next lower address bit in the destination address (e.g., the 7th address bit and the 6th lower address bit). Since the distance from the second address bit to the highest address bit in the destination address is to the data write line used to determine the destination address, the offset of the destination address in the data write line can be determined by the distance from the lowest address bit to the next lower address bit in the destination address. In the case where the second data length of the scalar memory data write line is Q bytes, [log2(Q)-1:0] in the destination address of the subinstruction can be determined as the second address offset of the subinstruction. Here, log2(Q) represents the second address bit, log2(Q)-1 represents the next lower address bit, and 0 represents the lowest address bit.

[0062] For example, the first data length R and the second data length Q are both 128. The memory read instruction includes four sub-instructions: sub-instruction 0 (corresponding to thread 0), sub-instruction 1 (corresponding to thread 1), sub-instruction 2 (corresponding to thread 2), and sub-instruction 3 (corresponding to thread 3). The source address (i.e., the memory address) is 48 bits, and the destination address is 16 bits. The source addresses of these four sub-instructions are 0x1000010, 0x1000020, 0x1000030, and 0x1000040, and the destination addresses are 0xA20, 0xA30, 0xA40, and 0xA00, respectively.

[0063] Therefore, log2(R)-1=6, log2(Q)-1=6. We can determine the [6:0] (0x10) in the source address 0x1000010 of subinstruction 0 as its first address offset, and the [6:0] (0x20) in the destination address 0xA20 of subinstruction 0 as its second address offset. Similarly, we can determine the [6:0] (0x20) in the source address 0x1000020 of subinstruction 1 as its first address offset, and the [6:0] (0x30) in the destination address 0xA30 of subinstruction 1 as its second address offset. The second address offset of subinstruction 1 can be determined; [6:0] in the source address 0x1000030 of subinstruction 2, i.e., 0x30, can be determined as the first address offset of subinstruction 2, and [6:0] in the destination address 0xA40 of subinstruction 2, i.e., 0x40, can be determined as the second address offset of subinstruction 2; [6:0] in the source address 0x1000040 of subinstruction 3, i.e., 0x40, can be determined as the first address offset of subinstruction 3, and [6:0] in the destination address 0xA00 of subinstruction 3, i.e., 0x00, can be determined as the second address offset of subinstruction 3.

[0064] In the embodiments of this disclosure, for any sub-instruction in the first cache read request, its first address offset can be determined based on the lowest address bit in the source address of the sub-instruction to the address bit lower than the first address bit, and its second address offset can be determined based on the lowest address bit in the destination address of the sub-instruction to the address bit lower than the second address bit. Thus, the first address offset and the second address offset of the sub-instruction can be quickly and accurately determined based on the address bits indicating inline offsets in the source address and destination address of the sub-instruction, thereby improving processing efficiency.

[0065] In some possible implementations, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in vector memory, the data read granularity supported by the memory read instruction (i.e., the length of data read by each sub-instruction) can be 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes, or 32 bytes, etc., meaning it supports a relatively fine data read granularity. In contrast, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, the data read granularity supported by the memory read instruction can be relatively coarse; for example, the data read granularity supported by the memory read instruction can be 16 bytes or 32 bytes, etc.

[0066] Based on this, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, the first address offset and the second address offset can be further optimized. In some possible implementations, the first target data corresponding to the first cache read request includes multiple sub-data, and each sub-instruction in the first cache read request corresponds to one sub-data. Specifically, determining the first address offset of the sub-instruction based on the lowest address bit in the source address of the sub-instruction to the address bit lower than the first address bit includes: determining the third address bit in the source address of the sub-instruction based on the third data length of the sub-data corresponding to the sub-instruction; wherein the third address bit is the address bit in the source address corresponding to the alignment granularity of the third data length, and the third address bit is lower than the first address bit; and determining the first address offset of the sub-instruction based on the third address bit in the source address to the address bit lower than the first address bit.

[0067] Since the value of the lower bits of the source address of a subinstruction is related to the length of the third data of the corresponding sub-data, for example, when the length of the third data is 16 bytes, the lower four bits of the source address of the subinstruction (i.e., [3:0]) are all 0. Therefore, the third address bit in the source address of each subinstruction can be determined according to the length of the third data of the corresponding sub-data. The third address bit is the address bit in the source address corresponding to the alignment granularity of the third data length. The alignment granularity of the third data length refers to the smallest alignment unit when reading and writing sub-data, which can be represented by an integer power of 2. The address bit in the source address corresponding to the alignment granularity of the third data length is the address bit corresponding to the exponent of the power of two of the third data length in the source address.

[0068] When determining the third address bit, first determine the exponent of the power of two corresponding to the third data length, and then determine the address bit corresponding to that exponent in the source address as the third address bit. If the third data length of the sub-instruction's sub-data is P bytes (P is a positive integer), the address bit corresponding to the value of log2(P) in the source address can be determined as the third address bit in the source address. The third address bit is lower than the first address bit. Then, the first address offset of the sub-instruction can be determined based on the distance from the third address bit in the source address to the address bit lower than the first address bit.

[0069] For example, the first data length R is 128, the third data length P is 16, and the memory read instruction includes four sub-instructions: sub-instruction 0 (corresponding to thread 0), sub-instruction 1 (corresponding to thread 1), sub-instruction 2 (corresponding to thread 2), and sub-instruction 3 (corresponding to thread 3). The source address (i.e., the memory address) is 48 bits. The source addresses of these four sub-instructions are 0x1000010, 0x1000020, 0x1000030, and 0x1000040, respectively. Therefore, log2(R)-1=6, log2(P)=4, so the [6:4] in the source address 0x1000010 of subinstruction 0, i.e., 0x1, can be determined as the first address offset of subinstruction 0; the [6:4] in the source address 0x1000020 of subinstruction 1, i.e., 0x2, can be determined as the first address offset of subinstruction 1; the [6:4] in the source address 0x1000030 of subinstruction 2, i.e., 0x3, can be determined as the first address offset of subinstruction 2; and the [6:4] in the source address 0x1000040 of subinstruction 3, i.e., 0x4, can be determined as the first address offset of subinstruction 3.

[0070] Compared to the first address offset of a subinstruction determined by the least significant bit in the source address of the subinstruction to the address one bit below the first address, the width of the first address offset of a subinstruction determined by the third significant bit in the source address of the subinstruction to the address one bit below the first address is smaller. For example, when log2(R)-1=6, the first address offset of the subinstruction determined by the least significant bit in the source address of the subinstruction to the address one bit below the first address is [6:0], with a width of 7 bits; while when log2(P)=4, the first address offset of the subinstruction determined by the third significant bit in the source address of the subinstruction to the address one bit below the first address is [6:4], with a width of 3 bits. Compared to the former, the width of the first address offset of each subinstruction is 4 bits smaller.

[0071] In the embodiments of this disclosure, the third address bit in the source address of the sub-instruction can be determined based on the third data length of the sub-data corresponding to the sub-instruction, and the first address offset of the sub-instruction can be determined based on the address bit below the first address bit in the source address of the sub-instruction. This reduces the binary width of the first address offset, thereby reducing the storage space occupied by the first address offset. When the first offset address is stored in the second buffer (instruction buffer) described below, this method can minimize the storage space occupied by the first offset address, thereby saving storage space in the second buffer and facilitating its reuse.

[0072] In some possible implementations, determining the second address offset of the subinstruction based on the lowest address bit to the address bit lower than the second address bit in the destination address of the subinstruction includes: determining the fourth address bit in the destination address of the subinstruction based on the third data length of the sub-data corresponding to the subinstruction; wherein the fourth address bit is the address bit in the destination address corresponding to the alignment granularity of the third data length, and the fourth address bit is lower than the second address bit; and determining the second address offset of the subinstruction based on the fourth address bit to the address bit lower than the second address bit in the destination address of the subinstruction.

[0073] Since the value of the lower bits of the destination address of a subinstruction is related to the length of the third data of the corresponding sub-data, for example, when the length of the third data is 16 bytes, the lower four bits (i.e., [3:0]) of the destination address of the subinstruction are all 0. Therefore, the fourth address bit in the destination address of each subinstruction can be determined according to the length of the third data of the corresponding sub-data. The fourth address bit is the address bit in the destination address corresponding to the alignment granularity of the third data length. The alignment granularity of the third data length refers to the smallest alignment unit when reading and writing sub-data, which can be represented by an integer power of 2. The address bit in the destination address corresponding to the alignment granularity of the third data length is the address bit corresponding to the exponent of the power of two of the third data length in the destination address.

[0074] When determining the fourth address bit, first determine the exponent of the power of two corresponding to the third data length, and then determine the address bit corresponding to that exponent in the destination address as the fourth address bit. If the third data length of the sub-instruction's sub-data is P bytes, the address bit corresponding to the value of log2(P) in the destination address can be determined as the fourth address bit in the destination address. The fourth address bit is lower than the second address bit. Then, the second address offset of the sub-instruction can be determined based on the fourth address bit in the destination address and the address bit lower than the second address bit.

[0075] For example, the second data length Q is 128, the third data length P is 16, and the memory read instruction includes four sub-instructions: sub-instruction 0 (corresponding to thread 0), sub-instruction 1 (corresponding to thread 1), sub-instruction 2 (corresponding to thread 2), and sub-instruction 3 (corresponding to thread 3), with a 16-bit destination address. The destination addresses of these four sub-instructions are 0xA20, 0xA30, 0xA40, and 0xA00, respectively. Therefore, log2(Q)-1=6, log2(P)=4, so the [6:4] in the destination address 0xA20 of subinstruction 0, i.e., 0x2, can be determined as the second address offset of subinstruction 0; the [6:4] in the destination address 0xA30 of subinstruction 1, i.e., 0x3, can be determined as the second address offset of subinstruction 1; the [6:4] in the destination address 0xA40 of subinstruction 2, i.e., 0x4, can be determined as the second address offset of subinstruction 2; and the [6:4] in the destination address 0xA00 of subinstruction 3, i.e., 0x0, can be determined as the second address offset of subinstruction 3.

[0076] Compared to the second address offset of a subinstruction determined by the distance from the least significant address bit to the next lower address bit in the destination address, the width of the first address offset of a subinstruction determined by the distance from the fourth address bit to the next lower address bit in the destination address is smaller. For example, when log2(Q)-1=6, the second address offset of the subinstruction determined by the distance from the least significant address bit to the next lower address bit in the destination address is [6:0], with a width of 7 bits; while when log2(P)=4, the second address offset of the subinstruction determined by the distance from the fourth address bit to the next lower address bit in the destination address is [6:4], with a width of 3 bits. Compared to the former, the width of the second address offset of each subinstruction is 4 bits smaller.

[0077] In the embodiments of this disclosure, the fourth address bit in the destination address of the sub-instruction can be determined based on the third data length of the sub-data corresponding to the sub-instruction, and the second address offset of the sub-instruction can be determined based on the address bit below the second address bit from the fourth address bit of the sub-instruction. This reduces the binary width of the second address offset, thereby reducing the storage space occupied by the second address offset. When the first offset address is stored in the second buffer (instruction buffer) described below, this method can minimize the storage space occupied by the first offset address, thereby saving storage space in the second buffer and facilitating the reuse of the second buffer.

[0078] In some possible implementations, storing the first target data corresponding to the first cache read request into scalar memory based on the first address offset, second address offset, and destination address of each sub-instruction in the first cache read request may include: for any sub-instruction in the first cache read request, determining the sub-data corresponding to the sub-instruction from the first target data corresponding to the first cache read request based on the first address offset of the sub-instruction, and determining the update position of the sub-data corresponding to the sub-instruction based on the second address offset of the sub-instruction; updating the position of each sub-data in the first target data corresponding to the first cache read request based on the update position of the sub-data corresponding to each sub-instruction in the first cache read request to obtain the updated target data; and storing the updated first target data into scalar memory based on the second address bit to the highest address bit of the destination address of any sub-instruction in the first cache read request.

[0079] After obtaining the first target data corresponding to the first cache read request, for any sub-instruction in the first cache read request, the sub-data corresponding to the sub-instruction can be determined from the first target data based on the first address offset of the sub-instruction. Then, the update position of the sub-data corresponding to the sub-instruction can be determined based on the second address offset of the sub-instruction. Based on the update position of the sub-data corresponding to each sub-instruction in the first cache read request, the position of each sub-data in the first target data is updated. That is, the sub-data in the first target data is recombinated and rearranged to obtain the updated target data. This allows for immediate updating of the positions of each sub-data in the first target data after obtaining the first target data corresponding to the first cache read request, without waiting for other first cache read requests to complete, thus improving processing efficiency.

[0080] After obtaining the updated first target data, the updated first target data can be stored in scalar memory according to the second to highest address bits of the destination address of any sub-instruction in the first cache read request, i.e., [D_highbit:log2(Q)] of the destination address of any sub-instruction. In other words, when storing the updated first target data in scalar memory, only one interface information, [D_highbit:log2(Q)] of the destination address of any sub-instruction, is used. In contrast, related technologies require the same number of interface information as the number of sub-instructions in the first cache read request; for example, if the number of sub-instructions in the first cache read request is 4, the related technologies require 4 pieces of interface information. Therefore, compared with related technologies, the embodiments of this disclosure can effectively reduce the hardware interface information required when storing the updated first target data in scalar memory, thereby saving hardware resources.

[0081] In some possible implementations, the data reading method of this disclosure embodiment may further include: determining a sub-instruction mask for each first cache read request; wherein the sub-instruction mask is used to indicate the sub-instructions included in the first cache read request among a plurality of sub-instructions; storing at least one first cache read request and the sub-instruction mask for each first cache read request in a first buffer; storing instruction information of a memory read instruction in a second buffer; wherein the instruction information includes an identifier of the buffer block storing the first first cache read request corresponding to the memory read instruction in the first buffer, the number of first cache read requests corresponding to the memory read instruction, and a first address offset and a second address offset for each sub-instruction in the memory read instruction; for any first cache read request, after obtaining the first target data corresponding to the first cache read request, obtaining the sub-instruction mask of the first cache read request from the first buffer, and determining the sub-instructions included in the first cache read request according to the sub-instruction mask; obtaining the first address offset and the second address offset for each sub-instruction in the first cache read request from the second buffer.

[0082] After merging multiple sub-instructions of a memory read instruction into at least one first cache read request, a sub-instruction mask can be determined for any given first cache read request. The sub-instruction mask indicates the sub-instructions included in the first cache read request among the multiple sub-instructions. The sub-instruction mask is a binary number with a bit width equal to the number of sub-instructions. For example, if a memory read instruction includes four sub-instructions: sub-instruction 0, sub-instruction 1, sub-instruction 2, and sub-instruction 3, then the sub-instruction mask for the first cache read request is a 4-bit binary number. When sub-instructions 0, 1, 2, and 3 are merged into one first cache read request, the sub-instruction mask for that first cache read request is 1111. When sub-instructions 0 and 1 are merged into the first first cache read request, and sub-instructions 2 and 3 are merged into the second first cache read request, the sub-instruction mask for the first first cache read request is 0011, and the sub-instruction mask for the second first cache read request is 1100. In the aforementioned four-bit sub-instruction mask, from the least significant bit to the most significant bit, sub-instruction 0, sub-instruction 1, sub-instruction 2, and sub-instruction 3 are respectively represented.

[0083] Next, at least one first cache read request and the sub-instruction mask for each first cache read request can be stored in a first buffer, such as a cache request latency buffer. The first buffer can be a circular buffer. Then, the instruction information of the memory read instruction can be determined and stored in a second buffer (also called an instruction buffer). The instruction information of the memory read instruction includes the identifier of the buffer block corresponding to the first first cache read request stored in the first buffer (cache request latency buffer head id), the number of first cache read requests corresponding to the memory read instruction (cache request number), and the first address offset and second address offset of each sub-instruction in the memory read instruction.

[0084] For any first cache read request, after obtaining the first target data corresponding to the first cache read request, the sub-instruction mask of the first cache read request can be obtained from the first buffer, and the sub-instructions included in the first cache read request can be determined based on the sub-instruction mask. For example, if the sub-instruction mask of the first cache read request obtained from the first buffer is 1111, then the sub-instructions included in the first cache read request are sub-instruction 0, sub-instruction 1, sub-instruction 2, and sub-instruction 3; if the sub-instruction mask of the first cache read request obtained from the first buffer is 0011, then the sub-instructions included in the first cache read request are sub-instruction 0 and sub-instruction 1; if the sub-instruction mask of the first cache read request obtained from the first buffer is 1100, then the sub-instructions included in the first cache read request are sub-instruction 2 and sub-instruction 3. Then, the first address offset and the second address offset of each sub-instruction in the first cache read request can be obtained from the instruction information of the memory read instructions stored in the second buffer.

[0085] In the embodiments of this disclosure, the sub-instruction mask of each first cache read request can be determined, and each first cache read request and its sub-instruction mask are stored in a first buffer; then, the instruction information of the memory read instruction is stored in a second buffer, thereby enabling the temporary storage of relevant information of the memory read instruction and its corresponding first cache read request through the first and second buffers during the execution of the memory read instruction. After obtaining the first target data corresponding to any first cache read request, the sub-instruction mask of the first cache read request is obtained from the first buffer, and the sub-instructions included in the first cache read request are determined according to the sub-instruction mask. Then, the first address offset and the second address offset of each sub-instruction in the first cache read request are obtained from the second buffer, thereby enabling the rapid and accurate acquisition of the first address offset and the second address offset of each sub-instruction in the first cache read request from the second buffer based on the sub-instruction mask after obtaining the first target data corresponding to the first cache read request, thus improving processing efficiency.

[0086] In some possible implementations, the data reading method of this disclosure embodiment may further include: when storing the first target data corresponding to any first cache read request into a scalar memory, determining that the first cache read request has been completed, and deleting the first cache read request and the sub-instruction mask of the first cache read request from the first buffer.

[0087] The execution progress of at least one first cache read request corresponding to the target read instruction may differ. For any first cache read request, if the first target data corresponding to the first cache read request is stored in scalar memory, it can be determined that the first cache read request has been completed. Then, the first cache read request and its sub-instruction mask are deleted from the first buffer. This allows the first cache read request and its sub-instruction mask to be deleted from the first buffer after any first cache read request has been completed, thus releasing the storage resources of the first buffer in a timely manner.

[0088] In some possible implementations, the data reading method of this disclosure embodiment may further include: determining whether all first cache read requests corresponding to the memory read instruction are deleted from the first buffer based on the identifier of the buffer block stored in the second buffer and the number of first cache read requests corresponding to the memory read instruction; if all first cache read requests corresponding to the memory read instruction are deleted from the first buffer, determining that the memory read instruction has been executed and deleting the instruction information of the memory read instruction from the second buffer.

[0089] Since the first buffer is a circular buffer, the first cache read requests stored in the first buffer are deleted sequentially. Therefore, based on the identifier of the buffer block storing the first first cache read request and the number of first cache read requests corresponding to the memory read instruction, it can be determined whether all first cache read requests corresponding to the memory read instruction have been deleted from the first buffer. For example, if the identifier of the buffer block storing the first first cache read request is 4 and the number of first cache read requests is 2, if the identifier of the buffer block storing the current first cache read request is 5, then it can be determined that all first cache read requests corresponding to the memory read instruction have not been deleted from the first buffer; if the identifier of the buffer block storing the current first cache read request is 6, then it can be determined that all first cache read requests corresponding to the memory read instruction have been deleted from the first buffer.

[0090] If all first cache read requests corresponding to a memory read instruction are deleted from the first buffer, it can be determined that the memory read instruction has been executed and the instruction information of the memory read instruction is deleted from the second buffer. Thus, the instruction information of the memory read instruction can be deleted from the second buffer after the memory read instruction is executed, and the storage resources of the second buffer can be released in a timely manner.

[0091] In some possible implementations, the data reading method of this disclosure embodiment may further include: when the destination addresses of multiple sub-instructions of a memory read instruction are all located in a vector memory, merging the sub-instructions whose source addresses are in the same cache line according to the source addresses of the multiple sub-instructions to obtain at least one second cache read request; executing at least one second cache read request to obtain third target data; and storing the third target data in the vector memory according to the destination address of any one of the sub-instructions.

[0092] When multiple sub-instructions of a memory read instruction have the same destination address (i.e., they share a common destination address), merging these sub-instructions does not require considering the destination address. Instead, sub-instructions whose source addresses are in the same cache line are merged based on their source addresses, resulting in at least one second cache read request. This second cache read request is then executed to obtain the third target data. The third target data is the data obtained after all second cache read requests have been executed.

[0093] At least one second cache read request reads third target data arranged in a manner convenient for reading from memory or cache. To facilitate writing the third target data into scalar memory, the third target data can be rearranged according to the source address of each sub-instruction in the memory read instruction. Since multiple sub-instructions share a single destination address, the rearranged third target data can be written into vector memory according to the destination address of any sub-instruction. This data rearrangement process can be viewed as a data packing process. The data packing process when the destination address is in vector memory is similar to the data packing process when the destination address is in scalar memory; both can share a single set of hardware processing logic, achieving hardware resource reuse and thus saving hardware resources and area.

[0094] In the embodiments of this disclosure, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in a vector memory, sub-instructions whose source addresses are in the same cache line can be merged to obtain at least one second cache read request; then, at least one second cache read request is executed to obtain third target data, and the third target data is stored in the vector memory according to the destination address of any one of the sub-instructions. This enables the merging of multiple sub-instructions in a memory read instruction when the destination addresses of multiple sub-instructions of a memory read instruction are all located in a vector memory, thereby reducing the number of cache read requests corresponding to the memory read instruction.

[0095] Based on this, the data reading method of this disclosure has a wide range of applications. It is applicable to scenarios where the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, as well as scenarios where the destination addresses of multiple sub-instructions of a memory read instruction are all located in vector memory. Moreover, when executing a memory read instruction, the data reading method of this disclosure can merge multiple sub-instructions in the memory read instruction into a cache read request before reading the data, thereby improving the processing efficiency during the data reading process.

[0096] Figure 2 This is a schematic diagram illustrating a data reading method provided in an embodiment of this disclosure. (Refer to...) Figure 2 The first processor 200 includes a parallel execution unit 210, a memory merging unit 220, a scalar memory 230, and a vector memory 240. The first processor 200 is connected to the memory 250 via a parallel bus, a serial bus, or a Network on Chip (NoC). When executing a memory read command that includes multiple sub-instructions, the parallel execution unit 210 in the first processor 200 can send the source and destination addresses of the multiple sub-instructions to the memory merging unit 220.

[0097] After receiving the source and destination addresses of multiple sub-instructions of a memory read instruction, the memory merging unit 220 can determine whether the destination addresses of all the sub-instructions of the memory read instruction are located in the scalar memory 230. If the destination addresses of all the sub-instructions of the memory read instruction are located in the scalar memory 230, the multiple sub-instructions can be merged, that is, sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory 230 are merged to obtain at least one first cache read request.

[0098] For any first cache read request, the memory merging unit 220 can determine the first address offset and the second address offset of each sub-instruction in the first cache read request, and determine the sub-instruction mask of the first cache read request based on the sub-instructions included in the first cache read request; then, it stores at least one first cache read request and the sub-instruction mask of each first cache read request into a first buffer; and stores the instruction information of the memory read instruction into a second buffer; wherein, the instruction information includes the identifier of the buffer block storing the first first cache read request corresponding to the memory read instruction in the first buffer, the number of first cache read requests corresponding to the memory read instruction, and the first address offset and the second address offset of each sub-instruction in the memory read instruction.

[0099] Then, at least one first cache read request corresponding to the memory read instruction is executed to read data from the cache or memory 250, obtaining the first target data corresponding to each first cache read request. For any first cache read request, the memory merging unit 220 can obtain the sub-instruction mask of the first cache read request from the first buffer, and determine the sub-instructions included in the first cache read request based on the sub-instruction mask. Then, it obtains the first address offset and the second address offset of each sub-instruction in the first cache read request from the second buffer. After that, data packing processing is performed, that is, the position of each sub-data in the first target data is updated according to the first address offset and the second address offset of each sub-instruction in the first cache read request, to obtain the updated first target data.

[0100] The memory merging unit 220 returns the updated first target data to the parallel execution unit 210 based on the second to the highest address bits of the destination address of any sub-instruction in the first cache read request. After receiving the first target data, the parallel execution unit 210 can store the first target data in the scalar memory 230 based on the second to the highest address bits of the destination address of any sub-instruction in the first cache read request.

[0101] It should be noted that the above example only illustrates the data reading method of this disclosure embodiment by taking the example that the destination addresses of multiple sub-instructions of the memory read instruction are all located in the scalar memory 230. The processing of multiple sub-instructions of the memory read instruction being located in the vector memory 240 is similar and will not be described again here.

[0102] The data reading method of this disclosure embodiment will be described exemplarily below with reference to examples.

[0103] Example 1 :

[0104] The first data length R of the cache line and the second data length Q of the scalar memory write line are both 128 (i.e., the length of both the cache line and the write line is 128 bytes). The third data length P is 16. The memory read instruction includes four sub-instructions: sub-instruction 0 (corresponding to thread 0), sub-instruction 1 (corresponding to thread 1), sub-instruction 2 (corresponding to thread 2), and sub-instruction 3 (corresponding to thread 3). The source address (i.e., the memory address) is 48 bits, and the destination address is 16 bits. The source addresses of these four sub-instructions are 0x1000010, 0x1000020, 0x1000030, and 0x1000040, and the destination addresses are 0xA20, 0xA30, 0xA40, and 0xA00, respectively. All four sub-instructions have their destination addresses located in scalar memory.

[0105] Therefore, log2(R) = 7 and log2(Q) = 7. When merging these four sub-instructions, since the source addresses [47:7] and destination addresses [15:7] are the same, these four sub-instructions can be merged into a single first cache read request. That is, this memory read instruction corresponds to one first cache read request, and in the case of a cache hit, one cycle is required to read data from the cache.

[0106] Since log2(R)-1=6, log2(Q)-1=6, and log2(P)=4, the [6:4] (i.e., 0x1) in the source address 0x1000010 of subinstruction 0 can be determined as the first address offset of subinstruction 0, and the [6:4] (i.e., 0x2) in the destination address 0xA20 of subinstruction 0 can be determined as the second address offset of subinstruction 0; similarly, the [6:4] (i.e., 0x2) in the source address 0x1000020 of subinstruction 1 can be determined as the first address offset of subinstruction 1, and the [6:4] (i.e., 0x2) in the destination address 0xA30 of subinstruction 1 can be determined as the second address offset of subinstruction 0. x3 is determined as the second address offset of sub-instruction 1; [6:4] in the source address 0x1000030 of sub-instruction 2, i.e., 0x3, can be determined as the first address offset of sub-instruction 2, and [6:4] in the destination address 0xA40 of sub-instruction 2, i.e., 0x4, can be determined as the second address offset of sub-instruction 2; [6:4] in the source address 0x1000040 of sub-instruction 3, i.e., 0x4, can be determined as the first address offset of sub-instruction 3, and [6:4] in the destination address 0xA00 of sub-instruction 3, i.e., 0x0, can be determined as the second address offset of sub-instruction 3.

[0107] Then the first cache read request can be executed to read data from the cache or memory to obtain the first target data corresponding to the first cache read request; then, according to the first address offset and the second address offset of each sub-instruction in the first cache read request, the position of each sub-data in the first target data is updated to obtain the updated first target data, and the updated first target data is stored in scalar memory according to the destination address of the sub-instruction.

[0108] Figure 3 This is a schematic diagram illustrating the position update of sub-data in a data reading method provided in an embodiment of this disclosure. (Refer to...) Figure 3 The first target data includes four sub-data segments: sub-data 0 corresponding to sub-instruction 0 (source address 0x1000010, destination address 0xA20), sub-data 1 corresponding to sub-instruction 1 (source address 0x1000020, destination address 0xA30), sub-data 2 corresponding to sub-instruction 2 (source address 0x1000030, destination address 0xA40), and sub-data 3 corresponding to sub-instruction 3 (source address 0x1000040, destination address 0xA00). Their address offsets in the cache line (i.e., the first address offset) are 0x1, 0x2, 0x3, and 0x4, respectively, while their address offsets in the data write line (i.e., the second address offset) are 0x2, 0x3, 0x4, and 0x0, respectively. According to... Figure 3 The position of each sub-data in the first target data is updated in the direction indicated by the middle arrow, resulting in the updated first target data.

[0109] Example 2:

[0110] The first data length R of the cache line and the second data length Q of the scalar memory write line are both 128 (i.e., the length of both the cache line and the write line is 128 bytes). The third data length P is 16. The memory read instruction includes four sub-instructions: sub-instruction 0 (corresponding to thread 0), sub-instruction 1 (corresponding to thread 1), sub-instruction 2 (corresponding to thread 2), and sub-instruction 3 (corresponding to thread 3). The source address (i.e., the memory address) is 48 bits, and the destination address is 16 bits. The source addresses of these four sub-instructions are 0x1000010, 0x1000020, 0x1000030, and 0x1000040, and the destination addresses are 0xA20, 0xA30, 0xB40, and 0xB00, respectively. All four sub-instructions have their destination addresses located in scalar memory.

[0111] Therefore, log2(R) = 7 and log2(Q) = 7. When merging these four sub-instructions, since the source addresses [47:7] and destination addresses [15:7] of sub-instructions 0 and 1 are the same, they can be merged into a single first cache read request. Similarly, since the source addresses [47:7] and destination addresses [15:7] of sub-instructions 2 and 3 are the same, they can be merged into a single first cache read request. In other words, this memory read instruction corresponds to two first cache read requests, requiring two cycles to read data from the cache in the event of a cache hit.

[0112] Since log2(R)-1=6, log2(Q)-1=6, and log2(P)=4, for the first first cache read request, the [6:4] in the source address 0x1000010 of subinstruction 0, i.e., 0x1, can be determined as the first address offset of subinstruction 0, and the [6:4] in the destination address 0xA20 of subinstruction 0, i.e., 0x2, can be determined as the second address offset of subinstruction 0; the [6:4] in the source address 0x1000020 of subinstruction 1, i.e., 0x2, can be determined as the first address offset of subinstruction 1, and the [6:4] in the destination address 0xA30 of subinstruction 1, i.e., 0x3, can be determined as the second address offset of subinstruction 1.

[0113] For the second first cache read request, [6:4] in the source address 0x1000030 of sub-instruction 2, i.e., 0x3, can be determined as the first address offset of sub-instruction 2, and [6:4] in the destination address 0xB40 of sub-instruction 2, i.e., 0x4, can be determined as the second address offset of sub-instruction 2; [6:4] in the source address 0x1000040 of sub-instruction 3, i.e., 0x4, can be determined as the first address offset of sub-instruction 3, and [6:4] in the destination address 0xB00 of sub-instruction 3, i.e., 0x0, can be determined as the second address offset of sub-instruction 3.

[0114] Then, these two first cache read requests can be executed to read data from the cache or memory, obtaining the first target data corresponding to each first cache read request. For any first cache read request, based on the first address offset and the second address offset of each sub-instruction in the first cache read request, the position of each sub-data in the first target data corresponding to the first cache read request is updated to obtain the updated first target data. Then, based on the destination address of the sub-instruction, the updated first target data is stored in scalar memory.

[0115] Figure 4 This is a schematic diagram illustrating the position update of sub-data in a data reading method provided in an embodiment of this disclosure. (Refer to...) Figure 4 The first target data includes four sub-data segments: sub-data 0 corresponding to sub-instruction 0 (source address 0x1000010, destination address 0xA20), sub-data 1 corresponding to sub-instruction 1 (source address 0x1000020, destination address 0xA30), sub-data 2 corresponding to sub-instruction 2 (source address 0x1000030, destination address 0xB40), and sub-data 3 corresponding to sub-instruction 3 (source address 0x1000040, destination address 0xB00). Their address offsets in the cache line (i.e., the first address offset) are 0x1, 0x2, 0x3, and 0x4, respectively, while their address offsets in the data write line (i.e., the second address offset) are 0x2, 0x3, 0x4, and 0x0, respectively. This can be based on... Figure 4 The position of each sub-data in the first target data is updated in the direction indicated by the middle arrow, resulting in the updated first target data.

[0116] It should be noted that in both Example 1 and Example 2 above, the first address offset and the second address offset are calculated based on the third data length P. Therefore, when using the first address offset and the second address offset for address location (e.g., determining the source address or destination address), it is necessary to multiply by the third data length P.

[0117] The embodiments provided in this disclosure, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, can merge sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory to obtain at least one first cache read request. Then, the at least one first cache read request is executed to read data from memory or cache, obtaining the first target data corresponding to each first cache read request, and storing the first target data in scalar memory. In this way, when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, the merging of multiple sub-instructions in a memory read instruction can be achieved, reducing the number of cache read requests corresponding to the memory read instruction. This not only reduces the processor's cache resource usage but also improves the execution efficiency of the memory read instruction.

[0118] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0119] In addition, this disclosure also provides a data reading device, an electronic device, and a computer-readable storage medium, all of which can be used to implement any of the data reading methods provided in this disclosure. The corresponding technical solutions and descriptions are described in the corresponding descriptions in the method section, and will not be repeated here.

[0120] Figure 5 This is a block diagram of a data reading device provided in an embodiment of the present disclosure.

[0121] Reference Figure 5 This disclosure provides a data reading device, which includes a first merging module 51, a first execution module 52, and a first storage module 53.

[0122] The first merging module 51 is used to merge sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, based on the source addresses and destination addresses of the multiple sub-instructions, to obtain at least one first cache read request.

[0123] The first execution module 52 is used to execute the at least one first cache read request to obtain the first target data corresponding to each first cache read request.

[0124] The first storage module 53 is used to store the first target data corresponding to each first cache read request into the scalar memory.

[0125] In some possible implementations, the first merging module 51 is specifically used to: determine a first address bit in the source address based on the first data length of the cache line; wherein the first address bit is an address bit in the source address corresponding to the alignment granularity of the first data length; determine a second address bit in the destination address based on the second data length of the data write line of the scalar memory; wherein the second address bit is an address bit in the destination address corresponding to the alignment granularity of the second data length; and based on the first address bit and the second address bit, merge the sub-instructions in the plurality of sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory into a first cache read request; wherein the source addresses with the same first address bit to the highest address bit are in the same cache line, and the destination addresses with the same second address bit to the highest address bit are in the same data write line of the scalar memory.

[0126] In some possible implementations, the first storage module 53 is specifically configured to: for any first cache read request, determine the first address offset and the second address offset of each sub-instruction in the first cache read request; wherein the first address offset refers to the address offset of the source address in the cache line, and the second address offset refers to the address offset of the destination address in the data write line; and store the first target data corresponding to the first cache read request into the scalar memory according to the first address offset, the second address offset and the destination address of each sub-instruction in the first cache read request.

[0127] In some possible implementations, the first storage module 53 is specifically configured to: for any sub-instruction in the first cache read request, determine the first address offset of the sub-instruction based on the lowest address bit in the source address of the sub-instruction to the address bit lower than the first address bit; and determine the second address offset of the sub-instruction based on the lowest address bit in the destination address of the sub-instruction to the address bit lower than the second address bit.

[0128] In some possible implementations, the first target data includes multiple sub-data, and each sub-instruction in the first cache read request corresponds to one sub-data; wherein, the first storage module 53 is specifically used to: determine the third address bit in the source address of the sub-instruction based on the third data length of the sub-data corresponding to the sub-instruction; wherein, the third address bit is the address bit in the source address corresponding to the alignment granularity of the third data length, and the third address bit is lower than the first address bit; and determine the first address offset of the sub-instruction based on the third address bit in the source address of the sub-instruction to the address bit lower than the first address bit.

[0129] In some possible implementations, the first storage module 53 is specifically configured to: for any sub-instruction in the first cache read request, determine the sub-data corresponding to the sub-instruction from the first target data corresponding to the first cache read request based on the first address offset of the sub-instruction, and determine the update position of the sub-data corresponding to the sub-instruction based on the second address offset of the sub-instruction; update the position of each sub-data in the first target data corresponding to the first cache read request based on the update position of the sub-data corresponding to each sub-instruction in the first cache read request, to obtain the updated first target data; and store the updated first target data in the scalar memory based on the second address bit to the highest address bit of the destination address of any sub-instruction in the first cache read request.

[0130] In some possible implementations, the first execution module 52 is specifically configured to: merge the first cache read requests corresponding to the same cache line into a target cache read request based on the source address of the sub-instruction in the at least one first cache read request and the first address bit; if the second target data corresponding to the target cache read request is located in the cache, read the second target data from the cache; and determine the first target data corresponding to the first cache read request included in the target cache read request from the second target data.

[0131] In some possible implementations, the apparatus further includes: a mask determination module, configured to determine a sub-instruction mask for each first cache read request; wherein the sub-instruction mask is used to indicate the sub-instructions included in the first cache read request among the plurality of sub-instructions; a second storage module, configured to store the at least one first cache read request and the sub-instruction mask of each first cache read request into a first buffer; a third storage module, configured to store instruction information of the memory read instruction into a second buffer; wherein the instruction information includes an identifier of the buffer block storing the first first cache read request corresponding to the memory read instruction in the first buffer, the number of first cache read requests corresponding to the memory read instruction, and a first address offset and a second address offset for each sub-instruction in the memory read instruction; a mask acquisition module, configured to, for any first cache read request, after obtaining the first target data corresponding to the first cache read request, acquire the sub-instruction mask of the first cache read request from the first buffer, and determine the sub-instructions included in the first cache read request based on the sub-instruction mask; and an offset acquisition module, configured to acquire the first address offset and the second address offset for each sub-instruction in the first cache read request from the second buffer.

[0132] In some possible implementations, the apparatus further includes: a first deletion module, configured to determine that the first cache read request has been completed when the first target data corresponding to any first cache read request is stored in the scalar memory, and to delete the first cache read request and the sub-instruction mask of the first cache read request from the first buffer.

[0133] In some possible implementations, the apparatus further includes: a determining module, configured to determine whether all first cache read requests corresponding to the memory read instruction have been deleted from the first buffer based on the identifier of the buffer block stored in the second buffer and the number of first cache read requests corresponding to the memory read instruction; and a second deleting module, configured to determine that the memory read instruction has been executed and delete the instruction information of the memory read instruction from the second buffer if all first cache read requests corresponding to the memory read instruction have been deleted from the first buffer.

[0134] In some possible implementations, the apparatus further includes: a second merging module, configured to merge sub-instructions whose source addresses are in the same cache line according to the source addresses of the multiple sub-instructions when the destination addresses of the multiple sub-instructions of the memory read instruction are all located in the vector memory, to obtain at least one second cache read request; a second execution module, configured to execute the at least one second cache read request to obtain third target data; and a fourth storage module, configured to store the third target data in the vector memory according to the destination address of any one of the sub-instructions.

[0135] Figure 6 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0136] Reference Figure 6 This disclosure provides an electronic device, which includes: at least one second processor 601; at least one memory 602; and one or more I / O interfaces 603 connected between the second processor 601 and the memory 602; wherein the memory 602 stores one or more computer programs that can be executed by at least one second processor 601, and the one or more computer programs are executed by at least one second processor 601 to enable at least one second processor 601 to perform the above-described data reading method.

[0137] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the data reading method described above. The computer-readable storage medium may be volatile or non-volatile.

[0138] This disclosure also provides a computer program product including computer-readable code, which, when executed in a processor of an electronic device, causes the processor in the electronic device to perform the aforementioned data reading method.

[0139] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0140] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable program instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0141] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0142] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0143] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0144] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0145] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0146] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0147] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0148] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A data reading method, characterized in that, The method includes: When the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, the sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory are merged according to the source addresses and destination addresses of the multiple sub-instructions to obtain at least one first cache read request. Execute the at least one first cache read request to obtain the first target data corresponding to each first cache read request; The first target data corresponding to each first cache read request is stored in the scalar memory.

2. The method according to claim 1, characterized in that, The step of merging sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory, based on the source and destination addresses of the multiple sub-instructions, to obtain at least one first cache read request, includes: Based on the first data length of the cache line, a first address bit in the source address is determined; wherein, the first address bit is the address bit in the source address corresponding to the alignment granularity of the first data length; The second address bit in the destination address is determined based on the second data length of the data write line of the scalar memory; wherein the second address bit is the address bit in the destination address that corresponds to the alignment granularity of the second data length; Based on the first address bit and the second address bit, the sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory are merged into a first cache read request; wherein, the source addresses with the same first address bit to the highest address bit are in the same cache line, and the destination addresses with the same second address bit to the highest address bit are in the same data write line of the scalar memory.

3. The method according to claim 1, characterized in that, The step of storing the first target data corresponding to each first cache read request into the scalar memory includes: For any first cache read request, determine the first address offset and the second address offset of each sub-instruction in the first cache read request; wherein, the first address offset refers to the address offset of the source address in the cache line, and the second address offset refers to the address offset of the destination address in the data write line; Based on the first address offset, second address offset, and destination address of each sub-instruction in the first cache read request, the first target data corresponding to the first cache read request is stored in the scalar memory.

4. The method according to claim 3, characterized in that, Determining the first address offset and the second address offset of each sub-instruction in the first cache read request includes: For any sub-instruction in the first cache read request, determine the first address offset of the sub-instruction based on the lowest address bit in the source address of the sub-instruction to the address bit lower than the first address bit; The second address offset of the subinstruction is determined based on the lowest address bit in the destination address of the subinstruction to the address bit lower than the second address bit.

5. The method according to claim 4, characterized in that, The first target data includes multiple sub-data, and each sub-instruction in the first cache read request corresponds to one sub-data. Wherein, determining the first address offset of the sub-instruction based on the least significant address bit in the source address of the sub-instruction to the address bit below the first address bit includes: The third address bit in the source address of the sub-instruction is determined based on the third data length of the sub-data corresponding to the sub-instruction; wherein the third address bit is the address bit in the source address corresponding to the alignment granularity of the third data length, and the third address bit is lower than the first address bit; The first address offset of the subinstruction is determined based on the third address bit in the source address of the subinstruction to the address bit lower than the first address bit.

6. The method according to claim 3, characterized in that, The step of storing the first target data corresponding to the first cache read request into the scalar memory according to the first address offset, second address offset, and destination address of each sub-instruction in the first cache read request includes: For any sub-instruction in the first cache read request, the sub-data corresponding to the sub-instruction is determined from the first target data corresponding to the first cache read request based on the first address offset of the sub-instruction, and the update position of the sub-data corresponding to the sub-instruction is determined based on the second address offset of the sub-instruction. Based on the update position of the sub-data corresponding to each sub-instruction in the first cache read request, the position of each sub-data in the first target data corresponding to the first cache read request is updated to obtain the updated first target data; The updated first target data is stored in the scalar memory according to the second address bit to the highest address bit of the destination address of any sub-instruction in the first cache read request.

7. The method according to claim 2, characterized in that, The step of executing the at least one first cache read request to obtain the first target data corresponding to each first cache read request includes: Based on the source address of the sub-instruction in the at least one first cache read request and the first address bit, the first cache read requests corresponding to the same cache line are merged into a target cache read request; If the second target data corresponding to the target cache read request is in the cache, the second target data is read from the cache. From the second target data, determine the first target data corresponding to the first cache read request included in the target cache read request.

8. The method according to claim 3, characterized in that, The method further includes: Determine a sub-instruction mask for each first cache read request; wherein the sub-instruction mask is used to indicate the sub-instructions included in the first cache read request among the plurality of sub-instructions; Store the at least one first cache read request and the sub-instruction mask of each first cache read request into the first buffer; The instruction information of the memory read instruction is stored in the second buffer; wherein, the instruction information includes the identifier of the buffer block in the first buffer that stores the first first cache read request corresponding to the memory read instruction, the number of first cache read requests corresponding to the memory read instruction, and the first address offset and second address offset of each sub-instruction in the memory read instruction; For any first cache read request, after obtaining the first target data corresponding to the first cache read request, the sub-instruction mask of the first cache read request is obtained from the first buffer, and the sub-instructions included in the first cache read request are determined according to the sub-instruction mask. From the second buffer, obtain the first address offset and the second address offset of each sub-instruction in the first cache read request.

9. The method according to claim 8, characterized in that, The method further includes: When storing the first target data corresponding to any first cache read request into the scalar memory, it is determined that the first cache read request has been completed, and the first cache read request and the sub-instruction mask of the first cache read request are deleted from the first buffer.

10. The method according to claim 8, characterized in that, The method further includes: Based on the identifier of the buffer block stored in the second buffer and the number of first cache read requests corresponding to the memory read instruction, determine whether all first cache read requests corresponding to the memory read instruction should be deleted from the first buffer; If all first cache read requests corresponding to the memory read instruction are deleted from the first buffer, it is determined that the memory read instruction has been executed and the instruction information of the memory read instruction is deleted from the second buffer.

11. The method according to any one of claims 1 to 10, characterized in that, The method further includes: When the destination addresses of multiple sub-instructions of a memory read instruction are all located in the vector memory, the sub-instructions whose source addresses are in the same cache line are merged according to the source addresses of the multiple sub-instructions to obtain at least one second cache read request. Execute the at least one second cache read request to obtain the third target data; The third target data is stored in the vector memory according to the destination address of any sub-instruction.

12. A data reading device, characterized in that, include: The first merging module is used to merge sub-instructions whose source addresses are in the same cache line and whose destination addresses are in the same data write line of the scalar memory when the destination addresses of multiple sub-instructions of a memory read instruction are all located in scalar memory, based on the source addresses and destination addresses of the multiple sub-instructions, to obtain at least one first cache read request. The first execution module is used to execute the at least one first cache read request and obtain the first target data corresponding to each first cache read request; The first storage module is used to store the first target data corresponding to each first cache read request into the scalar memory.

13. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs that can be executed by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the data reading method as described in any one of claims 1-11.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the data reading method as described in any one of claims 1-11.

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