Dynamic error correction method, system and apparatus for flash memory

Abstract

The application discloses a dynamic error correction method, system and device for flash memory, and the method comprises the following steps: obtaining state data of the flash memory, the state data being state data of the flash memory when a read operation is performed on target data in the flash memory; calling a preset joint quantization algorithm to calculate and process the state data to obtain a channel degradation index and a thermal risk index; constructing a joint optimization objective function according to the channel degradation index and the thermal risk index, and calling a preset optimization algorithm to calculate and process the joint optimization objective function to obtain a target error correction code iteration number; and adjusting an iteration number of error correction decoding when the read operation is performed on the target data based on the target error correction code iteration number. The application obtains the target error correction code iteration number by processing the state data of the flash memory, so that a suitable target error correction code iteration number can be obtained when a channel condition is good or when the channel condition deteriorates sharply, and the adaptability of the target error correction code iteration number is improved.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to a dynamic error correction method, system, and apparatus for flash memory. Background Technology

[0002] As flash memory storage density continues to increase, cell size shrinks, and the number of 3D stacking layers increases, the charge retention capability of cells decreases and interference between cells intensifies, leading to a significant increase in the original bit error rate. To ensure data reliability, modern flash memory controllers commonly employ advanced error correction technologies such as low-density parity-check codes.

[0003] Currently, existing error correction code schemes typically employ static error correction strategies with a fixed number of iterations or based on a simple threshold (such as a preset maximum number of iterations). However, static error correction strategies often lead to two extreme situations: when channel conditions are good, unnecessary iterations result in wasted controller power; when channel conditions deteriorate sharply, the fixed number of iterations may be insufficient for successful decoding, leading to read failures and increased data recovery delays.

[0004] Therefore, existing error correction code schemes suffer from poor adaptability in terms of the number of error correction code iterations. Summary of the Invention

[0005] The main objective of this application is to propose a dynamic error correction method, system, and apparatus for flash memory, aiming to solve the problem of poor adaptability of error correction code iteration times.

[0006] To achieve the above objectives, this application proposes a dynamic error correction method for flash memory, comprising: Acquire the status data of the flash memory, wherein the status data is the status data of the flash memory when reading target data in the flash memory; The channel degradation index and thermal risk index are obtained by calling a preset joint quantization algorithm to calculate and process the state data. A joint optimization objective function is constructed based on the channel degradation index and the thermal risk index, and a preset optimization algorithm is called to calculate and process the joint optimization objective function to obtain the number of iterations of the target error correction code; Based on the number of iterations of the target error correction code, the number of iterations of error correction decoding is adjusted when reading the target data.

[0007] In some embodiments, the flash memory includes one or more flash memory chips, each flash memory chip including multiple physical blocks, each physical block including multiple physical pages; acquiring the flash memory status data includes: Obtain the raw bit error rate of the target physical page, where the target physical page is the physical page storing the target data; Obtain the cumulative number of program erases and the maximum number of program erases tolerable for the target physical block, wherein the target physical block is the physical block containing the target physical page; The junction temperature, rated temperature, rated temperature variation range, and junction temperature variation rate of the target flash memory chip are obtained, wherein the target flash memory chip is a flash memory chip containing the target physical block.

[0008] In some embodiments, the step of using a preset joint quantization algorithm to calculate and process the state data to obtain the channel degradation index and the thermal risk index includes: CI=α×log10(RBER)+β×(PE_Cycle / PE_Max)+γ×(Tj-T_nom) / ΔT; TI = δ × TI_prev + ε × ΔTj; Where CI represents the channel degradation index, α represents the preset weight of the original bit error rate term, RBER represents the original bit error rate, β represents the preset weight of the cumulative programming and erasure times term, PE_Cycle represents the cumulative programming and erasure times, PE_Max represents the maximum tolerable programming and erasure times, γ represents the preset weight of the chip junction temperature term, Tj represents the chip junction temperature, T_nom represents the rated temperature, and ΔT represents the rated temperature variation range. TI represents the thermal risk index, δ represents the preset weight of the previous thermal risk index term, TI_prev represents the previous thermal risk index, the initial value of TI_prev is 0, ε represents the preset weight of the junction temperature change rate term, and ΔTj represents the junction temperature change rate.

[0009] In some embodiments, constructing a joint optimization objective function based on the channel degradation index and the thermal risk index includes: J=w1×Imax+λ1×P_fail(CI,Imax)+w2×(1 / VF)+λ2×g(TI,VF); Where J represents the joint optimization objective function, w1 represents the preset weight of the target error correction code iteration number term, Imax represents the target error correction code iteration number, λ1 represents the preset weight of the decoding failure penalty term, and P_fail(CI,Imax) represents the decoding failure penalty function. w2 represents the preset weight of the voltage frequency adjustment parameter, VF represents the voltage frequency adjustment parameter, λ2 represents the preset weight of the thermal risk penalty term, and g(TI,VF) represents the thermal risk penalty function.

[0010] In some embodiments, the step of calling a preset optimization algorithm to calculate the joint optimization objective function to obtain the target error correction code iteration number includes: The preset optimization algorithm is invoked to minimize the joint optimization objective function, thereby obtaining the number of iterations of the target error correction code and the voltage frequency adjustment parameters.

[0011] In some embodiments, adjusting the number of iterations for error correction decoding when reading the target data based on the number of iterations for the target error correction code includes: Based on the number of iterations of the target error correction code, adjust the number of iterations of error correction decoding when reading the target data; Based on the voltage and frequency adjustment parameters, the operating voltage and frequency are adjusted when reading the target data.

[0012] In some embodiments, obtaining the raw bit error rate of the target physical page includes: Obtain the raw bit error rate of the target physical page; The original bit error rate is corrected by calling a preset adjacent page interference cancellation algorithm to obtain the corrected original bit error rate.

[0013] In some embodiments, after adjusting the number of iterations for error correction decoding when reading the target data based on the number of iterations of the target error correction code, the method further includes: Collect the actual decoding success rate of the error correction decoding and the status data; The parameters in the preset joint quantization algorithm and the joint optimization objective function are optimized based on the actual decoding success rate and the state data.

[0014] This application further proposes a dynamic error correction system for flash memory, the dynamic error correction system for flash memory including a controller and flash memory, the controller being configured inside the flash memory, the flash memory including one or more flash memory chips, the flash memory chips including multiple physical blocks, the physical blocks including multiple physical pages; the controller is capable of executing the dynamic error correction method for flash memory described above.

[0015] This application further proposes a dynamic error correction device for flash memory, comprising: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that are executed by the at least one processor, which enable the at least one processor to perform the dynamic error correction method for flash memory described above.

[0016] This application's technical solution obtains the flash memory's state data during a read operation of target data; it then uses a preset joint quantization algorithm to calculate the channel degradation index and thermal risk index from the state data; it constructs a joint optimization objective function based on the channel degradation index and thermal risk index, and uses a preset optimization algorithm to calculate the target error correction code iteration count; based on the target error correction code iteration count, it adjusts the error correction decoding iteration count during the read operation of target data; by processing the flash memory's state data to obtain the target error correction code iteration count, a suitable target error correction code iteration count can be obtained whether the channel conditions are good or the channel conditions are rapidly deteriorating, thus improving the adaptability of the target error correction code iteration count. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating an embodiment of the dynamic error correction method for flash memory in this application; Figure 2 This is a flowchart illustrating another embodiment of the dynamic error correction method for flash memory in this application; Figure 3 This is a flowchart illustrating another embodiment of the dynamic error correction method for flash memory in this application; Figure 4 This is a flowchart illustrating another embodiment of the dynamic error correction method for flash memory in this application; Figure 5 This is a flowchart illustrating another embodiment of the dynamic error correction method for flash memory in this application; Figure 6 This is a schematic diagram of the structure of an embodiment of the dynamic error correction system for flash memory in this application; Figure 7 This is a schematic diagram of an embodiment of the dynamic error correction device for flash memory in this application. Detailed Implementation

[0018] The solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments in this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0020] It should also be noted that when a component is referred to as "fixed to" or "set on" another component, it can be directly on the other component or an intervening component can be present simultaneously. When a component is referred to as "connected to" another component, it can be directly connected to the other component or an intervening component can be present simultaneously.

[0021] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0022] This application proposes a dynamic error correction method for flash memory, referring to... Figure 1 , Figure 1 This is a flowchart illustrating one embodiment of the dynamic error correction method for flash memory according to this application. In some embodiments, the dynamic error correction method for flash memory includes: Step S110: Obtain the status data of the flash memory. The status data is the status data of the flash memory when the target data in the flash memory is read. Step S120: Call the preset joint quantization algorithm to calculate and process the state data to obtain the channel degradation index and thermal risk index; Step S130: Construct a joint optimization objective function based on the channel degradation index and the thermal risk index, and call a preset optimization algorithm to calculate and process the joint optimization objective function to obtain the number of iterations of the target error correction code; Step S140: Adjust the number of iterations of error correction decoding when reading target data based on the number of iterations of the target error correction code.

[0023] In this embodiment, the dynamic error correction method for flash memory can be configured as software, a program, or encapsulated as executable firmware, a driver-level plugin, or a modular tool; then it is configured to the controller so that the controller can run the dynamic error correction method for flash memory. Alternatively, it can be configured to other computer devices so that the computer device can run the dynamic error correction method for flash memory.

[0024] Understandably, the controller can be configured inside NAND flash memory, which includes one or more flash memory chips, each chip comprising multiple physical blocks, and each physical block comprising multiple physical pages. Each physical page consists of multiple storage cells. During data storage, retention, repeated erasure and writing, and temperature fluctuations, the storage cells experience phenomena such as charge leakage, charge interference, and tunneling losses, causing shifts in the stored 0 / 1 levels. This inevitably leads to bit errors when reading data, thus requiring error correction and decoding during data retrieval. The flash memory can be connected to a host computer, allowing users to write data into it. When the user needs to use this data, it can be read from the flash memory.

[0025] When performing a read operation on target data in the flash memory, the flash memory's status data is acquired. This status data refers to the flash memory's state at the time of the read operation. For example, when performing a read operation on target data in the flash memory, the controller can first acquire the flash memory's status data.

[0026] After acquiring the status data, a preset joint quantization algorithm can be invoked to calculate and process the status data to obtain the channel degradation index and the thermal risk index. For example, after acquiring the status data, the controller can invoke the preset joint quantization algorithm to calculate and process the status data, thereby obtaining the channel degradation index and the thermal risk index. The preset joint quantization algorithm can be pre-configured by the user on the controller.

[0027] After obtaining the channel degradation index and the thermal risk index, a joint optimization objective function can be constructed based on these indices. A preset optimization algorithm is then called to calculate and process the joint optimization objective function to obtain the target error correction code iteration count. For example, after obtaining the channel degradation index and the thermal risk index, the controller can construct a joint optimization objective function based on these indices; then, a preset optimization algorithm is called to solve the joint optimization objective function, thereby obtaining the target error correction code iteration count.

[0028] After obtaining the target error correction code iteration count, the number of error correction decoding iterations during the reading operation of the target data can be adjusted based on this count. For example, after obtaining the target error correction code iteration count, the controller can adjust the number of error correction decoding iterations during the reading operation of the target data to match the target error correction code iteration count, thereby using the target error correction code iteration count to perform error correction decoding on the target data.

[0029] The technical solution of this application obtains the target error correction code iteration number by processing the state data of flash memory, so that a suitable target error correction code iteration number can be obtained when the channel conditions are good or when the channel conditions deteriorate sharply, thereby improving the adaptability of the target error correction code iteration number.

[0030] Reference Figure 2 , Figure 2 This is a flowchart illustrating another embodiment of the dynamic error correction method for flash memory in this application. In some embodiments, the flash memory includes one or more flash memory chips, each flash memory chip includes multiple physical blocks, and each physical block includes multiple physical pages; the aforementioned acquisition of flash memory status data includes: Step S150: Obtain the raw bit error rate of the target physical page, where the target physical page is the physical page storing the target data; Step S151: Obtain the cumulative number of program erases and the maximum number of program erases tolerable for the target physical block. The target physical block is the physical block containing the target physical page. Step S152: Obtain the junction temperature, rated temperature, rated temperature variation range, and junction temperature variation rate of the target flash memory chip. The target flash memory chip is a flash memory chip containing the target physical block.

[0031] In this embodiment, as Figure 2 As shown, various status data can be acquired during step S110. Flash memory includes one or more flash memory chips, each flash memory chip includes multiple physical blocks, and each physical block includes multiple physical pages. A flash memory chip is the core hardware unit of flash memory; each flash memory chip can independently complete data storage, read / write control, and signal transmission; it supports parallel operation of multiple flash memory chips to improve storage capacity and read / write speed. A physical block is the smallest erase unit of flash memory, composed of multiple consecutive physical pages. Its lifespan is limited by the maximum program erase tolerance (Program Erase_Maximum, PE_Max). In this embodiment, the maximum program erase tolerance (PE_Max) and the maximum program / erase tolerance (P / E_Max) have the same meaning. A physical page is the smallest read / write unit of flash memory. The storage unit within a physical page is the direct storage carrier of the target data. A single read or programming operation is performed on only a single physical page, and data reliability indicators such as the original bit error rate are also statistically measured using physical pages.

[0032] Obtain the raw bit error rate (BER) of the target physical page. The target physical page is the physical page storing the target data. For example, when reading target data from the target physical page, the controller can acquire the raw output signal of the target physical page; then, it compares the acquired raw output signal bit-by-bit with the reference signal used when writing the target data, counting the number of bit errors (error bits); then, it calculates the raw BER using the raw BER calculation formula (raw BER = error bits / total number of bits in the target physical page). The raw BER ranges from [0,1]. A higher value indicates more severe charge leakage and level shift in the target physical page's storage units, a higher degree of channel degradation, and more iterations required for subsequent error correction and decoding.

[0033] The system obtains the cumulative number of program-erase cycles and the maximum tolerable number of program-erase cycles for the target physical block. The target physical block is the physical block containing the target physical pages. For example, the controller may include a counting module, and the flash memory may include registers. Each time the controller completes a full "program-erase" cycle on the target physical block, the controller's counting module automatically increments by 1. The controller obtains the cumulative number of program-erase cycles by reading the current value of the counter. The counting range of the counting module matches the maximum tolerable number of program-erase cycles, supporting full-range counting from 0 to the maximum tolerable number of program-erase cycles, and the counting result is maintained in a non-volatile memory unit after power failure. In this embodiment, the cumulative number of program-erase cycles and the cumulative number of program / erase cycles have the same meaning. The maximum tolerable number of program-erase cycles is an inherent hardware parameter of the physical block, calibrated by the manufacturer at the factory through testing, and stored in the flash memory registers. The controller obtains the maximum tolerable number of program-erase cycles by reading the registers.

[0034] The controller acquires the junction temperature, rated temperature, rated temperature range, and junction temperature change rate of the target flash memory chip. The target flash memory chip is the flash memory chip containing the target physical block. For example, the flash memory chip may include a temperature sensor (such as a thermistor or diode temperature sensor). The junction temperature is the actual operating temperature of the flash memory chip. The controller can acquire the junction temperature of the target flash memory chip in real time through the temperature sensor. The rated temperature is the standard operating temperature of the flash memory chip, calibrated by the manufacturer and stored in a register. The controller can obtain the rated temperature by reading the register. The rated temperature range is the allowable normal operating temperature fluctuation range of the flash memory chip, determined by the manufacturer based on the flash memory chip's reliability test results, and stored in a register. The rated temperature range is used to normalize the degree of temperature deviation. The controller can obtain the rated temperature range by reading the register. The controller can also calculate the junction temperature change rate using the two most recently sampled junction temperatures. The junction temperature change rate reflects the rate of change of the junction temperature and is used to assess the suddenness of thermal risks.

[0035] In some embodiments, the aforementioned calculation and processing of the state data using a preset joint quantization algorithm to obtain the channel degradation index and thermal risk index includes: CI=α×log10(RBER)+β×(PE_Cycle / PE_Max)+γ×(Tj-T_nom) / ΔT; TI = δ × TI_prev + ε × ΔTj; Where CI represents the channel degradation index, α represents the preset weight of the original bit error rate term, RBER represents the original bit error rate, β represents the preset weight of the cumulative programming and erasure times term, PE_Cycle represents the cumulative programming and erasure times, PE_Max represents the maximum tolerable programming and erasure times, γ represents the preset weight of the chip junction temperature term, Tj represents the chip junction temperature, T_nom represents the rated temperature, and ΔT represents the rated temperature variation range. TI represents the thermal risk index, δ represents the preset weight of the previous thermal risk index term, TI_prev represents the previous thermal risk index, the initial value of TI_prev is 0, ε represents the preset weight of the junction temperature change rate term, and ΔTj represents the junction temperature change rate.

[0036] In this embodiment, when executing step S120, a preset joint quantization algorithm can be invoked to calculate and process the state data to obtain the channel degradation index and the thermal risk index. Invoking the preset joint quantization algorithm to calculate and process the state data to obtain the channel degradation index and the thermal risk index includes: CI=α×log10(RBER)+β×(PE_Cycle / PE_Max)+γ×(Tj-T_nom) / ΔT; TI = δ × TI_prev + ε × ΔTj; Where CI represents the channel degradation index, α represents the preset weight of the original bit error rate (BER) term, RBER represents the original bit error rate (BER), β represents the preset weight of the cumulative programming and erasing count term, PE_Cycle represents the cumulative programming and erasing count, PE_Max represents the maximum tolerable programming and erasing count, γ represents the preset weight of the chip junction temperature term, Tj represents the chip junction temperature, T_nom represents the rated temperature, and ΔT represents the rated temperature variation range. α, β, and γ can be preset weights by the user according to actual conditions, and the sum of α, β, and γ can be 1.

[0037] The CI value typically ranges from [0, 5], with a larger value indicating more severe channel degradation. CI∈[0,1]: The channel state is good, and no additional error correction iterations are needed; CI∈[1,3]: The channel is slightly to moderately degraded, and the number of error correction iterations needs to be increased appropriately; CI∈[3,5]: The channel is severely degraded, requiring the number of error correction iterations to be maximized and the voltage frequency to be reduced.

[0038] The cumulative program erase count (PE_Cycle) and the cumulative program / erase count (P / E_Cycle) have the same meaning, and the maximum tolerable program erase count (PE_Max) and the maximum tolerable program / erase count (P / E_Max) have the same meaning. In this embodiment, to avoid the conflict between the " / " in "P / E_Cycle" or "P / E_Max" and the division sign ( / ) in the formula, the " / " in "P / E_Cycle" or "P / E_Max" is omitted.

[0039] TI represents the thermal risk index, δ represents the preset weight of the previous thermal risk index item, TI_prev represents the previous thermal risk index, the initial value of TI_prev is 0, ε represents the preset weight of the junction temperature change rate item, and ΔTj represents the junction temperature change rate; where δ and ε can be weights that can be preset by the user according to the actual situation, and the sum of δ and ε can be 1.

[0040] The TI value typically ranges from [0,3], with higher values ​​indicating a higher thermal risk. TI∈[0,1]: Low thermal risk, can maintain rated voltage frequency; TI∈[1,2]: Moderate thermal risk, voltage frequency needs to be appropriately reduced; TI∈[2,3]: High thermal risk, requiring a significant reduction in voltage frequency and a reduction in the number of error correction iterations (to reduce power consumption and heat generation).

[0041] For example: Assume: α=0.7, β=0.2, γ=0.1, δ=0.8, ε=0.2; PE_Max=5000 times, PE_Cycle=2000 times; T_nom=25℃, ΔT=40℃; TI_prev=0.5; sampling interval Δt=10ms; RBER=10 -4 Tj = 45℃ (i.e., the current sample Tj = 45℃), and the previous sample Tj = 44.92℃.

[0042] log10(RBER) = log10(10 -4 ) = -4; PE_Cycle / PE_Max=2000 / 5000=0.4; (Tj-T_nom) / ΔT=(45-25) / 40=20 / 40=0.5; CI = 0.7 × (-4) + 0.2 × 0.4 + 0.1 × 0.5 = -2.8 + 0.08 + 0.05 = -2.67; CI = -2.67 (absolute value 2.67), which belongs to the mild to moderate channel degradation.

[0043] ΔTj = (current sample Tj - previous sample Tj) / Δt = (45 - 44.92) / 10 = 0.08 / 10 = 0.008; TI = 0.8 × 0.5 + 0.2 × 0.008 = 0.4 + 0.0016 = 0.4016; TI = 0.4016, which indicates low thermal risk.

[0044] In some embodiments, the aforementioned construction of the joint optimization objective function based on the channel degradation index and the thermal risk index includes: J=w1×Imax+λ1×P_fail(CI,Imax)+w2×(1 / VF)+λ2×g(TI,VF); Where J represents the joint optimization objective function, w1 represents the preset weight of the target error correction code iteration number term, Imax represents the target error correction code iteration number, λ1 represents the preset weight of the decoding failure penalty term, and P_fail(CI,Imax) represents the decoding failure penalty function.

[0045] w2 represents the preset weight of the voltage frequency adjustment parameter, VF represents the voltage frequency adjustment parameter, λ2 represents the preset weight of the thermal risk penalty term, and g(TI,VF) represents the thermal risk penalty function.

[0046] In this embodiment, when constructing the joint optimization objective function based on the channel degradation index and the thermal risk index in step S130, the construction of the joint optimization objective function based on the channel degradation index and the thermal risk index includes: J=w1×Imax+λ1×P_fail(CI,Imax)+w2×(1 / VF)+λ2×g(TI,VF); Where J represents the joint optimization objective function, w1 represents the preset weight of the target error correction code iteration number term, Imax represents the target error correction code iteration number, λ1 represents the preset weight of the decoding failure penalty term, and P_fail(CI,Imax) represents the decoding failure penalty function. w2 represents the preset weight of the voltage frequency adjustment parameter, VF represents the voltage frequency adjustment parameter, λ2 represents the preset weight of the thermal risk penalty term, and g(TI,VF) represents the thermal risk penalty function.

[0047] For example: J represents the joint optimization objective function, with the optimization objective being to minimize J to achieve synergistic optimality of decoding reliability, performance, and thermal safety. w1 represents the preset weight of the target error correction code iteration number term, which can be set by the user according to actual conditions; w1 can be a constant with a value greater than 0. Imax represents the target error correction code iteration number, which is a positive integer. λ1 represents the preset weight of the decoding failure penalty term, which can be set by the user according to actual conditions; λ1 can be a constant with a value greater than 0. P_fail(CI,Imax) represents the decoding failure penalty function, whose function value is positively correlated with the channel degradation index CI and negatively correlated with the target error correction code iteration number Imax. w2 represents the preset weight of the voltage and frequency adjustment parameter term, which can be set by the user according to actual conditions; w2 can be a constant with a value greater than 0. VF represents the voltage and frequency adjustment parameter, a real number ranging from 0.5 to 1.0; VF=1.0 indicates operation at the rated voltage and frequency. λ2 represents the preset weight of the thermal risk penalty term, which can be set by the user according to actual conditions; λ2 can be a constant with a value greater than 0. g(TI,VF) represents the thermal risk penalty function, whose function value is positively correlated with the thermal risk index TI and the voltage frequency adjustment parameter VF.

[0048] In some embodiments, the aforementioned number of iterations for calculating the joint optimization objective function using a preset optimization algorithm to obtain the target error correction code includes: The preset optimization algorithm is invoked to minimize the joint optimization objective function, thereby obtaining the number of iterations of the target error correction code and the voltage frequency adjustment parameters.

[0049] In this embodiment, when the preset optimization algorithm is invoked in step S130 to calculate the joint optimization objective function and obtain the target error correction code iteration count, the target error correction code iteration count and voltage frequency adjustment parameters can be obtained. The controller invokes the preset optimization algorithm to minimize the joint optimization objective function, thereby obtaining the target error correction code iteration count and voltage frequency adjustment parameters. The preset optimization algorithm can be a user-preset configuration in the controller. For example, the preset optimization algorithm may include gradient descent, particle swarm optimization, genetic algorithm, or dynamic programming, etc., algorithms capable of multivariate constraint optimization.

[0050] For example, the controller can invoke a preset optimization algorithm to minimize the joint optimization objective function. The goal is to find a set of (Imax, VF) that minimizes the value of the joint optimization objective function J. During the optimization process, different combinations of Imax and VF are traversed or iteratively searched, the value of J corresponding to each set of variables is calculated, and the solution is gradually converged to the optimal solution. The solution that minimizes the value of J is determined as the optimal parameters; that is, the optimal Imax is the number of iterations for the target error correction code, and the optimal VF is the voltage frequency adjustment parameter.

[0051] Among them, when the channel degradation index CI is high, the preset optimization algorithm tends to increase Imax to reduce the probability of decoding failure; When the thermal risk index TI is high, the preset optimization algorithm tends to reduce VF to reduce heat generation and power consumption. When both the channel degradation index (CI) and the thermal risk index (TI) are normal, the preset optimization algorithm tends to maintain a smaller Imax and a higher VF to ensure read performance.

[0052] For example, the controller can be configured with a mapping table corresponding to the joint optimization objective function. Assume the initial parameters are: α=0.8, β=0.2, γ=0.1, P / E_Max=3000, T_nom=85°C, ΔT=40°C, w1=1.0, w2=0.5, λ1 initial=5.0, λ2 initial=2.0. The current read request targets a target physical page within a target physical block. The controller collects the following data: RBER of the target physical page=1e-3, P / E_Cycle of the target physical block=2000 cycles, chip junction temperature Tj=95°C, and temperature change rate ΔTj=dT / dt=0.5°C / ms. Through calculation: log10(1e-3)=-3; PE_Cycle / PE_Max=2000 / 3000=0.667; (Tj-T_nom) / ΔT=(95-85) / 40=0.25. Substituting into the preset joint quantization algorithm: CI = 0.8 × (-3) + 0.2 × 0.667 + 0.1 × 0.25 = -2.4 + 0.1334 + 0.025 = -2.2416. The thermal risk index TI is obtained by looking up the mapping table based on Tj and dT / dt, resulting in TI = 0.7 (high). Then, P_fail(CI, Imax) is obtained by looking up the mapping table: for CI = -2.24, P_fail = 0.01 when Imax = 10, and P_fail = 0.001 when Imax = 15. g(TI, VF) is calculated: for TI = 0.7, g = 0.7 × exp(-2.0) = 0.095 when VF = 0.8 (lower frequency), g = 0.7 × exp(-1.6) = 0.141. The joint optimization objective function J(Imax=10,VF=1.0)=1.0×10+0.5×(1 / 1.0)+5.0×0.01+2.0×0.095=10+0.5+0.05+0.19=10.74; J(Imax=15, VF=0.8) = 15 + 0.5 / 0.8 + 5.0 × 0.001 + 2.0 × 0.141 = 15 + 0.625 + 0.005 + 0.282 = 15.912. After enumerating other combinations, we find that J(Imax=12, VF=0.9) = 12 + 0.556 + 5.0 × 0.005 + 2.0 × 0.7 × exp(-1.8) = 12 + 0.556 + 0.025 + 0.212 = 12.793, which is the minimum value. Therefore, the output is: optimal Imax = 12, optimal VF = 0.9. At this point, the target error correction code iteration count is 12, and the voltage frequency adjustment parameter is 0.9.

[0053] Reference Figure 3 , Figure 3 This is a flowchart illustrating another embodiment of the dynamic error correction method for flash memory in this application. In some embodiments, the aforementioned adjustment of the number of iterations for error correction decoding during the reading operation of target data based on the number of iterations of the target error correction code includes: Step S160: Adjust the number of iterations for error correction decoding when reading target data based on the number of iterations for the target error correction code; Step S161: Based on the voltage and frequency adjustment parameters, adjust the operating voltage and operating frequency when reading the target data.

[0054] In this embodiment, as Figure 3 As shown, during step S140, the number of iterations, operating voltage, and operating frequency of the error correction decoding can be adjusted. The controller can adjust the number of iterations of the error correction decoding when reading target data based on the target error correction code iteration count. For example, the controller may also include an error correction decoding module; the controller can configure the upper limit of the iteration count of the error correction decoding module according to the target error correction code iteration count. For instance, if Imax is greater than the current default iteration count (e.g., default 10 times), the upper limit of the iteration count is updated to Imax, allowing iteration to Imax during decoding to improve error correction capability; if Imax is less than the current default iteration count, the upper limit of the iteration count is reduced, and iteration stops immediately after Imax is reached during decoding to reduce decoding latency. By configuring the upper limit of the iteration count of the error correction decoding module according to the target error correction code iteration count, the controller enables the error correction decoding module to perform error correction decoding iterations on the target data using the target error correction code iteration count.

[0055] The controller can also adjust the operating voltage and frequency when reading target data based on voltage-frequency adjustment parameters (VF). For example, the controller may also include a power management unit and a clock management unit. The controller may also have a pre-configured VF-voltage-frequency mapping table; the controller can query the VF-voltage-frequency mapping table through the voltage-frequency adjustment parameters to determine the operating voltage and frequency. The controller can control the power management unit to smoothly adjust the initial operating voltage to the operating voltage, and then control the clock management unit to adjust the clock frequency to the operating frequency through a phase-locked loop.

[0056] Reference Figure 4 , Figure 4 This is a flowchart illustrating another embodiment of the dynamic error correction method for flash memory in this application. In some embodiments, the aforementioned acquisition of the raw bit error rate of the target physical page includes: Step S170: Obtain the raw bit error rate of the target physical page; Step S171: Call the preset adjacent page interference cancellation algorithm to correct the original bit error rate and obtain the corrected original bit error rate.

[0057] In this embodiment, as Figure 4 As shown, when executing step S150, the raw bit error rate of the target physical page can be obtained first. The controller can obtain the raw bit error rate of the target physical page. For example, when reading target data in the target physical page, the controller can collect the raw output signal of the target physical page; then compare the collected raw output signal with the reference signal when the target data is written bit by bit, and count the number of bit errors (number of erroneous bits); then calculate the raw bit error rate according to the raw bit error rate calculation formula (raw bit error rate = number of erroneous bits / total number of bits in the target physical page). The raw bit error rate is in the range of [0,1]. The larger the value, the more serious the charge leakage and level offset of the storage unit of the target physical page, the higher the degree of channel degradation, and the more iterations are required for subsequent error correction and decoding.

[0058] After obtaining the raw bit error rate (BER), a preset adjacent page interference cancellation algorithm can be called to correct the BER, resulting in a corrected raw BER. For example, the controller can be pre-configured with a preset adjacent page interference cancellation algorithm. The preset adjacent page interference cancellation algorithm could be: Iinter = (k × Nprog) / D; Wherein, Iinter represents the interference intensity between adjacent pages, k represents the interference coefficient (calibrated by the manufacturer), Nprog represents the cumulative number of programming operations between adjacent pages, and D represents the physical distance (the physical distance between the target physical page and adjacent pages).

[0059] The controller first obtains the status information of adjacent pages, including the cumulative number of programming attempts and the physical distance between them. Then, it substitutes these values ​​into a preset adjacent page interference cancellation algorithm to calculate the adjacent page interference intensity. Next, it uses the adjacent page interference intensity to find a preset curve mapping to obtain the additional bit error rate caused by the interference. Finally, by subtracting the additional bit error rate caused by the interference from the original bit error rate, the corrected original bit error rate can be obtained.

[0060] The preset curve mapping can be determined by the manufacturer through pre-shipment testing and configured in the controller. For example, Iinter=0.3 corresponds to an additional bit error rate of 0.00003 caused by interference. Furthermore, if the corrected original bit error rate is less than 0, it is set to 0 (the bit error rate cannot be negative); if the corrected original bit error rate is greater than the original bit error rate, the original bit error rate is retained (to avoid anomalies caused by algorithm errors), ensuring the reasonableness of the correction result.

[0061] Reference Figure 5 , Figure 5 This is a flowchart illustrating another embodiment of the dynamic error correction method for flash memory in this application. In some embodiments, after adjusting the number of iterations for error correction decoding during the read operation of target data based on the number of iterations of the target error correction code, the method further includes: Step S180: Collect the actual decoding success rate and status data of the error correction decoding; Step S181: Optimize the parameters in the preset joint quantization algorithm and joint optimization objective function based on the actual decoding success rate and status data.

[0062] In this embodiment, as Figure 5 As shown, after executing step S140, the actual decoding success rate and status data of error correction decoding can also be collected. The controller can collect the actual decoding success rate and status data of error correction decoding. For example, the controller performs statistics on the decoding results of N consecutive read operations of the target physical page (e.g., N=100 times, which can be configured by the user according to the actual situation): counts the number of successful decodings (satisfying check code verification and data correctness) and the total number of reads; calculates the actual decoding success rate according to the formula: actual decoding success rate = number of successful decodings / total number of reads, with a value range of [0,1]; and records the decoding failure scenarios (e.g., failure rate when channel degradation is high or thermal risk is high), providing a scenario-based basis for parameter optimization. The status data of the corresponding read operation is obtained synchronously with the decoding success rate collection.

[0063] After obtaining the actual decoding success rate and status data, the parameters in the preset joint quantization algorithm and joint optimization objective function can be optimized based on these data. For example, the controller can optimize α, β, γ, δ, and ε in the preset joint quantization algorithm based on the actual decoding success rate and status data, enabling the channel degradation index and thermal risk index to more accurately reflect the actual channel and thermal state. The controller can also optimize w1, λ1, w2, and λ2 in the joint optimization objective function based on the actual decoding success rate and status data, making the value of the joint optimization objective function more closely match the priority of the current operating condition.

[0064] For example, optimization of α: If the actual decoding success rate is lower than the preset threshold (e.g., <99%) and CI is low, then increase α to improve the contribution of RBER to CI, so that CI can more accurately reflect channel degradation; if the actual decoding success rate is normal, but CI is consistently high, then decrease α to avoid performance loss caused by excessive error correction.

[0065] Optimization of β: If the physical block is severely aged (PE_Cycle / PE_Max>0.7) and the actual decoding success rate decreases, increase β to enhance the impact of aging factors on CI and provide early warning of channel degradation; if the physical block is relatively new (PE_Cycle / PE_Max<0.3) and CI is high, decrease β to reduce the excessive impact of aging factors.

[0066] Optimization of γ: If the actual decoding success rate decreases under high temperature conditions (Tj-T_nom>ΔT / 2), then increase γ to enhance the impact of temperature factors on CI and adapt to the increased bit error rate under high temperature conditions; if CI is too high under normal temperature conditions, then decrease γ to avoid excessive interference from temperature factors.

[0067] Optimization of δ and ε: If TI fails to provide timely warnings when thermal risks suddenly occur (ΔTj rises sharply), increase ε to improve the response speed to real-time temperature changes; if frequent temperature fluctuations cause TI oscillations, increase δ to enhance the smoothing effect of historical thermal risks and avoid false triggering of frequency reduction.

[0068] Optimization of w1 and λ1: If the actual decoding success rate is lower than the threshold, increase λ1 and decrease w1: increase the priority of the penalty for decoding failure, drive the algorithm to increase Imax, and prioritize reliability; if the actual decoding success rate is consistently 100%, decrease λ1 and increase w1: reduce the penalty for decoding failure, drive the algorithm to reduce Imax, and improve reading performance.

[0069] Optimization of w2 and λ2: If the thermal risk remains high (TI>2) and the chip junction temperature exceeds the limit, increase λ2 and decrease w2 to improve the priority of thermal risk penalty, drive the algorithm to reduce VF, and prioritize thermal safety; if the thermal risk remains low (TI<0.5), decrease λ2 and increase w2 to reduce the thermal risk penalty, drive the algorithm to maintain a high VF, and improve performance.

[0070] The technical solution of this application obtains the target error correction code iteration number by processing the state data of flash memory, so that a suitable target error correction code iteration number can be obtained when the channel conditions are good or when the channel conditions deteriorate sharply, thereby improving the adaptability of the target error correction code iteration number.

[0071] This application further proposes a dynamic error correction system for flash memory, referring to... Figure 6 , Figure 6 This is a schematic diagram of the structure of an embodiment of the dynamic error correction system for flash memory in this application. In some embodiments, the dynamic error correction system for flash memory includes a controller and flash memory. The controller is configured inside the flash memory. The flash memory includes one or more flash memory chips. The flash memory chips include multiple physical blocks. The physical blocks include multiple physical pages. The controller is capable of executing the dynamic error correction method for flash memory described above.

[0072] In this embodiment, as Figure 6 As shown, the dynamic error correction system for flash memory includes a controller and flash memory. The controller can be configured inside the flash memory, which includes one or more flash memory chips, each flash memory chip comprising multiple physical blocks, and each physical block comprising multiple physical pages. Figure 6 The illustration shows only one flash memory chip and does not constitute a limitation on the number of flash memory chips.

[0073] This application further proposes a dynamic error correction device for flash memory, referring to... Figure 7 , Figure 7 This is a schematic diagram of the structure of one embodiment of the dynamic error correction device for flash memory according to this application. In some embodiments, the dynamic error correction device for flash memory includes: At least one processor; and, A memory that is communicatively connected to at least one processor; wherein, The memory stores instructions that are executed by the at least one processor to enable the at least one processor to perform the dynamic error correction method of the flash memory described in any of the above descriptions.

[0074] In this embodiment, refer to Figure 7 The dynamic error correction device for flash memory in this application embodiment can be a processor capable of running a dynamic error correction method for flash memory; there is at least one processor. For example... Figure 7As shown, the dynamic error correction device for the flash memory may include: a processor 1001 (e.g., CPU), a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. The communication bus 1002 is used to establish communication between these components. The user interface 1003 may include a display screen or an input unit, such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be high-speed RAM or non-volatile memory, such as a disk drive. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0075] Those skilled in the art will understand that Figure 7 The structure of the dynamic error correction device for flash memory shown does not constitute a limitation on the dynamic error correction device for flash memory. It may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0076] like Figure 7 As shown, the memory 1005, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and computer programs.

[0077] exist Figure 7 In the flash memory dynamic error correction device shown, the network interface 1004 is mainly used to connect to the backend server and communicate data with the backend server; the user interface 1003 is mainly used to connect to the client (user end) and communicate data with the client; and the processor 1001 can be used to call the computer program stored in the memory 1005. When the computer program is called and executed by the processor 1001, it implements the steps of the above-mentioned flash memory dynamic error correction method.

[0078] The above description is only a part or preferred embodiment of this application. Neither the text nor the drawings should limit the scope of protection of this application. All equivalent structural transformations made using the content of this application's specification and drawings under the overall concept of this application, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application.

Claims

1. A dynamic error correction method for flash memory, characterized in that, include: Acquire the status data of the flash memory, wherein the status data is the status data of the flash memory when reading target data in the flash memory; The channel degradation index and thermal risk index are obtained by calling a preset joint quantization algorithm to calculate and process the state data. A joint optimization objective function is constructed based on the channel degradation index and the thermal risk index, and a preset optimization algorithm is called to calculate and process the joint optimization objective function to obtain the number of iterations of the target error correction code; Based on the number of iterations of the target error correction code, the number of iterations of error correction decoding is adjusted when reading the target data.

2. The dynamic error correction method for flash memory according to claim 1, characterized in that, The flash memory includes one or more flash memory chips, each flash memory chip includes multiple physical blocks, and each physical block includes multiple physical pages; acquiring the flash memory status data includes: Obtain the raw bit error rate of the target physical page, where the target physical page is the physical page storing the target data; Obtain the cumulative number of program erases and the maximum number of program erases tolerable for the target physical block, wherein the target physical block is the physical block containing the target physical page; The junction temperature, rated temperature, rated temperature variation range, and junction temperature variation rate of the target flash memory chip are obtained, wherein the target flash memory chip is a flash memory chip containing the target physical block.

3. The dynamic error correction method for flash memory according to claim 2, characterized in that, The process of calculating and processing the state data using a preset joint quantization algorithm to obtain the channel degradation index and thermal risk index includes: CI=α×log10(RBER)+β×(PE_Cycle / PE_Max)+γ×(Tj-T_nom) / ΔT; TI = δ × TI_prev + ε × ΔTj; Where CI represents the channel degradation index, α represents the preset weight of the original bit error rate term, RBER represents the original bit error rate, β represents the preset weight of the cumulative programming and erasure times term, PE_Cycle represents the cumulative programming and erasure times, PE_Max represents the maximum tolerable programming and erasure times, γ represents the preset weight of the chip junction temperature term, Tj represents the chip junction temperature, T_nom represents the rated temperature, and ΔT represents the rated temperature variation range. TI represents the thermal risk index, δ represents the preset weight of the previous thermal risk index term, TI_prev represents the previous thermal risk index, the initial value of TI_prev is 0, ε represents the preset weight of the junction temperature change rate term, and ΔTj represents the junction temperature change rate.

4. The dynamic error correction method for flash memory according to claim 3, characterized in that, The step of constructing a joint optimization objective function based on the channel degradation index and the thermal risk index includes: J=w1×Imax+λ1×P_fail(CI,Imax)+w2×(1 / VF)+λ2×g(TI,VF); Where J represents the joint optimization objective function, w1 represents the preset weight of the target error correction code iteration number term, Imax represents the target error correction code iteration number, λ1 represents the preset weight of the decoding failure penalty term, and P_fail(CI,Imax) represents the decoding failure penalty function. w2 represents the preset weight of the voltage frequency adjustment parameter, VF represents the voltage frequency adjustment parameter, λ2 represents the preset weight of the thermal risk penalty term, and g(TI,VF) represents the thermal risk penalty function.

5. The dynamic error correction method for flash memory according to claim 4, characterized in that, The number of iterations for calculating the target error correction code by calling a preset optimization algorithm to process the joint optimization objective function includes: The preset optimization algorithm is invoked to minimize the joint optimization objective function, thereby obtaining the number of iterations of the target error correction code and the voltage frequency adjustment parameters.

6. The dynamic error correction method for flash memory according to claim 5, characterized in that, The step of adjusting the number of iterations for error correction decoding when reading the target data based on the number of iterations for the target error correction code includes: Based on the number of iterations of the target error correction code, adjust the number of iterations of error correction decoding when reading the target data; Based on the voltage and frequency adjustment parameters, the operating voltage and frequency are adjusted when reading the target data.

7. The dynamic error correction method for flash memory according to claim 2, characterized in that, The process of obtaining the raw bit error rate of the target physical page includes: Obtain the raw bit error rate of the target physical page; The original bit error rate is corrected by calling a preset adjacent page interference cancellation algorithm to obtain the corrected original bit error rate.

8. The dynamic error correction method for flash memory according to any one of claims 1-7, characterized in that, After adjusting the number of iterations for error correction decoding when reading the target data based on the number of iterations of the target error correction code, the method further includes: Collect the actual decoding success rate of the error correction decoding and the status data; The parameters in the preset joint quantization algorithm and the joint optimization objective function are optimized based on the actual decoding success rate and the state data.

9. A dynamic error correction system for flash memory, characterized in that, The dynamic error correction system of the flash memory includes a controller and a flash memory, the controller being configured inside the flash memory, the flash memory including one or more flash memory chips, the flash memory chips including multiple physical blocks, the physical blocks including multiple physical pages; the controller is capable of executing the dynamic error correction method of the flash memory according to any one of claims 1 to 8.

10. A dynamic error correction device for flash memory, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that are executed by the at least one processor to enable the at least one processor to perform the dynamic error correction method of the flash memory according to any one of claims 1 to 8.

Images