Global autonomous thyristor-based computing power bottom-layer full-stack architecture

Abstract

The application discloses a full-domain autonomous thyristor-based computing power bottom-layer full-stack architecture, and belongs to the technical field of integrated circuit bottom-layer architecture and non-Von Neumann computing power hardware. The application integrates nine-domain quantitative fixed partition, dynamic hexagonal honeycomb elastic partition, three-order nine-grid mathematical quantitative base, triangular / regular hexagonal / triangular-pentagonal composite fractal spiral topology, benchmark single wire and heterogeneous double-track transmission, hardware closed-loop timing, global symmetry balance scheduling, single / multi-chip homologous expansion, quantum-photon-classical heterogeneous integration, and double-track independent closed-loop operation, to form a complete technical system with unified structure, scheduling and layout. The architecture discards the defects of traditional buses, realizes hardware-level working condition shunting, timing closed loop, load balancing, fault self-recovery and mode automatic switching, is compatible with mature silicon-based technology, three-dimensional S packaging and optical interconnection on chip, can realize significant improvement of computing power and energy efficiency under 14 / 28 processes, has full-scene adaptation, full-ecological compatibility, strong anti-avoidance and low-cost mass production characteristics, and is suitable for edge terminals, desktop computing, vehicle-mounted industrial control, cloud clusters and hybrid computing scenarios, and provides an autonomous and controllable bottom-layer complete solution for general computing power.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit underlying topology design, chip core architecture, multi-chip cluster interconnection, high-speed PCB integrated wiring, three-dimensional system-level packaging, embedded hardware and software collaborative scheduling, silicon-based quantum computing and silicon-based photonic waveguide heterogeneous integration, and non-von Neumann general computing power architecture. Specifically, it is a computing power underlying full-stack architecture that combines fixed quantization partitioning, dynamic elastic partitioning, composite fractal spiral topology, dual-track signal transmission, hardware closed-loop timing, global balanced scheduling, multi-chip homogeneous expansion, and multi-type computing power fusion. Background Technology

[0002] Traditional von Neumann two-dimensional planar bus computing architecture has many inherent defects, including a messy overall layout, disordered wiring, large data transmission redundancy, prominent electromagnetic interference and crosstalk problems, timing control that relies entirely on software scheduling, low hardware resource utilization, obvious drawbacks of storage-computing separation, poor software and hardware compatibility, weak device expansion capabilities, and inability to support the collaborative operation of multiple heterogeneous computing powers.

[0003] Currently, most of the improved architectures on the market only make partial optimizations, with a fixed overall architecture pattern, a single operation and scheduling method, and mass production applications that rely on high-end precision manufacturing processes. The overall usage cost is relatively high, and the scope of ecosystem adaptation is narrow. At the same time, existing similar structures are easily imitated by simply changing parameters and replacing the external structure, making it impossible to form a stable and complete underlying technical protection system and failing to meet the needs of autonomy, high reliability, low cost, and use in all scenarios.

[0004] Based on the shortcomings of the existing technologies, this invention proposes a novel underlying computing architecture solution. Summary of the Invention

[0005] Purpose of the invention The purpose of this invention is to overcome the various defects of existing traditional computing architectures, build a fully autonomous, all-scenario adaptable, and universal silicon-based computing power underlying hardware foundation, achieve a combination of fixed layout and dynamic adjustment, high-performance operation and low-power operation, and high-stability use and low-cost mass production, open up the adaptation channels between hardware architecture and various software systems, realize the integrated collaborative operation of conventional computing power, quantum computing power and photonic computing power, and create a new type of universal computing power underlying structure that cannot be easily imitated or circumvented and can be mass-produced on a large scale. Technical solution

[0006] The invention is composed of three integrated architectures with a unified design concept, matching technical parameters, and an overall structure that cannot be separated for independent use.

[0007] The first part is a nine-domain quantized partitioning system combined with a triangular fractal spiral basic architecture. It employs a nine-grid fixed area division method to complete the hardware area deployment, dividing the system into multiple independent functional areas. Each area has a clearly defined function and is physically isolated from the others, with dedicated electronic components deployed in separate areas. A central reference transmission line is set up in conjunction with a layered dual-track signal transmission line to distinguish between high-frequency computation data streams and low-speed storage return signals, achieving signal splitting at the hardware level. An equilateral triangular fractal spiral structure is used as the main signal transmission path, unifying the internal transmission structure parameters of chips, circuit boards, and packaging substrates. A multi-stage fixed hardware timing operation process is set up to unify the timing standards for various computing power operations. It supports independent use of a single chip and expansion using multiple chips in combination, employing a three-dimensional interconnection structure to replace traditional connection methods and reduce parasitic parameters on the lines. It is also equipped with dedicated low-level drivers and hardware adaptation interfaces to meet the needs of various new computing power access methods.

[0008] The second part is a hexagonal honeycomb dynamic elastic adaptability architecture, which uses a regular hexagonal grid structure to form flexibly adjustable computing power areas. It supports the free merging, splitting, and increasing / decreasing of computing power areas, and each adjustable area independently completes power consumption control, heat dissipation adjustment, and fault isolation. It is combined with hexagonal spiral trunk lines and diamond branch lines to form an overall transmission network, which can autonomously select transmission paths and has the ability to autonomously adapt to line faults. It has set up multiple load operation adjustment modes, which automatically adjust the operating frequency, computing power output, and signal transmission path according to the real-time operating status of the hardware. It adds a redundant transmission time slot structure to realize autonomous correction of data errors and rapid switching of line faults, effectively reducing the overall hardware manufacturing cost. At the same time, it integrates practical adaptation structures such as dynamic voltage adjustment, high-speed on-chip interconnection, and large-scale chip expansion.

[0009] The third part is a three-tier, nine-grid architecture with dual-track symmetrical countermeasures. It uses a three-tier matrix structure as the overall area division benchmark, unifying and solidifying core physical parameters such as overall topology line angles, line spacing, and transmission bandwidth. Internally, it sets up two completely independent operating systems: a lightweight, low-power operating mode and a parallel, countermeasured, high-performance operating mode. The power supply and clock lines of the two operating structures are completely separated and do not share resources. The operating mode can be automatically switched based on the device's real-time computing load and power consumption. It features a global balanced intelligent scheduling structure, which uniformly allocates overall computing resources, prioritizes tasks, optimizes signal transmission paths, and simultaneously balances power consumption and heat dissipation. It also features a multi-layered timing control structure and a hardware self-testing mechanism, providing global fault diagnosis and autonomous fault-tolerant operation capabilities. The entire system reserves standardized universal external interfaces, allowing direct adaptation to mainstream operating systems and various embedded control systems, and enabling direct hardware replacement and upgrades of existing computing devices. Beneficial effects

[0010] 1. The overall structure of this invention is well-designed, and the core operating mechanism, line topology, and hardware scheduling logic are all unified and solidified. It is impossible to bypass the core design of this structure by simply adjusting the external dimensions or changing the line angle, thus possessing extremely strong technical protection and anti-counterfeiting effects.

[0011] 2. It has a wide range of application scenarios and can simultaneously meet various usage requirements such as stable operation in fixed layout, dynamic and flexible operation, and high and low performance mode switching. It is compatible with small terminal devices, general computing devices, industrial vehicle-mounted devices, large cloud cluster devices, and hybrid computing devices.

[0012] 3. The entire system does not rely on high-end precision manufacturing processes. Mass production can be completed using conventional and mature production processes. Under conventional process conditions, it can effectively improve the overall computing power of the equipment, reduce the power consumption of the equipment, reduce data transmission latency, and effectively control the overall operating temperature of the equipment.

[0013] 4. The hardware structure integrates practical features such as independent heat dissipation, electromagnetic isolation, and autonomous fault switching, which greatly improves the stability of equipment operation and significantly reduces the overall mass production cost.

[0014] 5. The overall hardware structure is compatible with mainstream semiconductor manufacturing processes, 3D integrated packaging processes, and various new computing power access methods. It has strong industry chain adaptability and can be put into production quickly without the need to re-customize the manufacturing process.

[0015] 6. The overall external interface is universal, requiring no modification to the upper-layer application software and operating system. It can directly upgrade and replace the underlying hardware of old devices, making application deployment convenient and fast.

Claims

1. A fully autonomous and controllable silicon-based computing power underlying full-stack architecture, characterized in that, The architecture includes a nine-domain quantized fixed partitioning system, a dynamic hexagonal honeycomb elastic partitioning system, a third-order nine-grid mathematical quantization system, a triangular / regular hexagonal / triangular-pentagonal composite fractal spiral topology system, a baseline single-line and heterogeneous dual-track transmission system, a hardware closed-loop timing system, a global symmetric balancing scheduling system, a single-multi-chip expansion system, a quantum-photonics-classical heterogeneous integration system, and a dual-track independent closed-loop operation system. The architecture simultaneously supports fixed standard partitioning and dynamic elastic partitioning, employing a multi-level fractal spiral as the sole transmission path across the entire domain, achieving hardware-level load balancing, timing closed-loop, load balancing, fault self-healing, and symmetric balancing scheduling. It natively integrates two independent operating systems: single-track lightweight and dual-track parallel balancing, and supports automatic switching. It is compatible with full-node silicon-based processes, 3D S-package, on-chip optical interconnects, and silicon-based quantum computing power integration. It can improve computing power and energy efficiency without customizing high-end processes, and has the ability to adapt to all scenarios, be compatible with all ecosystems, and protect against circumvention.

2. A computing power scheduling method based on the architecture described in claim 1, characterized in that, Physical isolation and elastic scaling of computing power domains are achieved by combining fixed and dynamic partitioning; optimal path transmission is completed by fractal spiral topology; global computing power allocation, power consumption control, fault isolation and automatic dual-track switching are completed by adopting hardware closed-loop timing and symmetric balance model; and intelligent switching between single and dual tracks is achieved based on load and power consumption thresholds to ensure high reliability, low latency and high energy efficiency operation.

3. A hardware deployment method based on the architecture described in claim 1, characterized in that, The chip, PCB, and packaging substrate adopt the same topology and quantization parameters; vertical layered dual-track wiring, irregular topology wiring, dual voltage domain physical isolation, nine-domain independent heat dissipation and E anti-interference structure are adopted; and high-density, low parasitic and high-integration hardware is realized by replacing traditional bonding and T structure with spiral interconnect.

4. The fully autonomous and controllable silicon-based computing power underlying full-stack architecture according to claim 1, characterized in that: The three-order nine-grid mathematical quantization system uses a 3×3 fixed matrix as the basis for global computing power partitioning, and solidifies the geometric topology angle, pitch, and bandwidth ratio quantization parameters across the entire domain. Any equivalent substitution for approximate angle or size fine-tuning falls within the protection scope of this invention.

5. The fully autonomous and controllable silicon-based computing power underlying full-stack architecture according to claim 1, characterized in that: The dual-track independent closed-loop operation system includes a single-track lightweight mode with complete physical isolation and no shared power supply and clock, and a dual-track parallel balancing mode. When the overall computing power load is ≥70% or the instantaneous power consumption is ≥25, the mode switching is automatically triggered, and the system automatically recovers after the load falls back to the threshold.

6. The fully autonomous and controllable silicon-based computing power underlying full-stack architecture according to claim 1, characterized in that: The composite fractal spiral topology includes a 60° equilateral triangular spiral trunk, a 108° regular pentagonal convergence node, and a 120° regular hexagonal spiral branch. The global impedance difference is ≤2Ω, and it supports automatic switching to a backup branch path to achieve self-healing compensation in case of link failure.

7. The fully autonomous and controllable silicon-based computing power underlying full-stack architecture according to claim 1, characterized in that: The hardware closed-loop timing system adopts a five-stage fixed-phase timing scheduling with a fixed phase difference of 72°, which is suitable for cross-domain timing synchronization of classical computing power, silicon-based quantum computing power, and silicon-based photonic computing power.

8. The hardware deployment method according to claim 3, characterized in that: The nine-domain independent heat dissipation and E-anti-interference structure enable independent temperature control and electromagnetic physical isolation for each computing domain, making it suitable for extreme industrial and automotive environments with a wide temperature range of -40℃ to +85℃.

9. The fully autonomous and controllable silicon-based computing power underlying full-stack architecture according to claim 1, characterized in that: The single-to-multi-chip expansion system supports seamless expansion of 2 to 256 chips from the same source and three-dimensional spiral stacking S-package, which can complete the expansion of computing power clusters without redesigning the topology.

10. The architecture, scheduling method, and hardware deployment method according to any one of claims 1-9, characterized in that: The overall architecture is compatible with all mainstream operating systems, including Windows, Linux, Android, and HarmonyOS, and can complete the low-cost upgrade and replacement of existing computing power devices without the need for upper-layer software modifications.