A 3D chip-based cache data scheduling method and device and storage medium

Abstract

The application discloses a cache data scheduling method and device based on a 3D chip and a storage medium, the cache data scheduling method based on the 3D chip comprises a CPU core layer, a storage layer and a TSV array connecting the CPU core layer and the storage layer; the method comprises the following steps: acquiring the transmission delay of the TSV array; acquiring the bandwidth occupancy rate of the TSV array; acquiring high-frequency access data of the 3D chip; and scheduling the high-frequency access data according to the transmission delay and the bandwidth occupancy rate. Through real-time acquisition of the transmission delay and the bandwidth occupancy rate of the TSV array, and in combination with the identification result of the high-frequency access data, dynamic scheduling of cache data is realized, and the memory access efficiency of the chip is improved.

Description

Technical Field

[0001] This invention relates to the field of 3D chip technology, and more specifically to a cache data scheduling method, device and storage medium based on 3D chips. Background Technology

[0002] 3D chips are a semiconductor technology that achieves higher integration by vertically stacking multiple chip layers. Unlike traditional two-dimensional planar chips, they break through the physical limitations of planar layouts, stacking and packaging chips with different functions through vertical interconnect technologies (such as TSVs) to form a three-dimensional integrated circuit. Compared to traditional two-dimensional planar chips, 3D chips have faster signal transmission speeds because the short-distance vertical interconnects between chip layers reduce signal delay and increase data throughput.

[0003] In 3D stacked chips employing TSV vertical interconnects, data transmission between the CPU core layer and the memory layer heavily relies on the TSV array. When multiple CPU cores concurrently access the cache, the bandwidth of the TSV array is heavily consumed, leading to bandwidth congestion and increased transmission conflicts.

[0004] In existing technologies, 3D chips mostly use the static scheduling scheme of traditional 2D chips for cached data scheduling. This scheme stores data at fixed levels based solely on the frequency of data access, without considering the real-time transmission status of the TSV channel. When the TSV channel experiences latency or bandwidth congestion, high-frequency access data is still stored in the storage layer that requires cross-TSV access, further increasing the burden on the TSV channel, leading to a significant increase in data access latency and reducing the chip's memory access efficiency. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this application provides a cache data scheduling method, device, and storage medium based on a 3D chip. By acquiring the transmission delay and bandwidth occupancy of the TSV array in real time and combining the identification results of high-frequency access data, dynamic scheduling of cache data is achieved, thereby improving the memory access efficiency of the chip.

[0006] To address the above problems, the present invention provides the following technical solution: In a first aspect, embodiments of this application provide a cache data scheduling method based on a 3D chip. The 3D chip includes a CPU core layer, a storage layer, and a TSV array connecting the CPU core layer and the storage layer. The method includes: Obtain the transmission delay of the TSV array; Obtain the bandwidth utilization of the TSV array; Acquire high-frequency access data from 3D chips; High-frequency access data is scheduled based on transmission delay and bandwidth occupancy.

[0007] In some implementations, obtaining the transmission delay of the TSV array includes: A delay measurement circuit is set at the TSV array entrance. The delay measurement circuit includes a transmitter, a receiver, a counting module, and a processing module. The transmitting end sends a test signal to the TSV array and outputs a start signal to the counting module; The receiving end receives the test signal transmitted via the TSV array and simultaneously outputs a stop signal to the counting module; The counting module determines the original delay count value of the TSV array based on the time difference between the start signal and the stop signal; The processing module obtains the fixed delay parameters inside the chip and determines the actual transmission delay value of the TSV array based on the original delay count value and the fixed delay parameters inside the chip.

[0008] In some implementations, the TSV array includes multiple TSV channels, each of which includes an input and an output.

[0009] In some implementations, the delay measurement circuit also includes an input multiplexer and an output demultiplexer; The transmitting end is connected to the input of each TSV channel via an input multiplexer, and the receiving end is connected to the output of each TSV channel via an output demultiplexer.

[0010] In some implementations, obtaining the bandwidth occupancy of the TSV array includes: A bandwidth monitoring module is installed at the interface of the TSV array. The bandwidth monitoring module is used to collect the data transmission volume of the TSV array. The bandwidth utilization of the TSV array is determined based on the data transmission volume and the preset total bandwidth parameters of the TSV array.

[0011] In some implementations, acquiring high-frequency access data from the 3D chip includes: Acquire access events, which are read or write operations initiated by the CPU core layer on a cache line; Determine the number of times each cache line is accessed based on the access events; Cache lines whose access frequency exceeds a preset threshold are identified as high-frequency cache lines. High-frequency access data includes the physical address of each high-frequency cache line.

[0012] In some implementations, the CPU core layer includes a first cache partition and a second cache partition, and the storage layer includes a third cache partition, wherein the access latency of the first cache partition and the second cache partition is lower than that of the third cache partition, which needs to be accessed across the TSV array.

[0013] In some implementations, if the transmission delay of a TSV channel is lower than a preset first threshold and the bandwidth occupancy is less than a preset second threshold, the high-frequency access data stored in the third cache partition will be migrated to the first cache partition and / or the second cache partition through the TSV channel. If the transmission delay of a TSV channel is higher than the preset third threshold, or the bandwidth occupancy is greater than the preset fourth threshold, the use of the TSV channel for migration will be stopped. Among them, the first threshold is less than the third threshold, the second threshold is less than the fourth threshold, the first threshold and the third threshold form the hysteresis interval of transmission delay, and the second threshold and the fourth threshold form the hysteresis interval of bandwidth occupancy.

[0014] Secondly, embodiments of this application provide an electronic device, the electronic device comprising: At least one processor; and, A memory that is communicatively connected to at least one processor; wherein, The memory stores instructions that can be executed by at least one processor, which enables the at least one processor to perform a cached data scheduling method based on a 3D chip, as described in the first aspect.

[0015] Thirdly, embodiments of this application provide a computer-readable storage medium storing an executable program, which is executed by a processor to implement the cached data scheduling method based on a 3D chip as described in the first aspect.

[0016] This application provides a cache data scheduling method, device, and storage medium based on 3D chips. By combining two parameters, the transmission delay and bandwidth occupancy rate of the TSV channel, the cache data is dynamically scheduled, thereby improving the memory access efficiency of the 3D chip. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating the cache data scheduling method based on a 3D chip provided in an embodiment of this application.

[0018] Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0019] Figure 3 This is a structural block diagram of a computer-readable storage medium provided in an embodiment of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0022] The core adaptable object of the 3D chip-based cache data scheduling method provided in this application embodiment is a 3D general-purpose computing CPU chip or SoC chip whose CPU core layer and cache storage layer are vertically stacked and interconnected through a TSV array. It can also be adapted to all 3D chips that include a computing layer, a storage layer, and a TSV array, with the computing layer and storage layer vertically stacked.

[0023] The cache data scheduling method based on 3D chips provided in this application will be described in detail below with reference to the accompanying drawings.

[0024] The 3D chip provided in this application includes a CPU core layer, a memory layer, and a TSV array connecting the CPU core layer and the memory layer. Communication between the CPU core layer and the memory layer is achieved through the through-silicon via (TSV) array.

[0025] Specifically, the TSV array includes multiple TSV channels, each of which includes an input terminal and an output terminal.

[0026] Optionally, the TSV array includes 512 TSV channels.

[0027] Specifically, the CPU core layer includes a first cache partition L1, a second cache partition L2, and a TSV controller, while the storage layer includes a third cache partition L3. The first cache partition L1, the second cache partition L2, and the third cache partition L3 together constitute a vertically tiered cache pool. The access latency of the first and second cache partitions is lower than that of the third cache partition, which requires cross-TSV array access. When the CPU core layer initiates a data access request, it first searches in the first cache partition L1 and the second cache partition L2; if the data is not found, a cross-layer access request is initiated through the TSV array to the third cache partition L3 located in the storage layer. The latency of cross-layer access is higher than that of intra-layer access.

[0028] The first cache partition L1 is used to provide the CPU core with the lowest latency instruction and data temporary storage. The second cache partition L2 is used to cache batch data to be written or read, and to handle the data interaction between the first cache partition L1 and the third cache partition L3. The TSV controller is used to interact with the first cache partition L1 and the second cache partition L2, and to perform bidirectional data transmission with the third cache partition L3 through the TSV channel. The third cache partition L3 is used to receive and temporarily store downlink data from the TSV controller, and when it is read, it sends the corresponding data back to the TSV controller through the TSV channel for access by the CPU core layer.

[0029] Figure 1 This is a flowchart illustrating method 1 for cached data scheduling based on 3D chips. Figure 1 As shown, the 3D chip-based cache data scheduling method 1 includes steps S100 to S700.

[0030] Step S100: Obtain the transmission delay of the TSV array.

[0031] In some embodiments, step S100 includes steps S110 to S150, the specific steps of which are as follows: Step S110: Set up a delay measurement circuit at the TSV array inlet. The delay measurement circuit includes a transmitter, a receiver, a counting module, and a processing module. The transmission delay of the TSV array is acquired by the delay measurement circuit.

[0032] Specifically, the delay measurement circuit includes a transmitter, a counting module, and a processing module. The transmitter is located at the input of the TSV array and coupled to the input contacts of each TSV channel. The receiver is located at the output of the TSV array and coupled to the output contacts of each TSV channel. The receiver is also connected to the counting module, and the counting module is connected to the processing module.

[0033] Optionally, the delay measurement circuit further includes an input multiplexer and an output demultiplexer. The transmitting end of the delay measurement circuit is connected to the input of each TSV channel through the input multiplexer, and the receiving end of the delay measurement circuit is connected to the output of each TSV channel through the output demultiplexer.

[0034] Specifically, the input terminals of the input multiplexer are connected one-to-one with the input terminals of multiple channels of the TSV array, and the output terminal of the input multiplexer is connected to the transmitting end; the input terminals of the output demultiplexer are connected one-to-one with the output terminals of multiple channels of the TSV array, and the common output terminal of the output demultiplexer is connected to the receiving end; the input multiplexer and the output demultiplexer are synchronously controlled by the same set of address coding signals to achieve independent measurement of the transmission delay of each TSV channel.

[0035] Step S120: The transmitting end sends a test signal to the TSV array and outputs a start signal to the counting module.

[0036] Optionally, during operation, the input multiplexer sequentially selects the input terminals of each channel of the TSV array, while the output demultiplexer synchronously selects the output terminals of the corresponding TSV channels; the transmitting end sends a test pulse signal to the currently selected TSV channel and simultaneously sends a start signal to the counting module.

[0037] Step S130: The receiving end receives the test signal transmitted via the TSV array and simultaneously outputs a stop signal to the counting module.

[0038] Optionally, after the test pulse signal is vertically transmitted through the TSV channel, it is received by the receiving end through the output demultiplexer. At the same time as receiving the test pulse signal, the receiving end sends a stop trigger signal to the counting module.

[0039] Step S140: The counting module determines the original delay count value of the TSV array based on the time difference between the start signal and the stop signal.

[0040] Step S150: The processing module obtains the fixed delay parameters inside the chip and determines the actual transmission delay value of the TSV array based on the original delay count value and the fixed delay parameters inside the chip.

[0041] Optionally, the processing module obtains the original delay count value and, based on the internally stored fixed delay parameter value of the chip,... The actual transmission delay of the TSV channel is calculated using the following formula. : ; In the formula, For the first The actual transmission delay of each TSV channel, This refers to the fixed internal delay parameter value of the TSV channel within the chip. This is the original delay count value for the TSV channel.

[0042] Specifically, the fixed delay parameter value inside the chip is the inherent transmission delay of the input multiplexer, output demultiplexer, transmitter, receiver, and internal chip traces, and is independent of the TSV channel. The fixed delay parameter value inside the chip can be obtained in advance through the chip's internal self-test path, which is: input multiplexer — transmitter — internal traces — receiver — output demultiplexer.

[0043] The aforementioned technical solution, by setting up a delay measurement circuit, can detect the transmission delay of TSVs in real time and monitor all channels of a TSV array containing hundreds of channels sequentially. It can collect the transmission delay of all channels within microseconds, thus providing a basis for dynamically adjusting the storage location of cached data in the subsequent vertical hierarchical buffer pool. Simultaneously, the delay measurement circuit includes an input multiplexer and an output demultiplexer, enabling delay detection of hundreds of TSV channels. This avoids configuring a separate measurement circuit for each channel, significantly reducing hardware scale and mass production costs. Furthermore, by measuring multiple channels one by one, it effectively avoids signal crosstalk caused by simultaneous testing of multiple channels, ensuring high detection accuracy in large-scale TSV array scenarios and providing an accurate delay data foundation for subsequent buffer scheduling and prefetch optimization.

[0044] Step S200: Obtain the bandwidth occupancy of the TSV array.

[0045] In some embodiments, step S200 includes steps S210 to S220, the specific steps of which are as follows: Step S210: Set up a bandwidth monitoring module at the interface of the TSV array. The bandwidth monitoring module is used to collect the data transmission volume of the TSV array.

[0046] Specifically, the bandwidth monitoring module is a bandwidth monitoring counter. By setting a bandwidth monitoring counter at the interface of the TSV array, the bandwidth monitoring counter is used to periodically count the data transmission volume of the TSV array and calculate the bandwidth utilization rate according to the preset total TSV bandwidth parameters, providing a bandwidth status basis for subsequent buffer scheduling and prefetch control.

[0047] Specifically, the interface of the TSV array is the logical connection point between the TSV controller and the vertical hierarchical cache pool, and all cached data transmitted via the TSV array flows through this interface.

[0048] Specifically, the bandwidth monitoring counter includes multiple accumulators and a shared timer. Each accumulator corresponds to a TSV channel and is used to count the number of bytes transmitted by the channel within a preset time period. The timer is used to generate a statistical window for the preset time period, and one statistical window corresponds to one statistical period.

[0049] During operation, the CPU core layer sends cached data to the TSV controller, which then sends the cached data to the storage layer through the corresponding interface. The data packet carries the identifier information of the target TSV channel. The target TSV channel is the TSV channel used to carry this cached data transmission. Based on this identifier information, the bandwidth monitoring counter adds the number of bytes in the current data packet to the accumulator of the corresponding TSV channel.

[0050] Step S220: Determine the bandwidth occupancy of the TSV array based on the data transmission volume and the preset total bandwidth parameters of the TSV array.

[0051] At the end of each statistical period, the bandwidth monitoring counter reads the count values ​​of each accumulator and, in conjunction with the preset total bandwidth parameters of the TSV channels, calculates the bandwidth utilization rate of each channel according to the following formula: ; In the formula, It is the first Bandwidth occupancy of each TSV channel It is the first one within the preset time period Number of bytes transmitted per TSV channel For the preset time period, It is the first The nominal maximum bandwidth of each TSV channel.

[0052] Optionally, the bandwidth monitoring counter also collects queue depth information for each channel and generates a queue depth status table by reading the length of the pending request queue for each channel in the TSV controller.

[0053] At the end of each statistical period, the bandwidth monitoring counter resets the accumulators of each channel to zero and begins counting for the next statistical window.

[0054] The above technical solution, by configuring a bandwidth monitoring counter at the TSV controller interface, can monitor and obtain the bandwidth utilization rate of each TSV channel in real time, providing a basis for selecting a better channel during the cache scheduling process. This avoids scheduling cross-layer data access requests to congested TSV channels, effectively alleviating channel transmission congestion and improving the efficiency of data transmission between different layers.

[0055] Step S300: Obtain high-frequency access data from the 3D chip.

[0056] In some implementations, step S300 includes steps S310 to S330, and the specific steps are as follows: Step S310: Obtain an access event. An access event is a read or write operation on a cache line initiated by the CPU core layer.

[0057] Specifically, when the CPU core layer initiates a read or write operation on a cache line, it captures the access event, calculates a hash value based on the cache line address, locates the corresponding entry in the access frequency table, and increments the access counter for that cache line. The access frequency table is a fundamental hardware component inherent to the CPU core layer; it is a dedicated hardware storage array used to store the access frequency information of each cache line in real time.

[0058] Step S320: Determine the number of accesses for each cache line based on the access events.

[0059] Specifically, by capturing access events in real time, the number of accesses to each cache line is cumulatively counted in the access frequency table to obtain the cumulative number of accesses for each cache line. At the end of each preset statistical period, the number of accesses to each cache line within that period is counted.

[0060] Step S330: Cache lines whose access count exceeds a preset threshold are identified as high-frequency cache lines. High-frequency access data includes the physical address of each high-frequency cache line.

[0061] Specifically, the access count of each cache line is compared with a preset threshold. Cache lines whose access count exceeds the preset threshold are identified as high-frequency cache lines, and a high-frequency access dataset is generated. The high-frequency access dataset includes at least the physical address of each high-frequency cache line, its current cache partition, and access frequency information, providing a data basis for the scheduling decision in subsequent step S400.

[0062] Optionally, the preset threshold value ranges from 5 to 10, preferably 8, and the time window value can be 100 microseconds. Within the 100-microsecond statistical window, cache lines that are accessed more than 8 times are identified as high-frequency cache lines.

[0063] The above technical solution can adjust the level of cached data by accurately identifying high-frequency access data. For example, it can store high-frequency access data in the third cache partition L3 in a low-latency storage location, namely the first cache partition L1 and the second cache partition L2 located in the CPU core layer, which can effectively improve cache access efficiency.

[0064] Step S400: Schedule high-frequency access data based on transmission delay and bandwidth occupancy.

[0065] In some embodiments, step S400 includes steps S410 to S420, the specific steps of which are as follows: Step S410: If the transmission delay of a TSV channel is lower than a preset first threshold and the bandwidth occupancy is less than a preset second threshold, the high-frequency access data stored in the third cache partition L3 will be migrated to the first cache partition L1 and / or the second cache partition L2 through the TSV channel.

[0066] Specifically, step S410 includes steps S411 to S413, and the specific steps are as follows: Step S411: If the transmission delay of a TSV channel is lower than a preset first threshold and the bandwidth occupancy is less than a preset second threshold, identify the high-frequency access data to be migrated.

[0067] Specifically, high-frequency cache lines that are currently located in the third cache partition L3 of the storage layer and whose access frequency is higher than a preset threshold are selected from the high-frequency access dataset and used as the data to be migrated.

[0068] Preferably, the first threshold is 2ns to ensure sufficient timing margin for the admission channel, and the second threshold is 30%. If the nominal maximum bandwidth of a single channel is 4GB / s, a 30% occupancy rate corresponds to 1.2GB / s of used bandwidth, leaving 2.8GB / s, which can meet the bandwidth requirements of high-frequency access data. This threshold eliminates the risk of queue backlog and ensures the stability of the migration process.

[0069] Step S412: Perform cross-layer data migration.

[0070] Specifically, by controlling the TSV controller, the data to be migrated is transferred from the third cache partition L3 of the storage layer to the second cache partition L2 or the first cache partition L1 of the CPU core layer via the TSV array.

[0071] Step S413: Update cache metadata.

[0072] Specifically, once the migration is complete, update the cache metadata: change the physical address mapping that originally pointed to the third cache partition to point to the first or second cache partition.

[0073] The above technical solution schedules high-frequency access data based on transmission latency and bandwidth occupancy, migrating the high-frequency access data to the first cache partition L1 or the second cache partition L2, which is closer to the CPU core, thereby achieving low latency, avoiding the impact of TSV congestion, and improving the memory access efficiency of the 3D chip.

[0074] Step S420: If the transmission delay of a TSV channel is higher than a preset third threshold, or the bandwidth occupancy is greater than a preset fourth threshold, stop using the TSV channel for migration; wherein, the first threshold is less than the third threshold, the second threshold is less than the fourth threshold, the first threshold and the third threshold form a hysteresis interval for transmission delay, and the second threshold and the fourth threshold form a hysteresis interval for bandwidth occupancy.

[0075] Specifically, if the transmission delay of a TSV channel is higher than the preset third threshold, or the bandwidth occupancy is greater than the preset fourth threshold, the cross-layer migration operation will be suspended.

[0076] If no TSV channel meets the conditions described in step S410, the cross-layer migration operation will not be performed until a TSV channel that meets the conditions described in step S410 appears. By maintaining the status quo and continuously monitoring when no TSV channel meets the conditions, performance fluctuations that may be caused by forced migration when the overall load of the TSV array is high or the physical latency is generally large are avoided, ensuring the stable operation of the system under complex operating conditions.

[0077] Specifically, the scheduling unit suspends the operation of migrating high-frequency access data through the TSV channel from the third cache partition L3 to the second cache partition L2 or the first cache partition L1, so as to avoid increasing the transmission load of the TSV array.

[0078] Preferably, the third threshold is 5ns to prevent cache access from exceeding the CPU's timing window, which could lead to memory access failures and calculation errors. The fourth threshold is 80%; exceeding 80% will cause significant queue congestion in the TSV channel. There is a 3ns hysteresis interval between the third and first thresholds, and a 50% hysteresis interval between the fourth and second thresholds, to avoid scheduling oscillations caused by frequent TSV channel switching. For example, to initiate migration, the TSV channel's transmission latency must be below 2ns and its bandwidth utilization must be less than 30%. When the TSV channel is selected for migration, the transmission latency increases during this period, as does the bandwidth utilization. When the transmission latency exceeds 5ns or the bandwidth utilization exceeds 80%, migration stops. Only if the TSV channel's transmission latency falls below 2ns again and its bandwidth utilization is less than 30% can it be selected for migration again.

[0079] The above technical solution uses transmission latency as a physical quality indicator for the TSV channel, reflecting its hardware health, timing stability, inter-layer thermal coupling effects, and aging degradation. Bandwidth occupancy, on the other hand, is a load capacity indicator for the TSV channel, reflecting its service usage and remaining available bandwidth resources. The combination of these two metrics allows for rapid selection of usable TSV channels. If the transmission latency of a TSV channel exceeds the third threshold, cached data transmitted back through this channel will exceed the timing window, leading to cache access failure. If the bandwidth occupancy of a TSV channel exceeds the fourth threshold, the channel is congested and requires waiting.

[0080] It should be noted that if TSV channels are selected solely based on bandwidth occupancy, a TSV channel with idle bandwidth but degraded physical transmission latency due to aging or thermal effects may be selected, leading to an increase in actual access latency after the migration of high-frequency access data. Conversely, if selection is based solely on transmission latency, a TSV channel with good physical quality may be selected, but whose bandwidth is currently occupied by other services, causing congestion during the migration process and even exacerbating the congestion of the TSV array. This application ensures that the selected TSV channel has both good physical transmission quality and sufficient remaining bandwidth resources by simultaneously obtaining transmission latency and bandwidth occupancy and using them for judgment, thereby guaranteeing the smooth execution of the migration operation and an effective reduction in access latency after migration.

[0081] Furthermore, the aforementioned scheme suffers from several drawbacks. The transmission delay of the TSV channel in the 3D chip slowly drifts with chip operating temperature and interlayer thermal coupling effects, while bandwidth occupancy fluctuates due to changes in the memory access patterns of upper-layer applications. Using a single fixed threshold could easily lead to frequent switching between available and unavailable TSV channels, causing scheduling oscillations and requiring multiple cache metadata updates. By setting the aforementioned hysteresis interval, scheduling decisions are only triggered when the TSV channel state changes significantly, effectively avoiding scheduling jitter caused by instantaneous state fluctuations and improving system stability. Simultaneously, it avoids frequent migrations caused by instantaneous TSV state fluctuations, thus keeping migration overhead within a reasonable range.

[0082] In some embodiments, the present application further includes steps S500 to S700, the specific steps of which are as follows: Step S500: Obtain the cache hit rate and optimize the scheduling method based on the cache hit rate.

[0083] In some implementations, step S500 includes steps S510 to S530, the specific steps of which are as follows: Step S510: Collect the cache hit count and total cache access count of the first cache partition L1, the second cache partition L2, and the third cache partition L3 according to the preset statistical period.

[0084] Specifically, cache hit count is the number of times the target data can be directly found in the corresponding cache partition when the CPU core layer initiates an access request. Total cache access count is the total number of all cache access requests initiated by the CPU core layer.

[0085] Step S520: Determine the cache hit rate based on the number of cache hits and the total number of cache accesses.

[0086] Specifically, according to the formula, cache hit rate = number of cache hits / total number of cache accesses × 100%.

[0087] Step S530: Optimize the scheduling method based on the cache hit rate.

[0088] The cache hit rate is compared with a preset threshold. If the current cache hit rate is not less than the preset threshold, it indicates that the current scheduling method is reasonable and should be maintained. If the current cache hit rate is lower than the preset threshold, step S300 is repeated to re-identify the current high-frequency access data, and step S400 is executed to adjust the scheduling based on the updated TSV status.

[0089] Step S600: Determine the congestion level of TSV based on the bandwidth occupancy, queue depth information, and waiting time information of each channel.

[0090] Step S400 is used to filter out available TSV channels. When there are multiple available TSV channels, step S600 is designed to find the TSV channel with the lightest current load and most suitable for data migration.

[0091] In some implementations, step S600 includes steps S610 to S620, the specific steps of which are as follows: Step S610: Obtain the bandwidth occupancy, queue depth information, and waiting time information of each TSV channel.

[0092] Specifically, bandwidth utilization measures the percentage of data transmitted by a TSV channel per unit of time relative to its maximum transmission capacity. Queue depth information is used to read the length of the pending request queue for each channel in the TSV controller, i.e., the queuing level. Waiting time information is the time that the earliest request in the pending request queue corresponding to a specific TSV channel in the TSV controller has been waiting since it entered the queue and has not yet been processed. If only bandwidth utilization is used for judgment, misjudgments may occur when there is a backlog of request queues within the TSV controller even though the bandwidth is not saturated. Introducing queue depth and waiting time information can more accurately reflect the actual congestion status of TSV channels.

[0093] Specifically, bandwidth utilization and queue depth information can be obtained through step S200, with queue depth information retrieved from the queue depth status table. Waiting duration information can be obtained by setting a waiting time counter within each TSV channel. This waiting time counter collects the timestamps corresponding to data transmission requests sent by the CPU core layer or cache controller to the TSV channel. The waiting duration information is determined by subtracting the timestamp of the earliest incomplete request from the current timer value.

[0094] Step S620: Quantify the bandwidth utilization, queue depth information, and waiting time information.

[0095] Specifically, this application embodiment uses a normalization method to quantize bandwidth utilization, queue depth information, and waiting time information, mapping them to the [0,1] interval, respectively using... , and This represents the quantized value.

[0096] Optionally, This can be determined by dividing the current channel bandwidth occupancy by 100%. It can be determined by dividing the current channel's queue depth information by the preset queue depth limit. The waiting time can be determined by dividing the current channel's waiting time by the preset waiting time limit.

[0097] Specifically, the preset queue depth limit and preset waiting time limit can be preset based on the hardware buffer capacity of the TSV controller and the system's tolerance for access latency.

[0098] The degree of congestion can be calculated using a formula. : ; In the formula, As the first coefficient, As the second coefficient, The third coefficient, This is the quantized value of the TSV channel bandwidth occupancy. This is the quantized value of the TSV channel queue depth information. This is the quantized value of the waiting time information for this TSV channel. This indicates the level of congestion in the TSV channel.

[0099] Regarding the weighting coefficients, bandwidth occupancy directly reflects the real-time load status of the TSV channel and most directly represents the degree of congestion, therefore it is given a high weight; waiting time information directly reflects the queuing delay of requests and is closely related to system access performance, so it can be given the second highest weight; queue depth information, as an auxiliary indicator, is used to reflect the scale of backlogged requests and can be given a relatively low weight. For example, the first coefficient can be... Set to 0.5, the second coefficient Set to 0.2, third coefficient Set to 0.3, and satisfy... + + =1. The weighting coefficient can also be determined through system simulation or experimental optimization, which falls within the scope that those skilled in the art can reasonably choose after understanding this scheme.

[0100] The aforementioned technical solutions suffer from transmission delay, which is inherently affected by factors such as physical length and manufacturing process variations. Some components of this value are unrelated to real-time congestion status. Using transmission delay to calculate congestion level would lead to inaccurate results. This solution refers to the acquired dynamic congestion state of the TSV channel caused by the accumulation of real-time service load; therefore, transmission delay is not included in the weighted calculation parameters for congestion level. Queue depth, waiting time, and bandwidth occupancy are strongly correlated only with the real-time service load status of the channel, directly and accurately characterizing the real-time congestion level of the TSV channel. By calculating the real-time congestion level of the channel using weighted methods, the optimal channel for migration can be selected, ensuring the stability and speed of data migration and achieving load balancing of the TSV array.

[0101] Step S700: When there are multiple TSV channels that meet the dual threshold conditions described in step S400, select a TSV channel for migration according to the degree of congestion C.

[0102] Specifically, when a cross-layer access request is generated, the TSV channel with the lowest congestion score C is selected for transmission first, in order to improve transmission efficiency and achieve more reasonable allocation.

[0103] Specifically, after the migration is complete, the corresponding original data in the third cache partition L3 can be cleared to free up cache space for subsequent data use.

[0104] In summary, the cache data scheduling method based on 3D chips provided in this application has the following advantages: The beneficial effects of this application are: 1. By obtaining the transmission delay and bandwidth occupancy of multiple TSV channels, this application can ensure that the selected TSV channel has both good physical transmission quality and sufficient remaining bandwidth resources, thereby ensuring the smooth execution of the migration operation and the effective reduction of access latency after migration.

[0105] 2. This application enables successive testing of multiple TSV channels by setting up a delay measurement circuit. Time-division multiplexing and successive testing of multiple TSV channels are achieved through an input multiplexer and an output demultiplexer. Compared to the traditional approach of configuring a separate measurement circuit for each TSV channel, this application reduces costs. Simultaneously, the successive measurement method effectively avoids signal crosstalk problems during parallel testing of multiple channels, ensuring high transmission delay detection accuracy in large-scale TSV array scenarios and providing accurate data for subsequent buffer scheduling decisions.

[0106] 3. This application calculates the degree of congestion. It can select the optimal migration channel, ensuring the stability and speed of data migration.

[0107] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. For example... Figure 2 As shown, the electronic device 400 includes: one or more processors 410 and a memory 420. Figure 2 Take a processor 410 as an example.

[0108] In some implementations, the processor 410 and the memory 420 may be connected via a bus or other means. Figure 2 Taking the example of a connection between China and Israel via a bus.

[0109] In some implementations, the processor 410 is configured to acquire the transmission delay of the TSV array; acquire the bandwidth occupancy of the TSV array; acquire high-frequency access data of the 3D chip; and schedule the high-frequency access data based on the transmission delay and bandwidth occupancy.

[0110] In some implementations, memory 420 serves as a non-volatile computer-readable storage medium, used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules of the 3D chip-based cached data scheduling method in the embodiments of this application. Processor 410 executes various functional applications and data processing of electronic device 400 by running the non-volatile software programs, instructions, and modules stored in memory 420, thereby implementing the 3D chip-based cached data scheduling method of the above-described method embodiments.

[0111] In some embodiments, memory 420 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of electronic device 400, etc. Furthermore, memory 420 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 420 may optionally include memory remotely located relative to processor 410, and this remote memory may be connected to the controller via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0112] In some implementations, one or more modules are stored in memory 420, and when executed by one or more processors 410, they perform the 3D chip-based cache data scheduling method in any of the above method embodiments, for example, performing the above-described... Figure 1 The method steps S100 to S700.

[0113] In some implementations, the electronic device can be a chip, such as a data processing unit (DPU) chip used in a data center. Alternatively, the electronic device can be a network interface card that includes a chip and multiple interfaces (such as PCI / PCIE interfaces, UART interfaces, USB interfaces, etc.). Or, the electronic device can be a traditional server, or a server that includes a network interface card or chip. The server includes a host and a data processor. The data processor is used to schedule packets to the host or the data processor itself for processing. The host is used to process the packets scheduled by the data processor.

[0114] Please refer to Figure 3 , Figure 3 This is a structural block diagram of a computer-readable storage medium provided in an embodiment of this application. The computer-readable storage medium 500 stores program code 510, which can be called by a processor to execute the 3D chip-based cache data scheduling method described in the above method embodiments.

[0115] The computer-readable storage medium 500 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. Optionally, the computer-readable storage medium includes a non-volatile computer-readable storage medium. The computer-readable storage medium 500 has storage space for program code that performs any of the method steps of the above-described 3D chip-based cached data scheduling method. This program code can be read from or written to one or more computer program products. The program code may, for example, be compressed in an appropriate form.

[0116] In summary, this application provides a cache data scheduling method, device, and storage medium based on a 3D chip. The cache data scheduling method includes: obtaining the transmission delay of the TSV array; obtaining the bandwidth occupancy of the TSV array; obtaining high-frequency access data from the 3D chip; and scheduling the high-frequency access data based on the transmission delay and bandwidth occupancy. This application improves the memory access efficiency of the 3D chip by combining the transmission delay and bandwidth occupancy of the TSV channel for dynamic scheduling of cache data.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A cached data scheduling method based on a 3D chip, characterized in that, The 3D chip includes a CPU core layer, a storage layer, and a TSV array connecting the CPU core layer and the storage layer; The method includes: Obtain the transmission delay of the TSV array; Obtain the bandwidth occupancy of the TSV array; Obtain high-frequency access data from the 3D chip; The high-frequency access data is scheduled based on the transmission delay and the bandwidth occupancy.

2. The cache data scheduling method based on a 3D chip according to claim 1, characterized in that, The step of obtaining the transmission delay of the TSV array includes: A delay measurement circuit is set at the entrance of the TSV array. The delay measurement circuit includes a transmitting end, a receiving end, a counting module, and a processing module. The transmitting end sends a test signal to the TSV array and outputs a start signal to the counting module; The receiving end receives the test signal transmitted via the TSV array and simultaneously outputs a stop signal to the counting module; The counting module determines the original delay count value of the TSV array based on the time difference between the start signal and the stop signal; The processing module obtains the fixed delay parameters inside the chip and determines the actual transmission delay value of the TSV array based on the original delay count value and the fixed delay parameters inside the chip.

3. The cache data scheduling method based on a 3D chip according to claim 2, characterized in that, The TSV array includes multiple TSV channels, each of which includes an input terminal and an output terminal.

4. The cache data scheduling method based on a 3D chip according to claim 3, characterized in that, The delay measurement circuit also includes an input multiplexer and an output demultiplexer; The transmitting end of the delay measurement circuit is connected to the input of each TSV channel through the input multiplexer, and the receiving end of the delay measurement circuit is connected to the output of each TSV channel through the output demultiplexer.

5. The cache data scheduling method based on a 3D chip according to claim 1, characterized in that, The process of obtaining the bandwidth occupancy of the TSV array includes: A bandwidth monitoring module is installed at the interface of the TSV array, and the bandwidth monitoring module is used to collect the data transmission volume of the TSV array; The bandwidth occupancy of the TSV array is determined based on the data transmission volume and the preset total bandwidth parameters of the TSV array.

6. The cache data scheduling method based on a 3D chip according to claim 1, characterized in that, The acquisition of high-frequency access data from the 3D chip includes: Obtain an access event, wherein the access event is a read or write operation on a cache line initiated by the CPU core layer; Based on the access events, determine the number of accesses for each cache line; The cache lines whose access count exceeds a preset threshold are identified as high-frequency cache lines, and the high-frequency access data includes the physical address of each high-frequency cache line.

7. The cache data scheduling method based on a 3D chip according to claim 1, characterized in that, The CPU core layer includes a first cache partition and a second cache partition, and the storage layer includes a third cache partition. The access latency of the first cache partition and the second cache partition is lower than that of the third cache partition, which needs to be accessed across the TSV array.

8. The cache data scheduling method based on a 3D chip according to claim 3, characterized in that, The step of scheduling the high-frequency access data based on the transmission delay and the bandwidth occupancy includes: If the transmission delay of a TSV channel is lower than a preset first threshold and the bandwidth occupancy is less than a preset second threshold, the high-frequency access data stored in the third cache partition will be migrated to the first cache partition and / or the second cache partition through the TSV channel. If the transmission delay of a TSV channel is higher than a preset third threshold, or the bandwidth occupancy is greater than a preset fourth threshold, the use of the TSV channel for migration will be stopped. Wherein, the first threshold is less than the third threshold, the second threshold is less than the fourth threshold, the first threshold and the third threshold form a hysteresis interval of transmission delay, and the second threshold and the fourth threshold form a hysteresis interval of bandwidth occupancy.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the cached data scheduling method based on a 3D chip as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores an executable program, which is executed by a processor to implement the cached data scheduling method based on a 3D chip as described in any one of claims 1 to 8.

Images