Data security access authorization method for solid state disk

Abstract

The application relates to the technical field of data security, in particular to a data security access authorization method for a solid state disk, which comprises the following steps: generating a pseudo-random logical block address sequence in a non-sensitive reserved address interval of the solid state disk according to a preset shared seed key, opening a ring buffer in a controller to establish a bit array storage structure limited by an anti-overflow threshold condition, and mapping to generate a target bit array. In the application, the main encryption key is only extracted and used for ciphertext data block decryption during an authorized valid period, and the main encryption key is destroyed and the access authorization trigger instruction is revoked immediately after the request is completed or the authorization time window is timed out, so that the key residence time can be shortened, the risk that the key is intercepted, repeatedly called or used by unauthorized persons can be reduced, and the concealed authentication capability in the data reading process of the solid state disk is improved.

Description

Technical Field

[0001] This invention relates to the field of data security technology, and in particular to a method for authorizing secure data access to solid-state drives. Background Technology

[0002] Data security technology involves the security protection of data throughout the entire process of data generation, storage, transmission, access, retrieval, backup, recovery and destruction, and focuses on solving the problems of unauthorized reading, tampering, leakage, copying, destruction or misuse of data.

[0003] Current data security processes typically revolve around identity authentication, access control, key management, encryption / decryption, and permission revocation. In practice, access permissions are often centrally bound to account identities, fixed credentials, static permission tables, or external authentication results. After a data read request enters the storage device, common processing paths focus more on whether the request originates from an authorized entity, while failing to adequately characterize the correlation between request address sequences, arrival order, irrelevant read / write interference, and continuous request behavior. Once an attacker obtains valid credentials, reuses historical authorization states, or simulates compliant read entries, the storage side struggles to promptly distinguish between genuine and forged access behaviors. This is especially problematic in high-speed queue concurrency scenarios on solid-state drives, where normal read / write requests and probing read / write requests may intersect. Traditional authorization determination, relying solely on single identity results or fixed key release conditions, is prone to issues such as expanded authorization scope, infiltration of abnormal requests, and excessively long key residency times. For example, when a logged-in terminal is invoked by a malicious process, the process can use existing access permissions to continuously probe the location of sensitive data. Therefore, improvements are needed. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a data security access authorization method for solid-state drives.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a data security access authorization method for solid-state drives, comprising the following steps: Based on the preset shared seed key, a pseudo-random logical block address sequence is generated within the non-sensitive reserved address range of the solid-state drive, and a ring buffer is opened in the controller to establish a bit array storage structure restricted by the overflow prevention threshold condition, which is then mapped to generate the target bit array. The host sends a read request command based on the pseudo-random logical block address sequence; the controller scans the NVMe protocol queue, verifies the input logical block address based on the target bit array, and constructs a set of hit addresses containing the matched logical block addresses; the number of irrelevant read and write commands between consecutive valid addresses is counted and sorted by arrival time to generate a noisy input sequence; Extract the sequence edit distance parameter and position inversion count between the noisy input sequence and the pseudo-random sequence; compare the number of irrelevant read / write instructions, position inversion count, and sequence edit distance parameter with preset anti-brute-force threshold, out-of-order tolerance threshold, and fault tolerance threshold respectively. If all conditions are met, generate an access authorization trigger instruction; otherwise, reset the monitoring state. In response to the access authorization trigger command, the master encryption key is retrieved from the secure storage area, the ciphertext data block is decrypted into plaintext data payload, and the data is returned in response to subsequent data read requests; after the request is completed or the authorization time window expires, the master encryption key is destroyed and the command is revoked, restoring the system to the unauthorized locked state.

[0006] Preferably, the step of obtaining the pseudo-random logical block address sequence is as follows: Write a shared seed key into the host-side key storage unit and the solid-state drive controller key register unit. Read the key byte sequence from the host-side key storage unit and the key byte sequence from the solid-state drive controller key register unit. Compare the character value, length value, and arrangement order of the two key byte sequences bit by bit according to the byte position. If the character value, length value, and arrangement order are all consistent, the shared seed key is retained as the input basis for subsequent address generation. If any character value, length value, or arrangement order is inconsistent, the address generation process is terminated, and the shared seed key is obtained. The current round input byte sequence corresponding to the shared seed key is read round by round according to the preset iteration rounds. Irreversible compression transformation is performed on the current round input byte sequence. Numerical fragments are extracted from the output digest of each round. The numerical fragments are converted into candidate logical block address values. The start boundary value, end boundary value, and interval span value of the non-sensitive reserved address interval of the solid-state drive are called. The remainder is applied to the candidate logical block address values ​​so that the applied logical block addresses fall into the non-sensitive reserved address interval of the solid-state drive. The applied logical block addresses are arranged according to the iteration round order to generate a pseudo-random logical block address sequence.

[0007] Preferably, the step of obtaining the target bit set is as follows: In the solid-state drive controller's memory space, a contiguous buffer storage segment is defined. The write pointer, read pointer, and wraparound boundary identifier of the contiguous buffer storage segment are configured as ring buffer control parameters. A bit array storage structure with equal or compressed mapping is established according to the number of address elements in the pseudo-random logical block address sequence. Each address element in the pseudo-random logical block address sequence is read and converted into a bit position index in the bit array storage structure. The occupied quantity between the write pointer and the read pointer is detected. If the occupied quantity does not reach the overflow prevention threshold, the bit value corresponding to the bit position index is set to a valid state. If the occupied quantity reaches the overflow prevention threshold, writing address elements is stopped, and the target bit array is obtained.

[0008] Preferably, the step of obtaining the set of hit addresses is as follows: The host invokes the pseudo-random logical block address sequence, reads the address elements in the pseudo-random logical block address sequence one by one, writes each address element into the logical block address field of the read request instruction, marks the operation type field of the read request instruction as the read type, fills the submission order field of the read request instruction according to the arrangement position of the address elements in the pseudo-random logical block address sequence, submits the filled read request instruction to the command receiving port of the solid-state drive, and generates a read request instruction. The solid-state drive controller calls the target bit array and scans the read request instructions one by one from the head to the tail of the NVMe protocol queue. It reads the logical block address field in the read request instruction, converts the logical block address field into an input logical block address, and maps the input logical block address to the bit position index in the target bit array. If the bit value corresponding to the bit position index is valid, the input logical block address is retained. If the bit value corresponding to the bit position index is not valid, the input logical block address is filtered. The retained input logical block addresses are collected according to the scanning order to construct a set of hit addresses.

[0009] Preferably, the step of obtaining the noisy input sequence is as follows: Read the arrival timestamp of each matched logical block address in the set of hit addresses, arrange the matched logical block addresses in order of arrival timestamp, count the non-hit read instructions and non-hit write instructions that occur between two adjacent matched logical block addresses, obtain the number of irrelevant read and write instructions between consecutive valid addresses, bind the matched logical block addresses, arrival timestamps, and number of irrelevant read and write instructions in the same arrangement position to form an address arrangement content with interval interference markers, and generate a noisy input sequence.

[0010] Preferably, the step of obtaining the sequence edit distance parameter is as follows: The input address elements in the noisy input sequence are read one by one according to their arrangement positions. The standard address elements in the pseudo-random logic block address sequence are read according to the same arrangement positions. The address values, arrangement positions, and missing states of the input address elements are compared bit by bit. If the address value of the input address element is different from the address value of the standard address element, or if there are no input address elements with the same arrangement positions in the noisy input sequence, the number of element differences is accumulated once to obtain the sequence edit distance parameter.

[0011] Preferably, the step of obtaining the access authorization trigger instruction is as follows: Continue calling the noisy input sequence and the pseudo-random logic block address sequence, extract the arrival time sorting position of each input address element in the noisy input sequence, extract the standard sorting position of the same address element in the pseudo-random logic block address sequence, compare the arrival time sorting position and the standard sorting position item by item, if the arrival time order of any two input address elements is different from the standard order order in the pseudo-random logic block address sequence, then accumulate one sorting reversal record to obtain the position reversal count; The sequence edit distance parameter and the number of irrelevant read / write instructions in the noisy input sequence are called. The number of irrelevant read / write instructions is compared with a preset anti-brute-force threshold item by item. If the number of irrelevant read / write instructions does not exceed the preset anti-brute-force threshold, the position inversion count is compared with a preset out-of-order tolerance threshold, and the sequence edit distance parameter is compared with a preset fault tolerance threshold. If the position inversion count meets the preset out-of-order tolerance threshold and the sequence edit distance parameter meets the preset fault tolerance threshold, the current authorization determination state of the noisy input sequence is retained. If any comparison result does not meet the corresponding set threshold condition, the current noisy input sequence is discarded and the listening state is reset, and an access authorization trigger instruction is generated.

[0012] Preferably, the specific steps to restore to an unauthorized locked state are as follows: In response to the access authorization trigger command, the solid-state drive controller reads the authorization identifier, generation timestamp, secure storage area index, and key extraction permission bit from the access authorization trigger command. It verifies item by item whether the authorization identifier is valid, whether the generation timestamp falls within the authorization time window, and whether the key extraction permission bit corresponds to the secure storage area index. If the authorization identifier is valid, the generation timestamp falls within the authorization time window, and the key extraction permission bit corresponds to the secure storage area index, then the key reading channel of the secure storage area is opened, and the key byte content is read from the key storage location of the access authorization trigger command pointed to by the secure storage area index to obtain the master encryption key. The solid-state drive controller reads the page address, block number, offset, and length identifier of the encrypted data block from the underlying flash memory medium. It locates the physical page of the underlying flash memory medium according to the page address, locks the corresponding storage block according to the block number, extracts the encrypted byte segment to be processed according to the offset, limits the reading boundary of the encrypted byte segment to be processed according to the length identifier, loads the master encryption key into the key operation register in the memory of the solid-state drive controller, and restores the encrypted byte segment to be processed block by block into readable byte content to generate plaintext data payload. The solid-state drive controller reads the target logical block address, read length, host-side memory space address, and transmission interface bus queue identifier from the subsequent data read request issued by the host. It locates the payload segment to be transmitted back from the plaintext data payload according to the target logical block address, segments the payload segment to be transmitted back according to the read length, writes the segmented payload segment to be transmitted back to the transmission interface bus according to the transmission interface bus queue identifier, and completes the write confirmation according to the host-side memory space address. After the subsequent data read request is completed or the authorization time window expires, it clears the master encryption key from the solid-state drive controller's memory, revokes the validity of the access authorization trigger instruction, and restores the controller to an unauthorized locked state.

[0013] Compared with the prior art, the advantages and positive effects of the present invention are as follows: This invention generates a pseudo-random logical block address sequence through a shared seed key, placing access authorization as an implicit verification process at the address sequence level. This eliminates the reliance on explicit passwords or fixed permission identifiers for authorization triggering. The pseudo-random logical block address sequence is confined to the non-sensitive reserved address range of the solid-state drive, reducing disturbance to real business data addresses. The target bit array carries the address mapping relationship through a circular buffer and an anti-overflow threshold condition, enabling rapid filtering of unmatched input logical block addresses during the queue scanning phase, reducing the probability of invalid requests participating in authorization determination. The set of matched addresses is further sorted by the number of irrelevant read / write instructions and arrival time to form a noisy input sequence, ensuring normal business operations are protected. Read / write interference can be quantified and absorbed. Sequence edit distance parameter, position inversion count, anti-brute force threshold, out-of-order tolerance threshold and fault tolerance threshold are jointly used for judgment. It can simultaneously cover abnormal situations such as address errors, sequence forgery, insertion interference and brute force attempts. The access authorization trigger command is only generated when multiple conditions are met. The master encryption key is only extracted and used for decrypting ciphertext data blocks during the authorization period. The master encryption key is destroyed and the access authorization trigger command is revoked immediately after the request is completed or the authorization time window expires. This can shorten the key residence time and reduce the risk of key interception, repeated use or unauthorized reuse, thereby improving the covert authentication capability during solid-state drive data reading. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a pseudo-random logical block address sequence; Figure 2 This diagram illustrates the number of read / write instructions that are independent of each other between consecutive valid addresses. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0016] Please see Figure 1-2 This invention provides a technical solution for a data security access authorization method for solid-state drives, comprising the following steps: Based on the preset shared seed key, a pseudo-random logical block address sequence is generated within the non-sensitive reserved address range of the solid-state drive, and a ring buffer is opened in the controller to establish a bit array storage structure restricted by the overflow prevention threshold condition, which is then mapped to generate the target bit array. The host sends a read request command based on a pseudo-random logical block address sequence; the controller scans the NVMe protocol queue, verifies the input logical block address based on the target bit array, and constructs a set of hit addresses containing the matched logical block addresses; it counts the number of irrelevant read and write commands between consecutive valid addresses and sorts them by arrival time to generate a noisy input sequence. Extract the sequence edit distance parameter and position inversion count between the noisy input sequence and the pseudo-random sequence; compare the number of irrelevant read / write commands, position inversion count, and sequence edit distance parameter with the preset anti-brute-force threshold, out-of-order tolerance threshold, and fault tolerance threshold, respectively. If all conditions are met, generate an access authorization trigger command; otherwise, reset the listening state. In response to the access authorization trigger command, the system retrieves the master encryption key from the secure storage area, decrypts the ciphertext data block into plaintext data payload, and responds to subsequent data read requests by sending back the data. After the request is completed or the authorization time window expires, the system destroys the master encryption key, revokes the command, and restores the system to the unauthorized locked state.

[0017] The steps for obtaining a pseudo-random logical block address sequence are as follows: Write a shared seed key into the host-side key storage unit and the solid-state drive controller key register unit. Read the key byte sequence from the host-side key storage unit and the key byte sequence from the solid-state drive controller key register unit. Compare the character value, length value, and arrangement order of the two key byte sequences bit by bit according to the byte position. If the character value, length value, and arrangement order are all consistent, the shared seed key is retained as the input basis for subsequent address generation. If any character value, length value, or arrangement order is inconsistent, the address generation process is terminated, and the shared seed key is obtained. The system reads the current round input byte sequence corresponding to the shared seed key in each round according to the preset iteration rounds. It performs an irreversible compression transformation on the current round input byte sequence, extracts the numerical fragments from the output digest of each round, converts the numerical fragments into candidate logical block address values, calls the start boundary value, end boundary value and interval span value of the non-sensitive reserved address interval of the solid-state drive, performs remainder approximation processing on the candidate logical block address values, so that the approximated logical block addresses fall into the non-sensitive reserved address interval of the solid-state drive, and arranges the approximated logical block addresses according to the iteration round order to generate a pseudo-random logical block address sequence.

[0018] Specifically, a shared seed key is written to both the host-side key storage unit and the solid-state drive (SSD) controller key register unit. This writing operation is completed via a secure channel provided by the secure boot process or the Trusted Platform Module (TPM), establishing a foundation for key consistency between the two ends. Then, the complete key byte sequence is read from the host-side UEFI variable storage area and the dedicated non-volatile static random access memory (SRAM) or eFuse array within the SSD controller, respectively. The comparison process initiates a loop, the number of loops being equal to the byte length of the shared seed key. For example, a 256-bit key corresponds to 32 bytes, so the loop is repeated 32 times. In each loop, the i-th byte from the host-side key byte sequence and the byte from the SSD controller key register unit are retrieved. For the i-th byte of the controller key byte sequence, perform an XOR operation on the two bytes and then perform a logical OR accumulation on the XOR results of all loop rounds. After all bytes are compared, check the final accumulation result. If the result is zero, it means that the two key byte sequences are completely consistent in character value, length value, and arrangement order. At this time, a "key verification passed" flag is set in the controller status register, and this shared seed key is retained as the only input for subsequent pseudo-random address generation. If the accumulation result is non-zero, or if the length value of any key is found to be inconsistent with the preset standard length (e.g., 32 bytes) during the reading process, a "key mismatch" error flag is immediately set in the status register, and all subsequent processes of the entire authorized access mechanism are terminated. No more address generation is performed, and the shared seed key is obtained.

[0019] The shared seed key's current round input byte sequence is read round by round according to a preset iteration number. This preset iteration number is determined by the length of the required pseudo-random sequence. For example, if a sequence containing 16 logical block addresses is needed, the iteration number is set to 16. In the first iteration, the complete shared seed key is used as the initial input byte sequence. SHA-256 is applied to it for irreversible compression, generating a 32-byte hash digest. The first 8 bytes are extracted from the beginning of this digest and interpreted as a 64-bit unsigned integer, which is the candidate logical block address value. Then, the boundary parameters of the predefined non-sensitive reserved address range in the SSD firmware are called. This range is an over-configuration space invisible to ordinary users. For example, if the starting boundary value is 0xC0000000 and the ending boundary value is 0xC00FFFFF, the range span is 0x100000. A modulo operation is performed on the aforementioned 64-bit candidate logical block address value, i.e., the remainder is calculated by dividing it by the range span value. This remainder is then added to the starting boundary value. The calculation formula is: Logical block address after inclusion = The formula (candidate logical block address value MOD range span value) + starting boundary value ensures that the calculated new address falls within the specified non-sensitive reserved address range. After the first round, for the subsequent nth round (n>1) iteration, the 32-byte hash digest generated in the (n-1)th round is concatenated with a counter value representing the current round (e.g., a byte representing n-1) to form a new input byte sequence. The above SHA-256 transformation, value extraction, and remainder input processing are repeated until all preset iteration rounds are completed. Finally, the logical block addresses generated in each round are arranged according to the order of iteration to form an address list with a definite order but pseudo-random content, generating a pseudo-random logical block address sequence.

[0020] The steps to obtain the target bit set are as follows: In the solid-state drive controller's memory space, a contiguous buffer storage segment is defined. The write pointer, read pointer, and wraparound boundary identifier of the contiguous buffer storage segment are configured as ring buffer control parameters. A bit array storage structure with equal or compressed mapping is established according to the number of address elements in the pseudo-random logical block address sequence. Each address element in the pseudo-random logical block address sequence is read and converted into a bit position index in the bit array storage structure. The occupied quantity between the write pointer and the read pointer is detected. If the occupied quantity does not reach the overflow prevention threshold, the bit value corresponding to the bit position index is set to a valid state. If the occupied quantity reaches the overflow prevention threshold, writing address elements is stopped, and the target bit array is obtained.

[0021] Specifically, a contiguous buffer storage segment is allocated within the solid-state drive controller's memory space. This segment serves as a static bitmap, the size of which is determined based on the mapping relationship. For example, to reduce memory usage, instead of directly mapping the entire logical block address space, a hash mapping method is used. First, a fixed-size bit array is allocated, such as 65536 bits (8 KB), forming the bit array storage structure. Then, the number of address elements in the pseudo-random logical block address sequence, for example, 16, is compared with the size of the bit array. An overflow prevention threshold based on a fill factor is set, calculated as 75% of the total number of bits in the bit array. If the length of the pseudo-random logical block address sequence exceeds this threshold, the initial parameter setting is considered unreasonable and the process is terminated. If the threshold is not reached, the address elements in the pseudo-random logical block address sequence are read one by one. A fast, non-cryptographic hash function, such as MurmurHash3, is applied to each address element to generate a 32-bit hash value. Then, this hash value is modulo the size of the bit array (65536) to obtain a bit position index in the range of 0 to 65535. The calculation process is: bit position index = MurmurHash3(address element) MOD 65536. Then, the bit position corresponding to the bit position index in the bit array is set to 1 to mark it as valid. The circular buffer control parameters (write pointer, read pointer, wraparound boundary identifier) ​​are configured for the NVMe submission queue that receives host instructions later. In this step, only the association settings are performed and no actual operation is performed. After repeatedly performing hash calculation and bit setting operations on all address elements in the pseudo-random logical block address sequence, a sparsely filled target bit array for quickly verifying the validity of the input address is finally obtained.

[0022] The steps to obtain the set of hit addresses are as follows: The host calls the pseudo-random logical block address sequence, reads the address elements in the pseudo-random logical block address sequence one by one, writes each address element into the logical block address field of the read request instruction, marks the operation type field of the read request instruction as read type, fills the submission order field of the read request instruction according to the arrangement position of the address elements in the pseudo-random logical block address sequence, and submits the filled read request instruction to the command receiving port of the solid-state drive to generate the read request instruction. The solid-state drive controller calls the target bit array and scans the read request commands one by one from the head to the tail of the NVMe protocol queue. It reads the logical block address field in the read request command, converts the logical block address field into an input logical block address, and maps the input logical block address to the bit position index in the target bit array. If the bit value corresponding to the bit position index is valid, the input logical block address is retained. If the bit value corresponding to the bit position index is not valid, the input logical block address is filtered. The retained input logical block addresses are collected according to the scan order to construct the hit address set.

[0023] Specifically, the host invokes a pseudo-random logical block address sequence. Authorized applications or drivers on the host side read this sequence from the secure storage area and extract logical block address LBA elements one by one according to the order of elements in the sequence. For each extracted LBA, a standard NVMe read command submission queue entry is constructed. The specific filling process is as follows: the SQE opcode field is set to the code corresponding to the read operation, for example, 0x02; the command namespace identifier field is set to the identifier of the target storage space; the starting logical block address field is filled with the LBA value currently extracted from the sequence; and the logical block quantity field is set to 0, indicating that one logical block is read. To preserve the original... The host driver fills the command identifier field of the command with the original position index (e.g., from 0 to 15) of the address element in the pseudo-random logical block address sequence to complete the construction of an SQE. After that, it writes it into the commit queue buffer allocated for the NVMe queue in the host memory and moves the tail pointer of the queue. This process is repeated for all address elements in the sequence. All the constructed read request commands are placed in order after the commit queue. Finally, the host driver notifies the controller that there is a new command to process by writing a new tail pointer value to the solid-state drive controller doorbell register mapped to the host memory address space, thus generating a read request command.

[0024] The SSD controller, after being woken up by the host via the doorbell register, calls the target bit array. It then begins processing instructions in the NVMe commit queue. The controller maintains an internal queue head pointer and retrieves each SQE (Submission Queue Entries) sequentially from the position pointed to by this pointer, until it reaches the new queue tail pointer position written by the host. For each retrieved SQE, it first checks if its opcode is a read type. If so, it extracts the starting logical block address field, which is the input logical block address. Next, the controller uses the same hash algorithm and parameters as when the target bit array was generated to calculate this input logical block address. For example, it applies the MurmurHash3 function and takes the modulo of the bit array size (e.g., 65536) to obtain a bit position index, calculated as: Index to be Queryed = MurmurHash3(Input Logical Block Address) MOD 65536, then access the bit corresponding to the index in the target bit array and check if its value is 1 (valid state). If the bit value is 1, it means that the input logic block address is a member of the expected knock sequence. The controller then stores this input logic block address, along with its command identifier (CID) in the submission queue and the current arrival timestamp generated by the controller's internal high-precision timer, into a temporary list located in the controller's internal SRAM. If the bit value corresponding to the bit position index is 0 (invalid state), the address is considered an irrelevant instruction, and the controller will filter it out from the current knock sequence verification process, but it will still continue the subsequent IO processing process as a normal read instruction (usually returning an error due to access restrictions). Through continuous scanning, verification, and filtering of all new instructions in the queue, all retained input logic block addresses and their associated information are finally collected to construct the hit address set.

[0025] The steps for obtaining a noisy input sequence are as follows: Read the arrival timestamp of each matched logical block address in the hit address set, arrange the matched logical block addresses in order of arrival timestamp, count the non-hit read instructions and non-hit write instructions that occur between two adjacent matched logical block addresses, obtain the number of irrelevant read and write instructions between consecutive valid addresses, bind the matched logical block addresses, arrival timestamps, and number of irrelevant read and write instructions in the same arrangement position to form an address arrangement content with interval interference markers, and generate a noisy input sequence.

[0026] Specifically, the arrival timestamp of each matching logical block address in the hit address set is read. First, all entries in the entire hit address set are sorted in ascending order based on their arrival timestamp fields to ensure that the processing order of the addresses matches their actual arrival order with the controller. After sorting, the controller initializes an irrelevant instruction counter to 0 and begins traversing the sorted hit address set. Starting from the first valid address, the controller backtracks and checks the original instruction stream it has processed (including all instructions that are hits and misses). It counts the total number of all miss read instructions and miss write instructions processed from the time the previous valid address appeared until the time the current valid address appeared. This total number is the irrelevant read / write instruction count between these two consecutive valid addresses. Let the count be, for example, if the controller also processes 3 irrelevant read instructions and 2 irrelevant write instructions between the sorted hit addresses A and B, then the number of irrelevant read and write instructions in this interval is 5, and this count value of 5 is bound and stored with the next arriving hit address B. For the first hit address in the set, the number of its preceding irrelevant instructions is the total number of irrelevant instructions encountered from the start of the listening state until the address appears. By calculating and associating such a preceding interval count value for each hit address in the set except for the first element, a composite data structure sequence is finally formed, in which each element contains the hit matching logical block address, the sorted arrival timestamp, and a number of irrelevant read and write instructions that quantifies the degree of interference in the instruction stream, generating a noisy input sequence.

[0027] The steps to obtain the sequence edit distance parameter are as follows: The input address elements in the noisy input sequence are read one by one according to their arrangement positions. The standard address elements in the pseudo-random logic block address sequence are read according to the same arrangement positions. The address values, arrangement positions, and missing states of the input address elements are compared bit by bit. If the address value of the input address element is different from the address value of the standard address element, or if there is no input address element with the same arrangement position in the noisy input sequence, the number of element differences is accumulated once to obtain the sequence edit distance parameter.

[0028] Specifically, the input address elements in the noisy input sequence are read item by item according to their arranged positions. Here, "arranged positions" refers to the index positions of the noisy input sequence after sorting by arrival timestamps. Simultaneously, the standard address elements in the pre-generated and stored pseudo-random logic block address sequence are read item by item according to their original, undisturbed arranged positions. To calculate the difference between the two sequences, a dynamic programming method is used to calculate their edit distance. Specifically, a two-dimensional matrix D is created with dimensions (m+1) x (n+1), where m is the length of the noisy input sequence and n is the length of the pseudo-random logic block address sequence. Each element D(i, j) of the matrix represents the minimum number of edit operations (including insertion, deletion, and replacement) required to transform the first i elements of the noisy input sequence into the first j elements of the pseudo-random logic block address sequence. The first row and first column of the matrix are initialized: D(i, 0) = i, D(0, j) = j. Then, the remaining part of the matrix is ​​filled iteratively. For each element D(i, j)... The value of D(i, j) is calculated according to the following rules: if the value of the i-th address in the noisy input sequence is equal to the value of the j-th address in the pseudo-random logic block address sequence, then the replacement cost is 0; otherwise, it is 1. The value of D(i, j) is taken from the minimum value of its three adjacent elements to its left, above, and upper left, and adjusted according to the replacement cost. The calculation formula is as follows: In this context, cost is 0 when the address values ​​are the same and 1 when they are different. i and j represent the row and column indices of the matrix, respectively. After the entire matrix is ​​filled, the value of the element D(m, n) located in the lower right corner of the matrix is ​​the minimum edit distance between the two sequences. This value is recorded to obtain the sequence edit distance parameter.

[0029] The steps to obtain the access authorization trigger command are as follows: Continue calling the noisy input sequence and the pseudo-random logic block address sequence, extract the arrival time sorting position of each input address element in the noisy input sequence, extract the standard sorting position of the same address element in the pseudo-random logic block address sequence, compare the arrival time sorting position with the standard sorting position item by item, if the arrival time order of any two input address elements is different from the standard order order in the pseudo-random logic block address sequence, then accumulate one sorting reversal record to obtain the position reversal count; The system calls the sequence editing distance parameter and the number of irrelevant read / write commands in the noisy input sequence. It compares the number of irrelevant read / write commands item by item with a preset anti-brute-force threshold. If the number of irrelevant read / write commands does not exceed the preset anti-brute-force threshold, it compares the position inversion count with a preset out-of-order tolerance threshold and the sequence editing distance parameter with a preset fault tolerance threshold. If the position inversion count meets the preset out-of-order tolerance threshold and the sequence editing distance parameter meets the preset fault tolerance threshold, it retains the authorization determination state of the current noisy input sequence. If any comparison result does not meet the corresponding set threshold condition, it discards the current noisy input sequence, resets the listening state, and generates an access authorization trigger command.

[0030] Specifically, continuing to call the noisy input sequence and the pseudo-random logic block address sequence, to calculate the position inversion count, first a mapping table is created to store the correspondence between each address element in the pseudo-random logic block address sequence and its standard sorting position (i.e., array index). For example, address A has an index of 0 in the standard sequence, address B has an index of 1, and so on. Then, the noisy input sequence sorted by arrival time is traversed. For each input address element, the aforementioned mapping table is used to find its standard sorting position in the standard sequence, thus obtaining a new integer sequence P. The value of the i-th element of sequence P is the original index of the i-th arrived address in the noisy input sequence in the standard sequence. For example, if the arrival order of the noisy sequence is [address C, address A, address B], and the standard sequence is [address A, address B, address C], then the generated integer sequence P is [2, 0, 1]. Then, the number of inversion pairs of this integer sequence P is calculated. An inversion pair is any pair of elements P[i] and P[j] in the sequence that satisfies i < j but P[i] > 1. The condition for P[j] can be calculated using a nested loop: the outer loop iterates from i=0 to the sequence length -2, and the inner loop iterates from j=i+1 to the sequence length -1. In the loop, the values ​​of P[i] and P[j] are compared. If P[i] > P[j], a sorting inversion counter initialized to 0 is incremented by 1. After the traversal is completed, the final value of the counter is the indicator of the degree of disorder in the sequence, and the position inversion count is obtained.

[0031] The system invokes the sequence editing distance parameter and the number of irrelevant read / write instructions in the noisy input sequence to initiate a three-level verification process to determine the validity of the authorization request. The first level of verification is a defense against brute-force attacks. It checks the number of irrelevant read / write instructions between each consecutive valid address segment recorded in the noisy input sequence and compares it with a preset anti-brute-force threshold. This threshold is set based on statistical analysis of normal system background I / O activity. For example, by sampling the I / O instruction stream of the system under idle and medium load conditions for one hour, the average number of irrelevant I / O operations and the standard deviation between any two related operations are calculated. The threshold is then set to 1.5 times the average plus one standard deviation. For example, if the calculated average is 4 and the standard deviation is 2, then the anti-brute-force threshold is... If the number of irrelevant instructions in any interval exceeds 8, it is immediately judged as an attack, the current sequence is discarded and the listening state is reset. If all intervals meet the conditions, the second level of verification is entered, and the position inversion count calculated in the previous step is compared with the preset out-of-order tolerance threshold. This threshold is set empirically based on the sequence length and network latency characteristics. For example, for a sequence of length 16, the maximum number of inversions that can be tolerated is set to 3. If the position inversion count is not greater than 3, the third level of verification is entered, and the sequence edit distance parameter is compared with the preset fault tolerance threshold. This threshold allows users to make a small number of errors when inputting the knocking sequence. For example, for a sequence of length 16, the fault tolerance threshold can be set to 2, allowing a maximum of two address errors or omissions. If both the position inversion count and the sequence edit distance parameter meet their respective threshold conditions, the authorization determination state of the current noisy input sequence is retained, and an access authorization trigger instruction is generated.

[0032] The specific steps to restore to an unauthorized locked state are as follows: In response to the access authorization trigger command, the solid-state drive controller reads the authorization identifier, generation timestamp, secure storage area index, and key retrieval permission bit from the access authorization trigger command. It verifies item by item whether the authorization identifier is valid, whether the generation timestamp falls within the authorization time window, and whether the key retrieval permission bit corresponds to the secure storage area index. If the authorization identifier is valid, the generation timestamp falls within the authorization time window, and the key retrieval permission bit corresponds to the secure storage area index, then the key reading channel of the secure storage area is opened. The key bytes are read from the key storage location of the access authorization trigger command pointed to by the secure storage area index to obtain the master encryption key. The solid-state drive controller reads the page address, block number, offset, and length identifier of the encrypted data block from the underlying flash memory medium. It locates the physical page of the underlying flash memory medium according to the page address, locks the corresponding storage block according to the block number, extracts the encrypted byte segment to be processed according to the offset, limits the reading boundary of the encrypted byte segment to be processed according to the length identifier, loads the master encryption key into the key operation register in the memory of the solid-state drive controller, and restores the encrypted byte segment to be processed block by block into readable byte content to generate plaintext data payload. The solid-state drive controller reads the target logical block address, read length, host-side memory space address, and transmission interface bus queue identifier from the subsequent data read request issued by the host. It locates the payload segment to be returned from the plaintext data payload according to the target logical block address, segments the payload segment to be returned according to the read length, writes the segmented payload segment to be returned to the transmission interface bus according to the transmission interface bus queue identifier, and completes the write confirmation according to the host-side memory space address. After the subsequent data read request is completed or the authorization time window expires, it clears the master encryption key in the solid-state drive controller's memory, revokes the validity of the access authorization trigger instruction, and restores the controller to the unauthorized locked state.

[0033] Specifically, in response to the access authorization trigger command, the security state machine within the SSD controller receives an internal signal containing an authorization identifier, a generation timestamp, a secure storage area index, and a key retrieval permission bit. The controller first verifies whether the authorization identifier is a predefined valid pattern, such as 0x5A5A. Then, it reads the controller's internal real-time clock counter and compares it with the generation timestamp in the command, calculating the time difference. This difference must be less than a preset authorization time window, such as 100 milliseconds. This window value is designed to balance operational convenience with security against command replay attacks. If the timestamp verification passes, the controller further checks whether the key retrieval permission bit in the command matches the secure storage area index; this is a hardware-level verification. For example, if the index points to security zone 0, the permission bits must be specific values ​​bound to zone 0 to prevent privilege escalation attacks. Once all verification items (valid authorization identifier, timestamp within the window, and matching permission bits) are confirmed, the controller will temporarily unlock the hardware lock on the specific secure storage area. The specific operation may involve writing a specific configuration to the memory management unit to temporarily map the physical memory area to an accessible address space. Subsequently, the controller reads a predetermined length of bytes from the specified offset position of the secure storage area according to the secure storage area index, such as reading 32 bytes starting from index 0x100. This process does not go through any buffer and is a direct register-to-register or SRAM transfer. The obtained bytes are the master encryption key required for subsequent decryption operations.

[0034] The solid-state drive (SSD) controller reads the encrypted data block page address, encrypted data block number, encrypted data block offset, and encrypted data block length identifier from the underlying flash memory medium. After obtaining the master encryption key, the controller, based on the logical block address in subsequent regular data read requests from the host, queries its internal logical-to-physical address translation table (LBA) to parse the LBA into specific physical storage location information. This information includes the address of the flash memory chip, channel, block, and page where the data resides—that is, the encrypted data block page address and block number. Simultaneously, the L2P table also records the starting offset and length of the data within the physical page. The controller first loads the master encryption key obtained from the secure storage area into its internally integrated dedicated advanced encryption... The key register of the AES hardware encryption / decryption engine is used to configure the engine's operating mode according to the encryption mode (e.g., AES-XTS). Then, the controller sends instructions to the flash memory controller to read complete encrypted data pages or blocks containing the target data from the NAND flash memory medium based on the parsed physical address information. These ciphertext byte segments are then sent to the data input port of the AES hardware engine. The AES engine uses the loaded master encryption key and sector information (for XTS mode adjustment) to perform high-speed decryption operations on the input ciphertext byte segments. The processed readable byte content is then output to a dedicated DRAM buffer inside the controller to generate plaintext data payload.

[0035] The solid-state drive (SSD) controller reads the target logical block address, read length, host-side memory space address, and transfer interface bus queue identifier from the subsequent data read request issued by the host. Based on the target logical block address and read length in the request, it precisely locates the data segment actually needed by the host within the plaintext data payload that has already been decrypted in its internal DRAM buffer. This data segment is then divided according to the requested read length to obtain the payload segment to be transmitted back. Next, the controller obtains the physical address in the host memory used to receive the data based on the physical region page list or scatter / aggregate list specified in the request. The controller configures its internal Direct Memory Access (DMA) engine to directly transfer the payload segment to be transmitted back from the controller's DRAM buffer to the host's specified memory physical address via the PCIe bus. After the transfer is complete, the controller constructs a completion queue entry containing the corresponding data segment. The command identifier and operation success status code are written to the completion queue specified by the host. Then, the host is notified that the data transmission is complete via interrupt or host polling. At the same time, an authorization timer inside the controller runs continuously. The timeout period of this timer is the authorization time window, for example, set to 5 seconds. This value is set based on a security policy trade-off to minimize exposure risk while providing sufficient operation time. Once all subsequent data read requests are completed, or the authorization timer expires, the controller immediately executes a security cleanup procedure: first, it completely overwrites and clears the copy of the master encryption key stored in the internal key register and SRAM by writing all zeros or random data multiple times; then, it resets the internal authorization status flag and revokes the special memory mapping of the secure storage area, restoring it to a hardware-locked, inaccessible state, and returning it to an unauthorized locked state.

[0036] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A data security access authorization method for solid-state drives, characterized in that, Includes the following steps: Based on the preset shared seed key, a pseudo-random logical block address sequence is generated within the non-sensitive reserved address range of the solid-state drive, and a ring buffer is opened in the controller to establish a bit array storage structure restricted by the overflow prevention threshold condition, which is then mapped to generate the target bit array. The host sends a read request command based on the pseudo-random logical block address sequence; the controller scans the NVMe protocol queue, verifies the input logical block address based on the target bit array, and constructs a set of hit addresses containing the matched logical block addresses; Count the number of irrelevant read / write instructions between consecutive valid addresses and sort them by arrival time to generate a noisy input sequence; Extract the sequence edit distance parameter and position inversion count between the noisy input sequence and the pseudo-random sequence; compare the number of irrelevant read / write instructions, position inversion count, and sequence edit distance parameter with preset anti-brute-force threshold, out-of-order tolerance threshold, and fault tolerance threshold respectively. If all conditions are met, generate an access authorization trigger instruction; otherwise, reset the monitoring state. In response to the access authorization trigger command, the master encryption key is retrieved from the secure storage area, the ciphertext data block is decrypted into plaintext data payload, and the data is returned in response to subsequent data read requests; after the request is completed or the authorization time window expires, the master encryption key is destroyed and the command is revoked, restoring the state to unauthorized lock. The steps for obtaining the sequence edit distance parameter are as follows: The input address elements in the noisy input sequence are read one by one according to their arrangement positions. The standard address elements in the pseudo-random logic block address sequence are read according to the same arrangement positions. The address values, arrangement positions, and missing states of the input address elements are compared bit by bit. If the address value of the input address element is different from the address value of the standard address element, or if there are no input address elements with the same arrangement positions in the noisy input sequence, the number of element differences is accumulated once to obtain the sequence edit distance parameter. The steps for obtaining the access authorization trigger instruction are as follows: Continue calling the noisy input sequence and the pseudo-random logic block address sequence, extract the arrival time sorting position of each input address element in the noisy input sequence, extract the standard sorting position of the same address element in the pseudo-random logic block address sequence, compare the arrival time sorting position and the standard sorting position item by item, if the arrival time order of any two input address elements is different from the standard order order in the pseudo-random logic block address sequence, then accumulate one sorting reversal record to obtain the position reversal count; The sequence edit distance parameter and the number of irrelevant read / write instructions in the noisy input sequence are called. The number of irrelevant read / write instructions is compared with a preset anti-brute-force threshold item by item. If the number of irrelevant read / write instructions does not exceed the preset anti-brute-force threshold, the position inversion count is compared with a preset out-of-order tolerance threshold, and the sequence edit distance parameter is compared with a preset fault tolerance threshold. If the position inversion count meets the preset out-of-order tolerance threshold and the sequence edit distance parameter meets the preset fault tolerance threshold, the current authorization determination state of the noisy input sequence is retained. If any comparison result does not meet the corresponding set threshold condition, the current noisy input sequence is discarded and the listening state is reset, and an access authorization trigger instruction is generated.

2. The data security access authorization method for solid-state drives according to claim 1, characterized in that, The steps for obtaining the pseudo-random logical block address sequence are as follows: Write a shared seed key into the host-side key storage unit and the solid-state drive controller key register unit. Read the key byte sequence from the host-side key storage unit and the key byte sequence from the solid-state drive controller key register unit. Compare the character value, length value, and arrangement order of the two key byte sequences bit by bit according to the byte position. If the character value, length value, and arrangement order are all consistent, the shared seed key is retained as the input basis for subsequent address generation. If any character value, length value, or arrangement order is inconsistent, the address generation process is terminated, and the shared seed key is obtained. The current round input byte sequence corresponding to the shared seed key is read round by round according to the preset iteration rounds. Irreversible compression transformation is performed on the current round input byte sequence. Numerical fragments are extracted from the output digest of each round. The numerical fragments are converted into candidate logical block address values. The start boundary value, end boundary value, and interval span value of the non-sensitive reserved address interval of the solid-state drive are called. The remainder is applied to the candidate logical block address values ​​so that the applied logical block addresses fall into the non-sensitive reserved address interval of the solid-state drive. The applied logical block addresses are arranged according to the iteration round order to generate a pseudo-random logical block address sequence.

3. The data security access authorization method for solid-state drives according to claim 1, characterized in that, The steps for obtaining the target bit set are as follows: In the solid-state drive controller's memory space, a contiguous buffer storage segment is defined. The write pointer, read pointer, and wraparound boundary identifier of the contiguous buffer storage segment are configured as ring buffer control parameters. A bit array storage structure with equal or compressed mapping is established according to the number of address elements in the pseudo-random logical block address sequence. Each address element in the pseudo-random logical block address sequence is read and converted into a bit position index in the bit array storage structure. The occupied quantity between the write pointer and the read pointer is detected. If the occupied quantity does not reach the overflow prevention threshold, the bit value corresponding to the bit position index is set to a valid state. If the occupied quantity reaches the overflow prevention threshold, writing address elements is stopped, and the target bit array is obtained.

4. The data security access authorization method for solid-state drives according to claim 1, characterized in that, The steps for obtaining the set of hit addresses are as follows: The host invokes the pseudo-random logical block address sequence, reads the address elements in the pseudo-random logical block address sequence one by one, writes each address element into the logical block address field of the read request instruction, marks the operation type field of the read request instruction as the read type, fills the submission order field of the read request instruction according to the arrangement position of the address elements in the pseudo-random logical block address sequence, submits the filled read request instruction to the command receiving port of the solid-state drive, and generates a read request instruction. The solid-state drive controller calls the target bit array and scans the read request instructions one by one from the head to the tail of the NVMe protocol queue. It reads the logical block address field in the read request instruction, converts the logical block address field into an input logical block address, and maps the input logical block address to the bit position index in the target bit array. If the bit value corresponding to the bit position index is valid, the input logical block address is retained. If the bit value corresponding to the bit position index is not valid, the input logical block address is filtered. The retained input logical block addresses are collected according to the scanning order to construct a set of hit addresses.

5. The data security access authorization method for solid-state drives according to claim 1, characterized in that, The steps for obtaining the noisy input sequence are as follows: Read the arrival timestamp of each matched logical block address in the set of hit addresses, arrange the matched logical block addresses in order of arrival timestamp, count the non-hit read instructions and non-hit write instructions that occur between two adjacent matched logical block addresses, obtain the number of irrelevant read and write instructions between consecutive valid addresses, bind the matched logical block addresses, arrival timestamps, and number of irrelevant read and write instructions in the same arrangement position to form an address arrangement content with interval interference markers, and generate a noisy input sequence.

6. The data security access authorization method for solid-state drives according to claim 1, characterized in that, The specific steps to restore to an unauthorized locked state are as follows: In response to the access authorization trigger command, the solid-state drive controller reads the authorization identifier, generation timestamp, secure storage area index, and key extraction permission bit from the access authorization trigger command. It verifies item by item whether the authorization identifier is valid, whether the generation timestamp falls within the authorization time window, and whether the key extraction permission bit corresponds to the secure storage area index. If the authorization identifier is valid, the generation timestamp falls within the authorization time window, and the key extraction permission bit corresponds to the secure storage area index, then the key reading channel of the secure storage area is opened, and the key byte content is read from the key storage location of the access authorization trigger command pointed to by the secure storage area index to obtain the master encryption key. The solid-state drive controller reads the page address, block number, offset, and length identifier of the encrypted data block from the underlying flash memory medium. It locates the physical page of the underlying flash memory medium according to the page address, locks the corresponding storage block according to the block number, extracts the encrypted byte segment to be processed according to the offset, limits the reading boundary of the encrypted byte segment to be processed according to the length identifier, loads the master encryption key into the key operation register in the memory of the solid-state drive controller, and restores the encrypted byte segment to be processed block by block into readable byte content to generate plaintext data payload. The solid-state drive controller reads the target logical block address, read length, host-side memory space address, and transmission interface bus queue identifier from the subsequent data read request issued by the host. It locates the payload segment to be transmitted back from the plaintext data payload according to the target logical block address, segments the payload segment to be transmitted back according to the read length, writes the segmented payload segment to be transmitted back to the transmission interface bus according to the transmission interface bus queue identifier, and completes the write confirmation according to the host-side memory space address. After the subsequent data read request is completed or the authorization time window expires, it clears the master encryption key from the solid-state drive controller's memory, revokes the validity of the access authorization trigger instruction, and restores the controller to an unauthorized locked state.

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