Power grid table conversion method, device, equipment, storage medium and product

Abstract

The application discloses an electrical network table conversion method, device, equipment, storage medium and product, relates to the network table automation technical field, and the electrical network table conversion method comprises the steps of obtaining a target model and traversing a component tree of the target model to read class information of a component; for a current component traversed, querying a pre-stored component mapping table, if a hit is obtained, obtaining corresponding deterministic mapping rules from the component mapping table, if a miss is obtained, calling a large language model, generating candidate mapping rules from the large language model according to the class information of the current component, and performing validity verification on the candidate mapping rules, and after the verification is passed, storing the candidate mapping rules as new mapping rules in the component mapping table; determining a network table line corresponding to the current component according to the deterministic mapping rules or the new mapping rules obtained from the component mapping table; and aggregating the network table lines corresponding to the components to generate an electrical network table. The application solves the technical problem of poor consistency in the electrical network table conversion process.

Description

Technical Field

[0001] This application relates to the field of netlist automation technology, and in particular to electrical netlist conversion methods, devices, equipment, storage media and products. Background Technology

[0002] In engineering scenarios such as power electronics, multi-domain coupled systems, and co-simulation of control algorithms, it is often necessary to convert models that are equation-oriented and hierarchical component descriptions into fixed-format electrical netlists or instruction sequences to interface with external solvers, real-time simulation platforms, or hardware-in-the-loop systems. Conventional techniques primarily rely on manually maintained mapping rule libraries. This involves pre-configuring rules for full type names, pin lists, parameter mappings, etc., and then having a rule engine convert each component in the model into a netlist row in a specific direction.

[0003] However, conventional techniques suffer from significant limitations in scalability in practical applications. When new component libraries or custom components are introduced into the model, a large number of mapping configurations need to be manually written or modified, resulting in high rule maintenance costs and a high risk of omissions or errors. Furthermore, pure rule engines based on conventional techniques struggle to handle non-standard naming conventions, annotated components, hierarchical path combinations, and complex topologies (such as signal routing blocks and control signal tracing), leading to semantic gaps in the conversion process and inconsistencies between the generated netlist and the actual connection relationships or parameter values ​​of the original model.

[0004] To address the aforementioned issues of insufficient scalability and semantic gaps, some improvement solutions have attempted to enhance transformation capabilities through more robust configuration management or more complex rule branching code. However, these solutions still rely on the pre-defined deterministic rules and cannot dynamically adapt to unknown component types or ambiguous semantic scenarios. Furthermore, the generated netlist lacks an effective consistency verification mechanism between itself and the simulation settings and parameter values ​​in the modeling environment, resulting in poor reliability of the netlist generation results. Summary of the Invention

[0005] The main objective of this application is to provide an electrical grid meter conversion method, apparatus, device, storage medium, and product, which aims to solve the technical problem of poor consistency in the electrical grid meter conversion process in conventional technologies.

[0006] To achieve the above objectives, this application proposes an electrical network meter conversion method, the method comprising: Obtain the target model and traverse the component tree of the target model to read the class information of the components; For the current component being traversed, the pre-stored component mapping table is queried. If a match is found, the corresponding deterministic mapping rule is obtained from the component mapping table. If no match is found, the large language model is called. The large language model generates candidate mapping rules based on the class information of the current component, and the validity of the candidate mapping rules is verified. If the verification is successful, the new mapping rule is stored in the component mapping table. The netlist row corresponding to the current component is determined based on the deterministic mapping rule obtained from the component mapping table or the new mapping rule. Aggregate the netlist rows corresponding to all components to generate an electrical netlist.

[0007] In one embodiment, the class information includes the fully qualified name of each component type, the short name of the component, the pin list, and the documentation text. The step of obtaining the target model and traversing the component tree of the target model to read the class information of the components includes: Read the current model key value from the class manager, and locate the target model based on the current model key value; Recursively traverse the component tree of the target model, skipping components that are masked by annotations; Read the full name of the type, the short name of the component, the pin list, and the documentation text for each component.

[0008] In one embodiment, the validity check includes syntactic validity check and graph theory consistency check. The step of calling the large language model, generating candidate mapping rules based on the class information of the current component, and performing validity check on the candidate mapping rules includes: Assemble the fully qualified class name, documentation text, and pin list of the current component into a prompt word and input it into the large language model; Receive candidate mapping rules that conform to a predetermined data format output by the large language model; Based on a predetermined data format, the candidate mapping rules are subjected to syntax validity verification. The candidate mapping rules are subjected to graph theory consistency verification, which includes checking the number of connections, the existence of ground nodes, and the existence of power nodes.

[0009] In one embodiment, the netlist row includes a network name, parameter string, dedicated signal connection row, and control signal row. The step of determining the netlist row corresponding to the current component based on the deterministic mapping rule obtained from the component mapping table or the new mapping rule includes: Based on the pin definitions in the deterministic mapping rule or the new mapping rule, determine the network names to which the positive and negative pins of the current component are connected; Based on the parameter fields in the deterministic mapping rule or the new mapping rule, read the corresponding parameter values ​​from the target model and format them as parameter strings; When the current component is marked as a signal routing block, a dedicated signal connection row in the corresponding netlist row is generated based on the number of ports in the signal routing block. When the current component contains control variables, trace the signal source of the control variables along the connection diagram, and generate the corresponding control signal row in the netlist row based on the tracing result.

[0010] In one embodiment, the step of aggregating the netlist rows corresponding to all components to generate an electrical netlist includes: Read the preset partition annotations for each component, which are used to indicate the computation partition to which the component belongs; Based on the preset partition annotations, the netlist rows obtained from the conversion of each component are written into the corresponding partition string; When the current component does not have the preset partition annotation, the netlist row of the current component is written into the preset default partition string; Each partition string is output as the partition netlist text, and all partition netlist texts are aggregated to obtain the electrical netlist.

[0011] In one embodiment, after determining the netlist row corresponding to the current component, the method further includes: Retrieve the parameter string from the netlist row corresponding to the current component; The parameter string is compared with the actual parameter values ​​of the corresponding components in the target model; When the comparison results are inconsistent, mark the netlist behavior of the current component as pending correction. The netlist row in the state to be corrected is re-input into the large language model, which then generates a corrected parameter string based on the actual parameter values ​​and replaces the corresponding part in the original netlist row.

[0012] Furthermore, to achieve the above objectives, this application also proposes an electrical grid meter conversion device, which includes: The acquisition module is used to acquire the target model and traverse the component tree of the target model to read the class information of the components; The query module is used to query the pre-stored component mapping table for the current component being traversed. If a match is found, the corresponding deterministic mapping rule is obtained from the component mapping table. If no match is found, the large language model is called. The large language model generates candidate mapping rules based on the class information of the current component and performs validity verification on the candidate mapping rules. If the verification is successful, the new mapping rule is stored in the component mapping table. The conversion module is used to determine the netlist row corresponding to the current component based on the deterministic mapping rule obtained from the component mapping table or the new mapping rule; The aggregation module is used to aggregate the netlist rows corresponding to all components to generate an electrical netlist.

[0013] In addition, to achieve the above objectives, this application also proposes an electrical grid meter conversion device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the electrical grid meter conversion method as described above.

[0014] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the electrical netlist conversion method described above.

[0015] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the electrical netlist conversion method described above.

[0016] One or more technical solutions proposed in this application have at least the following technical effects: Compared to related technologies that rely on manual maintenance of mapping rules or pure rule engine conversion, which can easily lead to semantic discrepancies, misaligned connections, and inconsistent parameter values ​​between the netlist and the original model, this application achieves the following: First, it obtains the target model and traverses its component tree to read the class information of the components. Then, for each traversed component, it queries a pre-stored component mapping table. If a match is found, the corresponding deterministic mapping rule is obtained from the component mapping table. If no match is found, a large language model is invoked, which generates candidate mapping rules based on the class information of the current component. The candidate mapping rules are then validated, and if valid, they are stored as new mapping rules in the component mapping table. Finally, based on the deterministic mapping rule obtained from the component mapping table or the new mapping rule, the netlist row corresponding to the current component is determined. Finally, all netlist rows corresponding to all components are aggregated to generate an electrical netlist.

[0017] Understandably, this application employs a step where, when a mapping rule for the current component does not exist in the component mapping table, a large language model is invoked to generate candidate mapping rules based on the component's class information, and then validity verification is performed. This achieves dynamic generation and reliability verification of mapping rules for unknown component types. Therefore, conversion is performed based on the rules stored in the mapping table after the validity verification is passed, ensuring that the mapping rules for each component are strictly consistent with the semantics and port definitions of the original model. This ensures that the converted netlist rows accurately reflect the connection relationships and parameter values ​​in the model, ultimately completing the entire process of consistent conversion from the target model to the electrical netlist. This solves the technical problem of poor consistency in the electrical netlist conversion process in conventional technologies. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating an embodiment of the electrical network meter conversion method of this application. Figure 2 This is a flowchart illustrating Embodiment 2 of the electrical network meter conversion method of this application; Figure 3 This is a flowchart illustrating Embodiment 3 of the electrical network meter conversion method of this application; Figure 4 This is a flowchart illustrating Embodiment 3 of the electrical network meter conversion method of this application; Figure 5 This is a flowchart illustrating Embodiment 3 of the electrical network meter conversion method of this application; Figure 6 This is a schematic diagram of the module structure of the electrical network table conversion device according to an embodiment of this application; Figure 7 This is a schematic diagram of the equipment structure of the hardware operating environment involved in the electrical netlist conversion method in this application embodiment.

[0021] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0023] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0024] The main solution in this application's embodiments is: Obtain the target model and traverse the component tree of the target model to read the class information of the components; For the current component being traversed, the pre-stored component mapping table is queried. If a match is found, the corresponding deterministic mapping rule is obtained from the component mapping table. If no match is found, the large language model is called. The large language model generates candidate mapping rules based on the class information of the current component, and the validity of the candidate mapping rules is verified. If the verification is successful, the new mapping rule is stored in the component mapping table. The netlist row corresponding to the current component is determined based on the deterministic mapping rule obtained from the component mapping table or the new mapping rule. Aggregate the netlist rows corresponding to all components to generate an electrical netlist.

[0025] In this embodiment, the application uses an electrical grid meter conversion device as the execution subject. For ease of description, it will be referred to as "device" in detail below.

[0026] Because conventional electrical netlist conversion mainly relies on manually maintained mapping rule bases, a large number of mapping configurations need to be manually written when new components or private libraries are introduced into the model, resulting in insufficient scalability of the conversion process. At the same time, pure rule engines have difficulty handling semantic scenarios such as non-standard naming, annotated components, complex topology structures, and control signal tracing. Furthermore, the generated netlist lacks a consistency verification mechanism between the simulation settings and parameter values ​​in the modeling environment, resulting in misaligned connection relationships or parameter value deviations between the netlist and the original model, leading to poor consistency.

[0027] This application provides a solution that enables a conversion system to automatically adapt to unknown component types and ensures that the netlist output is strictly consistent with the original model. The overall principle behind this application in solving the above problems lies in constructing a dual-path conversion framework that coordinates deterministic rules and a large language model. For component types already existing in the mapping table, a deterministic conversion path is followed to ensure processing efficiency and repeatability. For component types missing from the mapping table, the large language model is invoked to generate candidate mapping rules based on the component's class information, port definitions, and document text. The validity of these candidate rules is verified through syntax validation and graph theory consistency checks. Once verified, the mapping table is dynamically expanded, giving the conversion system self-expansion capabilities. Simultaneously, by tracing the mapping rules and parameter values ​​used in the conversion process back to the class information and actual parameter values ​​in the original model, and supplemented by parameter comparison and correction mechanisms, it is ensured that the netlist rows obtained from each component conversion maintain consistency with the connection relationships and parameter values ​​in the original model.

[0028] This embodiment aims to improve the scalability and consistency of electrical netlist conversion. The research background addressed in this embodiment is the engineering problem of diverse model component types, frequent updates to private libraries, and the difficulty of existing rule engines to dynamically adapt in multi-physics domain modeling environments. The application scenario addressed in this embodiment is the conversion of models oriented towards equations and hierarchical component descriptions into electrical netlist text for hardware-in-the-loop simulation or real-time platform interfacing. Through the aforementioned collaborative framework, this application can automatically expand the mapping rule base without manual intervention, while ensuring the traceability and reliability of the netlist generation results, thereby overcoming the technical problems of insufficient scalability and poor consistency in conventional technologies.

[0029] Based on this, embodiments of this application provide an electrical network meter conversion method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the electrical network meter conversion method of this application.

[0030] In this embodiment, the electrical grid meter conversion method includes steps S10 to S40: Step S10: Obtain the target model and traverse the component tree of the target model to read the class information of the components; It should be noted that the target model refers to the model to be converted corresponding to the current model key value obtained from the class manager. This model includes, but is not limited to, hierarchical descriptions of electrical systems, control subsystems, and multi-physical domain coupled systems. The component tree refers to the tree-shaped data structure in which all components in the target model are organized in a hierarchical manner, where each node represents a component instance. Class information refers to the type definition information of the component, including but not limited to the full name of the type, the short name of the component, the pin list, and the documentation text.

[0031] Understandably, this step obtains the target model and traverses its component tree to read the class information of the components, providing a complete and accurate source of component data for subsequent mapping queries and netlist conversions, ensuring that the conversion process can cover all valid components in the model.

[0032] Step S20: For the current component that is traversed, query the pre-stored component mapping table. If a match is found, obtain the corresponding deterministic mapping rule from the component mapping table. If no match is found, call the large language model. The large language model generates candidate mapping rules based on the class information of the current component and performs validity verification on the candidate mapping rules. After the verification is passed, store them as new mapping rules in the component mapping table. It should be noted that the component mapping table is a pre-configured data set used to store the correspondence between component types and conversion rules. Each record in this mapping table includes, but is not limited to, the component type identifier, pin definitions, parameter field mappings, and a flag indicating whether a netlist is output. Deterministic mapping rules refer to fixed rules that can be directly obtained from the component mapping table and used for conversion without additional processing. The large language model refers to a deep learning model trained on a large-scale corpus that can understand and generate natural language and structured data. Candidate mapping rules refer to structured conversion rule data generated by the large language model based on the component class information. Its format includes, but is not limited to, pin positive and negative definitions, parameter mapping relationships, and netlist output flags. Validity verification refers to the quality check performed on candidate mapping rules. This check includes, but is not limited to, syntax format verification and graph theory consistency verification. Graph theory consistency verification includes checking the number of connections, the existence of ground nodes, and the existence of power nodes.

[0033] Understandably, this step first queries the pre-stored component mapping table. When a match is found, a deterministic mapping rule is directly obtained to ensure conversion efficiency. When a match is not found, a large language model is called to generate candidate mapping rules, and the mapping table is dynamically expanded after validity verification. This allows the mapping rule library to automatically expand as the conversion process progresses, adapting to unknown component types without manual intervention, thereby improving the scalability of the conversion method.

[0034] Step S30: Determine the netlist row corresponding to the current component based on the deterministic mapping rule obtained from the component mapping table or the new mapping rule; It should be noted that a netlist line refers to a text line describing a single electrical component instance. This text line includes, but is not limited to, the component instance name, the network name to which the pins are connected, and the component's parameter strings.

[0035] Understandably, this step converts the current component into the corresponding netlist row based on the mapping rules obtained from the component mapping table, ensuring that the conversion result of each component is consistent with the connection relationships and parameter values ​​in the original model, thus providing accurate netlist fragments for subsequent aggregation output.

[0036] Step S40: Aggregate the netlist rows corresponding to all components to generate an electrical netlist.

[0037] It should be noted that an electrical netlist is a text file that aggregates the netlist rows corresponding to all components in a predetermined order. This file is used to describe the topology and parameter configuration of a complete electrical system.

[0038] Understandably, this step completes the entire process of converting the target model into an electrical netlist by aggregating the netlist rows corresponding to all components and outputting the electrical netlist. The output electrical netlist can be directly used for integration with external solvers, hardware-in-the-loop simulation, or real-time simulation platforms.

[0039] This embodiment provides an electrical netlist conversion method. When a mapping rule for the current component does not exist in the component mapping table, a large language model is invoked to generate candidate mapping rules based on the component's class information, and then validity verification is performed. This achieves dynamic generation and reliability verification of mapping rules for unknown component types. Therefore, conversion is performed based on the rules stored in the mapping table after validity verification, ensuring that the mapping rules for each component are strictly consistent with the semantics and port definitions of the original model. This ensures that the converted netlist rows accurately reflect the connection relationships and parameter values ​​in the model, ultimately completing a consistent conversion process from the target model to the electrical netlist. This solves the technical problem of poor consistency in the electrical netlist conversion process in conventional technologies.

[0040] In one feasible implementation, the class information includes the fully qualified name of each component type, the short name of the component, the pin list, and the documentation text. The step of obtaining the target model and traversing the component tree of the target model to read the class information of the components includes: Read the current model key value from the class manager, and locate the target model based on the current model key value; Recursively traverse the component tree of the target model, skipping components that are masked by annotations; Read the full name of the type, the short name of the component, the pin list, and the documentation text for each component.

[0041] It should be noted that the class manager refers to a system component in the modeling environment used to manage and access all class definitions in the model. This class manager provides application programming interfaces (APIs) for reading current model keys, traversing the component tree, and obtaining detailed component information. The current model key is an identifier or handle that uniquely identifies the currently opened model to be converted. Recursive traversal refers to a traversal method that starts from the root node of the component tree and visits each child node and its descendant nodes in a depth-first or breadth-first order. Components marked as annotations are components that are marked as annotations by the user in the model and do not participate in simulation or conversion; this marking is usually determined by the modeling team. The environment provides: The fully qualified type name (FQC) refers to the complete path name of the class to which the component belongs, including the namespace and class name; the short name of the component refers to the instance name of the component in the current model, used to uniquely identify the component instance; the pin list refers to the collection of electrical or signal ports that the component connects to, with each pin including its name and direction; the documentation text refers to the descriptive text accompanying the component class definition, describing the component's functions, parameters, and usage; and the pre-allocated component information cache refers to a temporary storage area in memory pre-allocated to temporarily store component information read during traversal, allowing for quick access in subsequent conversion steps.

[0042] It is understandable that this implementation locates the target model by reading the current model key value from the class manager, and uses a recursive traversal method to completely access all nodes in the component tree and skip components that are blocked by annotation marks, ensuring that only valid components are included in the conversion scope; at the same time, the read component information is stored in a preset component information cache to avoid repeatedly reading the class manager and improve conversion efficiency.

[0043] In one feasible implementation, the validity check includes syntactic validity check and graph theory consistency check. The step of calling the large language model, generating candidate mapping rules based on the class information of the current component, and performing validity check on the candidate mapping rules includes: Assemble the fully qualified class name, documentation text, and pin list of the current component into a prompt word and input it into the large language model; Receive candidate mapping rules that conform to a predetermined data format output by the large language model; Based on a predetermined data format, the candidate mapping rules are subjected to syntax validity verification. The candidate mapping rules are subjected to graph theory consistency verification, which includes checking the number of connections, the existence of ground nodes, and the existence of power nodes.

[0044] It should be noted that the prompt word refers to the natural language text assembled from the fully qualified class name, documentation text, and pin list of the current component according to a predetermined template. This text is used to guide the large language model to generate structured mapping rules that meet the requirements. The predetermined data format refers to the predefined data exchange specification, which specifies the field names, field types, number of occurrences of fields, and hierarchical relationships between fields that should be included in the candidate mapping rules. Syntax validation refers to checking whether the candidate mapping rules meet the specification requirements of the predetermined data format, including but not limited to field integrity validation, data type validation, and field value range validation. Graph theory consistency validation refers to performing a logical consistency check on the electrical topology described in the candidate mapping rules using graph theory methods. This check abstracts components as nodes and connections as edges to construct a topology graph. The number of connections refers to the total number of edges in the topology graph, used to compare with the number of actual connections in the original model. Ground node existence refers to checking whether there are ground nodes marked as reference zero potential in the topology graph. Power node existence refers to checking whether there are power-type nodes in the topology graph that can provide voltage or current excitation.

[0045] Understandably, this implementation assembles the fully qualified class name, documentation text, and pin list of the component into prompt words and inputs them into the large language model. This enables the large language model to fully understand the semantic information of the component and generate structured candidate mapping rules. By performing syntactic validation on the candidate mapping rules, it ensures that their format conforms to predetermined specifications, avoiding conversion failures caused by format errors. By performing graph theory consistency validation on the candidate mapping rules, it verifies the rationality and completeness of the mapping rules in electrical topology logic from three dimensions: the number of connections, the existence of ground nodes, and the existence of power nodes. This effectively suppresses the illusionary output that the large language model may produce and improves the reliability of the mapping rules.

[0046] In one feasible implementation, the netlist row includes a network name, parameter strings, dedicated signal connection rows, and control signal rows. The step of determining the netlist row corresponding to the current component based on the deterministic mapping rule obtained from the component mapping table or the new mapping rule includes: Based on the pin definitions in the deterministic mapping rule or the new mapping rule, determine the network names to which the positive and negative pins of the current component are connected; Based on the parameter fields in the deterministic mapping rule or the new mapping rule, read the corresponding parameter values ​​from the target model and format them as parameter strings; When the current component is marked as a signal routing block, a dedicated signal connection row in the corresponding netlist row is generated based on the number of ports in the signal routing block. When the current component contains control variables, trace the signal source of the control variables along the connection diagram, and generate the corresponding control signal row in the netlist row based on the tracing result.

[0047] It should be noted that pin definition refers to the correspondence between the positive and negative pins of a component specified in the mapping rules and the nodes in the electrical network. This definition includes, but is not limited to, pin name, pin direction, and the network identifier to which the pin is connected. Positive and negative pins refer to the two polarity ports of an electrical component used to connect to external circuits. The positive pin usually identifies the direction of current flow or the high potential end, while the negative pin identifies the direction of current flow or the low potential end. Together, they constitute the external connection point of the electrical component. The network name refers to the identifier name of the node in the electrical network obtained from the connection relationship analysis. This name is used to uniquely identify a set of pins that are interconnected through connection statements. The parameter field refers to the mapping relationship between the component parameters specified in the mapping rules and the parameter names in the target model. The parameter value refers to the specific numerical value or expression read from the target model corresponding to the parameter field. The parameter string refers to the text fragment converted from the parameter value according to the netlist format specification. Includes parameter names and values; a signal routing block refers to a module in the model specifically used for signal distribution and combination, including but not limited to multiplexers, demultiplexers, and signal selectors; the number of ports refers to the number of input or output ports contained in the signal routing block; a dedicated signal connection line refers to a line of text generated individually for each port of the signal routing block, which describes the routing relationship of signals from input to output; a control variable refers to a parameter marked as a controlled signal in the model, whose value is dynamically determined by other components or control algorithms rather than statically assigned; a connection diagram refers to a topological graphical structure composed of connection statements between components, which records the transmission paths of all electrical and control signals in the model; a signal source refers to the starting component or port in the connection diagram that serves as the origin of the control variable; a control signal line refers to a line of text generated based on the traced signal source, describing the source and transmission path of the control variable.

[0048] Understandably, this implementation method ensures that the port connection relationship of each component strictly corresponds to the electrical topology in the original model by determining the network name connected to the positive and negative pins according to the pin definition in the mapping rules; by reading parameter values ​​from the target model and formatting them into parameter strings, it ensures the accuracy of parameter values ​​and the standardization of the format; when the component is a signal routing block, it expands and generates multiple dedicated signal connection rows according to the number of ports, and expands the routing relationship of multiple signals one by one into an explicit connection description to avoid the loss of topology information; when the component contains control variables, it traces the signal source along the connection diagram and generates control signal rows, converting the dynamic control relationship into a static description that can be recognized by the netlist, thereby completely preserving the control semantics in the model and improving the consistency of netlist conversion.

[0049] In one feasible implementation, the step of aggregating the netlist rows corresponding to all components to generate an electrical netlist includes: Read the preset partition annotations for each component, which are used to indicate the computation partition to which the component belongs; Based on the preset partition annotations, the netlist rows obtained from the conversion of each component are written into the corresponding partition string; When the current component does not have the preset partition annotation, the netlist row of the current component is written into the preset default partition string; Each partition string is output as the partition netlist text, and all partition netlist texts are aggregated to obtain the electrical netlist.

[0050] It should be noted that the preset partition annotation refers to the marking information pre-attached to the component definition. This marking information is used to indicate the computing partition to which the component belongs. The computing partition includes, but is not limited to, the CPU partition, the FPGA partition, and the digital signal processor partition. The partition string refers to the text buffer in memory used to temporarily store all netlist rows belonging to the same computing partition. Each computing partition corresponds to an independent partition string. The preset default partition string refers to the text buffer pre-configured to store the netlist rows of components that do not have preset partition annotations. The computing partition corresponding to this default partition string is set as the default partition. The partition netlist text refers to the independent text file or text block obtained by outputting the contents of each partition string according to the netlist format specification.

[0051] Understandably, this implementation method reads the preset partition annotations of each component and writes the netlist rows corresponding to different computational partitions into their respective independent partition strings, thereby achieving component-level computational partition aggregation. When a component does not have a preset partition annotation, it is written into a preset default partition string to ensure that all components are reasonably assigned to a certain partition. Each partition string is output as a partition netlist text and aggregated to obtain an electrical netlist, enabling the final electrical netlist to directly support the hardware partitioning requirements in heterogeneous computing scenarios and improve the deployment flexibility of the netlist in hardware-in-the-loop simulation.

[0052] In one feasible implementation, after determining the netlist row corresponding to the current component, the method further includes: Retrieve the parameter string from the netlist row corresponding to the current component; The parameter string is compared with the actual parameter values ​​of the corresponding components in the target model; When the comparison results are inconsistent, mark the netlist behavior of the current component as pending correction. The netlist row in the state to be corrected is re-input into the large language model, which then generates a corrected parameter string based on the actual parameter values ​​and replaces the corresponding part in the original netlist row.

[0053] It should be noted that the parameter string refers to the text fragment in the generated netlist row that describes the component parameter values. This text fragment includes the parameter name and its corresponding numerical expression. The actual parameter value of the corresponding component in the target model refers to the original parameter value directly read from the component instance of the target model without any transformation processing. This actual parameter value serves as the benchmark truth value for comparison. The state to be corrected refers to the mark attached to the netlist row. This mark is used to indicate that the parameter string in the netlist row is inconsistent with the actual parameter value and needs to be corrected. The corrected parameter string refers to the parameter string text that the large language model regenerates based on the actual parameter value and replaces the corresponding part of the original netlist row.

[0054] Understandably, this implementation method obtains the parameter strings from the netlist rows after they are generated and compares them item by item with the actual parameter values ​​of the corresponding components in the target model. This allows for the timely detection of parameter deviations that may occur during the conversion process. When the comparison results are inconsistent, the netlist row is marked as needing correction and re-entered into the large language model. The large language model then generates a corrected parameter string based on the actual parameter values ​​and replaces the original part. This adds a parameter-level verification and correction step to the deterministic rule conversion or the initial generation of the large language model, eliminating parameter inconsistencies caused by inaccurate mapping rules, incorrect parameter reading, or format conversion errors, and further improving the consistency of electrical netlist conversion.

[0055] For example, this embodiment provides a method for converting a large-scale Modelica model to an electrical netlist, which can be deployed as a plugin in a Modelica modeling environment (e.g., the MWorksSysplorer class platform based on a class manager and graphical schematics). Figure 2 The diagram illustrates the overall architecture of this embodiment. The method includes a model reading and base information module, a component mapping and type parsing module, a connection analysis and hierarchy flattening module, a netlist row generation module, a large model-based verification and iteration module, and an output and delivery module.

[0056] Figure 3 The timing diagram of the large model's complement mapping and verification closed-loop is shown. For example... Figure 3 As shown, when the mapping table is missing, the system calls the large language model to generate candidate mappings, which are then verified and written back to the mapping library.

[0057] In the model reading and base information module, the current model key value is obtained through the class manager handle, and simulation settings (start and end times, step size, discrete algorithm, etc.) and the local Internet Protocol Address (IP address), algorithm and simulator information in the annotations are read to generate the netlist header base information block. This step corresponds to the readNetlistBaseMessage semantics in the project.

[0058] In the component mapping and type resolution module, the ModelicaComponent structure is maintained. This structure includes fields such as the fully qualified name of the type, abbreviated name, a list of positive and negative pins, whether it is three-phase, whether it is a transformer, whether it is a circuit breaker, whether it is a power supply, whether it outputs netlist text, and control and input / output signals. Mapping sources include pre-built JavaScript Object Notation (JSON) configuration files and table imports. When a type does not match the mapping table, the large language model is called: the input is the fully qualified class name, optional ExportDocumentation text, and a list of port names; the output is structured JSON (containing positive and negative pins, parameter fields, and whether it participates in netlist output), which is then written to the mapping library after schema validation and manual confirmation.

[0059] Figure 4 A flowchart illustrating the connection analysis and port mapping construction process is shown.

[0060] In the netlist row generation module, each electrical component is converted into a netlist message line according to the mapping: containing the instance name, pin network name, and parameter string. Control variables are traced from the wiring diagram to obtain control signals (getControlSignal). Circuit breakers, multiphase and output parameter mapping tables are formatted according to the configuration table branches (formatOutputParam). Writing to the root area and other partitions (corresponding to the OutputNetListStringPack structure in the project) is supported by Central Processing Unit (CPU) or Field-Programmable Gate Array (FPGA) partitions.

[0061] Figure 5 The OutputNetListStringPack partitioned output structure is shown. For example... Figure 5 As shown, based on the model type and number string in the annotation, the netlist is segmented and written to the root region and multiple CPU or FPGA sub-regions.

[0062] In the verification and iteration module involving the large model, a consistency check is performed: the generated netlist fragments are compared with the number of critical connections, grounding points, and power sources. If an anomaly is found, the large model is prompted to explain the missing connections or error types and provide repair suggestions (e.g., adding grounding points, correcting port names). For variable sets that require exporting dynamic link libraries (DLLs) or dynamic observations, the large model generates a list of candidate variable names from natural language requirements and then intersects it with the set of dynamic instructions allowed by NetlistInstruct.

[0063] In the output and delivery module, merged and sorted message lines (OutputNetlistMessage stable sorting) output a complete netlist text file, and can trigger numbered model write-back or graphical side annotation cleanup.

[0064] As an optional refinement step, this embodiment also includes the following process: Step 1: Read the root model key value and retrieve the simulation base information.

[0065] Step 2: Recursively traverse the components. If the type is in the mapping table and the output netlist text marker (_is_output_netlist_text) is true, proceed to generate the netlist row; otherwise, skip or trigger the large model supplementary mapping.

[0066] Step 3: Establish bidirectional port mapping for each type of connection, and perform flattening and hierarchical path splicing.

[0067] Step 4: For electrical classes, call the positive and negative port lookup, and generate rows by combining the control parameter and output parameter mapping table; generate dedicated syntax lines for blocks such as SysplorerEmbeddedCoder.SignalRouting.Mux or DeMux.

[0068] Step 5: The large model performs semantic consistency scoring on the netlist fragments. If the score is not passed, it returns to Step 2 or prompts the user.

[0069] Step 6: Output the partition netlist and end marker to complete file writing.

[0070] In one alternative, for components that do not match the mapping table, a rule-template-based approximate matching method can be used as a supplement or pre-processing step to the large language model. This involves pre-defining several fuzzy matching rules (e.g., automatically inferring the positive and negative pin order based on keywords in the type name). When a fuzzy match is successful, candidate rules are generated directly; the large language model is only invoked when a fuzzy match fails. In another alternative, the partitioned output is not limited to the root region and other regions. It can also dynamically create any number of sub-partitions based on annotation fields in the model (e.g., "targetCPU" and "targetFPGA"). Each sub-partition corresponds to an independent string buffer, and the final output is concatenated according to the partition number order. In yet another alternative, after the large model generates candidate mapping rules, in addition to syntax verification and graph theory consistency verification, a historical rule base similarity comparison can be added: the similarity between the newly generated rule and the stored rules is calculated. If the similarity is higher than a threshold, the historical rule is automatically adopted, and the user is prompted for confirmation to avoid duplicate generation.

[0071] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the electrical network table conversion method of this application. Any simple transformations based on this technical concept are within the protection scope of this application.

[0072] This application also provides an electrical grid meter conversion device; please refer to... Figure 6 The electrical grid meter conversion device includes: The acquisition module 10 is used to acquire the target model and traverse the component tree of the target model to read the class information of the components; The query module 20 is used to query the pre-stored component mapping table for the current component that is traversed. If a match is found, the corresponding deterministic mapping rule is obtained from the component mapping table. If no match is found, the large language model is called. The large language model generates candidate mapping rules based on the class information of the current component and performs validity verification on the candidate mapping rules. After the verification is passed, the new mapping rule is stored in the component mapping table. The conversion module 30 is used to determine the netlist row corresponding to the current component based on the deterministic mapping rule obtained from the component mapping table or the new mapping rule; The aggregation module 40 is used to aggregate the netlist rows corresponding to all components to generate an electrical netlist.

[0073] And / or, the electrical grid meter conversion device includes: The first reading module is used to read the current model key value from the class manager and locate the target model based on the current model key value; The first traversal module is used to recursively traverse the component tree of the target model, skipping components that are masked by annotations. The first reading submodule is used to read the full name of the type, the short name of the component, the pin list, and the documentation text for each component.

[0074] And / or, the electrical grid meter conversion device includes: The first assembly module is used to assemble the full class name, document text, and pin list of the current component into a prompt word for input into the large language model; The first receiving module is used to receive the candidate mapping rules that conform to a predetermined data format output by the large language model; The first verification module is used to perform syntax validity verification on the candidate mapping rules based on a predetermined data format. The second verification module is used to perform graph theory consistency verification on the candidate mapping rules. The graph theory consistency verification includes checking the number of connections, the existence of ground nodes, and the existence of power nodes.

[0075] And / or, the electrical grid meter conversion device includes: The first determining module is used to determine the network name to which the positive and negative pins of the current component are connected, based on the pin definition in the deterministic mapping rule or the new mapping rule. The first formatting module is used to read the corresponding parameter values ​​from the target model and format them into parameter strings according to the parameter fields in the deterministic mapping rule or the new mapping rule; The first generation module is used to generate a dedicated signal connection row in the corresponding netlist row when the current component is marked as a signal routing block, based on the number of ports of the signal routing block. The first tracing module is used to trace the signal source of the control variable along the connection diagram when the current component contains a control variable, and generate the control signal row in the corresponding netlist row according to the tracing result.

[0076] And / or, the electrical grid meter conversion device includes: The second reading module is used to read the preset partition annotation of each component, wherein the preset partition annotation is used to indicate the computing partition to which the component belongs; The first writing module is used to write the netlist rows converted from each component into the corresponding partition string according to the preset partition annotation; The second writing module is used to write the netlist rows of the current component into the preset default partition string when the current component does not have the preset partition annotation. The first output module is used to output each partition string as partition netlist text, and aggregate all partition netlist texts to obtain the electrical netlist.

[0077] And / or, the electrical grid meter conversion device includes: The second acquisition module is used to acquire the parameter string in the netlist row corresponding to the current component; The first comparison module is used to compare the parameter string with the actual parameter values ​​of the corresponding components in the target model; The first marking module is used to mark the netlist behavior of the current component as needing correction when the comparison results are inconsistent. The first correction module is used to re-input the netlist row in the state to be corrected into the large language model, and the large language model generates a corrected parameter string based on the actual parameter values ​​and replaces the corresponding part in the original netlist row.

[0078] The electrical network meter conversion device provided in this application, employing the electrical network meter conversion method in the above embodiments, can solve the technical problem of poor consistency in the electrical network meter conversion process in conventional technology. Compared with related technologies, the beneficial effects of the electrical network meter conversion device provided in this application are the same as those of the electrical network meter conversion method provided in the above embodiments, and other technical features in the electrical network meter conversion device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0079] This application provides an electrical netlist conversion device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, which are executed by the at least one processor to enable the at least one processor to perform the electrical netlist conversion method in Embodiment 1 above.

[0080] The following is for reference. Figure 7 The diagram illustrates a structural schematic of an electrical network table conversion device suitable for implementing embodiments of this application. The electrical network table conversion device in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, tablets, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital televisions and desktop computers. Figure 7 The electrical grid conversion device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of this application.

[0081] like Figure 7As shown, the electrical netlist conversion device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the electrical netlist conversion device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the electrical network meter conversion device to communicate wirelessly or wiredly with other devices to exchange data. Although the figures show electrical network meter conversion devices with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0082] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0083] The electrical network meter conversion device provided in this application, employing the electrical network meter conversion method described in the above embodiments, can solve the technical problem of poor consistency in the electrical network meter conversion process in conventional technologies. Compared with related technologies, the beneficial effects of the electrical network meter conversion device provided in this application are the same as those of the electrical network meter conversion method provided in the above embodiments, and other technical features of this electrical network meter conversion device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0084] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0085] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0086] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to perform the electrical netlist conversion method in the above embodiments.

[0087] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0088] The aforementioned computer-readable storage medium may be included in the electrical network table conversion device; or it may exist independently and not be assembled into the electrical network table conversion device.

[0089] The aforementioned computer-readable storage medium carries one or more programs that, when executed by the electrical network meter conversion device, cause the electrical network meter conversion device to: Obtain the target model and traverse the component tree of the target model to read the class information of the components; For the current component being traversed, the pre-stored component mapping table is queried. If a match is found, the corresponding deterministic mapping rule is obtained from the component mapping table. If no match is found, the large language model is called. The large language model generates candidate mapping rules based on the class information of the current component, and the validity of the candidate mapping rules is verified. If the verification is successful, the new mapping rule is stored in the component mapping table. The netlist row corresponding to the current component is determined based on the deterministic mapping rule obtained from the component mapping table or the new mapping rule. Aggregate the netlist rows corresponding to all components to generate an electrical netlist.

[0090] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0091] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0092] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0093] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described electrical netlist conversion method, which can solve the technical problem of poor consistency in the electrical netlist conversion process in conventional technology. Compared with related technologies, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the electrical netlist conversion method provided in the above embodiments, and will not be repeated here.

[0094] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the electrical netlist conversion method described above.

[0095] The computer program product provided in this application can solve the technical problem of poor consistency in the electrical netlist conversion process in conventional technology. Compared with related technologies, the beneficial effects of the computer program product provided in this application are the same as those of the electrical netlist conversion method provided in the above embodiments, and will not be repeated here.

[0096] All acquisition of signals, information, or actions in this application are carried out in compliance with the relevant data protection laws and policies of the country where the application is located, and with the authorization of the relevant device owner.

[0097] The above description is only a part of the embodiments of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the technical concept of this application and using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included in the scope of protection of this application.

Claims

1. A method for converting electrical network meters, characterized in that, The method includes: Obtain the target model and traverse the component tree of the target model to read the class information of the components; For the current component being traversed, the pre-stored component mapping table is queried. If a match is found, the corresponding deterministic mapping rule is obtained from the component mapping table. If no match is found, the large language model is called. The large language model generates candidate mapping rules based on the class information of the current component, and the validity of the candidate mapping rules is verified. If the verification is successful, the new mapping rule is stored in the component mapping table. The netlist row corresponding to the current component is determined based on the deterministic mapping rule obtained from the component mapping table or the new mapping rule. Aggregate the netlist rows corresponding to all components to generate an electrical netlist.

2. The method as described in claim 1, characterized in that, The class information includes the full name of each component's type, abbreviated name of the component, pin list, and documentation text. The step of obtaining the target model and traversing the component tree of the target model to read the class information of the components includes: Read the current model key value from the class manager, and locate the target model based on the current model key value; Recursively traverse the component tree of the target model, skipping components that are masked by annotations; Read the full name of the type, the short name of the component, the pin list, and the documentation text for each component.

3. The method as described in claim 1, characterized in that, The validity check includes syntactic validity check and graph theory consistency check. The step of calling the large language model, generating candidate mapping rules based on the class information of the current component, and validating the candidate mapping rules includes: Assemble the fully qualified class name, documentation text, and pin list of the current component into a prompt word and input it into the large language model; Receive candidate mapping rules that conform to a predetermined data format output by the large language model; Based on a predetermined data format, the candidate mapping rules are subjected to syntax validity verification. The candidate mapping rules are subjected to graph theory consistency verification, which includes checking the number of connections, the existence of ground nodes, and the existence of power nodes.

4. The method as described in claim 1, characterized in that, The netlist row includes a network name, parameter string, dedicated signal connection row, and control signal row. The step of determining the netlist row corresponding to the current component based on the deterministic mapping rule obtained from the component mapping table or the new mapping rule includes: Based on the pin definitions in the deterministic mapping rule or the new mapping rule, determine the network names to which the positive and negative pins of the current component are connected; Based on the parameter fields in the deterministic mapping rule or the new mapping rule, read the corresponding parameter values ​​from the target model and format them as parameter strings; When the current component is marked as a signal routing block, a dedicated signal connection row in the corresponding netlist row is generated based on the number of ports in the signal routing block. When the current component contains control variables, trace the signal source of the control variables along the connection diagram, and generate the corresponding control signal row in the netlist row based on the tracing result.

5. The method as described in claim 1, characterized in that, The step of aggregating all component-corresponding netlist rows to generate an electrical netlist includes: Read the preset partition annotations for each component, which are used to indicate the computation partition to which the component belongs; Based on the preset partition annotations, the netlist rows obtained from the conversion of each component are written into the corresponding partition string; When the current component does not have the preset partition annotation, the netlist row of the current component is written into the preset default partition string; Each partition string is output as the partition netlist text, and all partition netlist texts are aggregated to obtain the electrical netlist.

6. The method as described in claim 1, characterized in that, After determining the netlist row corresponding to the current component, the method further includes: Retrieve the parameter string from the netlist row corresponding to the current component; The parameter string is compared with the actual parameter values ​​of the corresponding components in the target model; When the comparison results are inconsistent, mark the netlist behavior of the current component as pending correction. The netlist row in the state to be corrected is re-input into the large language model, which then generates a corrected parameter string based on the actual parameter values ​​and replaces the corresponding part in the original netlist row.

7. An electrical grid meter conversion device, characterized in that, The device includes: The acquisition module is used to acquire the target model and traverse the component tree of the target model to read the class information of the components; The query module is used to query the pre-stored component mapping table for the current component being traversed. If a match is found, the corresponding deterministic mapping rule is obtained from the component mapping table. If no match is found, the large language model is called. The large language model generates candidate mapping rules based on the class information of the current component and performs validity verification on the candidate mapping rules. If the verification is successful, the new mapping rule is stored in the component mapping table. The conversion module is used to determine the netlist row corresponding to the current component based on the deterministic mapping rule obtained from the component mapping table or the new mapping rule; The aggregation module is used to aggregate the netlist rows corresponding to all components to generate an electrical netlist.

8. An electrical grid meter conversion device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the electrical netlist conversion method as described in any one of claims 1 to 6.

9. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the electrical netlist conversion method as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the electrical netlist conversion method as described in any one of claims 1 to 6.

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