Method and apparatus for flattening hierarchy of module instances, electronic device, and storage medium

Abstract

The present application relates to the technical field of chip design, and discloses a module instance hierarchical flattening method and device, electronic equipment and a storage medium, the present application extracts features of a target module instance to obtain instance design features of the target module instance, wherein the instance design features include multiple features representing instance design from different dimensions; based on a preset evaluation strategy, the instance design features are evaluated to obtain a hierarchical flattening score of the target module instance; and based on the hierarchical flattening score, a hierarchical flattening strategy of the target module instance is determined. Thus, the instance design features are used to reflect the design of the target module instance from different dimensions, the preset evaluation strategy is used to realize diversified design and optimization strategies of the target module instance, the evaluation of the target module instance is quantified and standardized, and the flattening effect of the target module instance is improved.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and more specifically to a method, apparatus, electronic device, and storage medium for leveling up module instances. Background Technology

[0002] In the digital chip design flow, logic synthesis is a crucial step in converting register-transfer-level (RTL) descriptions into process-dependent gate-level netlists. To improve optimization quality, synthesis tools often provide commands to flatten hierarchies, removing hierarchical boundaries between modules and enabling the optimizer to perform global optimizations across modules.

[0003] Currently, the decision to level modules mainly relies on manual leveling or built-in automatic leveling methods within tools. However, manual leveling depends on engineer experience and cannot provide a global balance or quantification, while automatic leveling cannot adapt to diverse design goals and lacks adaptive optimization capabilities. Therefore, current leveling methods cannot achieve optimal leveling results. Summary of the Invention

[0004] This invention provides a method, apparatus, electronic device, and storage medium for leveling the hierarchy of a module instance, in order to solve the problem that current leveling methods cannot achieve optimal leveling results.

[0005] In a first aspect, the present invention provides a method for flattening the hierarchy of module instances, the method comprising: Feature extraction is performed on the target module instance to obtain the instance design features of the target module instance. The instance design features include multiple features that characterize the instance design from different dimensions. Based on the preset evaluation strategy, the design features of the instance are evaluated to obtain the hierarchical leveling score of the target module instance. Based on the hierarchical leveling score, determine the hierarchical leveling strategy for the target module instance.

[0006] In one optional implementation, the instance design features include the number of ports of the target module instance. Feature extraction is performed on the target module instance to obtain the instance design features of the target module instance, including: The number of valid ports in the target module instance is counted to obtain port quantity characteristics. Valid ports are those that have connections with other logical units.

[0007] In one optional implementation, the instance design features include the logical coupling degree features of the target module instance. Feature extraction is performed on the target module instance to obtain the instance design features of the target module instance, including: The number of external logic units input to each input port of the target module instance is counted to obtain the total number of input units. The external logic units are logic units located outside the target module instance. The total number of output units is obtained by counting the number of external logic units output to each output port of the target module instance. The logic coupling degree characteristic is obtained by calculating the ratio of the sum of the total number of input units and the total number of output units of the target module instance to the number of effective ports.

[0008] In one optional implementation, the instance design features include the temporal criticality features of the target module instance. Feature extraction is performed on the target module instance to obtain the instance design features of the target module instance, including: Obtain the timing path of each valid port in the target module instance; The number of timing paths with a logic level greater than or equal to a preset level is counted to obtain the number of critical paths; The time-series criticality feature is obtained by calculating the ratio of the number of critical paths to the number of effective ports.

[0009] In one optional implementation, the instance design features include the local complexity features of the target module instance. Feature extraction is performed on the target module instance to obtain the instance design features of the target module instance, including: The number of isolated logical units in the target module instance is counted to obtain the number of isolated units. Calculate the square root of the number of isolated units to obtain the local complexity feature.

[0010] In one optional implementation, the instance design features are evaluated based on a preset evaluation strategy to obtain a hierarchical leveling score for the target module instance, including: Based on the preset evaluation strategy, determine the weight information corresponding to each feature in the instance design features; Based on the weight information corresponding to each feature, the instance design features are calculated to obtain the hierarchical leveling score; Based on the hierarchical leveling score, the hierarchical leveling strategy for the target module instance is determined, including: If the leveling score is greater than the preset score, the leveling strategy is determined to be the target module instance. If the leveling score is less than or equal to the preset score, the leveling strategy is to retain the target module instance.

[0011] In one optional implementation, the instance design features are evaluated based on a preset evaluation strategy to obtain a hierarchical leveling score for the target module instance, and the method further includes: Based on the instance design features of the target module instance, the instance design feature set of each module instance to be evaluated is updated. The design feature set includes multiple feature sets that characterize the instance design from different dimensions. Based on the instance design features of each module instance in the instance design feature set, the instance design features are normalized.

[0012] In a second aspect, the present invention provides a layer flattening device for module instances, the device comprising: The feature extraction module is used to extract features from the target module instance to obtain the instance design features of the target module instance. The instance design features include multiple features that characterize the instance design from different dimensions. The feature evaluation module is used to evaluate the features of the instance design based on a preset evaluation strategy, and obtain the hierarchical leveling score of the target module instance. The strategy determination module is used to determine the hierarchical leveling strategy for the target module instance based on the hierarchical leveling score.

[0013] Thirdly, the present invention provides an electronic device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the layer flattening method of the module instance of the first aspect or any corresponding embodiment described above.

[0014] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the layer flattening method of the module instance of the first aspect or any corresponding embodiment thereof.

[0015] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the layer flattening method of the module instance of the first aspect or any corresponding embodiment thereof.

[0016] The hierarchical leveling method for module instances provided in this invention extracts features from target module instances to obtain instance design features. These instance design features include multiple features that characterize the instance design from different dimensions, thereby enabling a comprehensive evaluation of the target module instance design. Simultaneously, based on a preset evaluation strategy, the instance design features are evaluated to obtain a hierarchical leveling score for the target module instance. This preset evaluation strategy enables diverse design and optimization strategies for the target module instance, quantifying and standardizing the evaluation of the target module instance. Based on the hierarchical leveling score, a hierarchical leveling strategy for the target module instance is determined. The hierarchical leveling score is then used as a quantitative standard for leveling the target module instance, and the target module instance is leveled based on the hierarchical leveling strategy to improve the overall leveling effect. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the first method for leveling the hierarchy of module instances according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the second method for leveling the hierarchy of module instances according to an embodiment of the present invention; Figure 3 This is a structural block diagram of a layer flattening device according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0021] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0022] In the digital chip design flow, logic synthesis is a crucial step in converting register-transfer-level (RTL) descriptions into process-dependent gate-level netlists. To improve optimization quality, synthesis tools often provide commands to flatten hierarchies, removing hierarchical boundaries between modules and enabling the optimizer to perform global optimizations across modules.

[0023] Currently, the decision to level modules primarily relies on manual leveling or built-in automatic leveling methods within software tools. Manual leveling involves design engineers adding leveling instructions to specific modules in scripts based on experience. Built-in automatic leveling uses an integrated automatic hierarchical management strategy, automatically leveling certain levels during optimization based on built-in decision logic. However, manual leveling relies on engineer experience and cannot provide a holistic assessment or quantification, while automatic leveling cannot adapt to diverse design goals and lacks adaptive optimization capabilities. Therefore, current leveling methods fail to achieve optimal leveling results.

[0024] To address the aforementioned issues, this invention provides a method for hierarchical leveling of module instances. It extracts features from target module instances to obtain instance design features, which include multiple features representing the instance design from different dimensions. This allows for a comprehensive evaluation of the target module instance's design. Simultaneously, based on a preset evaluation strategy, the instance design features are evaluated to obtain a hierarchical leveling score for the target module instance. This preset evaluation strategy enables diverse design and optimization strategies for the target module instance, quantifying and standardizing the evaluation. Based on the hierarchical leveling score, a hierarchical leveling strategy for the target module instance is determined. The hierarchical leveling score is then used as a quantitative standard for leveling the target module instance, and the target module instance is leveled based on the hierarchical leveling strategy, improving the overall leveling effect.

[0025] The module instance hierarchy flattening method provided in this embodiment of the invention can be applied to the design flow of various synthesis or physical implementation EDA tools, such as the Genus tool. Furthermore, it can be integrated into any stage after the initialization of the design flow, and can provide module instance hierarchy flattening suggestions at any stage, exhibiting strong flexibility and adaptability.

[0026] According to an embodiment of the present invention, a method embodiment for leveling up the hierarchy of module instances is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0027] This embodiment provides a method for leveling up module instances, which can be used in various synthesis or physical implementation EDA tools. Figure 1 This is a schematic diagram of the first type of layer flattening method for module instances according to an embodiment of the present invention, as shown below. Figure 1 As shown, the process includes the following steps: Step S101: Extract features from the target module instance to obtain the instance design features of the target module instance.

[0028] In this embodiment of the invention, the target module instance is a module instance in chip design that needs to be evaluated for whether to perform hierarchical flattening. Hierarchical flattening refers to removing the hierarchical boundaries between modules and promoting the logic units inside the sub-module, such as AND gates, OR gates, flip-flops, and multiplexers, to the parent module, so that the optimizer can perform global optimization across modules.

[0029] In this embodiment of the invention, instance design features are used to quantitatively describe the design characteristics of target module instances from different dimensions. The instance design features include multiple features that characterize instance design from different dimensions, thereby reflecting the optimization benefits or costs that the target module instances may bring after hierarchical flattening from different dimensions.

[0030] In this embodiment of the invention, feature extraction is performed on the target module instance. Specifically, features such as ports and logic units contained in the target module instance can be extracted and analyzed to obtain multi-dimensional instance design features of the target module instance.

[0031] Step S102: Based on the preset evaluation strategy, evaluate the instance design features to obtain the hierarchical leveling score of the target module instance.

[0032] In this embodiment of the invention, a preset evaluation strategy is used to provide a comprehensive approach for evaluating multi-dimensional instance design features. Furthermore, the invention offers multiple preset evaluation strategies, each with a different emphasis on evaluating the multi-dimensional instance design features. For example, strategies prioritizing module performance or module area may be used. Based on the user's evaluation needs, a strategy is selected to evaluate the instance design features, thus flexibly adapting to diverse optimization objectives. Based on the preset evaluation strategy, the instance design features are evaluated to obtain a hierarchical leveling score for the target module instance. This hierarchical leveling score is then used to synthesize the multi-dimensional instance design features into a single score, which is then used to quantitatively evaluate the leveling benefit of the target module instance.

[0033] Step S103: Based on the hierarchical leveling score, determine the hierarchical leveling strategy for the target module instance.

[0034] In this embodiment of the invention, a leveling strategy for a target module instance is determined based on the specific value of the leveling score, and a corresponding leveling operation is performed on the target module instance based on the determined leveling strategy. The leveling strategy may include performing a leveling operation or not performing a leveling operation. If the leveling score is within the score range corresponding to performing a leveling operation, the leveling strategy for the target module instance is determined to be performing a leveling operation; if the leveling score is within the score range corresponding to not performing a leveling operation, the leveling strategy for the target module instance is determined to be not performing a leveling operation.

[0035] The hierarchical leveling method for module instances provided in this invention extracts features from target module instances to obtain instance design features. These instance design features include multiple features that characterize the instance design from different dimensions, thereby enabling a comprehensive evaluation of the target module instance design. Simultaneously, based on a preset evaluation strategy, the instance design features are evaluated to obtain a hierarchical leveling score for the target module instance. This preset evaluation strategy enables diverse design and optimization strategies for the target module instance, quantifying and standardizing the evaluation of the target module instance. Based on the hierarchical leveling score, a hierarchical leveling strategy for the target module instance is determined. The hierarchical leveling score is then used as a quantitative standard for leveling the target module instance, and the target module instance is leveled based on the hierarchical leveling strategy to improve the overall leveling effect.

[0036] This embodiment provides a method for leveling up module instances, which can be used in various synthesis or physical implementation EDA tools. Figure 2 This is a schematic diagram of the first type of layer flattening method for module instances according to an embodiment of the present invention, as shown below. Figure 2 As shown, the process includes the following steps: Step S201: Extract features from the target module instance to obtain the instance design features of the target module instance.

[0037] In this embodiment of the invention, the instance design features include the number of ports, logical coupling, timing criticality, and local complexity of the target module instance.

[0038] In one optional implementation, the port quantity feature is used to characterize the density of connections between the target module instance and external modules or logic units. The higher the number of ports corresponding to the port quantity feature, the more complex the connections between the target module instance and other modules or logic units, and the higher the necessity for leveling off. The port quantity feature is obtained by counting the number of valid ports in the target module instance. Valid ports are those that have connections with other logic units. Floating ports and ports that are only connected to power or ground are not included in the number of valid ports because they do not participate in substantive logical interactions.

[0039] In one optional implementation, the logical coupling degree feature is used to characterize the tightness of the connection between the target module instance and external modules or logical units. The higher the coupling degree corresponding to the logical coupling degree feature, the more the cross-boundary connections are converted into direct internal connections after the target module instance is flattened, which is more conducive to logic optimization and has a higher flattening benefit. The logical coupling degree feature can be extracted through the following steps: Step a1: Count the number of external logic units input to each input port of the target module instance to obtain the total number of input units. The external logic units are logic units located outside the target module instance.

[0040] In step a1, for each input port in the target module instance, the input logic cone of that input port is obtained, which is the set of all logic units that can drive that input port through the timing path. Logic units located inside the target module instance are removed from this set, and the remaining units are the external logic units. The number of external logic units in the set is counted to obtain the number of external logic units for a single input port. The total number of external logic units for all input ports in the target module instance is then summed to obtain the total number of input units.

[0041] Step a2: Count the number of external logic units output to each output port of the target module instance to obtain the total number of output units.

[0042] In step a2, for each output port in the target module instance, the output logic cone of that output port is obtained, which is the set of all logic units that can be directly or indirectly driven by that output port. The logic units located inside the target module instance in this set are removed, and the remaining ones are the external logic units. The number of external logic units in the set is counted to obtain the number of external logic units for one output port. The number of external logic units for all output ports in the target module instance is summed to obtain the total number of output units.

[0043] Step a3: Calculate the ratio of the sum of the total number of input units and the total number of output units of the target module instance to the number of effective ports to obtain the logic coupling degree characteristic.

[0044] In step a3, the sum of the total number of input units and the total number of output units of the target module instance is calculated and divided by the number of effective ports, which is the port number feature, to obtain the logic coupling feature, which can be specifically shown in the following formula (1): Formula (1) in, For target module instance The logical coupling characteristics, The total number of input cells. This represents the total number of output units. For target module instance The number of ports is a characteristic.

[0045] In one optional implementation, the timing criticality feature is used to characterize the number or proportion of critical timing paths across module boundaries of the target module instance. A higher timing criticality feature indicates more long logic-level timing paths between the target module instance and other modules. Flattening the target module instance and then performing operations such as cross-path reorganization, logic reorganization, or pipeline insertion can more effectively optimize timing. The timing criticality can be extracted through the following steps: Step b1: Obtain all timing paths that pass through each valid port in the target module instance. Here, a timing path refers to a logic unit link consisting of all logic units traversed from the timing start point, such as the clock pin or input port of a flip-flop, to the timing end point, such as the data pin or output port of a flip-flop.

[0046] Step b2: Count the number of timing paths with a logic level greater than or equal to a preset level to obtain the number of critical paths.

[0047] In step b2, the logic level is the number of cascaded logic units traversed by the timing path. For each timing path, the number of timing points contained in that path is obtained. A timing point is a key node on the timing path containing timing information, typically including input pins, output pins, clock pins, and data pins, etc. For example, an input port and an output port traversed by a timing path can be counted as two timing points. A logic unit contains two timing points, and the start and end points of a timing path each correspond to one timing point. The number of logic levels is obtained by subtracting the start and end points from the total number of timing points in the timing path and then dividing by 2. Specifically, if this invention is applied in the pre-mapping stage, the logic level corresponds to the number of GTECH units; if applied in the post-mapping stage, the logic level corresponds to the number of standard units. The preset number of levels can be adjusted according to user needs, and no specific restrictions are imposed here. Different preset number of levels can be set according to different projects and processes. If the frequency of the target module instance is low and the timing requirements are relatively easier to meet, the preset number of levels can be set to a larger value. If the frequency of the target module instance is high and the timing requirements are relatively more difficult to meet, the preset number of levels can be set to a smaller value.

[0048] In step b2, timing paths with a logic level greater than or equal to a preset level are identified as critical paths. The number of critical paths is then counted. Within the target module instance, each port corresponds to multiple timing paths. The logic level of all timing paths corresponding to each port in the target module instance is counted to determine the number of critical paths among all timing paths in the target module instance. Critical paths have longer logic levels, corresponding to higher path delays, and are more likely to become bottlenecks in timing convergence. Flattening these critical paths can provide greater timing optimization space. Therefore, counting the number of critical paths is used to determine whether flattening the hierarchy of the target module instance would result in better timing optimization space.

[0049] Step b3: Calculate the ratio of the number of critical paths to the number of effective ports to obtain the temporal criticality feature, which can be shown in the following formula (2): Formula (2) in, For target module instance The temporal criticality feature, For target module instance The number of ports is a characteristic. For target module instance The number of critical paths.

[0050] In one optional implementation, the local complexity feature is used to characterize the scale of the internal logic of the target module instance. The higher the complexity corresponding to the local complexity feature, the greater the increase in the logical scale of the parent module corresponding to the target module instance after flattening the target module instance. The number of isolated logical units in the target module instance is counted to obtain the number of isolated units. The isolated logical units refer to logical units that directly belong to the target module instance and are not included in other sub-modules. The square root of the number of isolated units is calculated to obtain the local complexity feature, which can be shown in the following formula (3): Formula (3) in, For target module instance The local complexity characteristics, For target module instance The number of isolated units.

[0051] Step S202: Based on the preset evaluation strategy, evaluate the instance design features to obtain the hierarchical leveling score of the target module instance.

[0052] Specifically, step S202 includes: Step S2021: Based on the preset evaluation strategy, determine the weight information corresponding to each feature in the instance design features.

[0053] In this embodiment of the invention, weight information corresponding to each feature in the instance design features is configured in a preset evaluation strategy. The weight information corresponding to each feature in the instance design features is determined based on the preset evaluation strategy selected by the user.

[0054] In one optional implementation, the preset evaluation strategy may include at least three preset evaluation strategies: a balanced mode, a performance-first mode, and an area-first mode. The balanced mode preset evaluation strategy comprehensively considers both performance and area, and its corresponding weight information can be set as follows: , , , ,in, The weight information corresponding to the port quantity feature. The weight information corresponding to the logical coupling degree feature. This refers to the weight information corresponding to the temporal criticality features. This refers to the weighting information corresponding to local complexity features. The preset evaluation strategy of the performance-first mode strengthens the weighting of timing criticality and logical coupling features, tending to balance modules that help improve timing, which is suitable for high-speed designs. Its corresponding weighting information can be set as follows: , , , The area-first mode's preset evaluation strategy reduces the weight of timing-critical features while increasing the weight of logical coupling features, favoring modules that contribute to area optimization. This is suitable for area-sensitive designs, and its corresponding weight information can be set as follows: , , , It should be noted that this embodiment only provides the above three preset evaluation strategies. In practice, multiple preset evaluation strategies can be customized according to user design requirements. No specific restrictions are placed on the preset evaluation strategies and their configured weights here.

[0055] Step S2022: Based on the weight information corresponding to each feature, calculate the instance design features to obtain the hierarchical leveling score.

[0056] In this embodiment of the invention, based on the weight information configured by the preset evaluation strategy, each feature in the instance design features is calculated to obtain a leveling score. Specifically, after configuring weights for the port quantity feature, logical coupling feature, timing criticality feature, and local complexity feature, the weighted port quantity feature, logical coupling feature, and timing criticality feature are added together to calculate the leveling benefit. Then, the weighted local complexity feature is subtracted to reflect the leveling cost. Thus, the leveling benefit is subtracted from the leveling cost to obtain the leveling score.

[0057] In one optional implementation, due to the significant differences in scale, port density, and logic depth among different chips, directly using the raw feature values ​​extracted from the target module instance would lead to scoring bias. Therefore, before weighting each feature in the instance design features, an adaptive normalization operation is performed on each feature to adapt to designs of different scales and styles, improving the algorithm's versatility and robustness. Specifically, based on the instance design features of the target module instance, the instance design feature set of each module instance to be evaluated is updated. The design feature set includes multiple feature sets characterizing the instance design from different dimensions, including a port quantity feature set, a logic coupling feature set, a timing criticality feature set, and a local complexity feature set. The module instances to be evaluated are all module instances in the current chip design that require evaluation for whether to perform hierarchical flattening. Based on the instance design features of each module instance in the instance design feature set, the instance design features are normalized. For each feature set, the feature values ​​are arranged in ascending order, and the feature value at the 75th percentile is determined as the normalization benchmark for that feature. Thus, the normalized features of each feature are obtained, as shown in the following formula (4):

[0058]

[0059]

[0060] Formula (4) in, For target module instance The port number normalization feature, For target module instance The normalized characteristics of logical coupling. For target module instance Temporal criticality normalized features, For target module instance The local complexity normalization feature; This serves as the normalized benchmark corresponding to the port quantity characteristic. The normalized benchmark corresponding to the logical coupling degree feature. The normalized benchmark is the one corresponding to the temporal criticality feature. This serves as the normalized benchmark corresponding to the local complexity features.

[0061] In one alternative implementation, after obtaining the normalized features corresponding to the design features of each instance, the hierarchical flattening score is calculated using the method shown in the following formula (5): Formula (5) in, For target module instance The level is equalized in the scoring.

[0062] Step S203: Based on the hierarchical leveling score, determine the hierarchical leveling strategy for the target module instance.

[0063] In this embodiment of the invention, if the level-level equalization score is greater than the preset score, the level-level equalization strategy is determined to equalize the target module instance; if the level-level equalization score is less than or equal to the preset score, the level-level equalization strategy is determined to retain the target module instance. The preset score can be set to 0, meaning that when the benefit of level-level equalization is greater than the cost, the target module instance is equalized; when the benefit of level-level equalization is less than the cost, the target module instance is retained. The preset score can also be adjusted according to the user's level-level equalization requirements, and no specific restrictions are imposed here.

[0064] The module instance leveling method provided in this invention extracts features of the target module instance from four dimensions: number of ports, logical coupling, timing criticality, and local complexity, thereby achieving a comprehensive quantification of the leveling benefits and costs of the target module instance. Simultaneously, it uses a selectable preset evaluation strategy to weight and score the instance design features, enabling diverse design and optimization strategies for the target module instance and quantifying and standardizing the evaluation of the target module instance. Furthermore, before weighting and scoring the instance design features, adaptive normalization is used to eliminate biases caused by different design scales, thus automatically adapting to chip designs of various complexities and improving the algorithm's versatility and robustness.

[0065] This embodiment also provides a layer-flattening device for module instances, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, hardware implementations, or a combination of software and hardware, are also possible and contemplated.

[0066] This embodiment provides a layer flattening device for module instances, such as... Figure 3 As shown, it includes: The feature extraction module 301 is used to extract features from the target module instance to obtain the instance design features of the target module instance, wherein the instance design features include multiple features that characterize the instance design from different dimensions; The feature evaluation module 302 is used to evaluate the instance design features based on a preset evaluation strategy to obtain the hierarchical leveling score of the target module instance. The strategy determination module 303 is used to determine the hierarchical leveling strategy for the target module instance based on the hierarchical leveling score.

[0067] In one optional implementation, the instance design features include the number of ports of the target module instance, and the feature extraction module 301 includes: The port count unit is used to count the number of valid ports in the target module instance to obtain port count characteristics. Valid ports are those that have connections with other logical units.

[0068] In one optional implementation, the instance design features include the logical coupling degree features of the target module instance, and the feature extraction module 301 includes: The input unit statistics unit is used to count the number of external logic units input to each input port of the target module instance to obtain the total number of input units. The external logic units are logic units located outside the target module instance. The output unit statistics unit is used to count the number of external logic units output to each output port of the target module instance, and obtain the total number of output units. The logic coupling calculation unit is used to calculate the ratio of the sum of the total number of input units and the total number of output units of the target module instance to the number of effective ports, thereby obtaining the logic coupling characteristic.

[0069] In one optional implementation, the instance design features include the temporal criticality features of the target module instance, and the feature extraction module 301 includes: The timing path acquisition unit is used to acquire the timing path of each valid port in the target module instance. The critical path count unit is used to count the number of time-series paths with a logical level greater than or equal to a preset level, and to obtain the number of critical paths. The time-series criticality calculation unit is used to calculate the ratio of the number of critical paths to the number of effective ports, thereby obtaining the time-series criticality feature.

[0070] In one optional implementation, the instance design features include the local complexity features of the target module instance, and the feature extraction module 301 includes: The isolated unit statistics unit is used to count the number of isolated logical units in the target module instance to obtain the number of isolated units; The local complexity calculation unit is used to calculate the square root of the number of isolated units to obtain the local complexity feature.

[0071] In one optional implementation, the feature evaluation module 302 includes: The weight determination unit is used to determine the weight information corresponding to each feature in the instance design features based on a preset evaluation strategy. The scoring unit is used to calculate the instance design features based on the weight information corresponding to each feature, and obtain the hierarchical leveling score.

[0072] In an optional implementation, the feature evaluation module 302 further includes: The feature set update unit is used to update the instance design feature set of each module instance to be evaluated based on the instance design features of the target module instance. The design feature set includes multiple feature sets that characterize the instance design from different dimensions. The normalization unit is used to normalize the instance design features based on the instance design features of each module instance in the instance design feature set.

[0073] In one alternative implementation, the strategy determination module 303 includes: The first strategy determination unit is used to determine the leveling strategy as the leveling target module instance if the leveling score is greater than the preset score. The second strategy determination unit is used to determine the leveling strategy as retaining the target module instance if the leveling score is less than or equal to the preset score.

[0074] The layer flattening device for module instances provided in this embodiment of the invention can execute the layer flattening method for module instances provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects for executing the method. Further functional descriptions of the various modules and units described above are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0075] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0076] The following is a detailed reference. Figure 4 This diagram illustrates a structural schematic suitable for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 401, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 402 or a program loaded from memory 408 into random access memory (RAM) 403. The RAM 403 also stores various programs and data required for the operation of the electronic device. The processor 401, ROM 402, and RAM 403 are interconnected via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0077] Typically, the following devices can be connected to I / O interface 405: input devices 406 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 407 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 408 including, for example, magnetic tapes, hard disks, etc.; and communication devices 409. Communication device 409 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 4 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0078] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 409, or installed from a memory 408, or installed from a ROM 402. When the computer program is executed by the processor 401, it performs the functions defined in the layer flattening method of the module instance of the embodiments of the present invention.

[0079] Figure 4 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0080] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the hierarchical flattening method of the module examples shown in the above embodiments is implemented.

[0081] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0082] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for flattening the hierarchy of module instances, characterized in that, The method includes: Feature extraction is performed on the target module instance to obtain the instance design features of the target module instance, wherein the instance design features include multiple features that characterize the instance design from different dimensions; Based on a preset evaluation strategy, the design features of the instance are evaluated to obtain the hierarchical leveling score of the target module instance. Based on the leveling score, the leveling strategy for the target module instance is determined.

2. The method according to claim 1, characterized in that, The instance design features include the number of ports of the target module instance. The step of extracting features from the target module instance to obtain its instance design features includes: The number of valid ports in the target module instance is counted to obtain the port quantity characteristics, wherein the valid ports are ports that have a connection relationship with other logical units.

3. The method according to claim 1, characterized in that, The instance design features include the logical coupling degree features of the target module instance. The step of extracting features from the target module instance to obtain its instance design features includes: The number of external logic units input to each input port of the target module instance is counted to obtain the total number of input units, wherein the external logic units are logic units located outside the target module instance; The total number of output units is obtained by counting the number of external logic units output to each output port of the target module instance. The logical coupling characteristic is obtained by calculating the ratio of the sum of the total number of input units and the total number of output units of the target module instance to the number of effective ports.

4. The method according to claim 1, characterized in that, The instance design features include the temporal criticality features of the target module instance. The step of extracting features from the target module instance to obtain its instance design features includes: Obtain the timing path of each valid port in the target module instance; The number of timing paths with a logic level greater than or equal to a preset level is counted to obtain the number of critical paths; The time-series criticality feature is obtained by calculating the ratio of the number of critical paths to the number of effective ports.

5. The method according to claim 1, characterized in that, The instance design features include the local complexity features of the target module instance. The step of extracting features from the target module instance to obtain its instance design features includes: The number of isolated logical units in the target module instance is counted to obtain the number of isolated units. The local complexity feature is obtained by calculating the square root of the number of isolated units.

6. The method according to any one of claims 1-5, characterized in that, The evaluation of the instance design features based on a preset evaluation strategy to obtain the hierarchical leveling score of the target module instance includes: Based on the preset evaluation strategy, determine the weight information corresponding to each feature in the instance design features; Based on the weight information corresponding to each feature, the instance design features are calculated to obtain the leveling score; The step of determining the hierarchical leveling strategy for the target module instance based on the hierarchical leveling score includes: If the leveling score is greater than the preset score, the leveling strategy is determined to level the target module instance. If the leveling score is less than or equal to the preset score, the leveling strategy is determined to retain the target module instance.

7. The method according to claim 6, characterized in that, The step of evaluating the instance design features based on a preset evaluation strategy to obtain the hierarchical leveling score of the target module instance also includes: Based on the instance design features of the target module instance, the instance design feature set of each module instance to be evaluated is updated respectively, wherein the design feature set includes multiple feature sets that characterize the instance design from different dimensions. Based on the instance design features of each module instance in the instance design feature set, the instance design features are normalized.

8. A layer flattening device for module instances, characterized in that, The device includes: The feature extraction module is used to extract features from the target module instance to obtain the instance design features of the target module instance, wherein the instance design features include multiple features that characterize the instance design from different dimensions; The feature evaluation module is used to evaluate the instance design features based on a preset evaluation strategy to obtain the hierarchical leveling score of the target module instance. The strategy determination module is used to determine the leveling strategy of the target module instance based on the leveling score.

9. An electronic device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the hierarchical flattening method of the module instance according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to execute the layer flattening method of the module instance according to any one of claims 1 to 7.

Images