A complex electronic verification method and system for converting digital signals to analog signals

Abstract

The application discloses a complex electronic verification method and system for converting digital signals into analog signals, and belongs to the field of civil aircraft complex electronic verification. The application runs a functional simulation case through a simulation platform, and stores a digital excitation signal generated in a simulation process into an excitation file in a text format. An analysis module of a test device is used to analyze the excitation file, and digital excitation data is extracted. A time sequence adding module is used to add time sequence parameters to the analyzed data, and continuous analog signal data meeting complex electronic input time sequence requirements is generated. A direct memory access first-in-first-out channel is used to transmit the data to a complex electronic hardware under test. Finally, physical test results are compared with simulation results for verification. The application realizes equivalence of simulation excitation and physical test excitation, solves problems of complex configuration, poor stability, single function and non-equivalent verification of excitation data in a traditional analog signal excitation mode, and significantly improves verification efficiency and reliability of complex electronic hardware.

Description

Technical Field

[0001] This invention relates to the field of verification of complex electronic hardware for civil aircraft, specifically to a method and system for verifying complex electronic hardware that converts digital signals to analog signals. It is particularly suitable for functional verification scenarios of complex electronic hardware (such as FPGA, ASIC, CPLD) involving analog signal inputs such as intermediate frequency signals and envelope signals in traffic monitoring systems. Background Technology

[0002] With the successful commercial operation of the C919 large passenger aircraft, China's civil aviation industry has witnessed an explosive growth in aircraft types. In the field of aviation safety, compared with traditional safety measures, adopting more advanced technologies to improve flight safety is particularly urgent. Traffic surveillance systems, acting as the "eyes" of aircraft, can monitor the distance and location information of other aircraft over long distances, and are an important new type of equipment in the civil aviation industry. This system has significant advantages in improving aircraft safety and operational efficiency, promoting the construction of smart civil aviation, enhancing the international competitiveness of China's civil aviation, and reducing operating costs and resource consumption.

[0003] The complex electronic hardware in traffic monitoring systems involves several analog signal inputs, with intermediate frequency (IF) signals and envelope signals used to achieve the two core functions of direction finding and distance measurement, respectively. The verification of this complex electronic hardware typically employs either simulation verification or physical testing. However, the excitation signals generated by these methods are generally digital signals. How to effectively convert digital signals into analog signals and fully verify the complex electronic hardware remains a current technical challenge.

[0004] In existing technologies, directly generating analog signals such as intermediate frequency and envelope through physical testing equipment has the following problems: First, using traditional signal generators and other tools to generate analog signals places high demands on hardware equipment, and the generated signals suffer from problems such as poor stability, low accuracy, limited functionality, and inflexible adjustment, making it difficult to meet the diverse testing needs of complex electronic hardware.

[0005] Second, directly using the analog signal excitation generated by the test equipment software has the drawback that a single signal cannot be adjusted midway, and the initial configuration of signal parameters is too complex. It is difficult to construct analog signals with specific timing requirements or special waveform requirements, which limits the completeness of test coverage.

[0006] Third, the two verification methods, simulation verification and physical testing, are independent of each other and cannot directly prove that the stimuli used in the simulation process are equivalent to those used in the physical testing process. This makes it difficult for the results of the two verification methods to correspond effectively, affecting the credibility of the verification conclusions.

[0007] In summary, existing technologies lack a method for generating and verifying analog signals that can unify simulation stimuli with physical test stimuli and achieve efficient equivalent verification. Summary of the Invention

[0008] The purpose of this invention is to provide a complex electronic verification method and system for converting digital signals to analog signals, which solves the technical problems in the prior art such as complex analog signal excitation configuration, single signal function, poor stability, and inability to verify excitation data equivalently, thereby efficiently completing the verification of complex electronic hardware and improving the reliability and consistency of verification.

[0009] The technical solution of this invention is implemented as follows: In a first aspect, the present invention provides a complex electronic verification method for converting digital signals to analog signals, comprising the following steps: Step 1: Simulation stimulus generation steps: Build a simulation platform, run functional simulation test cases, and store the digital stimulus signals generated during the simulation process as stimulus files in text format.

[0010] Specifically, a simulation platform is built based on the functional requirements of complex electronic hardware. The test benchmark of the simulation platform reserves tasks for calling the simulated signals to be verified (such as intermediate frequency signals and envelope signals). Functional simulation test cases are written based on these reserved tasks, and signal data storage tasks are called while the functional simulation is running. After the functional simulation is completed, a text-formatted stimulus file is automatically generated. The discrete data contained in this file is exactly the same as the signal data sent to the design under test during the functional simulation.

[0011] The specific implementation method for generating incentive files is as follows: Use a system function to create a text file to store analog signal data; Using the clock edge (such as the rising edge) of the excitation signal as the trigger condition, the data on the excitation interface is written to the above-mentioned text format file through the file writing function; After the simulation ends, the text file is closed using the file close function.

[0012] The above operations can be integrated into a single task, which is started while analog signals are being sent, ensuring that data on the interface is synchronously recorded into a text file.

[0013] Step 2, stimulus file parsing step: The stimulus file is read by the parsing module of the test equipment, the file content is parsed, and the digital stimulus data is extracted.

[0014] The text-formatted stimulus file generated by the simulation platform is uploaded to the test equipment, where it is parsed by the equipment's parsing module. The parsing process employs appropriate processing methods based on the signal type. For excitation data of intermediate frequency signal type: The testing equipment software reads the contents of a text file, searches for all delimiters (usually semicolons) in the file, and determines the total amount of data to be sent based on the number of delimiters. Using a fixed total amount of data as the number of loops, the system converts a single input data string into an unsigned number (such as a 16-bit unsigned number), and ends the parsing operation after fixing the high and low bits of the data.

[0015] For excitation data of the envelope signal type: The testing equipment software reads the contents of a text file, searches for all delimiters in the file, and determines the number of data changes based on the number of delimiters. The number of data changes is used as the number of cycles for parsing. The envelope signal configuration file contains a value and the number of duration cycles (for example, "255, 5" means that the envelope data is decimal 255 and lasts for 5 clock cycles). The test equipment software parses the configuration file into a one-dimensional array and expands the values ​​according to the number of consecutive periods (for example, "255, 5" is expanded into "255, 255, 255, 255, 255").

[0016] Step 3: Timing Parameter Addition Step: Using the timing addition module of the test equipment, add timing parameters to the parsed digital excitation data to generate continuous analog signal data that meets the timing requirements of complex electronic inputs.

[0017] After the complex electronic hardware under test is initialized, the default state data is output first to ensure the accuracy of the data evolution, thereby achieving the purpose of adding timing parameters.

[0018] Taking the envelope signal as an example, assuming the configuration file is "55, 3, 127, 2", and two identical data frames need to be sent simultaneously, with an interval of 2 clock cycles between each frame, without a timing addition module, the parsed data would be "55, 55, 55, 127, 127". Such continuous data input into complex electronics could lead to timing errors. To solve this problem, timing information needs to be added at the beginning and end of each data frame. The default data state of the envelope signal is all high (e.g., 8-bit all high, i.e., decimal 255). After processing by the timing addition module, the parsed data becomes: "255 (default state), 55, 55, 55, 127, 127 (end of first frame data), 255, 255 (interval default state), 55, 55, 55, 127, 127 (end of second frame data), 255 (end of total data default state)" By inserting default state data as an interval between adjacent frames, the data transmission is ensured to meet the timing requirements of complex electronic hardware.

[0019] Step 4: Data transmission: The continuous analog signal data is transmitted to the complex electronic hardware under test via the direct memory access first-in-first-out channel.

[0020] On the test equipment (such as an NI device), use LabVIEW to create a Direct Memory Access (DMA) First-In-First-Out (FIFO) channel and configure channel properties, including name, type, and number of requested elements. On the complex electronic hardware under test, instantiate a Direct Memory Access Controller (such as an AXI DMA IP core) in the FPGA code and configure the FIFO interface.

[0021] The test equipment uses write operations (such as FPGA Write DMA FIFO VI) to write intermediate frequency, envelope and other data into the DMA buffer; the complex electronic hardware under test reads data from memory (such as DDR memory) through the DMA controller and stores it into the local FIFO buffer to achieve high-speed, low-latency data transmission.

[0022] Step 5: Result Comparison and Verification Step: Collect the physical test results of the complex electronic hardware under test under the excitation of the continuous analog signal data, compare them with the simulation results generated by the simulation platform under the same excitation, and verify the functional correctness of the complex electronic hardware based on the comparison results.

[0023] By comparing the physical test waveform files generated in the test equipment and the simulation waveform files generated in the simulation platform, we can check whether the processing results of the complex electronic hardware after the stimulus file generated by the simulation platform is input into the test equipment are consistent with the simulation results. If they are consistent, it proves that the simulation stimulus and the physical test stimulus are equivalent, and the functional verification of the complex electronic hardware is successful; if they are inconsistent, further analysis of the reasons for the difference is required.

[0024] Secondly, the present invention provides a complex electronic verification system for converting digital signals to analog signals, comprising: The simulation stimulus generation module is configured to build a simulation platform and run functional simulation test cases, and to store the digital stimulus signals generated during the simulation process as stimulus files in text format. The incentive file parsing module is configured to read the incentive file, parse the file content, and extract digital incentive data; The timing parameter addition module is configured to add timing parameters to the parsed digital excitation data to generate continuous analog signal data that meets the timing requirements of complex electronic inputs. The data transmission module is configured to access the first-in-first-out channel via direct memory to transmit the continuous analog signal data to the complex electronic hardware under test. The result comparison and verification module is configured to collect the physical test results of the complex electronic hardware under test under the excitation of the continuous analog signal data, compare them with the simulation results generated by the simulation platform under the same excitation, and output the verification conclusion based on the comparison results.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. High flexibility in excitation generation: This invention generates excitation files through a simulation platform, which allows for a wider range of configurable scenarios and enables the flexible construction of analog signals with various complex waveforms and special timing requirements, overcoming the problems of traditional signal generators having limited functionality and inflexible adjustment.

[0026] 2. Improved signal stability and accuracy: This invention uses digital methods to generate excitation data, which is then converted into an analog signal after parsing and timing addition. This avoids the signal jitter problem caused by the instability of traditional analog signal source hardware, and improves the stability and accuracy of the excitation signal.

[0027] 3. Verification equivalence guarantee: This invention achieves a unified source of simulation stimulus and physical test stimulus. By using the same stimulus file generated by the simulation platform for physical testing, it can be directly proven that the stimulus used by the two verification methods is equivalent, so that the simulation verification and physical test results can correspond effectively, thereby improving the credibility of the verification conclusion.

[0028] 4. Simplified operation process: This invention forms a complete automated process for stimulus generation, parsing, timing addition, data transmission, and result comparison, reducing the complexity of manually configuring signal parameters and improving verification efficiency.

[0029] 5. Wide range of applications: This invention is not only applicable to intermediate frequency and envelope signal verification in traffic monitoring systems, but can also be extended to other complex electronic hardware fields involving digital signal to analog signal verification, and has good versatility and scalability.

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0031] Figure 1 This is an overall flowchart of the complex electronic verification method for converting digital signals to analog signals according to the present invention; Figure 2 This is a schematic diagram illustrating the process of building a simulation platform and generating a TXT format stimulus file for this invention. Figure 3 This is a schematic diagram illustrating the process of parsing txt format data using the parsing module of the testing equipment according to the present invention; Figure 4 This is a schematic diagram illustrating the process of adding timing parameters to the parsed data using the timing addition module of the test equipment according to the present invention; Figure 5 This is a schematic diagram illustrating the process of transmitting intermediate frequency and envelope data to complex electronics via DMA FIFO in this invention. Figure 6 This is a schematic diagram of the process for comparing the consistency between physical test results and simulation results in this invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are some embodiments of this invention, but not all embodiments.

[0033] The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the invention, and should not be construed as limiting the invention.

[0034] Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this invention.

[0035] The following is in conjunction with the appendix Figure 1-6 The embodiments of the present invention will be described in detail below.

[0036] Example 1 This embodiment provides a complex electronic verification method for converting digital signals to analog signals, used to verify the processing capabilities of complex electronic hardware (such as FPGA) in traffic monitoring systems for intermediate frequency signals and envelope signals.

[0037] I. Simulation stimulus generation (see...) Figure 1 , Figure 2 ) A simulation platform was built based on the functional requirements for intermediate frequency (IF) and envelope signals in complex electronic hardware. Tasks related to IF and envelope signals were reserved in the testbase of the simulation platform. Functional simulation test cases were written based on these reserved tasks.

[0038] While running the functional simulation test cases, the signal data storage task is invoked. The specific implementation of this task is as follows: First, the system function `$fopen` creates a text file to store intermediate frequency (IF) or envelope signal data. This function appends new content to the end of the file if it already exists, and the file content is processed in binary format.

[0039] Secondly, using the clock of the intermediate frequency or envelope signal as the trigger condition, the data on the excitation interface is written to the above text format file through the system function $fwrite at the rising edge of the clock.

[0040] Finally, after a delay to ensure the simulation is completely finished, use the system function $fclose to close the text file.

[0041] The above operations are integrated into a single task, which is initiated simultaneously with the transmission of envelope or intermediate frequency signals to ensure that data from the interface is synchronously recorded to a text file. After the functional simulation is completed, a txt excitation file is automatically generated, containing discrete data that is identical to the intermediate frequency and envelope data sent to the design under test during the functional simulation.

[0042] II. Incentive Document Parsing (see...) Figure 1 , Figure 3 ) The TXT format stimulus file generated by the simulation platform is uploaded to the test equipment, where it is parsed by the equipment's parsing module. Different parsing strategies are employed depending on the signal type.

[0043] Intermediate frequency signal analysis: The testing equipment software first reads the contents of a txt file, searches for all delimiters (usually semicolons) in the file, and determines the total amount of data to be sent based on the number of semicolons. Using this determined total amount of data as the loop count, it converts each input data string into a 16-bit unsigned number, and after fixing the high and low bits of the data, ends the intermediate frequency signal parsing operation.

[0044] Envelope signal analysis: The testing equipment software reads the contents of a TXT file, searches for all delimiters, and determines the number of data changes by the number of semicolons. The parsing process uses this number of changes as the loop count. The envelope signal configuration file contains 8 bits of data and the duration of the envelope signal, for example, "255, 5", indicating that the envelope data is decimal 255, and the duration is 5 clock cycles. The testing equipment software parses the configuration file into a one-dimensional array; for example, "255, 5" expands to "255, 255, 255, 255, 255".

[0045] III. Adding Timing Parameters (see...) Figure 1 , Figure 4 ) After the complex electronic hardware under test is initialized, the timing addition module first outputs the default state data to ensure the accuracy of the data evolution, thereby achieving the purpose of adding timing parameters.

[0046] Taking an envelope signal as an example, suppose the configuration file is "55, 3, 127, 2", and two identical frames of data need to be sent simultaneously, with an interval of two clock cycles between each frame. Without a timing enhancement module, the parsed data would be "55, 55, 55, 127, 127". Directly inputting this continuous data into complex electronics could lead to timing errors, as complex electronic hardware expects intervals between frames.

[0047] To address this issue, the timing addition module adds timing information to the beginning and end of each frame of data. The default data state of the envelope signal is 8 bits of all high level, i.e., decimal 255. After processing by the timing addition module, the parsed data becomes: Before the first frame begins: Output the default value "255". First frame of data: Output "55, 55, 55, 127, 127" sequentially. Between the end of the first frame and the start of the second frame: output two default states "255, 255" as an interval. The second frame of data will output "55, 55, 55, 127, 127" sequentially. After all data is processed: Output the default value "255". The final output data sequence is: "255, 55, 55, 55, 127, 127, 255, 255, 55, 55, 55, 127, 127, 255".

[0048] By employing the above methods, it is ensured that data transmission meets the timing requirements of complex electronic hardware, thus avoiding verification errors caused by insufficient intervals between frames.

[0049] IV. Data Transmission (see Figure 1 , Figure 5 ) On the NI device side, LabVIEW is used to create a DMA FIFO and configure its properties, including name, type, and the number of elements requested. On the complex electronic hardware side, the AXI DMA IP core is instantiated in the FPGA code, and the FIFO interface is configured.

[0050] The test equipment uses the FPGA Write DMA FIFO VI to write intermediate frequency (IF) and envelope data into the DMA buffer. The complex electronic hardware reads data from DDR memory and stores it in a local FIFO via an AXI DMA controller. This transmission method achieves high-speed, low-latency data transmission, meeting the real-time requirements of IF and envelope signals.

[0051] V. Result Comparison and Verification (see) Figure 1 , Figure 6 ) By comparing the physical test waveform files generated in the test equipment with the simulation waveform files generated in the simulation platform, we can see whether the processing results produced by the complex electronic hardware after the excitation file generated by the simulation platform is input into the test equipment are consistent with the simulation results.

[0052] Specifically, the output waveform acquired during the physical test is compared cycle by cycle with the output waveform obtained in the simulation environment under the same stimulus. If the two waveforms are completely identical, it proves that the function of the complex electronic hardware is implemented correctly, and that the simulation stimulus and the physical test stimulus are equivalent; if there are differences, the reasons for the differences are analyzed, which may be hardware implementation problems or test configuration problems, and further location and correction are required.

[0053] Through the above five steps, this invention realizes a complete closed loop from simulation stimulus generation to physical test verification, effectively solving the problems of complex configuration, poor stability, single function, and inability to verify stimulus data equivalently in traditional analog signal excitation methods, and significantly improving the verification efficiency and reliability of complex electronic hardware.

[0054] Example 2 This invention discloses a complex electronic verification method for converting digital signals to analog signals, which avoids problems such as complex configuration, single signal function, poor stability, and equivalence of excitation data of analog signals, thereby efficiently completing the complex electronic verification work of analog signals.

[0055] Specifically, the following steps are included: Step 1: Build a simulation platform and run the simulation to generate a txt format stimulus file; Step 2: Parse the txt format data using the parsing module of the test equipment; Step 3: Add timing parameters to the parsed data using the timing addition module of the test equipment; Step 4: Transmit intermediate frequency and envelope data to complex electronics via DMA FIFO; Step 5: Compare whether the actual results generated by the complex electronic physics test are consistent with the actual results generated by the simulation.

[0056] Preferably, step one includes the following steps: Step 11: Develop a simulation platform based on the requirements of complex electronic hardware and write functional simulation test cases based on the functions in the simulation platform; Step 12: Run the functional simulation test case and use the $fopen function to generate a txt file to store analog signal data such as intermediate frequency or envelope; Step 13: Use the $fwrite system function to write the data from the intermediate frequency or envelope interface to the txt file mentioned above; Step 14: Use the $fclose system function to close the txt file.

[0057] Preferably, in step two, the txt format file generated by the simulation platform needs to be uploaded to the test equipment for the test equipment's parsing module to parse the txt format data; Step 21: Use the testing equipment software to first read the contents of the txt file to determine the total amount of data to be sent; Step 22: Determine the amount of data to be sent as the number of loops required, convert the input single data string into a 16-bit unsigned number, and after fixing the high and low bits of the number, end the parsing operation; Preferably, in step three, the test equipment software adds timing parameters to the parsed data through the timing addition module; Step 31: After FPGA initialization, output the default state data first to ensure the accuracy of data edge transition, thereby achieving the purpose of adding timing parameters; Preferably, in step four, the intermediate frequency and envelope data are transmitted to the complex electronics via a DMA FIFO; Step 41: On the NI device side, create a DMA FIFO using LabVIEW and configure the DMA FIFO properties, such as name, type, number of requested elements, etc.; on the complex electronics side, instantiate the AXI DMA IP core in the FPGA code and configure the FIFO interface.

[0058] Step 42: The test equipment uses the FPGA Write DMA FIFO VI to write intermediate frequency, envelope, and other data into the DMA buffer; the complex electronics read data from DDR memory through the AXI DMA controller and store it into the local FIFO.

[0059] Preferably, in step five, it is necessary to compare the consistency between the actual results generated by physical testing during the complex electronic verification process and the actual results generated by simulation. Step 51: By comparing the waveform files generated in the test equipment with those generated in the simulation, check whether the complex electronic processing results produced by inputting the excitation file generated by the simulation platform into the test equipment are consistent.

[0060] The beneficial effects of this invention are as follows: 1. The steps of this invention are simple, the design is reasonable, and it is convenient to implement and use.

[0061] 2. The present invention offers richer configurable scenarios and greater flexibility, enabling the generation of various stimuli; 3. The present invention uses the stimulation data generated by the simulation platform for physical testing, which can realize the correspondence between functional simulation and physical testing, thereby achieving the consistency of verification.

[0062] In summary, the technical solution of this invention is reasonably designed. The TXT format data generated by the functional simulation test cases is parsed by the parsing module, and then the timing addition module is used to add the timing sequence of the parsed data. Finally, DMAFIFO is used to transfer the data to complex electronics, thereby realizing the generation of configurable, multi-scenario physical test excitation based on discrete intermediate frequency and envelope signals.

[0063] Example 3 This invention discloses a complex electronic verification method for converting digital signals to analog signals. It can process discrete digital signals generated by a simulation platform through test equipment software to generate continuous analog signals, thereby realizing complex electronic verification of digital signals to analog signals.

[0064] See Figure 1 As shown, the complex electronic verification method for converting digital signals to analog signals consists of five steps: building a simulation platform and running the simulation to generate a txt format stimulus file; parsing the txt format data through the parsing module of the test equipment; adding timing parameters to the parsed data through the timing addition module of the test equipment; transmitting intermediate frequency and envelope data to the complex electronics through DMA FIFO; and comparing the actual results generated by the complex electronics physics test with the actual results generated by the simulation. Each step is described in detail below.

[0065] Step 1: Build a simulation platform and run the simulation to generate a txt format stimulus file; Currently, there are many scenarios where analog signals are used in daily engineering projects. The following implementation will take common intermediate frequency and envelope signals as examples.

[0066] A simulation platform is built based on the requirements for intermediate frequency (IF) and envelope signals in complex electronic hardware. Tasks related to IF and envelope signals are reserved in the testbase of the simulation platform. Functional simulation test cases are written based on these reserved tasks. While running the functional simulation, the tasks storing the IF or envelope signal data are called. After the functional simulation is completed, a TXT file is automatically generated. The discrete data contained in the TXT file is the same as the IF and envelope data sent to the design under test during the functional simulation. The specific method for generating the TXT file from the tasks is as follows: Step 11: Use the $fopen function to generate a txt file to store intermediate frequency or envelope data. If the txt file already exists, the written content will be appended to the end of the file, and the content of the txt file will be processed in binary form. Step 12: Using the intermediate frequency or envelope signal clock as the trigger condition, write the data on the intermediate frequency or envelope interface to the above-mentioned txt format file at each rising edge of the clock using the $fwrite system function; Step 13: Wait for the simulation to finish before using the `$fclose` system function to close the txt file. Combine the above operations into a single task, and start this task simultaneously when transmitting envelope or intermediate frequency signals. This ensures that the intermediate frequency and envelope data from the interface are synchronously recorded to the txt file.

[0067] Step 2: Parse the txt format data using the parsing module of the test equipment; The steps for analyzing intermediate frequency signals are as follows: Step 21: First, use the testing device software to read the contents of the txt file and search for the number of delimiters in the content. The delimiter in the file is usually a semicolon. The total amount of data to be sent is determined by the number of semicolons. Step 22: Determine the amount of data to be sent as the number of loops required, convert the input single data string into a 16-bit unsigned number, and after fixing the high and low bits of the number, end the intermediate frequency signal parsing operation; The steps for envelope signal parsing are as follows: Step 23: First, use the testing equipment software to read the contents of the txt file and search for the number of delimiters in the content. The delimiter in the file is usually a semicolon. The number of semicolons determines the number of times the data was sent. Step 24: The number of cycles is determined by the number of data changes. The envelope signal configuration file contains 8 bits of data and the duration of the envelope signal, for example, 255, 5. The configuration of this envelope signal means that the envelope data is 255 in decimal and the duration is 5 clock cycles used by the envelope signal. The test equipment software finally parses it into a one-dimensional array with the content: 255, 255, 255, 255, 255.

[0068] Step 3: Add timing parameters to the parsed data using the timing addition module of the test equipment; Step 31: After the complex electronic initialization, the default state data is output first to ensure the accuracy of the data evolution, thereby achieving the purpose of adding timing parameters; Step 32: Taking the envelope signal as an example, if the configuration file is 55, 3, 127, 2, and two identical data frames need to be sent simultaneously, with an interval of 2 clock cycles between each frame, an additional module is needed if the interval is not reached. The parsed data is 55, 55, 55, 127, 127. However, this data will cause an error when input into complex electronics. To avoid this problem, timing information needs to be added to the beginning and end of each frame. Because the default data state of the envelope signal is 8 bits of all high level, i.e., decimal 255, the parsed data after adding the timing module is "255 (default state), 55, 55, 55, 127, 127 (end of first frame), 255, 255, (interval default state) 55, 55, 55, 127, 127, (end of second frame) 255 (end of total data default state)". Step 4: Transmit intermediate frequency and envelope data to complex electronics via DMA FIFO; Step 41: On the NI device side, create a DMA FIFO using LabVIEW and configure the DMA FIFO properties, such as name, type, number of requested elements, etc.; on the complex electronics side, instantiate the AXI DMA IP core in the FPGA code and configure the FIFO interface.

[0069] Step 42: The test equipment uses the FPGA Write DMA FIFO VI to write the intermediate frequency and envelope data into the DMA buffer; the complex electronics read data from the DDR memory through the AXI DMA controller and store it into the local FIFO.

[0070] Step 5: Compare the actual results generated by the complex electronic physics test with the actual results generated by the simulation to see if they are consistent. Step 51: By comparing the waveform files generated in the test equipment with those generated in the simulation, check whether the complex electronic processing results produced by inputting the excitation file generated by the simulation platform into the test equipment are consistent.

[0071] Thus, the objective of this invention has been achieved.

[0072] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A complex electronic verification method for converting digital signals to analog signals, characterized in that, Includes the following steps: Simulation stimulus generation steps: Build a simulation platform, run functional simulation test cases, and store the digital stimulus signals generated during the simulation process as stimulus files in text format; The stimulus file parsing steps are as follows: The stimulus file is read by the parsing module of the test equipment, the file content is parsed, and digital stimulus data is extracted; Timing parameter addition steps: Add timing parameters to the parsed digital excitation data through the timing addition module of the test equipment to generate continuous analog signal data that meets the timing requirements of complex electronic inputs; Data transmission steps: The continuous analog signal data is transmitted to the complex electronic hardware under test via the direct memory access first-in-first-out channel; The result comparison and verification steps are as follows: Collect the physical test results of the complex electronic hardware under test under the excitation of the continuous analog signal data, compare them with the simulation results generated by the simulation platform under the same excitation, and verify the functional correctness of the complex electronic hardware based on the comparison results.

2. A complex electronic verification system for converting digital signals to analog signals, characterized in that, include: The simulation stimulus generation module is configured to build a simulation platform and run functional simulation test cases, and to store the digital stimulus signals generated during the simulation process as stimulus files in text format. The incentive file parsing module is configured to read the incentive file, parse the file content, and extract digital incentive data; The timing parameter addition module is configured to add timing parameters to the parsed digital excitation data to generate continuous analog signal data that meets the timing requirements of complex electronic inputs. The data transmission module is configured to access the first-in-first-out channel via direct memory to transmit the continuous analog signal data to the complex electronic hardware under test. The result comparison and verification module is configured to collect the physical test results of the complex electronic hardware under test under the excitation of the continuous analog signal data, compare them with the simulation results generated by the simulation platform under the same excitation, and output the verification conclusion based on the comparison results.

3. The method according to claim 1 or the system according to claim 2, characterized in that, In the simulation excitation generation step, the digital excitation signals generated during the simulation are stored as an excitation file in text format, specifically including: Create text format files using system functions of the simulation platform; Using the clock edge of the excitation signal as the trigger condition, the data on the excitation interface is written to the text format file through the write file function; After the simulation is complete, the text format file is closed using the file close function.

4. The method according to claim 1 or the system according to claim 2, characterized in that, The incentive file parsing step involves parsing the file content and extracting the digital incentive data, specifically including: Read the contents of the stimulus file, search for delimiters in the file, and determine the total amount of data to be sent or the number of data changes based on the number of delimiters; The system performs a loop parsing process based on the total amount of data or the number of data changes, converting the input string data into unsigned numbers and ending the parsing operation after fixing the high and low digits of the data.

5. The method according to claim 4 or the system according to claim 4, characterized in that, In the excitation file parsing step, for excitation data of intermediate frequency signal type, the total amount of data to be sent is determined by searching the number of delimiters, and the individual data string is converted into a 16-bit unsigned number; For excitation data of envelope signal type, the number of data changes is determined by searching the number of delimiters, the values ​​and duration periods in the configuration file are parsed, and the configuration file is expanded into a one-dimensional array of data.

6. The method according to claim 1 or the system according to claim 2, characterized in that, The step of adding timing parameters involves adding timing parameters to the parsed digital excitation data, specifically including: After the complex electronic hardware under test is initialized, the default state data is output first; Add timing interval data at the beginning and end of each frame of data, and insert default state data as an interval between adjacent frames of data.

7. The method according to claim 1 or the system according to claim 2, characterized in that, In the data transmission step, the continuous analog signal data is transmitted to the complex electronic hardware under test via a direct memory access first-in-first-out channel, specifically including: Create a direct memory access first-in-first-out (DIFO) channel on the test equipment and configure the channel attributes; Instantiate a direct memory access controller on the complex electronic hardware under test and configure a first-in-first-out interface; The test equipment writes continuous analog signal data into the direct memory access buffer; The complex electronic hardware under test reads data from memory through the direct memory access controller and stores it in the local first-in-first-out buffer.

8. The method according to claim 7 or the system according to claim 7, characterized in that, The test equipment uses NI devices and a direct memory access first-in-first-out channel is created using LabVIEW; the complex electronic hardware under test reads data by instantiating an AXI direct memory access intellectual property core.

9. The method according to claim 1 or the system according to claim 2, characterized in that, In the result comparison and verification step, the physical test results of the complex electronic hardware under test under the continuous analog signal data excitation are collected and compared with the simulation results generated by the simulation platform under the same excitation. Specifically, this includes: Acquire the physical test waveform file generated by the test equipment during the excitation input process; Obtain the simulation waveform file generated by the simulation platform under the same excitation; The consistency between the physical test waveform file and the simulation waveform file is compared, and the functional correctness of the complex electronic hardware is judged based on the comparison results.

10. The method according to claim 1 or the system according to claim 2, characterized in that, The stimulus file generated in the simulation stimulus generation step is a text file in txt format. The digital stimulus signal includes an intermediate frequency signal and an envelope signal. The continuous analog signal data is used for functional verification of complex electronic hardware in the traffic monitoring system.

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