Timing optimization method and apparatus, electronic device, and storage medium

Abstract

The application provides a timing optimization method and device, electronic equipment and storage medium, and relates to the technical field of timing optimization. The method comprises the following steps: obtaining timing violation information corresponding to a target chip, and determining at least one timing violation path, a violation value of each timing violation path and a target violation point on each timing violation path according to the timing violation information; obtaining multiple types of filling units added in a preset blank area of the target violation point on the timing violation path; determining a target buffer corresponding to the timing violation path, and determining a target filling unit corresponding to the target violation point according to the type of the target buffer, a timing margin of the target violation point on the timing violation path and the violation value of the timing violation path; and inserting the target buffer into a position where the target filling unit is located according to filling information of the target filling unit, and performing wire routing. The method can improve timing optimization efficiency, and ensure timing repair effect without increasing chip area.

Description

Technical Field

[0001] This application relates to the field of timing optimization technology, and more specifically, to a timing optimization method, apparatus, electronic device, and storage medium. Background Technology

[0002] In the design of very large-scale chips (VLSI), the increasing number of module cells leads to increasingly larger design spaces, making the balance between area utilization and timing performance crucial. Typically, certain areas within a chip are prone to congestion due to the large number of module cells or limited wiring resources, and these congested areas are often accompanied by tight timing constraints. Therefore, how to rationally allocate and utilize space resources in congested areas to simultaneously meet the requirements of timing convergence and area optimization has become an urgent problem to be solved.

[0003] In existing technologies, timing repair typically involves deleting all padding cells, inserting buffers, and then using placement tools to automatically optimize the placement of the inserted buffers. After placement, padding cells are added again, and timing checks are performed after placement and routing. This process is repeated iteratively until timing convergence is achieved or no new violations occur.

[0004] The above method requires a large number of iterations, and the placement of the buffer is difficult to achieve as expected, making timing convergence difficult. Summary of the Invention

[0005] The purpose of this application is to address the shortcomings of the prior art by providing a timing optimization method, apparatus, electronic device, and storage medium, so as to reduce the iterative steps of timing optimization, while taking a compromise between timing and chip area, and ensuring the timing repair effect while minimizing the increase in chip area.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a timing optimization method, including: obtaining timing violation information corresponding to a target chip, and determining at least one timing violation path, violation value of each timing violation path, and target violation point on each timing violation path based on the timing violation information; Obtain various types of padding units added to the preset blank area of ​​the target violation point on the timing violation path; wherein the attributes of the padding units are determined according to the attributes of the buffer; Determine the target buffer corresponding to the timing violation path, and determine the target fill unit corresponding to the target violation point based on the type of the target buffer, the timing margin of the target violation point on the timing violation path, and the violation value of the timing violation path; Based on the filling information of the target filling unit, the target buffer is inserted into the position where the target filling unit is located, and winding is performed.

[0007] Optionally, determining at least one timing violation path, the violation value of each timing violation path, and the target violation point on each timing violation path based on the timing violation information includes: Based on the timing violation information, at least one timing violation path and the violation value of each timing violation path are determined; Based on the timing margin of each violation point on each timing violation path and the violation value of each timing violation path, the target violation point on each timing violation path is determined from the violation points on each timing violation path.

[0008] Optionally, determining the target violation point on each timing violation path from the violation points on each timing violation path based on the timing margin of each violation point on each timing violation path and the violation value of each timing violation path includes: The violation point with the largest timing margin on the timing violation path that is greater than the violation value of the timing violation path is taken as the target violation point on the timing violation path.

[0009] Optionally, determining the target padding unit corresponding to the target violation point based on the type of the target buffer, the timing margin of the target violation point on the timing violation path, and the violation value of the timing violation path includes: Based on the type of the target buffer corresponding to the timing violation path, at least one candidate padding unit matching the type of the target buffer is captured from a preset range of the target violation point on the timing violation path; Based on the timing margin of the target violation point on the timing violation path, the violation value of the timing violation path, and the distance information between each candidate fill unit and the target violation point, the target fill unit corresponding to the target violation point on the timing violation path is determined from each candidate fill unit.

[0010] Optionally, determining the target fill unit corresponding to the target violation point on the timing violation path from among the candidate fill units based on the timing margin of the target violation point on the timing violation path, the violation value of the timing violation path, and the distance information between each candidate fill unit and the target violation point includes: If the timing margin of the target violation point and the violation value satisfy a first relationship, then based on the distance information between each candidate fill unit and the target violation point, the candidate fill unit closest to the target violation point is determined from among the candidate fill units as the target fill unit; the first relationship is used to characterize that the timing margin of the target violation point is insufficient. If the timing margin of the target violation point and the violation value satisfy the second relationship, then the target filling unit corresponding to the target violation point is determined from each candidate filling unit according to the congestion level of the region where each candidate filling unit is located and the distance information between each candidate filling unit and the target violation point; the second relationship is used to characterize that the timing margin of the target violation point is sufficient.

[0011] Optionally, determining the target fill unit corresponding to the target violation point from among the candidate fill units based on the congestion level of the region where each candidate fill unit is located and the distance information between each candidate fill unit and the target violation point includes: Based on the congestion level of the region where each candidate filling unit is located, target candidate filling units with a congestion level less than a preset threshold are determined from each candidate filling unit. Based on the distance information between each target candidate fill unit and the target violation point, the target candidate fill unit closest to the target violation point is determined as the target fill unit.

[0012] Optionally, determining the target buffer corresponding to the timing violation path includes: Based on the violation value of the timing violation path, determine the target buffer corresponding to the timing violation path.

[0013] Optionally, the step of inserting the target buffer into the position of the target filling unit according to the filling information of the target filling unit and performing winding includes: The insertion position of the target buffer is determined based on the placement position of the target filling unit; The placement orientation of the target buffer is determined based on the placement orientation of the target filling unit; Based on the insertion position and orientation of the target buffer, insert the target buffer into the position where the target filling unit is located, and then delete the target filling unit.

[0014] Optionally, the filler units are added during the layout and routing phase.

[0015] Optionally, obtaining the timing violation information corresponding to the target chip includes: During the timing optimization phase, timing violation information corresponding to the target chip is obtained.

[0016] Secondly, embodiments of this application also provide a timing optimization apparatus, including: a determining module, an acquiring module, and a processing module; The determining module is used to obtain timing violation information corresponding to the target chip, and determine at least one timing violation path, the violation value of each timing violation path, and the target violation point on each timing violation path based on the timing violation information. The acquisition module is used to acquire multiple types of padding units added to the preset blank area of ​​the target violation point on the timing violation path; wherein the attributes of the padding units are determined according to the attributes of the buffer. The determining module is used to determine the target buffer corresponding to the timing violation path, and to determine the target fill unit corresponding to the target violation point based on the type of the target buffer, the timing margin of the target violation point on the timing violation path, and the violation value of the timing violation path. The processing module is used to insert the target buffer into the position of the target filling unit according to the filling information of the target filling unit, and perform winding.

[0017] Optionally, the determining module is specifically used to determine at least one timing violation path and the violation value of each timing violation path based on the timing violation information. Based on the timing margin of each violation point on each timing violation path and the violation value of each timing violation path, the target violation point on each timing violation path is determined from the violation points on each timing violation path.

[0018] Optionally, the determining module is specifically used to select the violation point with the largest timing margin on the timing violation path and greater than the violation value of the timing violation path as the target violation point on the timing violation path.

[0019] Optionally, the determining module is specifically used to extract at least one candidate padding unit that matches the type of the target buffer from a preset range of the target violation point on the timing violation path, based on the type of the target buffer corresponding to the timing violation path. Based on the timing margin of the target violation point on the timing violation path, the violation value of the timing violation path, and the distance information between each candidate fill unit and the target violation point, the target fill unit corresponding to the target violation point on the timing violation path is determined from each candidate fill unit.

[0020] Optionally, the determining module is specifically used to determine the candidate filling unit closest to the target violation point as the target filling unit based on the distance information between each candidate filling unit and the target violation point if the timing margin of the target violation point and the violation value satisfy a first relationship; the first relationship is used to characterize that the timing margin of the target violation point is insufficient. If the timing margin of the target violation point and the violation value satisfy the second relationship, then the target filling unit corresponding to the target violation point is determined from each candidate filling unit according to the congestion level of the region where each candidate filling unit is located and the distance information between each candidate filling unit and the target violation point; the second relationship is used to characterize that the timing margin of the target violation point is sufficient.

[0021] Optionally, the determining module is specifically used to determine each target candidate filling unit whose congestion level is less than a preset threshold from among the candidate filling units based on the congestion level of the region where each candidate filling unit is located. Based on the distance information between each target candidate fill unit and the target violation point, the target candidate fill unit closest to the target violation point is determined as the target fill unit.

[0022] Optionally, the determining module is specifically used to determine the target buffer corresponding to the timing violation path based on the violation value of the timing violation path.

[0023] Optionally, the processing module is specifically used to determine the insertion position of the target buffer based on the placement position of the target filling unit; The placement orientation of the target buffer is determined based on the placement orientation of the target filling unit; Based on the insertion position and orientation of the target buffer, insert the target buffer into the position where the target filling unit is located, and then delete the target filling unit.

[0024] Optionally, the filler units are added during the layout and routing phase.

[0025] Optionally, the determining module is specifically used to obtain timing violation information corresponding to the target chip during the timing optimization stage.

[0026] Thirdly, embodiments of this application provide an electronic device, including: a processor, a storage medium, and a bus. The storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to implement the timing optimization method provided in the first aspect.

[0027] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that is executed by a processor using the timing optimization method provided in the first aspect.

[0028] The beneficial effects of this application are: This application provides a timing optimization method, apparatus, electronic device, and storage medium, comprising: acquiring timing violation information corresponding to a target chip, and determining at least one timing violation path, the violation value of each timing violation path, and the target violation point on each timing violation path based on the timing violation information; acquiring multiple types of fill units added to a preset blank area of ​​the target violation point on the timing violation path; determining a target buffer corresponding to the timing violation path, and determining a target fill unit corresponding to the target violation point based on the type of the target buffer, the timing margin of the target violation point on the timing violation path, and the violation value of the timing violation path; inserting the target buffer into the position of the target fill unit according to the fill information of the target fill unit, and performing routing. This method pre-adds various types of padding cells around the target violation point in the timing violation path during the initial physical design and placement / routing phase. Then, during the timing optimization phase in the later stages of physical design, it can directly select the target padding cell from the added padding cells that matches the target buffer used for timing repair. The target buffer is then used to replace the target padding cell in situ, and finally, the target padding cell is deleted. This achieves rapid timing repair without triggering placement re-optimization, improving the efficiency of timing optimization. Simultaneously, the selection of the target padding cell effectively balances timing and chip area congestion, determining a more reasonable buffer insertion position. This solves timing problems while making reasonable use of congested areas, ensuring timing repair effectiveness without increasing chip area.

[0029] When timing is tight around the target violation point, the nearest fill cell is prioritized as the target fill cell. This effectively utilizes the congested area and reduces the increased routing costs associated with inserting the target buffer, thus better matching the latency introduced by buffer insertion. When timing is relatively ample around the target violation point, the nearest fill cell in a low-congestion area is prioritized as the target fill cell. This effectively frees up resources in the congested area to reserve space for buffer insertion should violations occur in the congested area later. Furthermore, inserting a buffer in a low-congestion area does not increase chip area, achieving a trade-off between timing and chip area. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1A flowchart illustrating the timing optimization method provided in the embodiments of this application. Figure 1 ; Figure 2 A flowchart illustrating the timing optimization method provided in the embodiments of this application. Figure 2 ; Figure 3 A flowchart illustrating the timing optimization method provided in the embodiments of this application. Figure 3 ; Figure 4 A flowchart illustrating the timing optimization method provided in the embodiments of this application. Figure 4 ; Figure 5 A schematic diagram illustrating the buffer insertion position provided in an embodiment of this application; Figure 6 A flowchart illustrating the timing optimization method provided in the embodiments of this application. Figure 5 ; Figure 7 A schematic diagram of a timing optimization device provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0033] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0034] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0035] In the design of very large-scale chips (VLSI), the chip area increases dramatically due to the increased number of module cells. During the physical design phase, timing convergence and chip area control become the core challenges. Typically, to meet stringent timing requirements, design tools often employ timing convergence by inserting buffers or increasing the size of driver cells, directly leading to increased chip area and power consumption. Conversely, compressing module cells to control area utilization can easily result in timing violations. Therefore, it is necessary to consider both chip area and timing in this way.

[0036] Secondly, as the design scale continues to expand, the time for each round of timing iteration optimization is also gradually increasing. The traditional placement and routing process requires multiple rounds of analysis and optimization cycles to finally achieve timing convergence, and how to reduce the number of iteration steps also needs to be considered simultaneously.

[0037] Based on this, this application provides a timing optimization method. In the early stages of physical design, during the placement and routing phase, filler cells of various attributes are pre-added around the violation points with the largest timing margins along the violation paths reported in the violation reports. In the later stages of physical design, during the timing optimization phase, matching filler cells are selected from around the violation points for replacement. The buffers required for timing repair can be directly replaced with the corresponding filler cells, and then the corresponding filler cells can be deleted. This eliminates the need to re-place and re-route the cells after inserting the buffers, effectively reducing the iterative steps of timing optimization.

[0038] Secondly, when selecting matching fill cells, the relationship between the timing margin of the violation point and the violation value of the violation path can be used to determine whether the timing around the violation point is tight. In this case, fill cells in the nearest location are selected for buffer replacement and insertion, while fill cells in the less congested area are selected for buffer replacement and insertion when the timing around the violation point is sufficient. This fully considers the trade-off between timing and area congestion, and prioritizes the use of congested area area for cells with tight timing, and prioritizes the use of area area with low congestion rate for cells with ample timing. This ensures that when timing is tight, the insertion of buffers will not increase the routing too much, and when timing is sufficient, the routing flexibility of low congestion rate area is reasonably utilized, reserving space for possible buffer insertion in subsequent congested areas.

[0039] Figure 1 A flowchart illustrating the timing optimization method provided in the embodiments of this application. Figure 1 The subject executing this method can be a computer device, such as... Figure 1 As shown, the method includes: S101. Obtain timing violation information corresponding to the target chip, and determine at least one timing violation path, the violation value of each timing violation path, and the target violation point on each timing violation path based on the timing violation information.

[0040] A target chip can refer to a chip that has timing violations and requires timing repair. In the early stages of physical design, the target chip can be designed through module placement and routing. In the later stages of physical design, during the timing optimization phase, timing optimization processes can be used to repair the timing of target chips that do not meet timing requirements.

[0041] Timing analysis of the target chip can be performed using timing tools, and timing violation information of the target chip can be output. Based on the timing violation information, at least one timing violation path on the target chip can be identified, as well as the violation value of each timing violation path. The violation value of a timing violation path can refer to the hold time violation value of the timing violation path.

[0042] Additionally, it can output the violation points contained in each timing violation path and the timing margin of the establishment time of each violation point. Therefore, the target violation point on each timing violation path can be determined based on the timing margin of the establishment time of each violation point.

[0043] S102. Obtain various types of fill units added to the preset blank area of ​​the target violation point on the timing violation path.

[0044] The properties of the fill cells are determined based on the properties of the buffer.

[0045] After identifying the target violation point, it is possible to further obtain various types of fill cells added around the target violation point. Among them, fill cells are pre-inserted in the early stage of physical design, that is, the placement and routing stage.

[0046] Filler cells refer to cells stored in the standard cell library that have no functionality and are only used for placement. This is similar to pre-writing the legal placeholders and parasitic environments for each type of buffer around the target violation point. In this way, during subsequent timing repair, buffers can be directly used to replace filler cells in situ, enabling rapid timing repair without triggering layout re-optimization.

[0047] It should be noted that the attributes of the fill cells may include, but are not limited to, the size and orientation of the fill cells. Specifically, the attributes of the various fill cells to be added can be determined based on the attributes of the various buffers that may be used during timing repair.

[0048] Each type of buffer has a corresponding size and orientation. When adding filler units, you can choose to add filler units that match the size and orientation of various buffers. Since the size of buffers varies, the size of the added filler units also varies to ensure that the corresponding filler units can be effectively matched when inserting buffers later, thus ensuring accurate insertion of the buffers.

[0049] S103. Determine the target buffer corresponding to the timing violation path, and determine the target fill unit corresponding to the target violation point based on the type of the target buffer, the timing margin of the target violation point on the timing violation path, and the violation value of the timing violation path.

[0050] Based on the specific size of the timing violation path, it can be determined which type of buffer needs to be inserted to repair the current timing violation, thus identifying the target buffer.

[0051] The target fill cell refers to the fill cell that needs to be replaced by the target buffer. The selection of the target fill cell needs to take into account both the type of the target buffer and the timing tension / timing leeway around the target violation point on the timing violation path.

[0052] The timing tension / timing leeway around the target violation point can be determined based on the timing margin of the target violation point and the violation value of the timing violation path.

[0053] By assessing the timing constraints around the target violation point, a compromise can be effectively struck between timing and chip area congestion to determine a more reasonable buffer insertion location. The buffer insertion location is also the location of the target fill cell to be determined.

[0054] S104. Based on the filling information of the target filling unit, insert the target buffer into the position where the target filling unit is located, and perform winding.

[0055] Based on the identified target fill cell, the target buffer can be replaced in situ. This means inserting the target buffer into the location of the target fill cell and then deleting the target fill cell. Afterward, the target buffer is connected to the violation point to complete the routing, without requiring additional modifications to the placement and routing of other existing modules or cells. This allows for the fastest possible timing repair, reducing the iterative steps required for timing optimization.

[0056] In summary, the timing optimization method provided in this embodiment includes: obtaining timing violation information corresponding to the target chip, and determining at least one timing violation path, the violation value of each timing violation path, and the target violation point on each timing violation path based on the timing violation information; obtaining multiple types of fill units added to the preset blank area of ​​the target violation point on the timing violation path; determining the target buffer corresponding to the timing violation path, and determining the target fill unit corresponding to the target violation point based on the type of the target buffer, the timing margin of the target violation point on the timing violation path, and the violation value of the timing violation path; inserting the target buffer into the position where the target fill unit is located based on the fill information of the target fill unit, and performing routing. This method pre-adds various types of padding cells around the target violation point in the timing violation path during the initial physical design and placement / routing phase. Then, during the timing optimization phase in the later stages of physical design, it can directly select the target padding cell from the added padding cells that matches the target buffer used for timing repair. The target buffer is then used to replace the target padding cell in situ, and finally, the target padding cell is deleted. This achieves rapid timing repair without triggering placement re-optimization, improving the efficiency of timing optimization. Simultaneously, the selection of the target padding cell effectively balances timing and chip area congestion, determining a more reasonable buffer insertion position. This solves timing problems while making reasonable use of congested areas, ensuring timing repair effectiveness without increasing chip area.

[0057] Figure 2 A flowchart illustrating the timing optimization method provided in the embodiments of this application. Figure 2 Optionally, in step S101, based on the timing violation information, determining at least one timing violation path, the violation value of each timing violation path, and the target violation point on each timing violation path includes: S201. Based on the timing violation information, determine at least one timing violation path and the violation value of each timing violation path.

[0058] In some embodiments, the timing violation information includes all relevant violation information for timing violations in the target chip. Therefore, at least one timing violation path and the violation value of each timing violation path in the target chip can be directly determined from the timing violation information. Here, the violation value can refer to the violation value of the hold time.

[0059] S202. Based on the timing margin of each violation point on each timing violation path and the violation value of each timing violation path, determine the target violation point on each timing violation path from the violation points on each timing violation path.

[0060] Typically, a timing violation path may contain multiple violation points. A violation point can refer to a checkpoint on the timing path that fails to meet a specific time constraint.

[0061] The timing margin of a violation point can refer to the timing margin of the establishment time of the violation point.

[0062] Hold time refers to the shortest time a data signal must remain stable after the arrival of a valid clock edge (such as a rising edge). Setup time refers to the shortest time a data signal must arrive and remain stable before the arrival of a valid clock edge (such as a rising edge).

[0063] Taking a timing violation path as an example, the timing margin of each violation point on the timing violation path and the violation value of the timing violation path can be compared with the violation value of the timing violation path to determine the target violation point.

[0064] It is worth noting that the identified target violation point can be a point that simultaneously satisfies electrical feasibility, physical safety, and operational controllability. By adding filler cells around the target violation point, it can be ensured that after subsequent in-situ replacement of the buffer, a stable timing convergence margin can still be maintained, even considering process fluctuations, changes in interconnect parasitic parameters, and signal integrity effects.

[0065] Optionally, in step S202, based on the timing margin of each violation point on each timing violation path and the violation value of each timing violation path, the target violation point on each timing violation path is determined from the violation points on each timing violation path, including: taking the violation point with the largest timing margin on the timing violation path and greater than the violation value of the timing violation path as the target violation point on the timing violation path.

[0066] In some embodiments, the timing margin of each violation point on the timing violation path can be compared with the violation value of the timing violation path, and the violation point with the largest timing margin and greater than the violation value can be selected as the target violation point.

[0067] Typically, violation points with the largest timing margins exceeding the violation value are located on the timing violation path that are furthest from the electrical failure point and have the best tolerance for buffer parameters. Furthermore, points with large timing margins within the path tend to have relatively loose local conditions and low congestion risk. Therefore, selecting target violation points in the above manner and subsequently inserting buffers around them for timing repair can improve the success rate of timing repair and avoid module relocation after buffer insertion, thus reducing the number of timing optimization iterations.

[0068] Optionally, in step S103, determining the target buffer corresponding to the timing violation path includes: determining the target buffer corresponding to the timing violation path based on the violation value of the timing violation path.

[0069] During the timing optimization phase, the type of target buffer to be inserted to fix the timing violation can be determined based on the violation value of the reported timing violation path. Different violation values ​​require different buffer types. For example, a violation value of 10p corresponds to a BUFV1 target buffer, while a violation value of 15p corresponds to a BUFV2 target buffer.

[0070] Figure 3 A flowchart illustrating the timing optimization method provided in the embodiments of this application. Figure 3 Optionally, in step S103, the target fill unit corresponding to the target violation point is determined based on the type of the target buffer, the timing margin of the target violation point on the timing violation path, and the violation value of the timing violation path, including: S301. Based on the type of the target buffer corresponding to the timing violation path, at least one candidate padding unit matching the type of the target buffer is captured from the preset range of the target violation point on the timing violation path.

[0071] First, all fill cells within a preset range can be captured, centered on the target violation point. The preset range here is similar in size to the preset range used when adding fill cells around the target violation point in advance, for example, both can be within a distance of 50um.

[0072] Based on all captured padding cells, at least one candidate padding cell matching the type of the target buffer can be selected from all padding cells according to the determined target buffer type. Specifically, at least one candidate padding cell matching the size of the target buffer can be selected from all padding cells according to the size of the target buffer, ensuring that the padding cell to be replaced can precisely accommodate the target buffer during subsequent in-situ buffer replacement.

[0073] S302. Based on the timing margin of the target violation point on the timing violation path, the violation value of the timing violation path, and the distance information between each candidate fill unit and the target violation point, determine the target fill unit corresponding to the target violation point on the timing violation path from each candidate fill unit.

[0074] Next, we can iterate through each of the selected candidate fill cells and determine the target fill cell according to the required distance based on the distance between each candidate fill cell and the target violation point.

[0075] Optionally, the timing severity around the target violation point can be determined first based on the timing margin of the target violation point and the violation value of the timing violation path. Then, for cases of timing severity, a distance selection method corresponding to timing severity can be used to select the corresponding target fill cell; conversely, for cases with sufficient timing, a distance selection method corresponding to sufficient timing can also be used to select the corresponding target fill cell. This allows for the determination of a more reasonable cache insertion location, which can solve timing problems while minimizing the increase in chip area.

[0076] Optionally, in step S302, the target filling unit corresponding to the target violation point on the timing violation path is determined from each candidate filling unit based on the timing margin of the target violation point on the timing violation path, the violation value of the timing violation path, and the distance information between each candidate filling unit and the target violation point. This includes: if the timing margin of the target violation point and the violation value satisfy a first relationship, then the candidate filling unit closest to the target violation point is determined from each candidate filling unit as the target filling unit based on the distance information between each candidate filling unit and the target violation point; the first relationship is used to characterize that the timing margin of the target violation point is insufficient.

[0077] In one scenario, when the timing margin of the target violation point is less than 10p greater than the violation value of the timing violation path (that is, when the timing margin is greater than the violation value, but does not exceed the violation value + 10p; of course, 10p here is determined based on experience, and can be flexibly adjusted in actual applications), although the timing margin is larger than the violation value, it is not much larger and is still relatively close to the violation value. Therefore, it is considered that the timing margin around the target violation point is insufficient and the timing is relatively tight.

[0078] When the timing around the target violation point is tight, the area of ​​the congested region can be used as a priority. Based on the distance information between each candidate fill cell and the target violation point, the candidate fill cell closest to the target violation point can be selected as the target fill cell.

[0079] When timing is tight, inserting a buffer at a closer location can better match the insertion delay and will not be affected by the trace's delay. If a buffer is inserted at a farther location, a longer trace is required. When the trace is too long, the delay is difficult to predict and crosstalk is likely to occur, which has a greater impact on timing.

[0080] If the timing margin of the target violation point and the violation value satisfy the second relationship, then the target filling unit corresponding to the target violation point is determined from each candidate filling unit based on the congestion level of the region where each candidate filling unit is located and the distance information between each candidate filling unit and the target violation point; the second relationship is used to characterize that the timing margin of the target violation point is sufficient.

[0081] In another case, when the timing margin of the target violation point is greater than the violation value by more than 10p (that is, when the timing margin is greater than the violation value and exceeds the violation value + 10p), the timing margin is much larger than the violation value. Therefore, it is considered that the timing margin around the target violation point is relatively sufficient and the timing is relatively generous.

[0082] When there is sufficient time around the target violation point, the resources of the region with lower congestion rate can be prioritized based on the congestion level of the region where each candidate fill unit is located and the distance information between each candidate fill unit and the target violation point. The target fill unit can be determined from the region with lower congestion rate, so as not to affect the situation where there is no place to insert the buffer when there is a violation in the subsequent congested region.

[0083] Figure 4 A flowchart illustrating the timing optimization method provided in the embodiments of this application. Figure 4 Optionally, in the above steps, determining the target fill unit corresponding to the target violation point from among the candidate fill units based on the congestion level of the region where each candidate fill unit is located and the distance information between each candidate fill unit and the target violation point includes: S401. Based on the congestion level of the region where each candidate filling unit is located, determine each target candidate filling unit whose congestion level is less than a preset threshold from among the candidate filling units.

[0084] Optionally, based on the congestion level of the region where each candidate filling unit is located, a target candidate filling unit whose congestion level is less than a preset threshold can be selected. For example, the preset threshold can be 80%. If the congestion level of a region is less than 80%, it is considered that the region's congestion rate is relatively low, and the region where the target candidate filling unit is located has a low congestion rate.

[0085] S402. Based on the distance information between each target candidate filling unit and the target violation point, determine the target candidate filling unit that is closest to the target violation point from each target candidate filling unit as the target filling unit.

[0086] Based on the identified target candidate filling units, the filling unit closest to the target violation point can be selected as the final target filling unit.

[0087] It's worth noting that when timing is tight around the target violation point, the nearest fill cell is prioritized as the target fill cell. This effectively utilizes the congested area and reduces the increased routing costs associated with inserting the target buffer, thus better matching the latency introduced by buffer insertion. Conversely, when timing is relatively ample around the target violation point, the nearest fill cell in a low-congestion area is prioritized as the target fill cell. This effectively frees up resources in the congested area, reserving space for buffer insertion should violations occur in the congested area later. Furthermore, inserting a buffer in a low-congestion area does not increase chip area, achieving a trade-off between timing and chip area.

[0088] Figure 5 This is a schematic diagram illustrating the buffer insertion position provided in an embodiment of this application, as shown below. Figure 5 The blue rectangle marks the location of the target violation point. When the timing around the target violation point is tight, the target buffer is inserted at the position indicated by red square 1. When the timing around the target violation point is sufficient, the target buffer is inserted at the position indicated by red square 2.

[0089] Figure 6 A flowchart illustrating the timing optimization method provided in the embodiments of this application. Figure 5 Optionally, in step S104, based on the filling information of the target filling unit, the target buffer is inserted into the position where the target filling unit is located, and winding is performed, including: S501. Determine the insertion position of the target buffer based on the placement position of the target filling unit.

[0090] Optionally, the placement position of the target filling unit can be determined based on the determined position coordinates of the target filling unit, and then the placement position can be used as the insertion position of the target buffer.

[0091] S502. Determine the placement orientation of the target buffer based on the placement orientation of the target filling unit.

[0092] The placement orientation determines the orientation of the buffer pins and the wiring topology. Each filler unit already satisfies the orientation constraint when it is added in advance. The placement orientation of the filler unit is usually automatically set by the placement tool according to the density / alignment rules. The buffer has a clear signal flow direction and must inherit or adapt to the main wiring direction of the local area. Therefore, the placement orientation of the target buffer can be determined according to the placement orientation of the target filler unit to ensure that the target buffer has the correct signal flow direction after insertion.

[0093] S503. Based on the insertion position and orientation of the target buffer, insert the target buffer into the position of the target filling unit and delete the target filling unit.

[0094] The target buffer can be inserted at the determined insertion position and placed according to the determined orientation. At the same time, the target fill unit replaced by the target buffer is deleted. Then, the winding is completed by connecting the target buffer with the target violation point.

[0095] Optionally, fill cells are added during the placement and routing phase.

[0096] In this embodiment, during the initial physical design and placement and routing phase, all types of fill cells in the cell library can be captured, and fill cells of various types can be added to the 50µm blank area around all points with the largest timing margin. The addition method can be to first add the largest fill cell, then add the second largest fill cell, and so on, adding fill cells of each size in a loop.

[0097] Optionally, in step S101, obtaining the timing violation information corresponding to the target chip includes: obtaining the timing violation information corresponding to the target chip during the timing optimization stage.

[0098] In some embodiments, during the timing optimization stage in the later stages of physical design, timing violation information corresponding to the target chip can be obtained based on the violation analysis data reported by the timing tool, and timing repair can be performed according to the timing repair method provided in the above embodiments.

[0099] In summary, the timing optimization method provided in this embodiment includes: obtaining timing violation information corresponding to the target chip, and determining at least one timing violation path, the violation value of each timing violation path, and the target violation point on each timing violation path based on the timing violation information; obtaining multiple types of fill units added to the preset blank area of ​​the target violation point on the timing violation path; determining the target buffer corresponding to the timing violation path, and determining the target fill unit corresponding to the target violation point based on the type of the target buffer, the timing margin of the target violation point on the timing violation path, and the violation value of the timing violation path; inserting the target buffer into the position where the target fill unit is located based on the fill information of the target fill unit, and performing routing. This method pre-adds various types of padding cells around the target violation point in the timing violation path during the initial physical design and placement / routing phase. Then, during the timing optimization phase in the later stages of physical design, it can directly select the target padding cell from the added padding cells that matches the target buffer used for timing repair. The target buffer is then used to replace the target padding cell in situ, and finally, the target padding cell is deleted. This achieves rapid timing repair without triggering placement re-optimization, improving the efficiency of timing optimization. Simultaneously, the selection of the target padding cell effectively balances timing and chip area congestion, determining a more reasonable buffer insertion position. This solves timing problems while making reasonable use of congested areas, ensuring timing repair effectiveness without increasing chip area.

[0100] When timing is tight around the target violation point, the nearest fill cell is prioritized as the target fill cell. This effectively utilizes the congested area and reduces the increased routing costs associated with inserting the target buffer, thus better matching the latency introduced by buffer insertion. When timing is relatively ample around the target violation point, the nearest fill cell in a low-congestion area is prioritized as the target fill cell. This effectively frees up resources in the congested area to reserve space for buffer insertion should violations occur in the congested area later. Furthermore, inserting a buffer in a low-congestion area does not increase chip area, achieving a trade-off between timing and chip area.

[0101] The following describes the apparatus, device, and storage medium used to implement the timing optimization method provided in this application. The specific implementation process and technical effects are described above and will not be repeated below.

[0102] Figure 7This is a schematic diagram of a timing optimization device provided in an embodiment of this application. The function implemented by this timing optimization device corresponds to the steps performed by the method described above. This device can be understood as the aforementioned computer equipment or server, or the processor of a server, or it can be understood as a component that implements the functions of this application under the control of a server, independent of the aforementioned server or processor. Figure 7 As shown, the device may include: a determining module 100, an acquiring module 200, and a processing module 300; The determination module 100 is used to obtain timing violation information corresponding to the target chip, and determine at least one timing violation path, the violation value of each timing violation path, and the target violation point on each timing violation path based on the timing violation information. The acquisition module 200 is used to acquire various types of padding units added to the preset blank area of ​​the target violation point on the timing violation path; wherein, the attributes of the padding units are determined according to the attributes of the buffer. The determination module 100 is used to determine the target buffer corresponding to the timing violation path, and to determine the target fill unit corresponding to the target violation point based on the type of the target buffer, the timing margin of the target violation point on the timing violation path and the violation value of the timing violation path. The processing module 300 is used to insert the target buffer into the position of the target filling cell according to the filling information of the target filling cell, and to perform winding.

[0103] Optionally, the determining module 100 is specifically used to determine at least one timing violation path and the violation value of each timing violation path based on the timing violation information. Based on the timing margin of each violation point on each timing violation path and the violation value of each timing violation path, the target violation point on each timing violation path is determined from the violation points on each timing violation path.

[0104] Optionally, the determining module 100 is specifically used to take the violation point with the largest timing margin on the timing violation path and greater than the violation value of the timing violation path as the target violation point on the timing violation path.

[0105] Optionally, the determining module 100 is specifically used to extract at least one candidate padding unit that matches the type of the target buffer from a preset range of the target violation point on the timing violation path, based on the type of the target buffer corresponding to the timing violation path. Based on the timing margin of the target violation point on the timing violation path, the violation value of the timing violation path, and the distance information between each candidate fill cell and the target violation point, the target fill cell corresponding to the target violation point on the timing violation path is determined from each candidate fill cell.

[0106] Optionally, the determining module 100 is specifically used to determine the candidate filling unit closest to the target violation point as the target filling unit based on the distance information between each candidate filling unit and the target violation point if the timing margin of the target violation point and the violation value satisfy the first relationship; the first relationship is used to characterize that the timing margin of the target violation point is insufficient. If the timing margin of the target violation point and the violation value satisfy the second relationship, then the target filling unit corresponding to the target violation point is determined from each candidate filling unit based on the congestion level of the region where each candidate filling unit is located and the distance information between each candidate filling unit and the target violation point; the second relationship is used to characterize that the timing margin of the target violation point is sufficient.

[0107] Optionally, the determining module 100 is specifically used to determine each target candidate filling unit whose congestion level is less than a preset threshold from each candidate filling unit according to the congestion level of the region where each candidate filling unit is located. Based on the distance information between each target candidate fill cell and the target violation point, the target candidate fill cell closest to the target violation point is selected as the target fill cell.

[0108] Optionally, the determining module 100 is specifically used to determine the target buffer corresponding to the timing violation path based on the violation value of the timing violation path.

[0109] Optionally, the processing module 300 is specifically used to determine the insertion position of the target buffer based on the placement position of the target filling unit; Determine the orientation of the target buffer based on the orientation of the target filling unit; Based on the insertion position and orientation of the target buffer, insert the target buffer into the position of the target fill cell, and then delete the target fill cell.

[0110] Optionally, fill cells are added during the placement and routing phase.

[0111] Optionally, the determination module 100 is specifically used to obtain timing violation information corresponding to the target chip during the timing optimization stage.

[0112] The above-described device is used to execute the method provided in the foregoing embodiments, and its implementation principle and technical effect are similar, so they will not be described again here.

[0113] These modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more digital signal processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). Alternatively, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a system-on-a-chip (SOC).

[0114] The modules described above can be connected or communicate with each other via wired or wireless connections. Wired connections may include metal cables, optical fibers, hybrid cables, or any combination thereof. Wireless connections may include connections via LAN, WAN, Bluetooth, ZigBee, or NFC, or any combination thereof. Two or more units can be combined into a single module, and any module can be divided into two or more units. Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems and devices described above can be referred to the corresponding processes in the method embodiments, and will not be repeated here.

[0115] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The device may be a computing device with data processing capabilities.

[0116] The device includes a processor 801, a storage medium 802, and a bus 803. The storage medium 802 stores program instructions that can be executed by the processor 801. When the electronic device is running, the processor 801 communicates with the storage medium 802 through the bus 803. The processor 801 executes the program instructions to implement the timing optimization method as described in the embodiment.

[0117] The storage medium 802 stores program code, which, when executed by the processor 801, causes the processor 801 to perform various steps in the timing optimization method according to various exemplary embodiments of this application as described in the "Exemplary Methods" section above.

[0118] The processor 801 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0119] Storage medium 802, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The storage medium can include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type storage medium, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage medium, magnetic disk, optical disk, etc. The storage medium is any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. In the embodiments of this application, storage medium 802 can also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0120] Optionally, this application also provides a program product, such as a computer-readable storage medium, including a program that, when executed by a processor, performs the above-described method embodiments.

[0121] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0122] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0123] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0124] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A timing optimization method, characterized in that, include: Obtain timing violation information corresponding to the target chip, and determine at least one timing violation path, the violation value of each timing violation path, and the target violation point on each timing violation path based on the timing violation information. Obtain various types of padding units added to the preset blank area of ​​the target violation point on the timing violation path; wherein the attributes of the padding units are determined according to the attributes of the buffer; Determine the target buffer corresponding to the timing violation path, and determine the target fill unit corresponding to the target violation point based on the type of the target buffer, the timing margin of the target violation point on the timing violation path, and the violation value of the timing violation path; Based on the filling information of the target filling unit, the target buffer is inserted into the position where the target filling unit is located, and winding is performed.

2. The method according to claim 1, characterized in that, The step of determining at least one timing violation path, the violation value of each timing violation path, and the target violation point on each timing violation path based on the timing violation information includes: Based on the timing violation information, at least one timing violation path and the violation value of each timing violation path are determined; Based on the timing margin of each violation point on each timing violation path and the violation value of each timing violation path, the target violation point on each timing violation path is determined from the violation points on each timing violation path.

3. The method according to claim 2, characterized in that, The step of determining the target violation point on each timing violation path from the violation points on each timing violation path based on the timing margin of each violation point on each timing violation path and the violation value of each timing violation path includes: The violation point with the largest timing margin on the timing violation path that is greater than the violation value of the timing violation path is taken as the target violation point on the timing violation path.

4. The method according to claim 1, characterized in that, The step of determining the target fill unit corresponding to the target violation point based on the type of the target buffer, the timing margin of the target violation point on the timing violation path, and the violation value of the timing violation path includes: Based on the type of the target buffer corresponding to the timing violation path, at least one candidate padding unit matching the type of the target buffer is captured from a preset range of the target violation point on the timing violation path; Based on the timing margin of the target violation point on the timing violation path, the violation value of the timing violation path, and the distance information between each candidate fill unit and the target violation point, the target fill unit corresponding to the target violation point on the timing violation path is determined from each candidate fill unit.

5. The method according to claim 4, characterized in that, The step of determining the target fill unit corresponding to the target violation point on the timing violation path from among the candidate fill units, based on the timing margin of the target violation point on the timing violation path, the violation value of the timing violation path, and the distance information between each candidate fill unit and the target violation point, includes: If the timing margin of the target violation point and the violation value satisfy a first relationship, then based on the distance information between each candidate fill unit and the target violation point, the candidate fill unit closest to the target violation point is determined from among the candidate fill units as the target fill unit; the first relationship is used to characterize that the timing margin of the target violation point is insufficient. If the timing margin of the target violation point and the violation value satisfy the second relationship, then the target filling unit corresponding to the target violation point is determined from each candidate filling unit according to the congestion level of the region where each candidate filling unit is located and the distance information between each candidate filling unit and the target violation point; the second relationship is used to characterize that the timing margin of the target violation point is sufficient.

6. The method according to claim 5, characterized in that, The step of determining the target fill unit corresponding to the target violation point from among the candidate fill units based on the congestion level of the region where each candidate fill unit is located and the distance information between each candidate fill unit and the target violation point includes: Based on the congestion level of the region where each candidate filling unit is located, target candidate filling units with a congestion level less than a preset threshold are determined from each candidate filling unit. Based on the distance information between each target candidate fill unit and the target violation point, the target candidate fill unit closest to the target violation point is determined as the target fill unit.

7. The method according to claim 1, characterized in that, Determining the target buffer corresponding to the timing violation path includes: Based on the violation value of the timing violation path, determine the target buffer corresponding to the timing violation path.

8. The method according to claim 1, characterized in that, The step of inserting the target buffer into the position of the target filling unit according to the filling information of the target filling unit and performing winding includes: The insertion position of the target buffer is determined based on the placement position of the target filling unit; The placement orientation of the target buffer is determined based on the placement orientation of the target filling unit; Based on the insertion position and orientation of the target buffer, insert the target buffer into the position where the target filling unit is located, and then delete the target filling unit.

9. The method according to claim 1, characterized in that, The filler units are added during the layout and routing phase.

10. The method according to claim 1, characterized in that, The step of obtaining the timing violation information corresponding to the target chip includes: During the timing optimization phase, timing violation information corresponding to the target chip is obtained.

11. A timing optimization device, characterized in that, include: The module is defined as the identification module, the acquisition module, and the processing module. The determining module is used to obtain timing violation information corresponding to the target chip, and determine at least one timing violation path, the violation value of each timing violation path, and the target violation point on each timing violation path based on the timing violation information. The acquisition module is used to acquire multiple types of padding units added to the preset blank area of ​​the target violation point on the timing violation path; wherein the attributes of the padding units are determined according to the attributes of the buffer. The determining module is used to determine the target buffer corresponding to the timing violation path, and to determine the target fill unit corresponding to the target violation point based on the type of the target buffer, the timing margin of the target violation point on the timing violation path, and the violation value of the timing violation path. The processing module is used to insert the target buffer into the position of the target filling unit according to the filling information of the target filling unit, and perform winding.

12. An electronic device, characterized in that, include: The device includes a processor, a storage medium, and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to implement the method as described in any one of claims 1-10.

13. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which is executed by a processor to implement the method as described in any one of claims 1-10.

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