A power device layout method and system based on terminal layout and cell constraint

Abstract

The application relates to the field of automatic design of semiconductor power device layout, and relates to a power device layout method and system based on terminal layout and cell constraint, which comprises the following steps: acquiring a power device, confirming global layout parameter nodes of the power device, calculating the number of cell arrays in rows and columns based on power device size parameters, cell arrangement periods and terminal ring parameters, constructing a single-side path based on the terminal ring parameters, performing a mirror Boolean merging operation on the single-side path to obtain a complete terminal ring structure, acquiring a gap region based on the complete terminal ring structure to obtain a gap path set, performing boundary analysis on an active cell array to obtain boundary feature data, and generating a metal connection structure based on the active cell array and a transition layout structure. The application can realize parameterized automatic layout and layout generation of a terminal ring and a cell array of a power device.

Description

Technical Field

[0001] This invention relates to the field of automated design of semiconductor power device layouts, and in particular to a power device layout method and system based on terminal layout and cell constraints. Background Technology

[0002] In the field of semiconductor power device design, automated layout has become a core support for modern chip design processes due to its high efficiency and consistent rules. As a key step in layout design, the quality of the termination ring structure layout and the active region cell array arrangement directly determines the device's voltage withstand performance and manufacturing yield. As power devices develop towards multiple varieties and process platforms, the termination structure has expanded from a single continuous ring to various forms such as point, mesh, and segmented hybrid structures, placing higher demands on the automation and parameterization capabilities of layout.

[0003] Currently, power device layout design mainly relies on manual drawing, where designers draw the termination rings and cell array patterns layer by layer based on process rules and design experience. Traditional methods often use a fixed template for local copying, which makes it difficult to automatically adapt to changes in termination boundaries under different chip sizes and process parameters, and cannot effectively handle the geometric connection problem between the rounded corner areas of the terminations and the regular cell array.

[0004] While traditional methods can achieve basic layout drawing, they lack automated constraint checks during the adaptation of terminals and cell boundaries. Each time different chip sizes or process parameters change, repeated manual adjustments are required, making it difficult to develop reusable layout strategies. Furthermore, the filling of the terminal ring gap region focuses on a single structural form, failing to establish a segmented adaptation mechanism between vertical, rounded, and horizontal segments. More critically, the transition between cell array edges and terminal arc boundaries in traditional processes relies on manual point-by-point adjustments, lacking unified boundary analysis and coordinate mapping methods, making it difficult to quickly regenerate a complete layout when process parameters change. Therefore, how to achieve parameterized construction of the terminal ring structure, automatic constraint screening of the cell array, and integrated assembly output of multi-structure layouts has become an urgent technical problem to be solved. Summary of the Invention

[0005] This invention provides a power device layout method based on terminal layout and cell constraints, and a computer-readable storage medium. Its main purpose is to realize the parameterized automatic layout and layout generation of power device terminal rings and cell arrays.

[0006] To achieve the above objectives, the present invention provides a power device layout method based on terminal layout and cell constraints, comprising:

[0007] The power device is acquired, and the global layout parameter node of the power device is identified. The global layout parameter node includes the power device size parameter, cell process parameter and terminal ring parameter. The cell arrangement period and cell arrangement step are obtained based on the cell process parameter. The number of rows and columns of the cell array is calculated based on the power device size parameter, cell arrangement period and terminal ring parameter.

[0008] A one-sided path is constructed based on the terminal ring parameters. A mirror Boolean merge operation is performed on the one-sided path to obtain a complete terminal ring structure. The complete terminal ring structure is then offset and expanded to obtain a cell-prohibited placement region.

[0009] Obtain real cells, generate multiple virtual cells based on the real cells, cell arrangement step distance and cell array row and column number, remove virtual cells that fall into the cell prohibition area from the multiple virtual cells to obtain a set of legal cell positions, place the real cells based on the set of legal cell positions to obtain an active cell array.

[0010] Based on the complete terminal ring structure, the gap region is obtained, the gap path set is obtained, the gap path set is parameterized and sampled to obtain the minimum polygon filling set, and Boolean operation is performed on the complete terminal ring structure and the minimum polygon filling set to obtain the target terminal structure.

[0011] Boundary analysis is performed on the active cell array to obtain boundary feature data. Edge transition cells are generated based on the boundary feature data and the complete terminal ring structure. The edge transition cells are then mapped onto the complete terminal ring structure to obtain a transition layout structure.

[0012] Based on the active cell array and transition layout structure, a metal connection structure is generated. The target terminal structure, active cell array, transition layout structure and metal connection structure are then assembled into the pre-constructed target layout to obtain the layout file.

[0013] Optionally, the power device dimensional parameters include: the lateral dimension of the power device and the longitudinal dimension of the power device;

[0014] The cell process parameters include: cell height, polysilicon gate width, contact hole width, and minimum spacing between the contact hole and the polysilicon.

[0015] The terminal ring parameters include: terminal boundary occupancy size, top reserved boundary height, terminal corner radius, terminal ring spacing set, and terminal ring width set.

[0016] Optionally, calculating the number of rows and columns of the cell array based on the power device size parameters, cell arrangement period, and terminal ring parameters includes:

[0017] The horizontal and vertical dimensions of the power device are extracted from the power device size parameters, and the terminal boundary occupancy size and top reserved boundary height are extracted from the terminal ring parameters.

[0018] The initial number of horizontal cells is calculated based on the horizontal dimension of the power device, the size occupied by the terminal boundary, the cell arrangement period, and the height of the top reserved boundary. The initial number of vertical cells is calculated based on the vertical dimension of the power device, the size occupied by the terminal boundary, the cell height, and the height of the top reserved boundary.

[0019] The initial number of columns of the horizontal cells is corrected for parity to obtain the initial corrected number of columns.

[0020] The horizontal remaining boundary width is calculated based on the initial number of corrected columns and the cell arrangement period. The horizontal remaining boundary width is compared with a preset minimum boundary width threshold. If the horizontal remaining boundary width is less than the minimum boundary width threshold, the number of corrected columns is reduced by a preset unit value, and the process returns to the step of calculating the horizontal remaining boundary width based on the initial number of corrected columns and the cell arrangement period, until the horizontal remaining boundary width is not less than the minimum boundary width threshold, and the number of corrected columns is obtained.

[0021] The vertical remaining boundary width is calculated based on the initial number of vertical cells and the cell height. If the vertical remaining boundary width is less than the minimum boundary width threshold, the initial number of vertical cells is reduced by the unit value, and the process returns to the step of calculating the vertical remaining boundary width based on the initial number of vertical cells and the cell height, until the vertical remaining boundary width is not less than the minimum boundary width threshold, and the corrected number of rows is obtained. The corrected number of columns and the corrected number of rows are then associated to obtain the number of rows and columns of the cell array.

[0022] Optionally, the step of constructing a single-sided path based on the terminal ring parameters and performing a mirror Boolean merge operation on the single-sided path to obtain a complete terminal ring structure includes:

[0023] Extract the terminal rounded corner radius, terminal ring spacing set, and terminal ring width set from the terminal ring parameters. Normalize the terminal ring spacing set and terminal ring width set to obtain the offset list.

[0024] A one-sided path is constructed based on the offset list and the terminal rounded corner radius;

[0025] Obtain the longitudinal axis of symmetry and the transverse centerline of the power device chip. Perform left and right mirroring on the single-sided path along the longitudinal axis of symmetry to obtain left and right mirrored paths. Perform up and down mirroring on the left and right mirrored paths along the transverse centerline of the chip to obtain a four-quadrant mirrored path set. Perform a Boolean union operation on the four-quadrant mirrored path set to obtain a complete termination ring structure.

[0026] Optionally, the step of obtaining the gap region based on the complete terminal ring structure, obtaining a gap path set, and performing parameterized sampling on the gap path set to obtain a minimum polygon fill set includes:

[0027] In the complete terminal ring structure, adjacent terminal rings are identified, and the gap region between adjacent terminal rings is confirmed. The gap region is abstracted into a gap path set, wherein the gap path set includes multiple gap paths, and each gap path includes a vertical segment, a rounded corner segment, and a horizontal segment.

[0028] Obtain the fill aspect ratio control node, which includes the start column aspect ratio and the end column aspect ratio;

[0029] Perform the following operation on each gap path in the gap path set:

[0030] Obtain the column number of the gap path in the gap path set, and calculate the fill ratio value of the gap path based on the column number and the fill aspect ratio control node;

[0031] Uniform sampling is performed along the vertical segment of the gap path to obtain a set of vertical segment sampling points, wherein the set of vertical segment sampling points includes multiple vertical segment sampling points;

[0032] For each vertical segment sampling point in the vertical segment sampling point set, perform the following operation:

[0033] The center point of the gap path is calculated based on the sampling points of the vertical segment to obtain the first center point. A first rectangular filling unit is constructed, and the first rectangular filling unit is stretched vertically according to the filling ratio value to obtain a vertically stretched rectangular filling unit. The vertically stretched rectangular filling unit is translated to the first center point to obtain the vertical segment filling polygon.

[0034] Summarize the filled polygons of the vertical segments to obtain the set of filled polygons of the vertical segments;

[0035] Uniform sampling is performed along the rounded corner segments of the gap path to obtain a set of rounded corner sampling points. The following operation is performed on each rounded corner sampling point in the set of rounded corner sampling points:

[0036] Based on the sampling points of the rounded corner segment, the center point and gradient on the gap path are calculated to obtain the second center point and path gradient. Based on the path gradient, the tangent direction angle is calculated, a second rectangular filling unit is constructed, and the second rectangular filling unit is rotated according to the tangent direction angle and then translated to the second center point to obtain the rounded corner segment filling polygon.

[0037] Summarize the rounded corner fill polygons to obtain the rounded corner fill polygon set;

[0038] Uniform sampling is performed along the horizontal segment of the gap path to obtain a set of horizontal segment sampling points. The following operation is performed on each horizontal segment sampling point in the set of horizontal segment sampling points:

[0039] The center point on the gap path is calculated based on the sampling points of the horizontal segment to obtain the third center point. A third rectangular filling unit is constructed, and the third rectangular filling unit is stretched horizontally according to the filling ratio value to obtain a horizontally stretched rectangular filling unit. The horizontally stretched rectangular filling unit is translated to the third center point to obtain the horizontal segment filling polygon.

[0040] Summarize the horizontal segment filled polygons to obtain the horizontal segment filled polygon set;

[0041] By summing up the sets of polygons filled with vertical segments, rounded corners, and horizontal segments, we obtain the minimum polygon filling set.

[0042] Optionally, the calculation of the tangent direction angle based on the path gradient includes:

[0043] Based on the path gradient, the lateral gradient component and the longitudinal gradient component are identified. The tangent direction angle is then calculated based on these components, using the following formula:

[0044] ;

[0045] in, Indicates the tangent direction angle. Represents the longitudinal gradient component. Represents the lateral gradient component. This represents the two-parameter arctangent function.

[0046] Optionally, performing a Boolean operation on the complete terminal ring structure and the minimum polygon fill set to obtain the target terminal structure includes:

[0047] Obtain the target terminal mode, wherein the target terminal mode is a continuous ring mode, a point mode, a mesh mode, or a segmented hybrid mode;

[0048] The minimum polygon fill set is divided into type subsets, resulting in straight line segment fill subset and rounded corner segment fill subset;

[0049] If the target terminal mode is a continuous ring mode, then the complete terminal ring structure is used as the target terminal structure.

[0050] If the target terminal mode is a dotted mode, then perform a Boolean difference operation on the complete terminal ring structure and the minimum polygon filling set to obtain the target terminal structure;

[0051] If the target terminal mode is mesh mode, then perform a Boolean union operation on the complete terminal ring structure and the minimum polygon fill set to obtain the target terminal structure;

[0052] If the target terminal mode is a segmented hybrid mode, then perform differentiated Boolean operations on the straight segment filling subset and the rounded corner segment filling subset and the complete terminal ring structure respectively, and merge the operation results to obtain the target terminal structure.

[0053] Optionally, the step of performing boundary analysis on the active cell array to obtain boundary feature data, generating edge transition cells based on the boundary feature data and the complete terminal ring structure, and mapping the edge transition cells onto the complete terminal ring structure to obtain a transition layout structure includes:

[0054] Boundary analysis is performed on the real cells in the active cell array to obtain boundary polygons. The extreme point operation is then performed on the boundary polygons to obtain the set of boundary key points.

[0055] The number of deployable units is calculated based on the set of boundary key points, and the number of deployable units is used to determine the set of generation locations for edge transition cells.

[0056] Extract symmetric boundary key points from the generated location set, and construct edge transition cells based on the symmetric boundary key points;

[0057] Key points are extracted from the edge transition cells, and rounded corner radius paths are obtained in the complete terminal ring structure. The key points are then mapped onto the rounded corner radius paths to obtain the transition layout structure.

[0058] Optionally, the step of generating a metal connection structure based on the active cell array and transition layout structure, and assembling the target terminal structure, active cell array, transition layout structure, and metal connection structure into a pre-constructed target layout to obtain a layout file, includes:

[0059] A source metal structure is generated based on the active cell array, and a gate metal structure and a gate bus connection structure are generated based on the active cell array and the transition layout structure.

[0060] Offset operations and fillet processing are performed on the source metal structure and gate metal structure to obtain a metal envelope structure. The pad opening region and passivation layer structure are defined based on the metal envelope structure.

[0061] By associating the source metal structure, gate metal structure, gate bus connection structure, pad opening region, and passivation layer structure, a metal connection structure is obtained.

[0062] The target terminal structure, active cell array, transition layout structure and metal connection structure are uniformly assembled into the preset target unit in the target layout, and the layout output operation is performed on the target unit to obtain the layout file.

[0063] To achieve the above objectives, the present invention also provides a power device layout system based on terminal layout and cell constraints, comprising:

[0064] The parameter configuration module is used to acquire power devices and identify the global layout parameter nodes of the power devices. The global layout parameter nodes include power device size parameters, cell process parameters, and terminal ring parameters. Based on the cell process parameters, the cell arrangement period and cell arrangement step size are acquired. Based on the power device size parameters, cell arrangement period, and terminal ring parameters, the number of rows and columns of the cell array is calculated.

[0065] The layout construction module is used to construct a single-sided path based on the terminal ring parameters, perform a mirror Boolean merge operation on the single-sided path to obtain a complete terminal ring structure, and perform offset expansion on the complete terminal ring structure to obtain a cell forbidden placement region.

[0066] Obtain real cells, generate multiple virtual cells based on the real cells, cell arrangement step distance and cell array row and column number, remove virtual cells that fall into the cell prohibition area from the multiple virtual cells to obtain a set of legal cell positions, place the real cells based on the set of legal cell positions to obtain an active cell array.

[0067] The terminal generation module is used to obtain gap regions based on the complete terminal ring structure, obtain a gap path set, perform parameterized sampling on the gap path set to obtain a minimum polygon filling set, and perform Boolean operations on the complete terminal ring structure and the minimum polygon filling set to obtain the target terminal structure.

[0068] The layout assembly module is used to perform boundary analysis on the active cell array to obtain boundary feature data, generate edge transition cells based on the boundary feature data and the complete terminal ring structure, and map the edge transition cells onto the complete terminal ring structure to obtain a transition layout structure.

[0069] Based on the active cell array and transition layout structure, a metal connection structure is generated. The target terminal structure, active cell array, transition layout structure and metal connection structure are then assembled into the pre-constructed target layout to obtain the layout file.

[0070] To address the above problems, the present invention also provides an electronic device, the electronic device comprising:

[0071] Memory, storing at least one instruction;

[0072] The processor executes the instructions stored in the memory to implement the power device layout method based on terminal layout and cell constraints described above.

[0073] To address the aforementioned problems, the present invention also provides a computer-readable storage medium storing at least one instruction, which is executed by a processor in an electronic device to implement the aforementioned power device layout method based on terminal layout and cell constraints.

[0074] To address the problems described in the background art, this invention obtains power devices and identifies global layout parameter nodes for the power devices. These global layout parameter nodes include power device size parameters, cell process parameters, and termination ring parameters. Based on the cell process parameters, the cell arrangement period and cell arrangement step size are obtained. Based on the power device size parameters, cell arrangement period, and termination ring parameters, the number of rows and columns of the cell array is calculated. This invention achieves automated layout planning of the cell array within the effective area by superimposing cell process dimensions into the arrangement period and combining termination boundary constraints and parity correction for row and column number calculation. Based on the termination ring parameters, a one-sided path is constructed, and a mirror Boolean merge operation is performed on the one-sided path to obtain the complete termination ring node. The invention constructs a complete symmetrical terminal ring structure by offset expansion to obtain the cell prohibition region. It is evident that this invention, through parameterized construction of a single-sided path and combining symmetric mirroring and Boolean merging, automatically generates a complete four-sided symmetrical terminal ring structure by defining only one side of the path. The cell prohibition region is determined through offset expansion, avoiding the tedious manual ring-by-ring drawing process. Real cells are obtained, and multiple virtual cells are generated based on these real cells, cell arrangement step distance, and the number of rows and columns in the cell array. Virtual cells falling into the cell prohibition region are removed from these virtual cells to obtain a set of legal cell positions. Real cells are then placed based on this legal cell position set to obtain an active cell array. This invention first generates the theoretically largest virtual cell array and then, based on the cell prohibition region... By filtering the placement area, the cell array and the terminal ring boundary are automatically adapted, ensuring that all placed real cells are within the legal area. Based on the complete terminal ring structure, gap areas are obtained, resulting in a gap path set. This gap path set is then parametrically sampled to obtain a minimum polygon fill set. Boolean operations are performed on the complete terminal ring structure and the minimum polygon fill set to obtain the target terminal structure. It is evident that this invention achieves automatic adaptation of the filled polygons to the arc-shaped boundary of the terminal ring by segmenting along the gap path and controlling the fill direction of the rounded segments according to the path gradient. Furthermore, it supports flexible generation of different terminal structure morphologies through various Boolean operation modes. Boundary analysis is performed on the active cell array to obtain boundary feature data. Edge transition cells are generated from the boundary feature data and the complete terminal ring structure, and these edge transition cells are mapped onto the complete terminal ring structure to obtain a transition layout structure. It is evident that this invention extracts the boundary extremum features of the active cell array, automatically generates suitable edge transition cells, and maps them to the rounded corner path of the terminal ring, achieving a continuous transition between the regular array and the arc-shaped terminal boundary. Based on the active cell array and the transition layout structure, a metal connection structure is generated. The target terminal structure, active cell array, transition layout structure, and metal connection structure are assembled into a pre-constructed target layout to obtain a layout file. It is clear that this invention ensures manufacturing reliability by automatically generating source and gate metal connection structures, combined with offset operations and rounded corner processing.This invention unifies the assembly and output of the terminal structure, cell array, transition structure, and metal structure, achieving a fully automated power device placement process from parameter input to complete layout file output. Therefore, this invention enables parametric automatic placement and layout generation of power device terminal rings and cell arrays. Attached Figure Description

[0075] Figure 1 This is a flowchart illustrating a power device layout method based on terminal layout and cell constraints, provided in an embodiment of the present invention.

[0076] Figure 2 This is a functional block diagram of a power device layout system based on terminal layout and cell constraints provided in an embodiment of the present invention;

[0077] Figure 3 This is a schematic diagram of an electronic device that implements the power device layout method based on terminal layout and cell constraints, according to an embodiment of the present invention.

[0078] Explanation of reference numerals in the attached figures:

[0079] 10. Electronic device; 11. Processor; 12. Memory; 13. Bus.

[0080] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0081] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0082] This application provides a power device layout method based on terminal layout and cell constraints. The executing entity of this power device layout method based on terminal layout and cell constraints includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the power device layout method based on terminal layout and cell constraints can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0083] Reference Figure 1 The diagram shown is a flowchart illustrating a power device layout method based on terminal layout and cell constraints according to an embodiment of the present invention. In this embodiment, the power device layout method based on terminal layout and cell constraints includes:

[0084] S1. Obtain the power device and identify the global layout parameter node of the power device. The global layout parameter node includes the power device size parameter, cell process parameter and terminal ring parameter. Based on the cell process parameter, obtain the cell arrangement period and cell arrangement step size. Based on the power device size parameter, cell arrangement period and terminal ring parameter, calculate the number of rows and columns of the cell array.

[0085] It should be explained that the power device is a semiconductor device used in the field of power electronics, capable of withstanding high voltage or large current. Common power devices include power MOSFETs, IGBTs, and power diodes. The global layout parameter node is a collection of all process and geometric parameters required to describe the layout of the power device, used to drive the subsequent automated layout process. The power device size parameter is the geometric dimension of the outer contour of the power device chip, which determines the overall spatial range of the layout. The cell process parameter is the process size parameter related to the internal unit structure of the power device, which determines the cell arrangement density and spacing relationship in the layout. The termination ring parameter is the geometric parameter of the termination protection ring structure around the active region. The termination protection ring is used to control the electric field distribution in the edge region of the power device to prevent edge breakdown. The cell arrangement period is the minimum repeating period size of a single cell in the lateral direction, obtained by superimposing the critical dimensions in the cell process parameters. The cell arrangement step is the arrangement interval between adjacent cells in the cell array in the lateral and longitudinal directions, determined by the cell arrangement period and the cell height. The number of rows and columns of the cell array is the number of rows and columns of the cell array within the active region, calculated from the available area of ​​the power device and the cell arrangement parameters.

[0086] It is understood that, in order to clarify the specific content of each structural parameter in the power device layout, the power device size parameters include: the power device lateral dimension and the power device longitudinal dimension;

[0087] The cell process parameters include: cell height, polysilicon gate width, contact hole width, and minimum spacing between the contact hole and the polysilicon.

[0088] The terminal ring parameters include: terminal boundary occupancy size, top reserved boundary height, terminal corner radius, terminal ring spacing set, and terminal ring width set.

[0089] It should be understood that the lateral dimension of the power device is the outer contour length of the power device chip in the horizontal direction. The longitudinal dimension of the power device is the outer contour length of the power device chip in the vertical direction. The cell height is the geometric height of a single cell in the longitudinal direction. The polysilicon gate width is the linewidth dimension of the polysilicon gate inside the cell. The contact hole width is the opening width dimension of the contact hole inside the cell. The minimum spacing between the contact hole and the polysilicon is the minimum allowable distance between the edge of the contact hole and the edge of the polysilicon gate, which is determined by the process design rules. The terminal boundary occupancy dimension is the width range occupied by the terminal ring structure in the chip edge direction, referring to the space occupied by the terminal boundary near the active region. The top reserved boundary height is the additional boundary space height reserved between the cell array and the terminal ring, used to ensure that the cell array does not get too close to the terminal structure. The terminal rounded corner radius is the arc transition radius used by the terminal ring at the corner, used to avoid electric field concentration at sharp corners leading to breakdown. The terminal ring spacing set is the collection of spacing between each terminal ring, containing multiple spacing values. The terminal ring width set is a collection of the widths of each terminal ring, containing multiple width values.

[0090] Furthermore, the process of obtaining the cell arrangement period and cell arrangement step size based on the cell process parameters is as follows: The polysilicon gate width, contact hole width, and minimum spacing between the contact hole and the polysilicon core are extracted from the cell process parameters. The cell arrangement period is then calculated based on the polysilicon gate width, contact hole width, and minimum spacing between the contact hole and the polysilicon core. The calculation formula is as follows:

[0091] ;

[0092] in, This indicates the periodicity of the cell arrangement. This indicates the polysilicon gate width. This indicates the width of the contact hole. This indicates the minimum distance between the contact hole and the polysilicon.

[0093] It should be explained that the calculation principle of the cell arrangement period is as follows: In the cell structure of a power device, a single cell contains at least one polysilicon gate and one contact hole in the lateral direction, and both sides of the contact hole need to maintain a minimum distance from the polysilicon gate. Therefore, the cell arrangement period is equal to the sum of the polysilicon gate width, the contact hole width, and twice the minimum distance between the contact hole and the polysilicon gate. The cell arrangement step size is a two-dimensional interval composed of the cell arrangement period and the cell height. The lateral step size is equal to the cell arrangement period, and the longitudinal step size is equal to the cell height.

[0094] In detail, to calculate the number of cells that can be placed within the active region, it is necessary to comprehensively consider the overall size of the power devices and the boundary space occupied by the termination ring. Therefore, the calculation of the number of rows and columns of the cell array based on the power device size parameters, cell arrangement period, and termination ring parameters includes:

[0095] The horizontal and vertical dimensions of the power device are extracted from the power device size parameters, and the terminal boundary occupancy size and top reserved boundary height are extracted from the terminal ring parameters.

[0096] The initial number of horizontal cells is calculated based on the horizontal dimension of the power device, the size occupied by the terminal boundary, the cell arrangement period, and the height of the top reserved boundary. The initial number of vertical cells is calculated based on the vertical dimension of the power device, the size occupied by the terminal boundary, the cell height, and the height of the top reserved boundary.

[0097] The initial number of columns of the horizontal cells is corrected for parity to obtain the initial corrected number of columns.

[0098] The horizontal remaining boundary width is calculated based on the initial number of corrected columns and the cell arrangement period. The horizontal remaining boundary width is compared with a preset minimum boundary width threshold. If the horizontal remaining boundary width is less than the minimum boundary width threshold, the number of corrected columns is reduced by a preset unit value, and the process returns to the step of calculating the horizontal remaining boundary width based on the initial number of corrected columns and the cell arrangement period, until the horizontal remaining boundary width is not less than the minimum boundary width threshold, and the number of corrected columns is obtained.

[0099] The vertical remaining boundary width is calculated based on the initial number of vertical cells and the cell height. If the vertical remaining boundary width is less than the minimum boundary width threshold, the initial number of vertical cells is reduced by the unit value, and the process returns to the step of calculating the vertical remaining boundary width based on the initial number of vertical cells and the cell height, until the vertical remaining boundary width is not less than the minimum boundary width threshold, and the corrected number of rows is obtained. The corrected number of columns and the corrected number of rows are then associated to obtain the number of rows and columns of the cell array.

[0100] It should be understood that the initial number of horizontal cell columns is the maximum number of horizontal cell columns calculated based on the available horizontal space of the power device and the cell arrangement period, without considering boundary constraints. The initial number of horizontal cell columns is calculated as follows: subtract the terminal boundary dimensions on both sides, twice the cell arrangement period, and the height of the reserved top boundaries on both sides from the horizontal dimensions of the power device, then divide by the cell arrangement period and round down. The calculation formula is as follows:

[0101] ;

[0102] in, This indicates the initial column number of the horizontal cell. This indicates the lateral dimension of the power device. This indicates the size occupied by the terminal boundary. This indicates the periodicity of the cell arrangement. This indicates the height of the top reserved boundary. This indicates a round-down operation.

[0103] Understandably, the initial row number of the vertical cells is calculated as follows: subtract the terminal boundary size on both sides, twice the cell height, and the reserved top boundary height on both sides from the vertical dimension of the power device, then divide by the cell height and round down. The calculation formula is as follows:

[0104] ;

[0105] in, This indicates the initial row number of the vertical cell. This indicates the longitudinal dimension of the power device. This indicates the height of the cell.

[0106] It should be explained that the parity correction is an adjustment operation performed on the initial number of columns in the horizontal cell array. The purpose is to maintain an odd number of columns in the cell array, thereby ensuring that the cell array forms a centrally symmetrical structure in the horizontal direction, which is beneficial for the uniform distribution of the electric field in the power device. If the initial number of columns in the horizontal cell array is even, it is reduced by one to make it odd, resulting in the initial correction column number. If the initial number of columns in the horizontal cell array itself is odd, it is directly used as the initial correction column number. The remaining horizontal boundary width is the space remaining on both sides of the cell array after subtracting the actual width occupied by the cell array from the available horizontal space of the power device. The minimum boundary width threshold is a manually set lower limit value for the boundary space, used to ensure sufficient spacing between the cell array and the terminal ring. The minimum boundary width threshold can be determined according to the process design rules. The unit value is the decreasing step size of the column or row number, usually set to 2, to ensure that the parity of the column number remains unchanged after the decrease.

[0107] For example, suppose an engineer needs to perform layout design for a power MOSFET device. The engineer obtains the following global layout parameters for the power device: lateral dimension of 5000 micrometers, vertical dimension of 5000 micrometers, polysilicon gate width of 2.0 micrometers, via width of 1.0 micrometer, minimum spacing between via and polysilicon core of 1.0 micrometer, cell height of 10 micrometers, termination boundary footprint of 150 micrometers, top reserved boundary height of 8 micrometers, termination corner radius of 60 micrometers, termination ring spacing set containing four spacing values ​​of 4 micrometers, 3 micrometers, 3 micrometers, and 2 micrometers, and termination ring width set containing five width values ​​of 5 micrometers, 4 micrometers, 4 micrometers, 3 micrometers, and 3 micrometers.

[0108] In detail, the cell arrangement period is calculated based on the cell process parameters: the cell arrangement period equals 2.0 plus 1.0 plus 2 multiplied by 1.0, resulting in a cell arrangement period of 5.0 micrometers. The lateral step size of the cell arrangement is 5.0 micrometers, and the longitudinal step size is 10 micrometers. The initial number of lateral cell columns is calculated as follows: from the lateral dimension of the power device of 5000 micrometers, subtract the size occupied by the two terminal boundaries by 2 multiplied by 150 equals 300 micrometers, then subtract twice the cell arrangement period by 2 multiplied by 5.0 equals 10 micrometers, and then subtract the height of the reserved boundaries on both sides by 2 multiplied by 8 equals 16 micrometers, resulting in 5000 minus 300 minus 10 minus 16 equals 4674 micrometers. Dividing this by the cell arrangement period of 5.0 and rounding down, the initial number of lateral cell columns is 934. Since 934 is an even number, parity correction is performed by subtracting 1 from 934, resulting in an initial corrected number of columns of 933. Calculate the lateral remaining boundary width: Subtract the 300-micron dimension occupied by the two terminal boundaries from the lateral dimension of the power device (5000 microns), then subtract the 16-micron height reserved at the top on both sides, and then subtract the initial correction column number (933) multiplied by the cell arrangement period (5.0), which equals 4665 microns. The final result is 5000 minus 300 minus 16 minus 4665 equals 19 microns. Setting the minimum boundary width threshold to 10 microns, the lateral remaining boundary width of 19 microns is greater than the minimum boundary width threshold of 10 microns, thus meeting the requirement. The corrected column number is determined to be 933.

[0109] Further, calculate the initial number of vertical cells: Subtract the size occupied by the two terminal boundaries by 2 multiplied by 150 equals 300 micrometers from the vertical dimension of the power device of 5000 micrometers, then subtract twice the cell height by 2 multiplied by 10 equals 20 micrometers, then subtract the height of the reserved boundary at the top on both sides by 2 multiplied by 8 equals 16 micrometers, finally 5000 minus 300 minus 20 minus 16 equals 4664 micrometers, divide by the cell height of 10 and round down to get the initial number of vertical cells as 466. The longitudinal remaining boundary width is calculated as follows: Subtract the 300-micron area occupied by the two terminal boundaries from the longitudinal dimension of the power device (5000 microns), then subtract the 16-micron height reserved at the top of both sides, and then subtract the initial number of vertical cells (466) multiplied by the cell height (10), which equals 4660 microns. The final result is 5000 - 300 - 16 - 4660 = 24 microns. The longitudinal remaining boundary width of 24 microns is greater than the minimum boundary width threshold of 10 microns, meeting the requirement. After correction, the number of rows is determined to be 466. The final cell array has 933 columns and 466 rows. This embodiment of the invention achieves automated layout planning of the cell array within the effective area by superimposing the cell process dimensions into a layout period and combining terminal boundary constraints and parity correction for row and column number calculation.

[0110] S2. Construct a single-sided path based on the terminal ring parameters, perform a mirror Boolean merge operation on the single-sided path to obtain a complete terminal ring structure, and perform offset expansion on the complete terminal ring structure to obtain a cell-prohibited placement region.

[0111] It should be explained that the single-sided path is a geometric path of the terminal ring constructed on one side of the power device chip based on the terminal ring parameters. This single-sided path is composed of vertical segments, rounded corner segments, and horizontal segments, which can represent the complete orientation of the terminal ring on one side of the chip. The mirror Boolean merge operation mirrors the single-sided path along the axis of symmetry of the power device and performs a Boolean union operation on the original path and the mirrored path to merge them into a complete closed ring structure. The complete terminal ring structure is a complete closed terminal protection ring around the active region obtained after the mirror Boolean merge operation. The offset expansion extends the complete terminal ring structure along its normal direction towards the active region by a certain distance, thereby obtaining a region boundary larger than the terminal ring body. The cell-prohibited placement region is the region obtained after the offset expansion. No cells are allowed to be placed in this region to ensure a safe distance between the cell array and the terminal ring.

[0112] Understandably, in order to accurately construct the geometric path of the terminating ring, it is necessary to convert the terminating ring spacing and width information into a uniform offset. Therefore, the step of constructing a single-sided path based on the terminating ring parameters and performing a mirror Boolean merging operation on the single-sided path to obtain the complete terminating ring structure includes:

[0113] Extract the terminal rounded corner radius, terminal ring spacing set, and terminal ring width set from the terminal ring parameters. Normalize the terminal ring spacing set and terminal ring width set to obtain the offset list.

[0114] A one-sided path is constructed based on the offset list and the terminal rounded corner radius;

[0115] Obtain the longitudinal axis of symmetry and the transverse centerline of the power device chip. Perform left and right mirroring on the single-sided path along the longitudinal axis of symmetry to obtain left and right mirrored paths. Perform up and down mirroring on the left and right mirrored paths along the transverse centerline of the chip to obtain a four-quadrant mirrored path set. Perform a Boolean union operation on the four-quadrant mirrored path set to obtain a complete termination ring structure.

[0116] It should be understood that the normalization is achieved by accumulating the values ​​in the terminal ring spacing set and the terminal ring width set in an alternating manner to obtain a sequence of offset distances of each terminal ring relative to the reference position, i.e., an offset list. Each offset in the offset list corresponds to the radial offset distance of a terminal ring path relative to the starting reference. The process of constructing a single-sided path is as follows: for each offset in the offset list, the actual rounded corner radius of the current ring is obtained by adding the offset to the terminal corner radius, and then sequentially splicing the vertical segment, rounded corner segment, and horizontal segment to form a single-sided continuous path extending from the top of the chip to the right side. The chip's longitudinal axis of symmetry is the vertical axis of symmetry through the transverse center position of the power device chip. The chip's transverse centerline is the horizontal axis of symmetry through the longitudinal center position of the power device chip. The left and right mirroring is the process of flipping the single-sided path with the chip's longitudinal axis of symmetry as the mirror axis to obtain a symmetrical path on the other side of the chip. The four-quadrant mirrored path set is a set of paths covering the four quadrants, formed by further flipping the left and right mirrored paths up and down along the transverse centerline of the chip, together with the original paths. The Boolean union operation merges all paths in the four-quadrant mirror path set, eliminating overlapping areas to obtain a completely closed terminal loop structure.

[0117] Furthermore, the process of offsetting and expanding the complete terminal ring structure to obtain the cell-prohibited region is as follows: taking the complete terminal ring structure as a reference, offsetting and expanding along the inner normal direction of the terminal ring structure towards the active region. The offset distance comprehensively considers the cell arrangement period, the height of the top reserved boundary, and the process compensation amount. Through this offset expansion, a closed region surrounding the active region is obtained. This closed region is the cell-prohibited region, and any subsequently generated virtual cells that fall into this region will be discarded.

[0118] For example, in the layout process of the aforementioned power MOSFET device, engineers extract the following parameters from the termination ring parameters: a termination corner radius of 60 micrometers, a set of termination ring spacings (4 micrometers, 3 micrometers, 3 micrometers, 2 micrometers), and a set of termination ring widths (5 micrometers, 4 micrometers, 4 micrometers, 3 micrometers, 3 micrometers). The termination ring spacing and width sets are normalized, and the spacing and width are accumulated in an alternating order to obtain an offset list of nine values: 0 micrometers, 5 micrometers, 9 micrometers, 13 micrometers, 16 micrometers, 20 micrometers, 22 micrometers, 25 micrometers, and 27 micrometers. Based on the offset list and the termination corner radius of 60 micrometers, a single-sided path is constructed, with the actual corner radii for each path being 60 micrometers, 65 micrometers, 69 micrometers, etc. The longitudinal symmetry axis (i.e., the vertical axis at a lateral position of 2500 micrometers) and the lateral centerline (i.e., the horizontal axis at a longitudinal position of 2500 micrometers) of the power device chip are obtained. Left-right mirroring and top-bottom mirroring are then performed sequentially on the single-sided path to obtain a four-quadrant mirrored path set. A Boolean union operation is then performed to obtain a complete terminal ring structure surrounding the entire active region. The complete terminal ring structure is then offset and extended. The offset and extension distance is determined based on parameters such as the cell arrangement period of 5.0 micrometers and the top reserved boundary height of 8 micrometers, resulting in a cell-prohibited area. This embodiment of the invention, by parametrically constructing a single-sided path and combining symmetric mirroring with Boolean merging, automatically generates a complete four-sided symmetrical terminal ring structure by defining only one side of the path. The cell-prohibited area is determined through offset extension, avoiding the tedious manual ring-by-ring drawing process.

[0119] S3. Obtain real cells, generate multiple virtual cells based on the real cells, cell arrangement step distance and cell array row and column number, remove virtual cells that fall into the cell prohibition area from the multiple virtual cells to obtain a set of legal cell positions, place the real cells based on the set of legal cell positions to obtain an active cell array.

[0120] It should be explained that the real cell is the complete cell layout unit actually used in the power device layout, including all process layer graphics such as polysilicon gate, contact via, source region, and drain region, and is the basic functional repeating unit of the active region of the power device. The virtual cell is a simplified geometric contour generated based on the outer contour of the real cell, retaining only the outer boundary information of the real cell and not including the detailed internal process layer graphics, used for rapid placement and position determination during the layout planning stage. The set of legal cell positions is the set of coordinates of all positions where real cells are allowed to be placed after filtering for prohibited cell placement areas. The active cell array is a cell array formed by placing real cells one by one according to the coordinates of the set of legal cell positions, constituting the active region of the power device.

[0121] It should be understood that the process of generating multiple virtual cells based on the real cells, cell arrangement step distance, and the number of rows and columns in the cell array is as follows: First, the outer contour shape is extracted from the real cells to obtain the geometric contour of a single virtual cell. Then, with the cell arrangement step distance as the horizontal and vertical intervals, the cells are copied and arranged according to the corrected number of columns and rows in the cell array, generating a virtual cell array that covers the theoretically largest effective area. This virtual cell array contains multiple virtual cells. At this point, the generated virtual cell array has not yet considered the constraints of the terminal ring structure, and some virtual cells at the edge positions may intrude into the terminal ring region.

[0122] Understandably, the process of removing virtual cells that fall into the prohibited placement region from multiple virtual cells is as follows: The geometric contour of each virtual cell in the virtual cell array is checked one by one to determine if any point in the contour point set of the virtual cell falls inside the prohibited placement region. If at least one point on the contour of the virtual cell is located within the prohibited placement region, the virtual cell is determined to be an invalid cell and removed from the virtual cell array. If all contour points of the virtual cell are not within the prohibited placement region, the virtual cell is determined to be a valid cell and its position information is retained. The position coordinates of all valid cells are summarized to obtain the valid cell position set.

[0123] Furthermore, the process of placing the real cells based on the set of legal cell locations is as follows: for each position coordinate in the set of legal cell locations, this position coordinate is used as the placement reference point for the real cell, and the layout unit of the real cell is placed at this position. After placing the real cells at all positions, an active cell array is obtained. By first generating a virtual cell array and then removing illegal cells, the boundary relationship between the terminal ring and the cell array can be automatically adapted, eliminating the need for manual judgment of the placement feasibility of each cell.

[0124] For example, in the layout process of the aforementioned power MOSFET device, engineers obtain real cells containing process layer patterns such as polysilicon gates, contact vias, and source / drain regions. The outer contour is extracted from the real cells to obtain a rectangular virtual cell contour with a width of 5.0 micrometers and a height of 10 micrometers. The cells are copied according to a rule of 933 columns and 466 rows at intervals of cell arrangement steps (5.0 micrometers horizontally and 10 micrometers vertically), generating a virtual cell array containing 434,778 virtual cells. The positional relationship between the contour of each virtual cell and the prohibited cell placement area is checked one by one. Virtual cells located at the edges and corners of the chip are discarded because their contour points fall into the prohibited cell placement area. After screening, a total of 432,150 valid cells remain, and their position coordinates form a valid cell position set. Real cells are placed one by one according to the coordinates in the valid cell position set to obtain an active cell array. The embodiments of the present invention automatically adapt the cell array to the boundary of the terminal ring by first generating the theoretical maximum virtual cell array and then filtering it according to the prohibited cell placement area, thus ensuring that all placed real cells are located within the legal area.

[0125] S4. Based on the complete terminal ring structure, obtain the gap region and the gap path set. Perform parameterized sampling on the gap path set to obtain the minimum polygon filling set. Perform Boolean operation on the complete terminal ring structure and the minimum polygon filling set to obtain the target terminal structure.

[0126] It should be explained that the gap region is the empty area between adjacent terminal rings in the complete terminal ring structure. Due to the certain spacing between the terminal rings, a ring-shaped gap space is formed between adjacent terminal rings. The gap path set is the set of paths obtained by abstracting each gap region into a geometric path. Each gap path extends along the centerline of the corresponding gap region and includes three sub-segments: a vertical segment, a rounded corner segment, and a horizontal segment. The parameterized sampling is the process of sampling at equal intervals along each sub-segment of the gap path and placing a rectangular filling unit at each sampling point. The minimum polygon filling set is the total set of rectangular filling polygons generated at each sampling point after parameterized sampling of all gap paths in the gap path set. The Boolean operation is the process of performing geometric Boolean operations on the complete terminal ring structure and the minimum polygon filling set, including Boolean union or Boolean difference operations. The target terminal structure is the final terminal structure obtained after the Boolean operation.

[0127] Understandably, in order to generate a filling structure in the gap region between terminal rings, it is necessary to sample and fill different segments along the gap path separately. Therefore, the step of obtaining the gap region based on the complete terminal ring structure, obtaining a gap path set, and parametrically sampling the gap path set to obtain the minimum polygon filling set includes:

[0128] In the complete terminal ring structure, adjacent terminal rings are identified, and the gap region between adjacent terminal rings is confirmed. The gap region is abstracted into a gap path set, wherein the gap path set includes multiple gap paths, and each gap path includes a vertical segment, a rounded corner segment, and a horizontal segment.

[0129] Obtain the fill aspect ratio control node, which includes the start column aspect ratio and the end column aspect ratio;

[0130] Perform the following operation on each gap path in the gap path set:

[0131] Obtain the column number of the gap path in the gap path set, and calculate the fill ratio value of the gap path based on the column number and the fill aspect ratio control node;

[0132] Uniform sampling is performed along the vertical segment of the gap path to obtain a set of vertical segment sampling points, wherein the set of vertical segment sampling points includes multiple vertical segment sampling points;

[0133] For each vertical segment sampling point in the vertical segment sampling point set, perform the following operation:

[0134] The center point of the gap path is calculated based on the sampling points of the vertical segment to obtain the first center point. A first rectangular filling unit is constructed, and the first rectangular filling unit is stretched vertically according to the filling ratio value to obtain a vertically stretched rectangular filling unit. The vertically stretched rectangular filling unit is translated to the first center point to obtain the vertical segment filling polygon.

[0135] Summarize the filled polygons of the vertical segments to obtain the set of filled polygons of the vertical segments;

[0136] Uniform sampling is performed along the rounded corner segments of the gap path to obtain a set of rounded corner sampling points. The following operation is performed on each rounded corner sampling point in the set of rounded corner sampling points:

[0137] Based on the sampling points of the rounded corner segment, the center point and gradient on the gap path are calculated to obtain the second center point and path gradient. Based on the path gradient, the tangent direction angle is calculated, a second rectangular filling unit is constructed, and the second rectangular filling unit is rotated according to the tangent direction angle and then translated to the second center point to obtain the rounded corner segment filling polygon.

[0138] Summarize the rounded corner fill polygons to obtain the rounded corner fill polygon set;

[0139] Uniform sampling is performed along the horizontal segment of the gap path to obtain a set of horizontal segment sampling points. The following operation is performed on each horizontal segment sampling point in the set of horizontal segment sampling points:

[0140] The center point on the gap path is calculated based on the sampling points of the horizontal segment to obtain the third center point. A third rectangular filling unit is constructed, and the third rectangular filling unit is stretched horizontally according to the filling ratio value to obtain a horizontally stretched rectangular filling unit. The horizontally stretched rectangular filling unit is translated to the third center point to obtain the horizontal segment filling polygon.

[0141] Summarize the horizontal segment filled polygons to obtain the horizontal segment filled polygon set;

[0142] By summing up the sets of polygons filled with vertical segments, rounded corners, and horizontal segments, we obtain the minimum polygon filling set.

[0143] It should be understood that the fill aspect ratio control nodes are the same parameter combination used to control the stretching ratio of the fill polygons on different column gap paths, so that the aspect ratio of the fill polygons gradually changes from the outside to the inside. The starting column aspect ratio is the aspect ratio parameter of the fill polygons on the outermost gap path. The ending column aspect ratio is the aspect ratio parameter of the fill polygons on the innermost gap path. The starting and ending column aspect ratios are determined by manually setting them according to the ratio between the width of the terminal ring gap and the size of the fill polygon, so that the wider gap area on the outside uses a larger stretching ratio and the narrower gap area on the inside uses a smaller stretching ratio, thereby ensuring that the fill polygons in each gap area are uniform and do not overlap. The column number is the sequence number of the gap path in the gap path set, starting from the outermost gap path. The fill ratio value is the stretching ratio of the current gap path obtained by interpolating between the starting and ending column aspect ratios based on the column number.

[0144] Specifically, the first center point is the center coordinate point calculated along the gap path at the sampling point location of the vertical segment. The first rectangular filling unit is a basic rectangle whose initial size is determined according to the gap width. The longitudinal stretching is an operation of scaling the rectangular filling unit in the longitudinal direction according to the filling ratio value. After stretching, the longitudinal dimension of the rectangle is equal to the initial longitudinal dimension multiplied by the filling ratio value. The vertical segment filling polygon is the filling polygon obtained after longitudinal stretching and translation to the first center point. The second center point is the center coordinate point calculated along the gap path at the sampling point location of the rounded corner segment. The path gradient is the rate of change vector of the gap path at the sampling point of the rounded corner segment, containing a horizontal gradient component and a vertical gradient component, reflecting the local orientation of the gap path at that sampling point.

[0145] Further, the calculation of the tangent direction angle based on the path gradient includes: identifying the lateral gradient component and the longitudinal gradient component from the path gradient, and calculating the tangent direction angle based on the lateral gradient component and the longitudinal gradient component, as shown in the following formula:

[0146] ;

[0147] in, Indicates the tangent direction angle. Represents the longitudinal gradient component. Represents the lateral gradient component. This represents the two-parameter arctangent function.

[0148] It should be explained that the two-parameter arctangent function is a type of arctangent function that can calculate the complete angle range based on the horizontal and vertical gradient components, and its output range is negative. To Zheng This allows for accurate determination of the quadrant in which the path tangent direction lies. The tangent direction angle represents the local orientation angle of the gap path at the sampling point of the rounded corner segment, used to control the rotation direction of the rectangular filling unit, ensuring that the filling unit aligns with the arcuate orientation of the rounded corner segment. The rotation of the second rectangular filling unit according to the tangent direction angle involves rotating the second rectangular filling unit as a whole, with its geometric center as the rotation center. After rotation, the major axis of the rectangle is parallel to the tangent direction of the gap path, thus ensuring that the filling polygon of the rounded corner segment naturally fits the boundary of the arcuate terminal ring.

[0149] Understandably, the third center point is the center coordinate point calculated along the gap path at the sampling point location of the horizontal segment. The horizontal stretching is an operation of scaling the rectangular fill unit in the horizontal direction according to the fill ratio value. The horizontal segment fill polygon is the fill polygon obtained after horizontal stretching and translation to the third center point. The minimum polygon fill set is the total set obtained by summing the fill polygons generated by the three types of sub-segments on all gap paths.

[0150] In detail, to support different types of terminal structures, different Boolean operations need to be performed on the complete terminal ring structure and the minimum polygon fill set according to the target terminal mode. Therefore, the step of performing Boolean operations on the complete terminal ring structure and the minimum polygon fill set to obtain the target terminal structure includes:

[0151] Obtain the target terminal mode, wherein the target terminal mode is a continuous ring mode, a point mode, a mesh mode, or a segmented hybrid mode;

[0152] The minimum polygon fill set is divided into type subsets, resulting in straight line segment fill subset and rounded corner segment fill subset;

[0153] If the target terminal mode is a continuous ring mode, then the complete terminal ring structure is used as the target terminal structure.

[0154] If the target terminal mode is a dotted mode, then perform a Boolean difference operation on the complete terminal ring structure and the minimum polygon filling set to obtain the target terminal structure;

[0155] If the target terminal mode is mesh mode, then perform a Boolean union operation on the complete terminal ring structure and the minimum polygon fill set to obtain the target terminal structure;

[0156] If the target terminal mode is a segmented hybrid mode, then perform differentiated Boolean operations on the straight segment filling subset and the rounded corner segment filling subset and the complete terminal ring structure respectively, and merge the operation results to obtain the target terminal structure.

[0157] It should be understood that the target terminal mode is a terminal structure form selected artificially based on the electric field distribution requirements and process requirements of the power device. The continuous ring mode is a mode where the terminal ring remains a complete closed loop, suitable for scenarios requiring continuous electric field shielding. The point-like mode forms discretely distributed point-like structural gaps on the terminal ring. By performing a Boolean difference on the minimum polygon fill set from the complete terminal ring structure, multiple dispersed windows are opened on the terminal ring, suitable for scenarios requiring control of charge distribution in the terminal area. The mesh mode forms a mesh-like connection structure in the gap region between terminal rings. By performing a Boolean union on the minimum polygon fill set and the complete terminal ring structure, connecting strips are added in the gap region, suitable for scenarios requiring enhanced conductivity in the terminal area. The segmented hybrid mode is a hybrid mode that uses different Boolean strategies for the straight segment fill subsets and rounded corner segment fill subsets of the vertical and horizontal segments. Optionally, the straight segments may use a continuous ring mode while the rounded corner segments use a mesh mode, or the straight segments may use a point-like mode while the rounded corner segments use a continuous ring mode, etc. The straight line segment fill subset is a subset of filled polygons generated from vertical and horizontal segments within the minimum polygon fill set. The rounded corner segment fill subset is a subset of filled polygons generated from rounded corner segments within the minimum polygon fill set. The differentiated Boolean operation is an operation that performs different Boolean operations based on the type of the fill subset.

[0158] For example, during the layout of the aforementioned power MOSFET device, engineers identified four gap regions in the complete termination ring structure (located between the first and second termination rings, the second and third termination rings, the third and fourth termination rings, and the fourth and fifth termination rings, respectively). Each gap region was abstracted as a gap path, resulting in a gap path set containing four gap paths. The aspect ratio of the starting column of the fill aspect ratio control node was set to 1.5, and the aspect ratio of the ending column was set to 0.8. Taking the second gap path as an example, its column number is 2, and there are a total of four gap paths in the gap path set. The fill ratio value of this gap path is calculated to be approximately 1.28. The vertical segment along the gap path is sampled using 8 uniform sampling points. For each vertical segment sampling point, a first center point is calculated, and a first rectangular filling unit with a width of 2 micrometers and a height of 2 micrometers is constructed. After stretching the vertical segment by a fill ratio of 1.28, the height becomes 2.56 micrometers. This is then translated to the first center point to obtain the vertical segment filling polygon. The sets of vertical segment filling polygons are then compiled. The rounded corner segment is sampled using 6 uniform sampling points. For each rounded corner segment sampling point, a second center point and path gradient are calculated. Assuming the horizontal gradient component at a certain sampling point is 0.707 and the vertical gradient component is 0.707, the tangent direction angle is equal to arctan2(0.707, 0.707), which equals 0.785 radians (i.e., 45 degrees). A second rectangular filling unit is constructed, rotated by 45 degrees, and then translated to the second center point to obtain the rounded corner segment filling polygon. The horizontal segment is sampled using 8 uniform sampling points, stretched horizontally by a fill ratio, and then translated to each third center point. The minimum polygon fill set is obtained by summarizing the vertical segment fill polygon set, the rounded corner fill polygon set, and the horizontal segment fill polygon set, and repeating the above operation for all four gap paths. Assuming the engineer selects a point-like pattern as the target terminal pattern, a Boolean difference operation is performed on the complete terminal ring structure and the minimum polygon fill set to form a uniformly distributed discrete point structure on the terminal ring, thus obtaining the target terminal structure. This embodiment of the invention achieves automatic adaptation of the fill polygons to the arc-shaped boundary of the terminal ring by sampling along the gap path and controlling the rounded corner fill direction according to the path gradient, and supports flexible generation of different terminal structure forms through various Boolean operation modes.

[0159] S5. Perform boundary analysis on the active cell array to obtain boundary feature data. Generate edge transition cells based on the boundary feature data and the complete terminal ring structure, and map the edge transition cells onto the complete terminal ring structure to obtain a transition layout structure.

[0160] It should be explained that the boundary feature data is a set of data describing the boundary morphology obtained after geometric analysis of the outer boundary of the active cell array, including geometric information such as boundary polygons and boundary key points. The edge transition cell is a transitional cell structure located between the edge of the active cell array and the complete terminal ring structure. Its function is to establish a smooth geometric connection between the regularly arranged cell array and the arc-shaped terminal boundary, avoiding connection interruptions caused by hard truncation of the cell array at the terminal boundary. The transition layout structure is a layout structure obtained by mapping the edge transition cells to the rounded corner area of ​​the complete terminal ring structure. This transition layout structure is adapted to both the active cell array and the terminal ring structure.

[0161] Understandably, since the active cell array is a regular rectangular array structure, while the complete terminal ring structure has a rounded boundary at the corner, there is a geometric difference between the two. This difference needs to be eliminated through boundary analysis and transition cell generation. Therefore, the process involves performing boundary analysis on the active cell array to obtain boundary feature data, generating edge transition cells based on the boundary feature data and the complete terminal ring structure, and mapping the edge transition cells onto the complete terminal ring structure to obtain a transition layout structure, including:

[0162] Boundary analysis is performed on the real cells in the active cell array to obtain boundary polygons. The extreme point operation is then performed on the boundary polygons to obtain the set of boundary key points.

[0163] The number of deployable units is calculated based on the set of boundary key points, and the number of deployable units is used to determine the set of generation locations for edge transition cells.

[0164] Extract symmetric boundary key points from the generated location set, and construct edge transition cells based on the symmetric boundary key points;

[0165] Key points are extracted from the edge transition cells, and rounded corner radius paths are obtained in the complete terminal ring structure. The key points are then mapped onto the rounded corner radius paths to obtain the transition layout structure.

[0166] It should be understood that the boundary polygon is the polygonal outline enclosed by the outer boundary of the active cell array, reflecting the actual external shape of the active cell array after being filtered through the cell-prohibited placement region. The extreme point extraction operation is the operation of extracting feature points with extreme coordinates (maximum and minimum horizontal and vertical coordinates) on the boundary polygon. The boundary key point set is the set of feature points obtained after the extreme point extraction operation. These feature points mark the boundary limit positions of the active cell array in various directions, including but not limited to: the horizontal extreme point on the highest boundary, the vertical extreme point on the rightmost boundary, and the vertical extreme point on the leftmost boundary.

[0167] Furthermore, the number of deployable units is a value calculated based on the ratio of the distance between relevant feature points in the boundary keypoint set to the cell arrangement period or cell height, used to determine how many transition cells can be placed on different boundary segments. The calculation method for the number of deployable units is as follows: extract the two lateral extreme points located on the highest boundary in the boundary keypoint set, calculate the lateral distance between them, and divide it by the cell arrangement period to obtain the number of lateral deployable units; extract the two vertical extreme points located on the rightmost boundary, calculate the vertical distance between them, and divide it by the cell height to obtain the number of vertical deployable units. The generated position set is a set of transition cell placement positions determined after uniformly distributing the deployable units on the corresponding boundary segments.

[0168] In detail, the symmetry boundary key points are boundary key points extracted from the generation location set and symmetrically distributed about the chip's symmetry axis, used to ensure the symmetry of the generated edge transition cells. The process of constructing edge transition cells is as follows: using the symmetry boundary key points as positioning references, a simplified cell structure adapted to the width or height of the real cell is generated. This simplified cell structure includes necessary polysilicon gate extension segments and contact hole connection segments, which can maintain electrical connection with adjacent real cells. The key points are feature positions in the edge transition cells that need to be geometrically aligned with the termination ring structure, including the contact positions of the transition cells and polysilicon endpoints, etc. The rounded corner radius path is the arc-shaped path segment of the complete termination ring structure in the corner region. The process of mapping the key points to the rounded corner radius path is as follows: the key points originally located on the straight boundary are mapped to the arc of the rounded corner radius path through coordinate transformation, so that the contact positions and polysilicon endpoints of the transition cells can be aligned and connected with the arc-shaped structure in the corner region of the termination ring.

[0169] For example, in the layout process of the aforementioned power MOSFET device, the engineer performs boundary analysis on the active cell array to obtain the boundary polygon of the active cell array. An extreme point extraction operation is performed on the boundary polygon to extract the coordinates of the horizontal maximum point (3250, 2310) and the horizontal minimum point (1750, 2310) on the highest boundary, the coordinates of the vertical maximum point (3400, 2200) and the vertical minimum point (3400, 100) on the rightmost boundary, and the vertical extreme point on the leftmost boundary, forming a set of boundary key points. Based on the boundary key point set, the number of arrangeable cells is calculated: the distance between horizontal extreme points is 3250 minus 1750 equals 1500 micrometers, divided by the cell arrangement period of 5.0 micrometers to obtain a horizontally arrangeable cell number of 300; the distance between vertical extreme points is 2200 minus 100 equals 2100 micrometers, divided by the cell height of 10 micrometers to obtain a vertically arrangeable cell number of 210. The set of generation locations for edge transition cells is determined based on the number of deployable cells. Symmetrical boundary key points, symmetrically distributed about the chip's axis of symmetry, are extracted from this set. Edge transition cells containing polysilicon gate extensions are constructed based on these symmetric boundary key points. Contact points and polysilicon endpoints are extracted from these edge transition cells. A rounded corner radius path with a radius of 60 micrometers is obtained within the complete termination ring structure. The key points are mapped onto this rounded corner radius path through coordinate transformation, ensuring the polysilicon endpoints of the transition cells are distributed along an arc, resulting in a transition layout structure. This embodiment of the invention automatically generates suitable edge transition cells by extracting the boundary extremum features of the active cell array and mapping them to the rounded corner path of the termination ring, achieving a continuous transition between a regular array and an arc-shaped termination boundary.

[0170] S6. Generate a metal connection structure based on the active cell array and transition layout structure, and assemble the target terminal structure, active cell array, transition layout structure and metal connection structure into the pre-constructed target layout to obtain the layout file.

[0171] It should be explained that the metal connection structure is a metal layer interconnect structure located above the cell array and transition structure, used to connect the source and gate of each cell to the corresponding pad area through metal leads, realizing the electrical interconnection function of the power device. The target layout is a layout design file framework used to accommodate and organize all geometric layers in the power device layout. The layout file is a complete layout output file generated after the target terminal structure, active cell array, transition layout structure, and metal connection structure are uniformly assembled, and can be directly used for subsequent layout verification and manufacturing.

[0172] Understandably, in order to achieve the electrical connection of each cell in the power device layout and complete the final layout output, it is necessary to automatically generate the metal layer structure and the protective layer structure. Therefore, the step of generating the metal connection structure based on the active cell array and the transition layout structure, assembling the target terminal structure, the active cell array, the transition layout structure and the metal connection structure into the pre-constructed target layout, and obtaining the layout file includes:

[0173] A source metal structure is generated based on the active cell array, and a gate metal structure and a gate bus connection structure are generated based on the active cell array and the transition layout structure.

[0174] Offset operations and fillet processing are performed on the source metal structure and gate metal structure to obtain a metal envelope structure. The pad opening region and passivation layer structure are defined based on the metal envelope structure.

[0175] By associating the source metal structure, gate metal structure, gate bus connection structure, pad opening region, and passivation layer structure, a metal connection structure is obtained.

[0176] The target terminal structure, active cell array, transition layout structure and metal connection structure are uniformly assembled into the preset target unit in the target layout, and the layout output operation is performed on the target unit to obtain the layout file.

[0177] It should be understood that the source metal structure is a metal pattern covering the source regions of each actual cell in the active cell array, used to connect the sources of all cells in parallel to the source pads. The source metal structure is generated by constructing a continuous metal pattern covering all source contact holes according to the positions of the source contact holes of the actual cells in the active cell array, so that the sources of each cell are electrically connected in parallel through this metal pattern. The gate metal structure is a metal pattern covering the gate lead-out regions in the active cell array and the transition layout structure, used to connect the gates of each cell to the gate pads. The gate bus connection structure is a metal bus trace structure connecting the gate metal structure and the gate pads, generated by constructing a metal bus trace extending from the array edge to the gate pad position according to the arrangement direction of the polysilicon gates in the active cell array and the polysilicon endpoint positions of the edge transition cells in the transition layout structure.

[0178] Furthermore, the offset operation is a geometric operation that extends the boundaries of the source and gate metal structures outward by a certain distance to ensure sufficient coverage margin between the metal pattern and the underlying contact holes. The rounded corner treatment is an operation that rounds the right-angled corners in the metal pattern to avoid manufacturing problems such as stress concentration or uneven etching at sharp corners. The metal envelope structure is the outer contour structure of the metal pattern obtained after the offset operation and rounded corner treatment of the source and gate metal structures. The pad opening area is an opening window defined on the passivation layer for wire bonding, corresponding to the positions of the source and gate pads, respectively. Its position and size are determined according to the metal envelope structure. The passivation layer structure is a protective dielectric layer pattern covering the metal layer. Except for the pad opening area, the passivation layer covers the entire chip surface to protect the metal layer from mechanical damage and chemical corrosion.

[0179] In detail, the target cell is a pre-created hierarchical unit in the target layout used to accommodate the complete power device layout. The process of uniformly assembling the target terminal structure, active cell array, transition layout structure, and metal connection structure into the target cell is as follows: adding the polygonal graphic of the target terminal structure to the terminal layer corresponding to the target cell; adding references to each actual cell in the active cell array to the target cell; adding references to the edge transition cells in the transition layout structure to the target cell; and adding the source metal structure, gate metal structure, gate bus connection structure, pad opening area, and passivation layer structure in the metal connection structure to the corresponding metal layer and dielectric layer of the target cell, respectively. The layout output operation is the operation of encoding all graphic layer information in the target cell according to the layout exchange format and writing it to a file. Optionally, the GDSII format or OASIS format is used for layout output.

[0180] For example, in the layout process of the aforementioned power MOSFET device, engineers generate a source metal structure covering the entire active region based on the source contact hole positions of each real cell in the active cell array. Based on the polysilicon gate arrangement direction of the active cell array and the polysilicon endpoint positions of the edge transition cells in the transition layout structure, a gate metal structure and a gate bus connection structure extending along the edge of the active region to one side of the chip are generated. An offset operation (extending outward by 2 micrometers) and a rounded corner treatment (rounded corner radius of 5 micrometers) are performed on the source metal structure and the gate metal structure, respectively, to obtain a metal envelope structure. Based on the metal envelope structure, a source pad opening region with a size of 2000 micrometers by 2000 micrometers is defined above the source metal, and a gate pad opening region with a size of 200 micrometers by 200 micrometers is defined above the gate metal. A passivation layer structure covering the entire chip surface, excluding the pad opening region, is generated. The source metal structure, gate metal structure, gate bus connection structure, pad opening region, and passivation layer structure are correlated to obtain the metal connection structure. The target termination structure (point-shaped termination ring), active cell array (containing 432,150 real cells), transition layout structure, and metal connection structure are uniformly assembled into the target cells of the target layout. A layout output operation is then performed, outputting the layout file in GDSII format. This embodiment of the invention automatically generates source and gate metal connection structures, combines offset operations and rounded corner processing to ensure manufacturing reliability, and uniformly assembles and outputs the termination structure, cell array, transition structure, and metal structure, achieving a fully automated power device layout process from parameter input to complete layout file output.

[0181] To address the problems described in the background art, this invention obtains power devices and identifies global layout parameter nodes for the power devices. These global layout parameter nodes include power device size parameters, cell process parameters, and termination ring parameters. Based on the cell process parameters, the cell arrangement period and cell arrangement step size are obtained. Based on the power device size parameters, cell arrangement period, and termination ring parameters, the number of rows and columns of the cell array is calculated. This invention achieves automated layout planning of the cell array within the effective area by superimposing cell process dimensions into the arrangement period and combining termination boundary constraints and parity correction for row and column number calculation. Based on the termination ring parameters, a one-sided path is constructed, and a mirror Boolean merge operation is performed on the one-sided path to obtain the complete termination ring node. The invention constructs a complete symmetrical terminal ring structure by offset expansion to obtain the cell prohibition region. It is evident that this invention, through parameterized construction of a single-sided path and combining symmetric mirroring and Boolean merging, automatically generates a complete four-sided symmetrical terminal ring structure by defining only one side of the path. The cell prohibition region is determined through offset expansion, avoiding the tedious manual ring-by-ring drawing process. Real cells are obtained, and multiple virtual cells are generated based on these real cells, cell arrangement step distance, and the number of rows and columns in the cell array. Virtual cells falling into the cell prohibition region are removed from these virtual cells to obtain a set of legal cell positions. Real cells are then placed based on this legal cell position set to obtain an active cell array. This invention first generates the theoretically largest virtual cell array and then, based on the cell prohibition region... By filtering the placement area, the cell array and the terminal ring boundary are automatically adapted, ensuring that all placed real cells are within the legal area. Based on the complete terminal ring structure, gap areas are obtained, resulting in a gap path set. This gap path set is then parametrically sampled to obtain a minimum polygon fill set. Boolean operations are performed on the complete terminal ring structure and the minimum polygon fill set to obtain the target terminal structure. It is evident that this invention achieves automatic adaptation of the filled polygons to the arc-shaped boundary of the terminal ring by segmenting along the gap path and controlling the fill direction of the rounded segments according to the path gradient. Furthermore, it supports flexible generation of different terminal structure morphologies through various Boolean operation modes. Boundary analysis is performed on the active cell array to obtain boundary feature data. Edge transition cells are generated from the boundary feature data and the complete terminal ring structure, and these edge transition cells are mapped onto the complete terminal ring structure to obtain a transition layout structure. It is evident that this invention extracts the boundary extremum features of the active cell array, automatically generates suitable edge transition cells, and maps them to the rounded corner path of the terminal ring, achieving a continuous transition between the regular array and the arc-shaped terminal boundary. Based on the active cell array and the transition layout structure, a metal connection structure is generated. The target terminal structure, active cell array, transition layout structure, and metal connection structure are assembled into a pre-constructed target layout to obtain a layout file. It is clear that this invention ensures manufacturing reliability by automatically generating source and gate metal connection structures, combined with offset operations and rounded corner processing.This invention unifies the assembly and output of the terminal structure, cell array, transition structure, and metal structure, achieving a fully automated power device placement process from parameter input to complete layout file output. Therefore, this invention enables parametric automatic placement and layout generation of power device terminal rings and cell arrays.

[0182] like Figure 2 The diagram shown is a functional block diagram of a power device layout system based on terminal layout and cell constraints provided in an embodiment of the present invention.

[0183] The power device layout system 100 based on terminal layout and cell constraints described in this invention can be installed in an electronic device. Depending on the functions implemented, the power device layout system 100 based on terminal layout and cell constraints may include a parameter configuration module 101, a layout construction module 102, a terminal generation module 103, and a layout assembly module 104. The module described in this invention can also be called a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and is stored in the memory of the electronic device.

[0184] The parameter configuration module 101 is used to acquire power devices and identify global layout parameter nodes of power devices. The global layout parameter nodes include power device size parameters, cell process parameters and terminal ring parameters. Based on the cell process parameters, the cell arrangement period and cell arrangement step size are acquired. Based on the power device size parameters, the cell arrangement period and terminal ring parameters are calculated to determine the number of rows and columns of the cell array.

[0185] The layout construction module 102 is used to construct a single-sided path based on the terminal ring parameters, perform a mirror Boolean merging operation on the single-sided path to obtain a complete terminal ring structure, and perform offset expansion on the complete terminal ring structure to obtain a cell-prohibited placement region.

[0186] Obtain real cells, generate multiple virtual cells based on the real cells, cell arrangement step distance and cell array row and column number, remove virtual cells that fall into the cell prohibition area from the multiple virtual cells to obtain a set of legal cell positions, place the real cells based on the set of legal cell positions to obtain an active cell array.

[0187] The terminal generation module 103 is used to obtain gap regions based on the complete terminal ring structure, obtain a gap path set, perform parameterized sampling on the gap path set to obtain a minimum polygon filling set, and perform Boolean operations on the complete terminal ring structure and the minimum polygon filling set to obtain the target terminal structure.

[0188] The layout assembly module 104 is used to perform boundary analysis on the active cell array to obtain boundary feature data, generate edge transition cells based on the boundary feature data and the complete terminal ring structure, and map the edge transition cells onto the complete terminal ring structure to obtain a transition layout structure.

[0189] Based on the active cell array and transition layout structure, a metal connection structure is generated. The target terminal structure, active cell array, transition layout structure and metal connection structure are then assembled into the pre-constructed target layout to obtain the layout file.

[0190] In detail, the modules in the power device layout system 100 based on terminal layout and cell constraints described in this embodiment of the invention adopt the same approach as described above when in use. Figure 1 This method employs the same technique as the power device layout method based on terminal layout and cell constraints described in the previous section, and can produce the same technical effect, so it will not be elaborated here.

[0191] like Figure 3 The diagram shown is a schematic representation of an electronic device that implements a power device layout method based on terminal layout and cell constraints, according to an embodiment of the present invention.

[0192] The electronic device 1 may include a processor 10, a memory 11 and a bus 12, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as a power device layout method program based on terminal layout and cell constraints.

[0193] The memory 11 includes at least one type of readable storage medium, such as flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as the portable hard drive of the electronic device 1. In other embodiments, the memory 11 can be an external storage device of the electronic device 1, such as a plug-in portable hard drive, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the electronic device 1. Furthermore, the memory 11 includes both internal storage units and external storage devices of the electronic device 1. The memory 11 can be used not only to store application software and various types of data installed on the electronic device 1, such as the code of a power device layout method program based on terminal layout and cell constraints, but also to temporarily store data that has been output or will be output.

[0194] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing power devices, graphics processors, and combinations of various control power devices. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules stored in the memory 11 (e.g., a power device layout method program based on terminal layout and cell constraints) and calls data stored in the memory 11 to perform various functions of the electronic device 1 and process data.

[0195] The bus 12 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 can be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize the connection and communication between the memory 11 and at least one processor 10, etc.

[0196] Figure 3 Only electronic devices with components are shown; it will be understood by those skilled in the art that... Figure 3 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0197] For example, although not shown, the electronic device 1 may also include a power supply (such as a battery) to power the various components. Preferably, the power supply can be logically connected to the at least one processor 10 through a power management device, thereby enabling functions such as charging management, discharging management, and power consumption management. The power supply may also include one or more DC or AC power supplies, recharging devices, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 1 may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be described in detail here.

[0198] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, a Bluetooth interface, etc.), which is typically used to establish communication connections between the electronic device 1 and other electronic devices.

[0199] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), and optionally, a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device 1 and to display a visual user interface.

[0200] The program for a power device layout method based on terminal layout and cell constraints stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When run in the processor 10, it can achieve the following:

[0201] The power device is acquired, and the global layout parameter node of the power device is identified. The global layout parameter node includes the power device size parameter, cell process parameter and terminal ring parameter. The cell arrangement period and cell arrangement step are obtained based on the cell process parameter. The number of rows and columns of the cell array is calculated based on the power device size parameter, cell arrangement period and terminal ring parameter.

[0202] A one-sided path is constructed based on the terminal ring parameters. A mirror Boolean merge operation is performed on the one-sided path to obtain a complete terminal ring structure. The complete terminal ring structure is then offset and expanded to obtain a cell-prohibited placement region.

[0203] Obtain real cells, generate multiple virtual cells based on the real cells, cell arrangement step distance and cell array row and column number, remove virtual cells that fall into the cell prohibition area from the multiple virtual cells to obtain a set of legal cell positions, place the real cells based on the set of legal cell positions to obtain an active cell array.

[0204] Based on the complete terminal ring structure, the gap region is obtained, the gap path set is obtained, the gap path set is parameterized and sampled to obtain the minimum polygon filling set, and Boolean operation is performed on the complete terminal ring structure and the minimum polygon filling set to obtain the target terminal structure.

[0205] Boundary analysis is performed on the active cell array to obtain boundary feature data. Edge transition cells are generated based on the boundary feature data and the complete terminal ring structure. The edge transition cells are then mapped onto the complete terminal ring structure to obtain a transition layout structure.

[0206] Based on the active cell array and transition layout structure, a metal connection structure is generated. The target terminal structure, active cell array, transition layout structure and metal connection structure are then assembled into the pre-constructed target layout to obtain the layout file.

[0207] Specifically, the processor 10's implementation method for the above instructions can be found in [reference needed]. Figures 1 to 3 The descriptions of the relevant steps in the corresponding embodiments are not repeated here.

[0208] Furthermore, if the modules / units integrated in the electronic device 1 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0209] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor of an electronic device, can perform the following:

[0210] The power device is acquired, and the global layout parameter node of the power device is identified. The global layout parameter node includes the power device size parameter, cell process parameter and terminal ring parameter. The cell arrangement period and cell arrangement step are obtained based on the cell process parameter. The number of rows and columns of the cell array is calculated based on the power device size parameter, cell arrangement period and terminal ring parameter.

[0211] A one-sided path is constructed based on the terminal ring parameters. A mirror Boolean merge operation is performed on the one-sided path to obtain a complete terminal ring structure. The complete terminal ring structure is then offset and expanded to obtain a cell-prohibited placement region.

[0212] Obtain real cells, generate multiple virtual cells based on the real cells, cell arrangement step distance and cell array row and column number, remove virtual cells that fall into the cell prohibition area from the multiple virtual cells to obtain a set of legal cell positions, place the real cells based on the set of legal cell positions to obtain an active cell array.

[0213] Based on the complete terminal ring structure, the gap region is obtained, the gap path set is obtained, the gap path set is parameterized and sampled to obtain the minimum polygon filling set, and Boolean operation is performed on the complete terminal ring structure and the minimum polygon filling set to obtain the target terminal structure.

[0214] Boundary analysis is performed on the active cell array to obtain boundary feature data. Edge transition cells are generated based on the boundary feature data and the complete terminal ring structure. The edge transition cells are then mapped onto the complete terminal ring structure to obtain a transition layout structure.

[0215] Based on the active cell array and transition layout structure, a metal connection structure is generated. The target terminal structure, active cell array, transition layout structure and metal connection structure are then assembled into the pre-constructed target layout to obtain the layout file.

[0216] In the embodiments provided by this invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and actual implementations may have other classification methods.

[0217] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0218] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0219] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0220] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A power device layout method based on terminal layout and cell constraints, characterized in that, The method includes: The power device is acquired, and the global layout parameter node of the power device is identified. The global layout parameter node includes the power device size parameter, cell process parameter and terminal ring parameter. The cell arrangement period and cell arrangement step are obtained based on the cell process parameter. The number of rows and columns of the cell array is calculated based on the power device size parameter, cell arrangement period and terminal ring parameter. A one-sided path is constructed based on the terminal ring parameters. A mirror Boolean merge operation is performed on the one-sided path to obtain a complete terminal ring structure. The complete terminal ring structure is then offset and expanded to obtain a cell-prohibited placement region. Obtain real cells, generate multiple virtual cells based on the real cells, cell arrangement step distance and cell array row and column number, remove virtual cells that fall into the cell prohibition area from the multiple virtual cells to obtain a set of legal cell positions, place the real cells based on the set of legal cell positions to obtain an active cell array. Based on the complete terminal ring structure, the gap region is obtained, the gap path set is obtained, the gap path set is parameterized and sampled to obtain the minimum polygon filling set, and Boolean operation is performed on the complete terminal ring structure and the minimum polygon filling set to obtain the target terminal structure. Boundary analysis is performed on the active cell array to obtain boundary feature data. Edge transition cells are generated based on the boundary feature data and the complete terminal ring structure. The edge transition cells are then mapped onto the complete terminal ring structure to obtain a transition layout structure. Based on the active cell array and transition layout structure, a metal connection structure is generated. The target terminal structure, active cell array, transition layout structure and metal connection structure are then assembled into the pre-constructed target layout to obtain the layout file.

2. The power device layout method based on terminal layout and cell constraints as described in claim 1, characterized in that, The power device dimensional parameters include: the power device's lateral dimension and the power device's longitudinal dimension; The cell process parameters include: cell height, polysilicon gate width, contact hole width, and minimum spacing between the contact hole and the polysilicon. The terminal ring parameters include: terminal boundary occupancy size, top reserved boundary height, terminal corner radius, terminal ring spacing set, and terminal ring width set.

3. The power device layout method based on terminal layout and cell constraints as described in claim 2, characterized in that, The calculation of the number of rows and columns of the cell array based on the power device size parameters, cell arrangement period, and terminal ring parameters includes: The horizontal and vertical dimensions of the power device are extracted from the power device size parameters, and the terminal boundary occupancy size and top reserved boundary height are extracted from the terminal ring parameters. The initial number of horizontal cells is calculated based on the horizontal dimension of the power device, the size occupied by the terminal boundary, the cell arrangement period, and the height of the top reserved boundary. The initial number of vertical cells is calculated based on the vertical dimension of the power device, the size occupied by the terminal boundary, the cell height, and the height of the top reserved boundary. The initial number of columns of the horizontal cells is corrected for parity to obtain the initial corrected number of columns. The horizontal remaining boundary width is calculated based on the initial number of corrected columns and the cell arrangement period. The horizontal remaining boundary width is compared with a preset minimum boundary width threshold. If the horizontal remaining boundary width is less than the minimum boundary width threshold, the number of corrected columns is reduced by a preset unit value, and the process returns to the step of calculating the horizontal remaining boundary width based on the initial number of corrected columns and the cell arrangement period, until the horizontal remaining boundary width is not less than the minimum boundary width threshold, and the number of corrected columns is obtained. The vertical remaining boundary width is calculated based on the initial number of vertical cells and the cell height. If the vertical remaining boundary width is less than the minimum boundary width threshold, the initial number of vertical cells is reduced by the unit value, and the process returns to the step of calculating the vertical remaining boundary width based on the initial number of vertical cells and the cell height, until the vertical remaining boundary width is not less than the minimum boundary width threshold, and the corrected number of rows is obtained. The corrected number of columns and the corrected number of rows are then associated to obtain the number of rows and columns of the cell array.

4. The power device layout method based on terminal layout and cell constraints as described in claim 1, characterized in that, The process of constructing a single-sided path based on the terminal ring parameters, and performing a mirror Boolean merge operation on the single-sided path to obtain a complete terminal ring structure includes: Extract the terminal rounded corner radius, terminal ring spacing set, and terminal ring width set from the terminal ring parameters. Normalize the terminal ring spacing set and terminal ring width set to obtain the offset list. A one-sided path is constructed based on the offset list and the terminal rounded corner radius; Obtain the longitudinal axis of symmetry and the transverse centerline of the power device chip. Perform left and right mirroring on the single-sided path along the longitudinal axis of symmetry to obtain left and right mirrored paths. Perform up and down mirroring on the left and right mirrored paths along the transverse centerline of the chip to obtain a four-quadrant mirrored path set. Perform a Boolean union operation on the four-quadrant mirrored path set to obtain a complete termination ring structure.

5. The power device layout method based on terminal layout and cell constraints as described in claim 4, characterized in that, The process involves obtaining a gap region based on the complete terminal ring structure, acquiring a gap path set, and then parametrically sampling the gap path set to obtain a minimum polygon fill set, including: In the complete terminal ring structure, adjacent terminal rings are identified, and the gap region between adjacent terminal rings is confirmed. The gap region is abstracted into a gap path set, wherein the gap path set includes multiple gap paths, and each gap path includes a vertical segment, a rounded corner segment, and a horizontal segment. Obtain the fill aspect ratio control node, which includes the start column aspect ratio and the end column aspect ratio; Perform the following operation on each gap path in the gap path set: Obtain the column number of the gap path in the gap path set, and calculate the fill ratio value of the gap path based on the column number and the fill aspect ratio control node; Uniform sampling is performed along the vertical segment of the gap path to obtain a set of vertical segment sampling points, wherein the set of vertical segment sampling points includes multiple vertical segment sampling points; For each vertical segment sampling point in the vertical segment sampling point set, perform the following operation: The center point of the gap path is calculated based on the sampling points of the vertical segment to obtain the first center point. A first rectangular filling unit is constructed, and the first rectangular filling unit is stretched vertically according to the filling ratio value to obtain a vertically stretched rectangular filling unit. The vertically stretched rectangular filling unit is translated to the first center point to obtain the vertical segment filling polygon. Summarize the filled polygons of the vertical segments to obtain the set of filled polygons of the vertical segments; Uniform sampling is performed along the rounded corner segments of the gap path to obtain a set of rounded corner sampling points. The following operation is performed on each rounded corner sampling point in the set of rounded corner sampling points: Based on the sampling points of the rounded corner segment, the center point and gradient on the gap path are calculated to obtain the second center point and path gradient. Based on the path gradient, the tangent direction angle is calculated, a second rectangular filling unit is constructed, and the second rectangular filling unit is rotated according to the tangent direction angle and then translated to the second center point to obtain the rounded corner segment filling polygon. Summarize the rounded corner fill polygons to obtain the rounded corner fill polygon set; Uniform sampling is performed along the horizontal segment of the gap path to obtain a set of horizontal segment sampling points. The following operation is performed on each horizontal segment sampling point in the set of horizontal segment sampling points: The center point on the gap path is calculated based on the sampling points of the horizontal segment to obtain the third center point. A third rectangular filling unit is constructed, and the third rectangular filling unit is stretched horizontally according to the filling ratio value to obtain a horizontally stretched rectangular filling unit. The horizontally stretched rectangular filling unit is translated to the third center point to obtain the horizontal segment filling polygon. Summarize the horizontal segment filled polygons to obtain the horizontal segment filled polygon set; By summing up the sets of polygons filled with vertical segments, rounded corners, and horizontal segments, we obtain the minimum polygon filling set.

6. The power device layout method based on terminal layout and cell constraints as described in claim 5, characterized in that, The calculation of the tangent direction angle based on the path gradient includes: Based on the path gradient, the lateral gradient component and the longitudinal gradient component are identified. The tangent direction angle is then calculated based on these components, using the following formula: ； in, Indicates the tangent direction angle. Represents the longitudinal gradient component. Represents the lateral gradient component. This represents the two-parameter arctangent function.

7. The power device layout method based on terminal layout and cell constraints as described in claim 6, characterized in that, The step of performing Boolean operations on the complete terminal ring structure and the minimum polygon fill set to obtain the target terminal structure includes: Obtain the target terminal mode, wherein the target terminal mode is a continuous ring mode, a point mode, a mesh mode, or a segmented hybrid mode; The minimum polygon fill set is divided into type subsets, resulting in straight line segment fill subset and rounded corner segment fill subset; If the target terminal mode is a continuous ring mode, then the complete terminal ring structure is used as the target terminal structure. If the target terminal mode is a dotted mode, then perform a Boolean difference operation on the complete terminal ring structure and the minimum polygon filling set to obtain the target terminal structure; If the target terminal mode is mesh mode, then perform a Boolean union operation on the complete terminal ring structure and the minimum polygon fill set to obtain the target terminal structure; If the target terminal mode is a segmented hybrid mode, then perform differentiated Boolean operations on the straight segment filling subset and the rounded corner segment filling subset and the complete terminal ring structure respectively, and merge the operation results to obtain the target terminal structure.

8. The power device layout method based on terminal layout and cell constraints as described in claim 1, characterized in that, The process involves performing boundary analysis on the active cell array to obtain boundary feature data, generating edge transition cells based on the boundary feature data and the complete terminal ring structure, and mapping the edge transition cells onto the complete terminal ring structure to obtain a transition layout structure, including: Boundary analysis is performed on the real cells in the active cell array to obtain boundary polygons. The extreme point operation is then performed on the boundary polygons to obtain the set of boundary key points. The number of deployable units is calculated based on the set of boundary key points, and the number of deployable units is used to determine the set of generation locations for edge transition cells. Extract symmetric boundary key points from the generated location set, and construct edge transition cells based on the symmetric boundary key points; Key points are extracted from the edge transition cells, and rounded corner radius paths are obtained in the complete terminal ring structure. The key points are then mapped onto the rounded corner radius paths to obtain the transition layout structure.

9. The power device layout method based on terminal layout and cell constraints as described in claim 1, characterized in that, The process involves generating a metal connection structure based on the active cell array and transition layout structure, assembling the target terminal structure, active cell array, transition layout structure, and metal connection structure into a pre-constructed target layout, and obtaining a layout file, including: A source metal structure is generated based on the active cell array, and a gate metal structure and a gate bus connection structure are generated based on the active cell array and the transition layout structure. Offset operations and fillet processing are performed on the source metal structure and gate metal structure to obtain a metal envelope structure. The pad opening region and passivation layer structure are defined based on the metal envelope structure. By associating the source metal structure, gate metal structure, gate bus connection structure, pad opening region, and passivation layer structure, a metal connection structure is obtained. The target terminal structure, active cell array, transition layout structure and metal connection structure are uniformly assembled into the preset target unit in the target layout, and the layout output operation is performed on the target unit to obtain the layout file.

10. A power device layout system based on terminal layout and cell constraints, characterized in that, The system includes: The parameter configuration module is used to acquire power devices and identify the global layout parameter nodes of the power devices. The global layout parameter nodes include power device size parameters, cell process parameters, and terminal ring parameters. Based on the cell process parameters, the cell arrangement period and cell arrangement step size are acquired. Based on the power device size parameters, cell arrangement period, and terminal ring parameters, the number of rows and columns of the cell array is calculated. The layout construction module is used to construct a single-sided path based on the terminal ring parameters, perform a mirror Boolean merge operation on the single-sided path to obtain a complete terminal ring structure, and perform offset expansion on the complete terminal ring structure to obtain a cell forbidden placement region. Obtain real cells, generate multiple virtual cells based on the real cells, cell arrangement step distance and cell array row and column number, remove virtual cells that fall into the cell prohibition area from the multiple virtual cells to obtain a set of legal cell positions, place the real cells based on the set of legal cell positions to obtain an active cell array. The terminal generation module is used to obtain gap regions based on the complete terminal ring structure, obtain a gap path set, perform parameterized sampling on the gap path set to obtain a minimum polygon filling set, and perform Boolean operations on the complete terminal ring structure and the minimum polygon filling set to obtain the target terminal structure. The layout assembly module is used to perform boundary analysis on the active cell array to obtain boundary feature data, generate edge transition cells based on the boundary feature data and the complete terminal ring structure, and map the edge transition cells onto the complete terminal ring structure to obtain a transition layout structure. Based on the active cell array and transition layout structure, a metal connection structure is generated. The target terminal structure, active cell array, transition layout structure and metal connection structure are then assembled into the pre-constructed target layout to obtain the layout file.

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