Design simulation method, apparatus, medium, and program based on co-planar packaging system

Abstract

The present application relates to the field of chip design, and particularly relates to a design simulation method, device, medium and program based on a co-planar packaging system, which comprises the following steps: S301, providing a co-planar packaging system; S302, obtaining a simulation description of the co-planar packaging system; S303, simulating the co-planar packaging system according to the simulation description to obtain a simulation result; S304, calculating a loss difference between the insertion loss and the design loss; S305, when the loss difference is greater than a set loss difference, performing S306; S306, generating an optimization suggestion according to the loss difference. For the co-planar packaging system, the present application provides an optimization design method for limiting and guiding the simulation direction, so as to provide an auxiliary simulation decision for engineers and reduce the simulation pressure.

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically to design simulation methods, equipment, media, and programs based on coplanar packaging systems. Background Technology

[0002] With the rapid development of technologies such as artificial intelligence, 5G communication, and high-performance computing, integrated circuit chips are evolving towards higher integration, higher power density, and higher operating frequencies. The number of transistors on chips is increasing exponentially, leading to a sharp rise in heat generated per unit area. Simultaneously, the widespread application of advanced packaging technologies such as 2.5D / 3D stacking and heterogeneous integration has enabled the high integration of multiple functional chips into a single package, further exacerbating heat accumulation and thermal interference problems.

[0003] Heat dissipation has become a key bottleneck restricting chip stability and performance. Increased temperature significantly increases the failure rate of electronic components. Furthermore, traditional air-cooling and passive heat dissipation methods are inadequate in handling transient high heat flux and localized hotspots. In addition, with the continuous increase in signal frequency, the dielectric loss of traditional substrate materials is relatively high, posing a serious challenge to signal transmission integrity.

[0004] Therefore, there is an urgent need to develop a new type of chip that combines excellent heat dissipation performance and good high-frequency transmission characteristics to meet increasingly demanding application requirements. Summary of the Invention

[0005] The purpose of this invention is to provide a design simulation method for coplanar packaging systems, which partially solves or alleviates the above-mentioned deficiencies in the prior art. It can enhance the heat dissipation and communication capabilities of the chip architecture by introducing a ceramic substrate, while optimizing its simulation design efficiency, so as to assist engineers in making rapid decision-making.

[0006] To solve the aforementioned technical problems, the present invention specifically adopts the following technical solution: A first aspect of the present invention is to provide a design simulation method based on a coplanar packaging system, comprising the following steps: S301, a coplanar packaging system is provided, the coplanar packaging system comprising: a ceramic substrate, wherein a photonic chip and an electronic chip are respectively disposed on the same surface of the ceramic substrate, and the photonic chip and the electronic chip communicate electrically through conductive paths on the ceramic substrate; S302, Obtain a simulation description of the coplanar packaging system; S303, The coplanar packaging system is simulated according to the simulation description to obtain simulation results, which include: main indicators, and the main indicators include: insertion loss; S304, Calculate the loss difference between the insertion loss and the design loss; S305, if the loss difference is greater than the set loss difference, then execute S306; S306, generates optimization suggestions based on the loss difference; these include: S3061, determine at least one loss line of the coplanar packaging system based on the loss difference; S3062, Delineate abnormal line areas based on at least one loss line; S3063, Select a local line area based on the abnormal line area; wherein, S3063 includes: Obtain the redundancy width; with the abnormal region as the center, expand the redundancy width outward around the abnormal region to form a local line region; S3064, Generate optimization suggestions based on the local line area.

[0007] In some embodiments, the ceramic substrate is an alumina ceramic, an aluminum nitride ceramic, a silicon nitride ceramic, or a beryllium oxide substrate.

[0008] In some embodiments, the simulation results further include: auxiliary simulation indicators, which include: temperature or current, and the attention weight of the auxiliary simulation indicators is less than the attention weight of the loss line. The attention weight is used to define the amount of update resources invested in the corresponding indicator. Correspondingly, during the simulation cycle, the simulation process is updated together based on the main indicator and the auxiliary simulation indicators.

[0009] In some embodiments, it also includes: The local line area is divided into at least one partition; To set an update priority for at least one partition, S3064 includes: Optimization suggestions are generated for the local line area based on the update priority.

[0010] In some embodiments, partitions with an update priority greater than a set priority are designated as partitions to be updated, and the optimization suggestions are generated based on the partitions to be updated.

[0011] In some embodiments, the steps further include: The priority is set according to the simulation stage; the later the simulation stage, the higher the priority.

[0012] In some embodiments, simulation optimization suggestions include at least one of the following types: packaging distance between photonic chips and electronic chips, length, density, width of signal paths, and thickness of ceramic substrates.

[0013] In some embodiments, the method further includes the step of: The simulation update score is generated based on the simulation stage, where the later the simulation stage, the smaller the simulation update score. Application update scores are generated according to the application scenario and set application rules. Redundant update scores are generated based on simulation update scores and application update scores; When the redundancy update score is greater than the set update score value, the update setting of the redundancy width is triggered.

[0014] This invention provides a computing device, comprising: Processor; and A memory having instructions stored thereon that, when executed by the processor, implement the steps of the method as described in any embodiment.

[0015] The present invention also provides a storage medium storing a computer program, which, when executed by a processor, implements the method described in any of the embodiments.

[0016] The present invention also provides a computer program product, including a computer program that, when executed by one or more processors, causes the one or more processors to perform the steps of the method as described in any of the embodiments.

[0017] Beneficial technical effects: To address the characteristics of coplanar packaging systems, such as long trace lengths and strong coupling of multiple physics fields, this invention provides a design simulation method primarily focused on limiting trace losses. This simulation method imposes constraints on the simulation iteration process through parameter dimensions (focusing on loss differences) and physical region dimensions (locally selecting key update regions). This aims to control the simulation costs invested in optimization while meeting optimization requirements as much as possible, thereby saving simulation computing power.

[0018] Furthermore, the present invention can restrictively select the local update region based on the distribution of abnormal points in the packaging system, so as to reduce the risk of getting trapped in a local solution while reasonably limiting update input.

[0019] Furthermore, the present invention can also combine the application scenario of the packaging system and the selection mechanism of the local update region (such as the selection of redundancy width) in the actual simulation stage to make update judgments, so as to further avoid or mitigate the risk of getting trapped in a local solution due to update constraints while limiting update input.

[0020] In other words, the present invention can dynamically adjust the selection scale of the local update region to improve the flexibility of local selection. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, The components or parts are not necessarily drawn to actual scale. Obviously, the accompanying drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0022] Figure 1 This is a schematic diagram of the method flow in an exemplary embodiment of the present invention; Figure 2 This is a schematic diagram of the method flow in another exemplary embodiment of the present invention; Figure 3 This is a block diagram of a computing device in an exemplary embodiment of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0024] In this document, suffixes such as "module," "part," or "unit" used to denote elements are used only for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "part," or "unit" may be used interchangeably.

[0025] In this document, the terms "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0026] In this document, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0027] In this document, "and / or" includes any and all combinations of one or more of the listed related items.

[0028] In this article, "multiple" means two or more, that is, it includes two, three, four, five, etc.

[0029] As used in this specification, the term "about" typically means + / -5% of the value, more typically + / -4% of the value, more typically + / -3% of the value, more typically + / -2% of the value, even more typically + / -1% of the value, and even more typically + / -0.5% of the value.

[0030] In this specification, certain embodiments may be disclosed in a range-bound format. It should be understood that this "range-bound" description is merely for convenience and brevity and should not be construed as a rigid limitation on the disclosed range. Therefore, the description of a range should be considered as having specifically disclosed all possible subranges and the individual numerical values ​​within those ranges. For example, a description of the range 1-6 should be considered as having specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and the individual numbers within those ranges, such as 1, 2, 3, 4, 5, and 6. This rule applies regardless of the breadth of the range.

[0031] For example, the conductive path can specifically be an RDL line disposed on a ceramic substrate. The RDL line is also referred to as a rewiring or redistribution line. Alternatively, the conductive path may also include an RDL line and conductive bumps connected to its two ends.

[0032] RDL, short for Redistribution Layer, is a process that allows I / O pads to be moved from the center of the chip to the edge, distributing them over a wider area.

[0033] Ceramic substrates: Ceramic substrates typically refer to substrates made of ceramic insulating material on which conductive circuit layers (such as TSV vias and RDL layers) are formed through appropriate metallization processes. These substrates are used to support semiconductor chips (such as photonic chips or electronic chips) and to achieve electrical interconnection between the chips and external components. For example, they can include various types such as high-temperature co-fired ceramic (HTCC) substrates, low-temperature co-fired ceramic (LTCC) substrates, direct copper-clad ceramic (DBC) substrates, or direct copper-plated ceramic (DPC) substrates. All types of ceramic substrates often possess high thermal conductivity and high electrical insulation.

[0034] Currently, with the rapid development of cloud computing, artificial intelligence computing power, and 5G communications, extremely high demands are being placed on the computing performance of semiconductor devices, especially on signal transmission speed and frequency. This application selects a novel ceramic-based chip to meet this growing demand for performance optimization.

[0035] It should be noted that although the ceramic substrate itself may not be conductive, metallizing the ceramic substrate can endow it with excellent conductive communication capabilities. Therefore, the metallized ceramic substrate possesses both strong heat dissipation and conductivity.

[0036] For example, the present invention provides a chip packaging system (or ceramic-based system, ceramic-based chip architecture) that incorporates a ceramic substrate as a packaging substrate.

[0037] Specifically, it can be directly applied to existing chip systems, that is, to directly replace the original silicon adapter board or silicon substrate, or it can adopt a new packaging scheme according to the characteristics of the ceramic substrate or the update of advanced packaging technology.

[0038] For example, ceramic substrate-based packaging can be divided into two categories: non-surface packaging and co-surface packaging. Non-surface packaging refers to electronic chips (EICs) and photonic chips (PICs) being disposed on opposite sides of the ceramic substrate, while co-surface packaging refers to electronic chips (EICs) and photonic chips (PICs) being disposed on the same surface of the ceramic substrate. In particular, it refers to all chips (such as photonic and electronic chips) being disposed on the same surface.

[0039] Compared with traditional substrates (such as silicon substrates), the simulation analysis of ceramic substrates (such as LTCC (low temperature co-fired ceramics), HTCC (high temperature co-fired ceramics) or aluminum nitride ceramics) faces more stringent challenges in terms of dimensionality and complexity, and their simulation time often increases exponentially.

[0040] First, ceramic substrates involve more intense multiphysics coupling effects during operation. For example, the Joule heating generated by chip operation not only leads to temperature increases but also induces thermal stress due to the significant difference in the coefficient of thermal expansion (CTE) between the ceramic material and the metal interconnect layers (such as RDLs and vias). This stress can further cause cracking at the RDL interface or delamination failure of the ceramic substrate. Therefore, when facing high-specification product design standards, the simulation of ceramic substrates needs to focus not only on individual electrical or thermal properties but also, often, on the coupling of the three physical fields—electricity, heat, and force—for a comprehensive analysis.

[0041] From another perspective, while ceramic substrates offer superior heat dissipation, their material parameters also exhibit greater temperature dependence. Key physical properties of ceramic materials and their metallized layers, such as thermal conductivity, resistivity, and elastic modulus, change significantly with temperature. In accurate simulations, these parameters are often treated as functions of temperature rather than constant values. This nonlinear characteristic further complicates the solution of the simulation equations.

[0042] Furthermore, the interconnect structures in ceramic substrates are far more complex. Multilayer ceramic substrates contain a large number of vias, cavities, and embedded components. To fully model and accurately solve their S-parameters or parasitic effects would consume enormous computational resources. If the current density distribution of RDL wiring, the electromigration lifetime of vias, and the thermal-mechanical reliability of interfaces are also taken into account, the degrees of freedom and mesh count of the simulation model will far exceed those of conventional substrates, resulting in a single simulation taking several hours or even days.

[0043] In summary, due to the strong coupling of multi-physics fields, material nonlinearity, and complex three-dimensional structure, ceramic substrates have a much higher simulation dimension and computational cost than conventional non-ceramic substrates.

[0044] Furthermore, the simulation optimization process for chip architecture design includes: setting simulation description parameters and simulation scenarios (i.e., simulation descriptions) according to design specifications, such as operating frequency band, port excitation method, material dielectric constant, metal conductivity, mesh generation accuracy, and absorption boundary conditions; subsequently, using full-wave electromagnetic field simulation tools based on the finite element method or finite-difference time-domain method to solve for the electromagnetic characteristics of the chip structure and obtain response results such as S-parameters, field distribution, or impedance characteristics. Based on this, with insertion loss, temperature, stability, or other performance indicators as optimization targets, iterative adjustments are made to key geometric dimensions and material parameters through parameter scanning, sensitivity analysis, or intelligent optimization algorithms (such as genetic algorithms, particle swarm optimization, etc.). After each iteration, the simulation is re-simulated and the performance is evaluated until the results meet the preset design threshold, thereby obtaining the optimal design scheme.

[0045] For example, in some embodiments, the simulation structural parameter description includes: device structural parameters necessary for designing the chip architecture, wherein the structural parameters may specifically be the area and thickness of the ceramic substrate, or the size of the photonic chip and the size of the electronic chip, etc., which are necessary parameter information for describing their physical physical architecture; and electrical parameters of the device structure, such as the dielectric constant of the ceramic substrate. That is to say, the simulation structural parameters may include any type of parameter that has a substantial impact on the chip's operating performance.

[0046] For example, structural parameters may also include: RDL layout parameters (such as line width, density or length, etc.).

[0047] For example, in some embodiments, the description types of the simulation scenario include: working environment (such as working temperature and humidity), computational task (such as a computational solution task designed for simulation testing) and / or operating rules (such as parameter constraints (or parameter ranges) during chip operation, such as communication speed constraints and computational efficiency constraints). For example, when the chip exceeds these parameter constraints, it may indicate that it is in an abnormal working state.

[0048] For example, three-dimensional full-wave electromagnetic field simulation software, such as HFSS, can be used for design simulation.

[0049] In response, this invention provides an optimized simulation design scheme for the special requirements of ceramic substrates (especially the simulation requirements of coplanar packaging systems).

[0050] For example, a ceramic substrate refers to a special process board in which copper foil is directly bonded to the surface (single-sided or double-sided) of an alumina (Al2O3) or aluminum nitride (AlN) ceramic substrate at high temperature.

[0051] For example, during multiple iterations of simulation, different optimization and update suggestions can be set for different abnormal situations based on the optimization algorithm or historical simulation records.

[0052] For example, in some embodiments, taking temperature anomalies as an example, in order to reduce the risk of temperature anomalies, the following optimization and update suggestions can be given: optimize the heat dissipation structure near the anomaly point (such as adding heat dissipation holes or increasing the radius of the heat dissipation holes), and reduce the wiring density of the RDL (in order to moderately alleviate the signal transmission pressure).

[0053] For example, in some embodiments, recommended simulation suggestions can be set for different anomaly types by recording historical simulation databases.

[0054] Specifically, for different anomaly types (such as localized temperature exceeding limits, excessive current density, stress concentration, signal delay exceeding limits, etc.), the simulation system can automatically extract its key characteristic parameters (including the peak value, gradient, spatial size of the anomaly region, and its coupling degree with adjacent structures, etc.) and match them with similar cases already labeled in the historical simulation database. Based on the matching results, it recommends adjustment strategies and their specific parameters (such as linewidth adjustment amount, metal fill rate change value, adjustment range expansion coefficient, etc.) that have been verified as effective in historical cases, and uses them as update and optimization suggestions for the current iteration.

[0055] Alternatively, in other embodiments, various optimization algorithms can be used to drive automatic parameter optimization in iterative simulation optimization to improve convergence efficiency and solution quality.

[0056] For example, for optimization problems with a small design variable space and a relatively smooth objective function, classic numerical optimization algorithms such as gradient descent or quasi-Newton methods can be used to rapidly iterate and approximate local optima by utilizing the sensitivity information of simulation results to design parameters along the descent direction of the objective function (such as peak temperature or maximum current density).

[0057] For example, for complex optimization problems with many design variables (such as when adjusting multiple structural descriptions simultaneously) and multi-peak or multi-constraint objective functions, optimization algorithms such as Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) can be used. This invention does not limit the specific update optimization mechanism.

[0058] It should be noted that by limiting the range of update parameters (such as the dimension to be updated), this invention can reduce the optimization difficulty and pressure during the simulation process.

[0059] Preferably, the present invention uses a coplanar packaging system to complete the packaging of the ceramic substrate system. This coplanar process is relatively easy to standardize for testing and mass production. Specifically, since all electrodes are on the same plane, it is convenient to achieve standardized and low-cost electrical connections with test probes and circuit boards.

[0060] In order to assist users in completing the rapid simulation design of coplanar packaging systems, this invention specifically provides a corresponding design simulation method for coplanar packaging systems.

[0061] See Figure 1 As shown, the present invention also provides a design simulation method based on a coplanar packaging system, including the following steps: S301, a coplanar packaging system is provided, the coplanar packaging system comprising: a ceramic substrate, wherein a photonic chip and an electronic chip are respectively disposed on the same surface of the ceramic substrate, and the photonic chip and the electronic chip communicate electrically through conductive paths on the ceramic substrate; S302, Obtain a simulation description of the coplanar packaging system; S303, Simulate the coplanar packaging system according to the simulation description to obtain the insertion loss; In this embodiment, insertion loss can be regarded as transmission loss S21.

[0062] S304, Calculate the loss difference between the insertion loss and the design loss; S305, when the loss difference is greater than the set loss difference, then execute S306: S306, generates optimization suggestions based on the loss difference; these include: S3061, determine at least one loss line (equivalent to an abnormal point) of the coplanar package system based on the loss difference. For example, one or more conductive paths exhibiting abnormal losses can be located. That is, a lossy line can correspond to at least one conductive path.

[0063] S3062, an abnormal line area (equivalent to an abnormal region) is defined based on at least one loss line. For example, in some embodiments, a functional area containing a lossy line is identified as an abnormal line area. This functional area can be divided according to the functional partitioning information in the initial chip design.

[0064] Alternatively, in some embodiments, the chip or substrate is pre-divided into gridded regions, and areas where lossy lines appear (such as a small grid) are regarded as abnormal line areas.

[0065] S3063, Select a local line area (equivalent to a local update area) based on the abnormal line area. For example, in some embodiments, an abnormal line area can be directly identified as a local line area.

[0066] S3064, Generate optimization suggestions based on the local line area.

[0067] In some embodiments, simulation optimization suggestions include at least one of the following types: packaging distance between photonic chips and electronic chips, length, density, width of signal paths, and thickness of ceramic substrates.

[0068] In other words, in this embodiment, the issue of long traces in the coplanar packaging system will be the focus of optimization during the simulation process.

[0069] Furthermore, S3063 includes: Obtain redundant width; Centered on the abnormal region, a redundant width is extended outward around the abnormal region to form a local line region.

[0070] For example, in some embodiments, expanding the redundant width outward around the abnormal region to form a local update region can be: expanding outward by a certain length (the length value is the redundant width) around the boundary of the abnormal region to form the expanded local update region.

[0071] Alternatively, a center point can be set based on the abnormal region (e.g., the center of the abnormal region can be used as the center point), and expansion can be made outward around the center point.

[0072] In some embodiments, the steps further include: The redundancy width is determined based on the abnormal density of the abnormal region, and the greater the abnormal density, the greater the redundancy width.

[0073] Among them, the density of anomalies can be characterized by the number of anomaly points in a unit anomaly region.

[0074] Alternatively, the density of anomalies can be characterized by the distribution density of anomaly points in anomaly regions.

[0075] For example, when the density of temperature anomalies is greater (such as a concentration of overheating points and a large number of them), there is a greater tendency to increase the redundancy of the simulation (specifically, to increase the redundancy width) in order to alleviate or reduce the overheating risk expansion problem that may be increased by thermal superposition.

[0076] In some embodiments, a redundancy update determination mechanism is also included, which includes the steps of: 1. The simulation update score is generated based on the simulation stage. The later the simulation stage, the smaller the simulation update score. For example, the simulation process can be pre-set into different simulation stages, and different simulation update scores can be assigned to different simulation stages. For instance, the simulation can be divided into initial simulation stage, optimization simulation stage, and verification simulation stage according to the time sequence of chip design, with the simulation update score increasing as the stage progresses. In other words, the size of the update area needs to be appropriately limited as the process progresses.

[0077] For example, the simulation stage can be characterized by the number of iterations or the magnitude of the target deviation. A higher number of iterations (which usually indicates a relatively late stage of the simulation) results in a higher simulation update score. Conversely, a smaller target deviation results in a higher simulation update score.

[0078] For example, target deviation refers to the deviation between the measured index and the standard index. For instance, taking insertion loss as an example, the measured index is the actual insertion loss, the standard index is the design loss, and the deviation is the loss difference. Alternatively, in other embodiments, in addition to the loss difference, other indices can be introduced to improve the accuracy and reliability of the simulation. For example, taking temperature as an example, the measured index is the actual temperature, and the standard index is the upper limit temperature that the chip architecture is allowed to reach when running a specified computational task under a given environment.

[0079] 2. Generate application update scores according to the application scenario and set application rules; For example, in some embodiments, when the application scenario is high-frequency signal transmission (such as RF / millimeter-wave signal transmission), the application update size is relatively small. In this case, it is necessary to allow for a moderate constraint on the redundancy width to be expanded. In high-frequency signal transmission scenarios, the high-frequency electromagnetic field energy may exhibit high localization, in which case targeted updates can be performed through small-scale local adjustments.

[0080] For example, in the automotive field, such as when it's an automotive-grade chip, the application update score is slightly higher, meaning a relatively higher redundancy width needs to be configured. For instance, ceramic materials are brittle, and stress peaks typically appear at RDL corners or metal-ceramic interfaces. In this case, if only the peak point is changed (e.g., only the linewidth is widened), the stress peak risks shifting to adjacent corners. Therefore, it's necessary to appropriately expand the size of the local update area.

[0081] For example, in applications where thermal management requirements are high, such as HPC (High-Performance Computing) chips or AI chips, the redundancy length can be configured to be higher. In this case, by increasing the redundancy length, the negative impact of the lateral heat conduction effect in the ceramic substrate on the overall chip can be appropriately reduced or mitigated.

[0082] 3. Generate redundant update scores based on simulation update scores and application update scores; 4. When the redundancy update score is greater than the set update score, the redundancy width update setting is triggered (that is, this embodiment provides a redundancy width update judgment mechanism).

[0083] For example, the scoring rule for redundant update scores is as follows: Redundancy update score = α * simulation update score + β * redundancy update score.

[0084] Here, α and β are the set update weights. Specifically, engineers can dynamically adjust the update weights according to their different levels of attention to the simulation process length or scenario.

[0085] Specifically, when the redundancy update score is greater than the update score value, the redundancy width can be updated from the original default value to a new value (which is higher than the default value).

[0086] Specifically, the new redundancy width value can be determined based on the size of the redundancy update score; for example, the larger the redundancy update score, the larger the redundancy width value.

[0087] Preferably, the present invention further includes the step of: Identify the optimization benefits under a set simulation period; When the optimization benefit is less than the set threshold, the judgment mechanism for updating the redundancy width is triggered (as in steps 1-4 above).

[0088] Among them, optimization benefit refers to the degree of optimization of indicators from the initial moment to the final moment of the set simulation cycle (such as the percentage decrease in loss difference or the percentage decrease in temperature).

[0089] For example, in some embodiments, the length of the simulation cycle can be set by the user, such as setting 5 iterations as a simulation cycle.

[0090] Preferably, in this embodiment, the redundancy width update is initiated only when the optimization benefit is weak, in order to save computing power. Simultaneously, by triggering the redundancy width update mechanism within a specific time period, the cost of each update can be reduced by limiting the update region, while also mitigating the risk of the optimization process getting trapped in a local solution.

[0091] In other words, this embodiment achieves a moderate balance between updating computing power and the risk of getting trapped in local solutions under the redundancy width-restricted update mechanism.

[0092] In some embodiments, the simulation results further include auxiliary simulation indicators, which include temperature or current, and the auxiliary simulation indicators have a lower weight than the weight of the loss line (or, lower than the weight of the primary indicator). The weight of the auxiliary simulation indicators is defined as the amount of update resources allocated to the corresponding indicator. Correspondingly, during the simulation cycle, the simulation process is updated jointly based on the primary indicator and the auxiliary simulation indicators.

[0093] In other words, in this embodiment, during the update process, it is necessary to consider not only the loss difference between insertion loss and design loss, but also the index difference corresponding to the auxiliary simulation index.

[0094] For example, in some embodiments, the simulation update process includes: after S302, performing the following steps: Calculate the difference between simulation metrics (including primary and secondary simulation metrics) and design metrics; Optimization suggestions are generated based on the differences in indicators.

[0095] Specifically, both primary and secondary simulation metrics can be used as targets for simulation optimization, but the focus weights are used to define their priority as optimization targets. Different update suggestions can be generated based on different priorities.

[0096] For example, firstly, multiple optimization objectives (including primary and secondary simulation metrics) can be determined based on the performance requirements of the packaging system. For each optimization objective, at least one key simulation parameter is set associated with it, such as dielectric layer thickness and signal line width associated with insertion loss, line spacing associated with crosstalk (equivalent to a secondary simulation metric), and reference layer distance associated with impedance matching (equivalent to a secondary simulation metric). Secondly, each of the key simulation parameters is assigned a level of concern (which is generated by different concern weights; the higher the weight, the higher the level of concern). In a preferred embodiment, the optimization objectives are divided into three priority levels: high, medium, and low. For example, in high-speed digital signal transmission scenarios, insertion loss and impedance consistency have the most direct impact on signal quality, so their corresponding parameters such as line width and dielectric thickness are set to higher concern (and insertion loss can be higher than impedance consistency); crosstalk has a secondary impact on the system bit error rate, so its corresponding parameters such as line spacing are set to medium concern; while secondary structural dimensions with less impact on heat dissipation are set to low concern.

[0097] Finally, during the iterative optimization process based on electromagnetic field simulation software (such as HFSS), simulation update resources are dynamically allocated according to the level of concern: for parameters of high concern, a parameter scan with a fine step size is performed near their current value or a high-precision adaptive mesh is used, and their values ​​are updated first in each iteration to ensure that they converge quickly to the optimal range; for parameters of medium concern, a coarser scan step size is used and the update frequency is reduced; for parameters of low concern, they are adjusted all at once in the later stage of the simulation process or roughly evaluated over a large range, thereby concentrating the main computational resources and time on the key parameters that have the most significant impact on the overall performance.

[0098] In other words, in this embodiment, selecting to generate different update suggestions can specifically be reflected in using different step sizes.

[0099] Through the above methods, this embodiment can significantly reduce the amount of simulation calculations and shorten the optimization cycle while ensuring that the overall performance of the packaging system meets the design specifications. It is especially suitable for the rapid design convergence of ceramic-based chip systems containing a large number of interconnect structures.

[0100] Furthermore, it also includes: The local line area is divided into at least one partition; Set the update priority for at least one partition.

[0101] For example, in some embodiments, the area can be divided according to the location of the line, such as corner area (i.e., RDL turning point, or area with interlayer vias), connection area (which can be via / Via connection area, such as RDL can be connected to vias set on the substrate), pad proximity area (that is, RDL lines that are attached to / close to pad pads, such as RDL usually has multiple layers, and one or more layers close to the pad can be set as pad proximity area), etc.

[0102] For example, the priority of the corner area, the connection area, and the pad adjacent area can be decreased in that order.

[0103] The update priority setting can be used to configure different update priorities. For example, partitions with higher update priorities are configured to receive higher attention, allowing for more granular configuration updates, while others can be updated with relatively simple auxiliary updates.

[0104] Specifically, the simulation process can calculate the loss difference of multiple conductive paths, and can locally update the settings for multiple conductive paths with abnormal losses.

[0105] In some embodiments, partitions with an update priority greater than a set priority are designated as partitions to be updated, and the optimization suggestions are generated based on the partitions to be updated.

[0106] For example, in this embodiment, more attention is paid to the partition to be updated, while the other partitions can remain unchanged or only undergo minor adaptive updates.

[0107] In some embodiments, the steps further include: The priority is set according to the simulation stage; the later the simulation stage, the higher the priority.

[0108] In other words, as the simulation progresses, the scope of interest is gradually constrained and narrowed to further limit the magnitude of later updates and reduce the risk of invalid calculations due to risk deviations.

[0109] For example, the simulation process can be pre-set into different simulation stages. These can be divided into initial simulation, optimization simulation, and verification simulation stages according to the time sequence of chip-related events, with higher priority assigned to later stages. In other words, the later the stage, the more restrictions need to be placed on the extent of updates.

[0110] For example, the simulation stage can be characterized by the number of iterations or the magnitude of the target deviation. A higher number of iterations (which usually indicates a later stage in the simulation) warrants a higher priority. Conversely, a smaller target deviation warrants a higher priority.

[0111] For example, target deviation refers to the deviation between the measured index and the standard index (i.e., the index difference mentioned above). For example, taking the temperature index as an example, the measured index is the measured temperature, and the standard index is the upper limit temperature that the chip architecture is allowed to reach when running a set computing task under a set environment.

[0112] In some embodiments, the ceramic substrate is alumina ceramic, aluminum nitride ceramic, silicon nitride ceramic, or beryllium oxide.

[0113] Furthermore, in some embodiments, the simulation optimization suggestions include at least one of the following types: The packaging distance of photonic chips and electronic chips, the length, density, and width of signal paths, and the thickness of ceramic substrates.

[0114] It should be noted that in this embodiment, for the long-distance communication problem of coplanar packaging, the length of the signal path and the packaging distance of the optoelectronic chip can be the key optimization or constraint objects.

[0115] Specifically, in this embodiment, since the electrodes are all on the top surface in the coplanar package, the signal must be connected to the outside through a long horizontal RDL or gold wire. During simulation, conductor loss can be reduced by adjusting the substrate thickness to widen the linewidth.

[0116] Meanwhile, the applicant noted that long bond wires or long RDLs primarily introduce series parasitic inductance (L). Simulations could preferentially focus on the arc height and span of the bond wire / RDL lines, or add matching networks (such as series capacitors) along the RDL path to compensate for the inductance, with the goal of flattening the roll-off of S21.

[0117] Furthermore, the method also includes: The redundancy width is determined based on the degree of variation in the chip's pad density; whereby the greater the degree of variation, the smaller the redundancy width. For example, the degree of variation can be characterized using standard deviation.

[0118] For example, the redundancy width can be customized. For instance, when the global density of the chip varies drastically (large standard deviation), the redundancy width can be reduced.

[0119] In other words, in this embodiment, when the density of the chip's pads varies significantly in a specific region, its reference level to the surrounding area can be appropriately limited in order to focus on updating the current area as much as possible, thereby reducing interference to the surrounding area (or, in other words, reducing the overall update pressure).

[0120] The present invention also provides a computer-readable storage medium storing computer instructions, wherein when the computer instructions are executed by one or more processors, the one or more processors cause the one or more processors to perform the steps of the method as described in any one of the present invention.

[0121] The present invention also provides a computer program product, comprising a computer program that, when executed by one or more processors, causes the one or more processors to perform the steps of the method as described in any one of the present invention.

[0122] The present invention also provides a schematic block diagram of the structure of a computer device, please see below. Figure 3 Computer programs can be used in situations such as Figure 3 It runs on the computer device shown. Figure 3 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The memory may include non-volatile storage media and internal memory. The non-volatile storage media may store an operating system and computer programs. The computer programs include program instructions that, when executed, cause the processor to perform arbitrary methods. The processor provides computational and control capabilities to support the operation of the entire computer device. The internal memory provides an environment for the execution of the computer programs in the non-volatile storage media; when executed by the processor, these programs cause the processor to perform arbitrary methods. The network interface is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 3The structures shown are merely block diagrams of a portion of the structure related to the present application and do not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than shown in the figures, or combine certain components, or have different component arrangements. It should be understood that the processor may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0123] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0124] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a computer terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0125] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A design simulation method based on a coplanar packaging system, characterized in that, Including the following steps: S301, a coplanar packaging system is provided, the coplanar packaging system comprising: a ceramic substrate, wherein a photonic chip and an electronic chip are respectively disposed on the same surface of the ceramic substrate, and the photonic chip and the electronic chip communicate electrically through conductive paths on the ceramic substrate; S302, Obtain a simulation description of the coplanar packaging system; S303, The coplanar packaging system is simulated according to the simulation description to obtain simulation results, which include: main indicators, and the main indicators include: insertion loss; S304, Calculate the loss difference between the insertion loss and the design loss; S305, if the loss difference is greater than the set loss difference, then execute S306; S306, generates optimization suggestions based on the loss difference; these include: S3061, determine at least one loss line of the coplanar packaging system based on the loss difference; S3062, Delineate abnormal line areas based on at least one loss line; S3063, Select a local line area based on the abnormal line area; wherein, S3063 includes: Obtain the redundancy width; with the abnormal region as the center, expand the redundancy width outward around the abnormal region to form a local line region; S3064, Generate optimization suggestions based on the local line area.

2. The method according to claim 1, characterized in that, The ceramic substrate is an alumina ceramic, an aluminum nitride ceramic, a silicon nitride ceramic, or a beryllium oxide substrate.

3. The method according to claim 1, characterized in that, The simulation results also include auxiliary simulation indicators, which include temperature or current. The attention weight of the auxiliary simulation indicators is less than that of the loss line. The attention weight is used to define the amount of update resources invested in the corresponding indicator. Correspondingly, during the simulation cycle, the simulation process is updated together based on the main indicator and the auxiliary simulation indicators.

4. The method according to claim 1, characterized in that, Also includes: The local line area is divided into at least one partition; To set an update priority for at least one partition, S3064 includes: Optimization suggestions are generated for the local line area based on the update priority.

5. The method according to claim 4, characterized in that, The partitions with an update priority higher than the set priority are designated as the partitions to be updated, and the optimization suggestions are used to generate the updates based on the partitions to be updated.

6. The method according to claim 5, characterized in that, It also includes the following steps: The priority is set according to the simulation stage; the later the simulation stage, the higher the priority.

7. The method according to claim 1, characterized in that, Simulation optimization suggestions include at least one of the following: packaging distance of photonic chips and electronic chips, length, density, width of signal paths, and thickness of ceramic substrates; And / or, the method further includes the step of: The simulation update score is generated based on the simulation stage, where the later the simulation stage, the smaller the simulation update score. Application update scores are generated according to the application scenario and set application rules. Redundant update scores are generated based on simulation update scores and application update scores; When the redundancy update score is greater than the set update score value, the update setting of the redundancy width is triggered.

8. A computing device, characterized in that, include: processor; as well as A memory having instructions stored thereon, which, when executed by the processor, implement the steps of the method as described in any one of claims 1-7.

9. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the method described in any one of claims 1-7.

10. A computer program product, characterized in that, Includes a computer program that, when executed by one or more processors, causes the one or more processors to perform the steps of the method as described in any one of claims 1-7.

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