Clock system multi-logic module flattening method, device, equipment and storage medium

Abstract

The application relates to the technical field of clock system design, in particular to a clock system multi-logic module flattening method and device, equipment and a storage medium. The method comprises the following steps: obtaining each logic submodule clock design graph and port information corresponding to each logic submodule clock design graph; analyzing preset module hierarchical data to obtain hierarchical association of each logic submodule clock design graph, integrating all logic submodule clock design graphs with hierarchical association to obtain multiple module subordinate pairs; for each module subordinate pair, extracting port information of a parent module design graph and corresponding submodule design graph, matching to obtain a same-name port group of the module subordinate pair; based on all same-name port groups, establishing a signal connection relationship between each logic submodule clock design graph to generate a logic connectivity view; obtaining graph element layout data corresponding to each logic submodule clock design graph, mapping graph elements of each logic submodule clock design graph to the logic connectivity view according to the graph element layout data to obtain a clock system flattening view. The application can improve the efficiency of design review and optimization.

Description

Technical Field

[0001] This application relates to the technical field of clock system design, and in particular to a method, apparatus, device and storage medium for flattening multiple logic modules of a clock system. Background Technology

[0002] In the field of electronic design automation (EDA) technology, the clock reset generator (CRG) is a core component of the chip, and the integrity and correctness of its design directly determine the operational stability of the device.

[0003] To improve design efficiency and adapt to the design requirements of complex systems, the industry generally adopts a multi-module parallel design model. This involves multiple designers collaborating on the design tasks of different sub-modules. After each sub-module is completed, the design lead summarizes, integrates, and flattens the results to form a complete and usable design solution. Currently, the integration work for multi-module clock system designs mainly relies on general-purpose design tools such as Visio and IODraw.

[0004] However, such tools can only meet the design requirements of a single module. In practice, the sub-module design files submitted by each designer are independent of each other. When faced with scattered sub-module files, designers cannot quickly switch between local and overall as needed. This not only hinders the immediate review of the macro structure of the system, but also limits the in-depth verification of local logic, thus seriously affecting the efficiency of design review and optimization. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, this application provides a method, apparatus, device and storage medium for flattening multiple logic modules of a clock system, which enables macroscopic review and local verification to be completed in the same view, thereby improving the efficiency of design review and optimization.

[0006] The technical solution adopted by this application to solve its technical problem is: In a first aspect, this application provides a method for flattening multiple logic modules in a clock system, the method comprising: Obtain the clock design diagram of each logic submodule and the port information corresponding to the clock design diagram of each logic submodule; Parse the preset module hierarchy data to obtain the hierarchical association of the clock design diagrams of each logical submodule, and integrate all the clock design diagrams of logical submodules with hierarchical associations to obtain multiple sets of module subordinate pairs; each set of module subordinate pairs includes a parent module design diagram and at least one submodule design diagram corresponding to the parent module design diagram; For each group of module dependent pairs, extract the port information of the parent module design diagram and the corresponding child module design diagram, and match them to obtain the same-name port group of the module dependent pair; Based on all the port groups with the same name, establish the signal connection relationship between the clock design diagrams of each logic submodule and generate a logic connectivity view; Obtain the element layout data corresponding to the clock design diagram of each logic submodule, and map the elements of the clock design diagram of each logic submodule to the logical connectivity view according to the element layout data to obtain the clock system flattened view.

[0007] Optionally, in the step of mapping the elements of each logic submodule clock design diagram to the logically connected view based on the element layout data, the element mapping method for a single logic submodule clock design diagram includes: The corresponding graphic element layout data is parsed to obtain several graphic elements, the relative position information between each graphic element, and the signal connection relationship between each graphic element; Based on all the placement information, the element placement is performed within the clock design diagram of the corresponding logical submodule in the logical connectivity view; In response to the completion of placement of all said elements, wiring is performed on all elements based on the signal connection relationships between each said element to complete the element mapping of the clock design diagram of a single logic submodule.

[0008] Optionally, the step of mapping the elements of each logic submodule clock design diagram to the logical connectivity view based on the element layout data includes: Based on the module hierarchy data, the hierarchical order of the clock design diagrams of each logic submodule is determined, and the clock design diagram of the logic submodule with the lowest hierarchy is selected as the current module to be processed. Perform the primitive mapping operation of the current module to be processed, and after all the clock design diagrams of the logic sub-modules at the current level have completed primitive mapping, update the clock design diagram of the logic sub-module at the next higher level in the hierarchical order to the current module to be processed. Repeat the primitive mapping operation and module update steps until the top-level logic submodule clock design diagram completes the primitive mapping and obtains the flattened view of the clock system.

[0009] Optionally, the step of establishing the signal connection relationship between the clock design diagrams of each logic submodule based on all the port groups with the same name, and generating a logical connectivity view, includes: The level corresponding to the clock design diagram of each logic submodule is determined according to the module level data. Based on the level corresponding to the clock design diagram of each logic submodule and the preset level order, non-overlapping arrangement coordinates are assigned to the clock design diagram of each logic submodule to complete the arrangement of the clock design diagram of each logic submodule. Traverse each of the aforementioned port groups with the same name to identify the source logic submodule clock design diagram and the target logic submodule clock design diagram that have signal connection relationships; Based on the output port coordinates of the source logic submodule clock design diagram and the input port coordinates of the target logic submodule clock design diagram, a layered connection line is planned in the vertical direction to avoid obstacles. The clock design diagrams of each logic submodule after the arrangement are integrated with the connection line to obtain the logic connectivity view.

[0010] Optionally, the step of parsing the preset module-level data to obtain the hierarchical association of the clock design diagrams of each logic submodule includes: Read the module hierarchy data and identify the clock design diagram of the top-level logic submodule as the current decomposition object; The submodule information contained in the current decomposition object is parsed, the submodule information is mapped to the clock design diagram of the next level logical submodule, and a hierarchical association is established between the current decomposition object and the clock design diagram of each next level logical submodule. The clock design diagrams of each of the next-level logical submodules are updated sequentially to the current decomposition object. The parsing and association establishment steps are repeated until the clock design diagrams of all levels are decomposed, and the hierarchical association of the clock design diagrams of each logical submodule is obtained.

[0011] Optionally, after obtaining the flattened view of the clock system, the method further includes: Monitor the first update operation for the clock design diagram or signal connection relationship of any logic submodule in the clock system unfolded view, and in response to the first update operation, synchronously update the corresponding hierarchical structure or port connection information in the module hierarchical data. Monitor the second update operation for any level structure or port connection information in the module-level data, and in response to the second update operation, synchronously update the clock design diagram layout or signal connection relationship of the corresponding logic submodule in the clock system flattened view.

[0012] Optionally, after obtaining the flattened view of the clock system, the method further includes: Configure a flattening switch for each of the logic submodule clock design diagrams, wherein the flattening switch is used to control the corresponding logic submodule clock design diagram to switch between a flattened state and a collapsed state; In response to the triggering operation of the flattening switch for any of the aforementioned logic submodule clock design diagrams, if the current state is collapsed, the corresponding logic submodule clock design diagram is switched to the flattened state, and the submodules and internal connections contained within the corresponding logic submodule clock design diagram are parsed and displayed. If the current state is flat, the clock design diagram of the corresponding logic submodule will be switched to the collapsed state, hiding the submodules and internal connections contained in the clock design diagram of the corresponding logic submodule.

[0013] Secondly, this application provides a clock system multi-logic module flattening device, comprising: The information acquisition module is used to acquire the clock design diagram of each logic submodule and the port information corresponding to the clock design diagram of each logic submodule. The hierarchical parsing module is used to parse the preset module hierarchical data, obtain the hierarchical association of the clock design diagrams of each logical submodule, and integrate all the logical submodule clock design diagrams with hierarchical associations to obtain multiple sets of module subordinate pairs; each set of module subordinate pairs includes a parent module design diagram and at least one submodule design diagram corresponding to the parent module design diagram; The subordinate construction module is used to extract the port information of the parent module design diagram and the corresponding child module design diagram for each group of the module subordinate pairs, and match them to obtain the port group with the same name of the module subordinate pairs; The logical connectivity module is used to establish the signal connection relationship between the clock design diagrams of each logical submodule based on all the port groups with the same name, and generate a logical connectivity view; The system flattening module is used to obtain the element layout data corresponding to the clock design diagram of each logic submodule, and map the elements of the clock design diagram of each logic submodule to the logical connectivity view according to the element layout data to obtain the clock system flattening view.

[0014] Thirdly, this application provides an electronic device, comprising: One or more processors; One or more memory units; And one or more computer programs, wherein the one or more computer programs are stored in the one or more memories, and the one or more computer programs include instructions that, when executed by the one or more processors, cause the electronic device to perform the methods described above.

[0015] Fourthly, this application provides a computer-readable storage medium storing a program or instructions that, when executed, implement the above-described method.

[0016] In summary, this application obtains the clock design diagrams and port information of each logic submodule, parses the preset module hierarchy data to determine the subordinate relationship between parent and child modules, and then integrates them to obtain multiple sets of module subordinate pairs. For each subordinate pair, the system extracts the port information of the parent and child modules and matches port groups with the same name. Based on this, it establishes the signal connection relationship between the clock design diagrams of the logic submodules to generate a logical connectivity view. Finally, it obtains the element layout data and maps the elements to this view, thereby obtaining a flattened view of the clock system.

[0017] As can be seen, this application transforms the scattered sub-module design files into a unified data structure. By parsing hierarchical data and matching ports with the same name, a fixed association between modules is established at the data level. Independent design diagrams are integrated into a single logically connected view, and internal details are directly presented in this view through primitive mapping, thereby achieving circuit flattening.

[0018] Therefore, the beneficial effects of this application are as follows: Compared to current mainstream applications where designers using general design tools to process independent files need to manually piece together content and cannot simultaneously view the overall architecture and local details on the same interface, the clock system flattened view generated by this application simultaneously includes the system's top-level structure and the internal connections of the underlying modules within a single interface. Designers can view local details at any level without switching between multiple independent files or redesigning, eliminating the view fragmentation caused by scattered files. This approach allows macro-level review and local verification to be completed under the same view, improving the efficiency of design review and optimization. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating the method for flattening multiple logic modules in a clock system according to an embodiment of this application; Figure 2 This is a hierarchical structure diagram of the module-level data provided in the embodiments of this application; Figure 3 This is a schematic diagram of the logical connectivity view provided in the embodiments of this application; Figure 4 This is a schematic diagram of the clock design diagram of the first logic submodule provided in the embodiments of this application; Figure 5 This is a schematic diagram of the clock design diagram of the second logic submodule provided in the embodiments of this application; Figure 6 This is a schematic diagram of the clock design diagram of the third logic submodule provided in the embodiments of this application; Figure 7 This is a schematic diagram of the clock design diagram of the fourth logic submodule provided in the embodiments of this application; Figure 8 This is a schematic diagram of the clock design diagram of the fifth logic submodule provided in the embodiments of this application; Figure 9 This is a schematic diagram of the clock design diagram of the sixth logic submodule provided in the embodiments of this application; Figure 10 This is an integrated schematic diagram of the clock system flattened view provided in the embodiments of this application; Figure 11 This is a schematic diagram of the virtual structure of the clock system multi-logic module flattening device provided in this application; Figure 12 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0020] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0021] The following will clearly and completely describe the concept, specific structure, and resulting technical effects of this application in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of this application. Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this application can be combined interactively without contradicting each other.

[0022] In the field of Electronic Design Automation (EDA), the clock reset generator (CRG) is a core component of a chip, and its design integrity directly determines the stability of the device's operation. To adapt to the needs of complex system designs, the industry generally adopts a multi-module parallel design model, where multiple designers divide the work to complete the design of sub-modules, and finally the person in charge summarizes and integrates them to form a complete solution.

[0023] Current integration work for multi-module clock system designs primarily relies on general-purpose design tools such as Visio and IODraw. These tools only support single-module design; in practice, the sub-module design files submitted by each designer are independent of each other. When faced with these scattered files, designers must manually open different documents to view their contents. If they need to switch from the overall architecture to a specific detail, they must close the current view and reload the specific sub-module file, or repeatedly switch between different windows.

[0024] Due to a lack of flexible view control capabilities, existing technologies cannot dynamically adjust the granularity of view display within the same interface when handling multi-module integration. Designers are unable to examine the internal logic of specific sub-modules while maintaining visibility of the macro structure, nor can they quickly collapse irrelevant modules to focus on the critical path. This fixed file browsing mode leads to a disconnect between macro-level review and local verification processes, making it difficult for designers to complete cross-level analysis within a continuous workflow, severely impacting the efficiency of design review and optimization.

[0025] To address the aforementioned technical deficiencies, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the method for flattening multiple logic modules in a clock system according to an embodiment of this application. Figure 1 The diagram illustrates several key steps involved in the view flattening method provided in this application. The following section combines these steps with... Figure 1 Each will be explained in detail: In step S1, the clock design diagram of each logic submodule and the port information corresponding to the clock design diagram of each logic submodule are obtained.

[0026] In this stage, the logic submodule clock design diagram specifically refers to an abstract graphical container that represents the external boundary of the functional unit. Its content only includes the module's name, outline, and boundary definition, and does not include detailed design elements such as the internal circuit structure, registers, or logic gates.

[0027] Port information refers to the interface attribute data attached to the boundary of the abstract graphical container, specifically covering the port name and port direction (for example, ports are divided into input and output types), which is used to define the channel for signal interaction between the module and the external environment.

[0028] Specifically, the design resources are first traversed to identify and extract the graphical containers representing each independent functional unit, namely the clock design diagram of the logic submodule. Then, the port definition data bound to the boundary of each logic submodule clock design diagram is read, and the port names are extracted and matched accordingly.

[0029] In step S2, the preset module hierarchy data is parsed to obtain the hierarchical association of the clock design diagrams of each logic submodule, and all logic submodule clock design diagrams with hierarchical associations are integrated to obtain multiple sets of module subordinate pairs.

[0030] Among them, module-level data refers to predefined configuration information that describes the instantiation relationship and contained structure between various logical units in the clock system. It clarifies which module is the top-level container, which modules are instantiated sub-units, and the membership paths between them.

[0031] Among them, a module dependency pair refers to the smallest processing unit formed by hierarchical association and binding. It consists of a parent module design diagram that serves as the upper-level container and at least one child module design diagram that is contained by the parent module. Logically, the two form a direct inclusion-inclusion relationship and are the basic objects for subsequent port matching and signal connection.

[0032] Specifically, the system first reads preset module hierarchy data, which is typically in the form of a list or tree structure. This data records the instantiation information of each submodule and its parent module. The system then traverses the module hierarchy data to identify each pair of modules with a direct calling relationship, thereby determining the hierarchical association between the clock design diagrams of each logical submodule. Subsequently, based on the hierarchical association, all logical submodule clock design diagrams with direct parent-child relationships are logically integrated to generate multiple sets of module dependency pairs.

[0033] Furthermore, to avoid hierarchical errors or submodule loss caused by skip-processing, this application embodiment proposes that the step of parsing the preset module hierarchy data to obtain the hierarchical association of the clock design diagrams of each logic submodule includes: Read the module hierarchy data and identify the clock design diagram of the top-level logic submodule as the current decomposition object; The submodule information contained in the current decomposition object is parsed, the submodule information is mapped to the clock design diagram of the next level logical submodule, and a hierarchical association is established between the current decomposition object and the clock design diagram of each next level logical submodule. The clock design diagrams of each of the next-level logical submodules are updated sequentially to the current decomposition object. The parsing and association establishment steps are repeated until the clock design diagrams of all levels are decomposed, and the hierarchical association of the clock design diagrams of each logical submodule is obtained.

[0034] Specifically, the module hierarchy data is first read to locate and identify the clock design diagram of the top-level logical submodule, which is then set as the initial current decomposition object. Next, the submodule information contained within this current decomposition object is parsed, these submodules are instantiated into clock design diagrams of the next-level logical submodules, and a parent-child hierarchical relationship is established between the current decomposition object and these newly generated next-level modules in the data structure.

[0035] After completing the decomposition of the current layer, the clock design diagrams of each lower-level logical submodule generated earlier are sequentially updated to the new current decomposition object. The operations of parsing submodule information, mapping to new level modules, and establishing hierarchical relationships are repeated. This process is repeated cyclically, shifting the processing focus down one level in each round, until all levels of logical submodule clock design diagrams have been traversed and no longer contain any unprocessed submodules. Ultimately, through this progressively deeper processing method, the original data is transformed into a complete hierarchical relationship network with clear hierarchical relationships.

[0036] Reference Figure 2 , Figure 2 This is a hierarchical structure diagram of the module-level data provided in the embodiments of this application. Figure 2 In the specific embodiment shown, the preset module hierarchy data is first parsed, that is, the complete tree topology shown in the attached figure, starting from the "TOP" root node and expanding downwards level by level, is read. By identifying the indentation level or expand / collapse symbols in the list, the hierarchical relationship between the clock design diagrams of each logic submodule is determined, thereby obtaining the hierarchical association.

[0037] For example, it was identified that the "TOP" node directly contains four child nodes: "TOP_CLK_CRG", "AONSYS_TOP_TOP_rstgen", "BLOCK001", and "BLOCK002", establishing their direct hierarchical relationship with "TOP"; at the same time, it was identified that "BLOCK001" contains "BLOCK001_CLK_CRG" and "BLOCK002" contains "BLOCK002_CLK_CRG".

[0038] Subsequently, based on these relationships, the nodes with direct connections are packaged into multiple module dependency pairs. Specifically, a module dependency pair is generated with "TOP" as the parent module design diagram and containing the above four sub-module design diagrams; at the same time, a module dependency pair is generated with "BLOCK001" as the parent module design diagram and "BLOCK001_CLK_CRG" as the sub-module design diagram, and a module dependency pair is generated with "BLOCK002" as the parent module design diagram and "BLOCK002_CLK_CRG" as the sub-module design diagram.

[0039] In step S3, for each group of module dependent pairs, the port information of the parent module design diagram and the corresponding child module design diagram are extracted, and the same-name port group of the module dependent pair is obtained by matching.

[0040] Among them, the same-name port group refers to a set formed within a specific module subordinate pair by pairing a port on the parent module design diagram with a port on the child module design diagram. These two ports have completely identical port name identifiers.

[0041] Specifically, each independent pair of modules is traversed. First, all port information on the boundary of the parent module's design diagram and all port information on the boundary of one or more corresponding sub-modules' design diagrams within the group are read, forming two lists of ports to be matched. Then, name comparison is performed within the group, verifying each port name in the parent module's port list against the port names in the sub-module's port list. If a port name in the parent module is found to be identical to a port name in the sub-module, a connection is determined, and this pair of ports is marked as a port group with the same name. Through this group-by-group scanning and name matching method, the originally isolated parent-child module interfaces are transformed into signal pairs with clear correspondences, thus constructing a logical connection from the parent module boundary to the sub-module boundary at the data level, completing the initial mapping of signal paths between layers.

[0042] In step S4, based on all the same-named port groups, the signal connection relationship between the clock design diagrams of each logic submodule is established, and a logic connectivity view is generated.

[0043] In this context, a logical connectivity view refers to a visual or data-structured representation of the system topology that integrates disparate logical submodule clock design diagrams into a unified whole through explicit connections. The logical connectivity view visually presents the signal flow, connection paths, and inter-level interactions between modules, reflecting the complete electrical connection network within the system.

[0044] Specifically, it iterates through all generated port groups with the same name, and for each group containing parent and child module ports, creates a unidirectional signal connection line in the data structure. This connection line is logically equivalent to a wire, directly connecting a specific port on the boundary of the parent module design diagram to the corresponding port on the boundary of the child module design diagram. As the traversal progresses, all port groups with the same name are transformed into concrete connection segments, coupling the originally independent parent and child modules together. Once the connection mapping of port groups with the same name in all module dependencies is completed, a global network diagram covering the entire architecture is formed, i.e., a logical connectivity view.

[0045] Reference Figure 3 , Figure 3 This is a connectivity diagram of the logical connectivity view provided in the embodiments of this application. Figure 3 Showing Figure 2 An example view of the logical connectivity view built for module-level data shows the actual signal interaction between the four core logic modules: TOP_CLK_CRG, AONSYS_TOP_TOP_rstgen, BLOCK001, and BLOCK002.

[0046] More specifically, to automate and visualize the signal connections between modules and improve the readability of complex system views, this application embodiment also proposes that the step of establishing the signal connection relationship between the clock design diagrams of each logical submodule based on all the same-named port groups and generating a logical connectivity view includes: The level corresponding to the clock design diagram of each logic submodule is determined according to the module level data. Based on the level corresponding to the clock design diagram of each logic submodule and the preset level order, non-overlapping arrangement coordinates are assigned to the clock design diagram of each logic submodule to complete the arrangement of the clock design diagram of each logic submodule. Traverse each of the aforementioned port groups with the same name to identify the source logic submodule clock design diagram and the target logic submodule clock design diagram that have signal connection relationships; Based on the output port coordinates of the source logic submodule clock design diagram and the input port coordinates of the target logic submodule clock design diagram, a layered connection line is planned in the vertical direction to avoid obstacles. The clock design diagrams of each logic submodule after the arrangement are integrated with the connection line to obtain the logic connectivity view.

[0047] The preset hierarchy order refers to the arrangement rules of modules on the canvas as defined by the system. It is usually based on the hierarchy depth or functional category of the modules, and specifies their distribution order in the vertical or horizontal direction (e.g., from left to right, from high level to low level) to ensure the clarity of the view structure.

[0048] Specifically, the process begins by reading the module hierarchy data to determine the level to which each logic submodule's clock design belongs. Based on a preset hierarchy order, independent, non-overlapping coordinates are assigned to each module on the canvas, completing the spatial arrangement of all modules and ensuring that higher-level and lower-level modules are visually layered. Next, all port groups with the same name are traversed, signal flow is analyzed, and the source logic submodule clock design and its output ports, as well as the target logic submodule clock design and its input ports, are identified for each group of signals. Subsequently, the specific coordinates of the source and target ports are obtained, and the routing algorithm is initiated to plan the connection lines in the vertical direction.

[0049] This algorithm forces interconnections to avoid overlapping modules at different levels, meaning the interconnections bypass other module physical areas in the vertical space, connecting the source and target only through blank areas or dedicated channels. Finally, the planned interconnections are integrated with the clock design diagram of the arranged logic submodules to form a logical connectivity view that includes the complete module layout and signal topology, making the signal paths clearly visible and allowing designers to intuitively trace the transmission paths of signals across modules.

[0050] In step S5, the element layout data corresponding to the clock design diagram of each logic submodule is obtained, and the elements of the clock design diagram of each logic submodule are mapped to the logical connectivity view according to the element layout data to obtain the clock system flattened view.

[0051] Among them, primitive layout data refers to structured information describing the position coordinates, geometry, pin orientation, and interconnection relationships of basic circuit units (such as AND gates, OR gates, multiplexers, PLLs, etc.) inside the logic module in a two-dimensional plane.

[0052] Specifically, firstly, the primitive layout data corresponding to the clock design diagram of each logical submodule is read, and the absolute position coordinates and orientation of each module instance in the global coordinate system are parsed out. Then, based on the logically connected view, the nodes representing modules in the view are replaced with primitives of actual size and shape, and these primitives are placed at designated positions on the global canvas according to the parsed coordinate data. Through this mapping process, modules that were originally contained or hidden within each other in the hierarchical structure are extracted and tiled on the same two-dimensional plane to form a clock unfolded view.

[0053] More specifically, in order to achieve automated restoration and high-fidelity display of the internal circuit structure of the module, this application embodiment also proposes that, in the step of mapping the elements of the clock design diagram of each logic submodule to the logical connectivity view according to the element layout data, the element mapping method for a single logic submodule clock design diagram includes: The corresponding graphic element layout data is parsed to obtain several graphic elements, the relative position information between each graphic element, and the signal connection relationship between each graphic element; Based on all the placement information, the element placement is performed within the clock design diagram of the corresponding logical submodule in the logical connectivity view; In response to the completion of placement of all said elements, wiring is performed on all elements based on the signal connection relationships between each said element to complete the element mapping of the clock design diagram of a single logic submodule.

[0054] Primitive mapping refers to the process of transforming abstract logical module nodes into detailed graphical representations that include specific internal circuit structures and connection relationships.

[0055] Specifically, firstly, the element layout data corresponding to the clock design diagram of the logic submodule is read and parsed to extract a list of all basic elements constituting the module (such as AND gates, NOR gates, multiplexers, etc.). Simultaneously, the specific placement information of each element and the signal connection relationship netlist between element ports are obtained. Next, the area occupied by the clock design diagram of the logic submodule is locked in the logic connectivity view. Based on the extracted placement information, all basic elements are placed one by one at their corresponding coordinate positions within this area. At this point, no electrical connection has been established between the elements; they are only spatially discretely distributed.

[0056] Finally, after all primitives have been spatially positioned, the previously extracted signal connections are traversed, and connecting lines are designed in the view to physically connect the ports of primitives with signal interaction relationships. This process ensures that not only is the circuit topology restored within the module, but the internal routing also remains consistent with the original layout data, thus completing a full mapping from abstract module nodes to detailed internal structures.

[0057] For ease of explanation, refer to Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 , Figure 4 This is a schematic diagram of the clock design diagram (TOP_CLK_CRG) of the first logic submodule provided in the embodiments of this application; Figure 5 This is a schematic diagram of the clock design diagram (AONSYS_TOP_TOP_rstgen) for the second logic submodule provided in this application embodiment; Figure 6 This is a schematic diagram of the clock design diagram (BLOCK001) of the third logic submodule provided in the embodiments of this application; Figure 7 This is a schematic diagram of the clock design diagram (BLOCK002) of the fourth logic submodule provided in the embodiments of this application; Figure 8 This is a schematic diagram of the clock design diagram (BLOCK001_CLK_CRG) of the fifth logic submodule provided in the embodiments of this application; Figure 9 This is a schematic diagram of the clock design diagram (BLOCK002_CLK_CRG) of the sixth logic submodule provided in the embodiments of this application; As can be seen, the primitive layout data of the four main modules TOP_CLK_CRG, AONSYS_TOP_TOP_rstgen, BLOCK001, and BLOCK002 are read first (corresponding to...). Figure 4 , Figure 5 , Figure 6 and Figure 7This process retrieves the overall shape of each module, the location of its external ports, and the spatial arrangement of its main internal sub-modules (such as u_gclk_0_div, u_AND2_cell, etc.). Next, it further reads the refined primitive layout data of BLOCK001_CLK_CRG and BLOCK002_CLK_CRG (corresponding to...). Figure 8 and Figure 9 These data reveal the deeper clock control logic inside BLOCK001 and BLOCK002, including the location and connection relationships of specific elements such as PLL units, enable gating, and reset synchronizers.

[0058] Subsequently, all the primitives of these six modules are mapped onto the same global canvas based on their respective local coordinates through coordinate transformation, keeping their relative positions unchanged. At the same time, based on the logical connectivity established in the previous step, cross-module signal connection lines are automatically designed.

[0059] Reference Figure 10 , Figure 10 This is an integrated schematic diagram of the clock system flattened view provided in the embodiments of this application, combined with Figure 10 As can be seen, the final clock flattened view not only shows the macroscopic connection between the four main modules, but also shows the layout and interconnection of the microscopic elements inside each module, forming a complete, continuous, and hierarchical clock network topology from the top-level interface to the bottom-level gate unit.

[0060] Furthermore, to ensure the sequential generation and coordinate consistency of views under the nested structure, this application embodiment also proposes that the step of mapping the elements of the clock design diagram of each logical submodule to the logically connected view according to the element layout data includes: Based on the module hierarchy data, the hierarchical order of the clock design diagrams of each logic submodule is determined, and the clock design diagram of the logic submodule with the lowest hierarchy is selected as the current module to be processed. Perform the primitive mapping operation of the current module to be processed, and after all the clock design diagrams of the logic sub-modules at the current level have completed primitive mapping, update the clock design diagram of the logic sub-module at the next higher level in the hierarchical order to the current module to be processed. Repeat the primitive mapping operation and module update steps until the top-level logic submodule clock design diagram completes the primitive mapping and obtains the flattened view of the clock system.

[0061] Specifically, the module hierarchy data is first parsed to determine the hierarchical order of the clock design diagrams for each logic submodule, and the lowest-level logic submodule clock design diagram is selected as the current module to be processed. A primitive mapping operation is performed on the current module, placing its internal primitives in the view according to the layout data. Once all logic submodule clock design diagrams at the current level have completed primitive mapping, the clock design diagram of the next higher-level logic submodule in the hierarchy is updated to reflect the current module. This primitive mapping operation and module update step is repeated until the top-level logic submodule clock design diagram completes its primitive mapping. During this process, lower-level modules form defined spatial positions after mapping, and the mapping operations of higher-level modules are based on these defined positions for primitive placement and signal connections.

[0062] The bottom-up processing sequence ensures that when processing the parent module, the primitive positions and port coordinates of the child module are already determined. The signal connection lines of the parent module can be directly anchored to the specific ports of the child module, avoiding coordinate conflicts or connection errors. Step-by-step iteration reduces the amount of data processed per cycle and supports the complete expansion of multi-level nested structures.

[0063] Furthermore, to ensure the consistency and accuracy of the design state, this application proposes a bidirectional synchronous interconnection mechanism, enabling designers to quickly adjust the layout and automatically solidify it to the data layer through intuitive graphical drag-and-drop, and also to instantly verify the effect in the view through precise editing of the underlying data. Specifically, after obtaining the flattened view of the clock system, the method further includes: Monitor the first update operation for the clock design diagram or signal connection relationship of any logic submodule in the clock system unfolded view, and in response to the first update operation, synchronously update the corresponding hierarchical structure or port connection information in the module hierarchical data. Monitor the second update operation for any level structure or port connection information in the module-level data, and in response to the second update operation, synchronously update the clock design diagram layout or signal connection relationship of the corresponding logic submodule in the clock system flattened view.

[0064] Specifically, a two-way real-time synchronization mechanism was established between the visual view and the underlying data. On the one hand, the first update operation for the clock flattened view is continuously monitored. When it is detected that the user has modified the arrangement of the clock design diagram of any logic submodule or adjusted the signal connection relationship, the graphic change is immediately parsed, converted into the corresponding data structure change instruction, and the corresponding hierarchical structure parameters or port connection information in the module-level data are updated synchronously to ensure that the underlying data reflects the latest visual state.

[0065] On the other hand, it also monitors the second update operation for module-level data. When it detects that the user has directly modified the underlying hierarchical structure or port connection information, it triggers the view redraw engine to recalculate the layout coordinates of the clock design diagram of the affected logic submodule or replan the signal connection lines based on the updated data, and refreshes the clock flattening view in real time to ensure that the visual presentation is consistent with the underlying data.

[0066] Furthermore, after the step of obtaining the flattened view of the clock system, the method further includes: Configure a flattening switch for each of the logic submodule clock design diagrams, wherein the flattening switch is used to control the corresponding logic submodule clock design diagram to switch between a flattened state and a collapsed state; In response to the triggering operation of the flattening switch for any of the aforementioned logic submodule clock design diagrams, if the current state is collapsed, the corresponding logic submodule clock design diagram is switched to the flattened state, and the submodules and internal connections contained within the corresponding logic submodule clock design diagram are parsed and displayed. If the current state is flat, the clock design diagram of the corresponding logic submodule will be switched to the collapsed state, hiding the submodules and internal connections contained in the clock design diagram of the corresponding logic submodule.

[0067] Specifically, firstly, an independent flattening switch is bound to the clock design diagram of each logical submodule in the clock flattening view. When a trigger operation for a certain flattening switch is detected, the current display state of the clock design diagram of that logical submodule is immediately read. If it is currently in the collapsed state, the unfolding logic is executed: the data parsing interface is called to extract the submodule definitions and internal connection relationships stored inside the clock design diagram of that logical submodule, these sub-elements are dynamically instantiated and designed in the coordinate area of ​​the current module, and the connection visualization between the submodule and the external port is established, thereby switching the module to the flattened state.

[0068] Conversely, if the current state is flattened, the collapse logic is executed: rendering of all submodule elements and internal connecting lines within the clock design diagram of this logic submodule is stopped, only the outer border and port information of the module are retained, the internal display resources are released, and the module is switched to the collapsed state. This process is real-time responsive, allowing users to flexibly control the information density of the view without changing the underlying data structure.

[0069] Reference Figure 11 , Figure 11 This is a virtual structural diagram of the clock system multi-logic module flattening device provided in this application. A second aspect of this application provides a clock system multi-logic module flattening device, comprising: The information acquisition module 100 is used to acquire the clock design diagram of each logic submodule and the port information corresponding to the clock design diagram of each logic submodule. The hierarchical parsing module 200 is used to parse the preset module hierarchical data, obtain the hierarchical association of the clock design diagrams of each logical submodule, and integrate all the clock design diagrams of logical submodules with hierarchical associations to obtain multiple sets of module subordinate pairs; each set of module subordinate pairs includes a parent module design diagram and at least one submodule design diagram corresponding to the parent module design diagram; Subordinate construction module 300 is used to extract the port information of the parent module design diagram and the corresponding child module design diagram for each group of module subordinate pairs, and match them to obtain the same-name port group of the module subordinate pairs; The logical connectivity module 400 is used to establish the signal connection relationship between the clock design diagrams of each logical submodule based on all the port groups with the same name, and generate a logical connectivity view; The system flattening module 500 is used to obtain the element layout data corresponding to the clock design diagram of each logic submodule, and to map the elements of the clock design diagram of each logic submodule to the logical connectivity view according to the element layout data to obtain the clock system flattening view.

[0070] The clock system multi-logic module flattening device described in this application embodiment can execute the clock system multi-logic module flattening method provided in the above embodiments. The clock system multi-logic module flattening device has the corresponding functional steps and beneficial effects of the clock system multi-logic module flattening method described in the above embodiments. For details, please refer to the embodiments of the clock system multi-logic module flattening method described above. The embodiments of this application will not be repeated here.

[0071] This application also provides an electronic device, please refer to... Figure 12 , Figure 12This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device may include a processor and a memory, which can be connected via a bus or other means. The processor may be a Central Processing Unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips. The memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the clock system multi-logic module flattening method in the embodiments of this application. The processor executes various functional applications and data processing by running the non-transitory software programs, instructions, and modules stored in the memory, thereby implementing the clock system multi-logic module flattening method in the above method embodiments.

[0072] The memory may include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a function; the data storage area may store data created by the processor, etc. Furthermore, the memory may include high-speed random access memory and non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. The one or more modules are stored in the memory and, when executed by the processor, perform the clock system multi-logic module flattening method as described in the above method embodiments. Specific details of the above electronic device can be understood by referring to the corresponding descriptions and effects in the above method embodiments, and will not be repeated here. Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it may include the processes of the embodiments of the above methods. The storage medium may be a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD), etc.; the storage medium may also include a combination of the above types of memory.

[0073] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0074] Similarly, it should be understood that, in order to streamline this disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of this application, various features of this application are sometimes grouped together in a single embodiment, figure, or description thereof. However, this approach to disclosure should not be construed as reflecting an intention that the claimed application requires more features than expressly recited in each claim. Rather, as reflected in the claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0075] It should be noted that the above embodiments are illustrative of this application and not restrictive of this application, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.

Claims

1. A method for flattening multiple logic modules in a clock system, characterized in that, The method includes: Obtain the clock design diagram of each logic submodule and the port information corresponding to the clock design diagram of each logic submodule; Parse the preset module hierarchy data to obtain the hierarchical association of the clock design diagrams of each logical submodule, and integrate all the clock design diagrams of logical submodules with hierarchical associations to obtain multiple sets of module subordinate pairs; each set of module subordinate pairs includes a parent module design diagram and at least one submodule design diagram corresponding to the parent module design diagram; For each group of module dependent pairs, extract the port information of the parent module design diagram and the corresponding child module design diagram, and match them to obtain the same-name port group of the module dependent pair; Based on all the port groups with the same name, establish the signal connection relationship between the clock design diagrams of each logic submodule and generate a logic connectivity view; Obtain the element layout data corresponding to the clock design diagram of each logic submodule, and map the elements of the clock design diagram of each logic submodule to the logical connectivity view according to the element layout data to obtain the clock system flattened view.

2. The method for flattening multiple logic modules in a clock system according to claim 1, characterized in that, In the step of mapping the elements of each logic submodule clock design diagram to the logical connectivity view based on the element layout data, the element mapping method for a single logic submodule clock design diagram includes: The corresponding graphic element layout data is parsed to obtain several graphic elements, the relative position information between each graphic element, and the signal connection relationship between each graphic element; Based on all the placement information, the element placement is performed within the clock design diagram of the corresponding logical submodule in the logical connectivity view; In response to the completion of placement of all said elements, wiring is performed on all elements based on the signal connection relationships between each said element to complete the element mapping of the clock design diagram of a single logic submodule.

3. The method for flattening multiple logic modules in a clock system according to claim 1, characterized in that, The step of mapping the elements of each logic submodule clock design diagram to the logical connectivity view based on the element layout data includes: Based on the module hierarchy data, the hierarchical order of the clock design diagrams of each logic submodule is determined, and the clock design diagram of the logic submodule with the lowest hierarchy is selected as the current module to be processed. Perform the primitive mapping operation of the current module to be processed, and after all the clock design diagrams of the logic sub-modules at the current level have completed primitive mapping, update the clock design diagram of the logic sub-module at the next higher level in the hierarchical order to the current module to be processed; Repeat the primitive mapping operation and module update steps until the clock design diagram of the top-level logic submodule is completed and the clock system unfolded view is obtained.

4. The method for flattening multiple logic modules in a clock system according to claim 1, characterized in that, The step of establishing the signal connection relationship between the clock design diagrams of each logic submodule based on all the port groups with the same name, and generating a logical connectivity view includes: The level corresponding to the clock design diagram of each logic submodule is determined according to the module level data. Based on the level corresponding to the clock design diagram of each logic submodule and the preset level order, non-overlapping arrangement coordinates are assigned to the clock design diagram of each logic submodule to complete the arrangement of the clock design diagram of each logic submodule. Traverse each of the aforementioned port groups with the same name to identify the source logic submodule clock design diagram and the target logic submodule clock design diagram that have signal connection relationships; Based on the output port coordinates of the source logic submodule clock design diagram and the input port coordinates of the target logic submodule clock design diagram, a layered connection line is planned in the vertical direction to avoid obstacles. The clock design diagrams of each logic submodule after the arrangement are integrated with the connection line to obtain the logic connectivity view.

5. The method for flattening multiple logic modules in a clock system according to claim 1, characterized in that, The step of parsing the preset module hierarchy data to obtain the hierarchical association of the clock design diagrams of each logic submodule includes: Read the module hierarchy data and identify the clock design diagram of the top-level logic submodule as the current decomposition object; The submodule information contained in the current decomposition object is parsed, the submodule information is mapped to the clock design diagram of the next level logical submodule, and a hierarchical association is established between the current decomposition object and the clock design diagram of each of the next level logical submodules. The clock design diagrams of each of the next-level logical submodules are updated sequentially to the current decomposition object. The parsing and association establishment steps are repeated until the clock design diagrams of all levels are decomposed, and the hierarchical association of the clock design diagrams of each logical submodule is obtained.

6. The method for flattening multiple logic modules in a clock system according to claim 1, characterized in that, After obtaining the flattened view of the clock system, the method further includes: Monitor the first update operation for the clock design diagram or signal connection relationship of any logic submodule in the clock system unfolded view, and in response to the first update operation, synchronously update the corresponding hierarchical structure or port connection information in the module hierarchical data. Monitor the second update operation for any level structure or port connection information in the module-level data, and in response to the second update operation, synchronously update the clock design diagram layout or signal connection relationship of the corresponding logic submodule in the clock system flattened view.

7. The method for flattening multiple logic modules in a clock system according to claim 1, characterized in that, After obtaining the flattened view of the clock system, the method further includes: Configure a flattening switch for each of the logic submodule clock design diagrams, wherein the flattening switch is used to control the corresponding logic submodule clock design diagram to switch between a flattened state and a collapsed state; In response to the triggering operation of the flattening switch for any of the aforementioned logic submodule clock design diagrams, if the current state is collapsed, the corresponding logic submodule clock design diagram is switched to the flattened state, and the submodules and internal connections contained within the corresponding logic submodule clock design diagram are parsed and displayed. If the current state is flat, the clock design diagram of the corresponding logic submodule will be switched to the collapsed state, hiding the submodules and internal connections contained in the clock design diagram of the corresponding logic submodule.

8. A multi-logic module flattening device for a clock system, characterized in that, include: The information acquisition module is used to acquire the clock design diagram of each logic submodule and the port information corresponding to the clock design diagram of each logic submodule. The hierarchical parsing module is used to parse the preset module hierarchical data, obtain the hierarchical association of the clock design diagrams of each logical submodule, and integrate all the logical submodule clock design diagrams with hierarchical associations to obtain multiple sets of module subordinate pairs; each set of module subordinate pairs includes a parent module design diagram and at least one submodule design diagram corresponding to the parent module design diagram; The subordinate construction module is used to extract the port information of the parent module design diagram and the corresponding child module design diagram for each group of the module subordinate pairs, and match them to obtain the port group with the same name of the module subordinate pairs; The logical connectivity module is used to establish the signal connection relationship between the clock design diagrams of each logical submodule based on all the port groups with the same name, and generate a logical connectivity view; The system flattening module is used to obtain the element layout data corresponding to the clock design diagram of each logic submodule, and map the elements of the clock design diagram of each logic submodule to the logical connectivity view according to the element layout data to obtain the clock system flattening view.

9. An electronic device, characterized in that, include: One or more processors; One or more memory units; And one or more computer programs, wherein the one or more computer programs are stored in the one or more memories, the one or more computer programs including instructions that, when executed by the one or more processors, cause the electronic device to perform the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The storage medium stores a program or instructions that, when executed, implement the method as described in any one of claims 1 to 7.

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