Machine learning collaborative calibration system and method for clock phase of multi-channel sd card

Abstract

The application belongs to the technical field of integrated circuit testing, and specifically discloses a machine learning collaborative calibration system and method for clock phase of a multi-channel SD card, which comprises: a feature management module, which is used for calculating a feature vector based on real-time channel data and writing the feature vector into an inference engine hardware module; the inference engine hardware module is used for outputting a predicted clock phase and a confidence degree based on the feature vector written in real time, and transmitting the prediction result to an intelligent decision module; wherein, in a software development environment, a light machine learning model is trained using historical calibration data, and the pre-trained machine learning model is automatically converted into an RTL code by using an HLS tool to generate a customized inference engine hardware module; the intelligent decision module is used for generating a phase delay configuration instruction of a target channel based on the clock phase prediction value; and the application realizes hardware inference with nanosecond-level and deterministic delay with minimum resource consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and in particular to a machine learning collaborative calibration system and method for the clock phase of a multi-channel SD card. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] As the speed of SD cards (Secure Digital Storage Cards) increases, in order to improve the theoretical speed on a limited number of pins, the UHS-I mode pushes the clock frequency very high (208MHz), resulting in the transmission time window (i.e., the data valid window) for each data bit being compressed to only about 2.4 nanoseconds (ns).

[0004] To ensure accurate data sampling, the host controller needs to dynamically adjust the sampling clock phase. The sampling clock phase refers to the time offset (delay) of the sampling clock relative to the data signal emitted by the SD card; dynamically adjusting the sampling clock phase means dynamically moving the position of the sampling clock edge so that it falls in the center of the valid data window (2.4ns).

[0005] In existing technologies, clock phase adjustment often employs direct clock signal adjustment schemes based on phase-locked loops (PLLs) or mixed-mode clock managers (MMCMs). For example, existing technologies disclose the use of a variable-phase PLL within an FPGA to adjust the sampling clock phase in fixed steps (e.g., 1 / 32 of a clock cycle). This method is highly efficient in single-channel (point-to-point) scenarios, but a single PLL phase can only generate one delay value, while multi-channel systems require multiple independent delay values ​​that can be optimized in real time. Therefore, this method is not suitable for multi-channel test systems.

[0006] While existing technologies disclose a dynamic phase adjustment method based on IDELAYE2 for each channel during multi-channel SD card clock phase collaborative calibration, allowing each data channel to have an independent and dynamically adjustable delay line, this method requires 32 read / write CMD19 operations for each channel to verify the tuning pattern, which takes a lot of time. Summary of the Invention

[0007] To address the aforementioned issues, this invention proposes a machine learning collaborative calibration system and method for multi-channel SD card clock phase. This system efficiently and cost-effectively integrates a machine learning prediction engine into a multi-channel test system based on an FPGA, achieving optimal resource utilization and calibration speed while ensuring high accuracy and adaptability.

[0008] In some implementations, the following technical solutions are adopted: A machine learning-based collaborative calibration system for the clock phase of a multi-channel SD card includes: The feature management module is used to calculate feature vectors based on real-time channel data and write them into the inference engine hardware module; The inference engine hardware module is used to output predicted clock phase and confidence based on real-time written feature vectors and transmit the prediction results to the intelligent decision module. In the software development environment, a lightweight machine learning model is trained using historical calibration data, and the pre-trained machine learning model is automatically converted into RTL code using the HLS tool to generate a customized inference engine hardware module. The intelligent decision-making module is used to generate phase delay configuration instructions for the target channel based on the clock phase prediction value; The phase execution module is used to generate a new clock phase delay value based on the phase delay configuration command, so as to lock the sampling clock phase of the SD card data input path at the predicted optimal position; and to calibrate the new clock phase delay value after the phase configuration is completed.

[0009] As a further approach, when using HLS tools to automatically convert pre-trained machine learning models into RTL code, the following design constraints are included: Expand the prediction loop to achieve single-cycle or pipeline prediction; The weights and threshold parameters of the machine learning model are stored in the memory blocks inside the FPGA chip. Define the feature vector input interface and clock phase output interface of the machine learning model as a stream interface or register interface of type ap_uint<bit width> to interface with surrounding logic.

[0010] As a further solution, a customized inference engine hardware module is generated, specifically: The RTL code output by the HLS tool is encapsulated into an IP core format recognizable by Vivado and added to the Vivado project in the main project.

[0011] As a further embodiment, the input interface of the inference engine hardware module is hardwired to the output interface of the feature management module; the output interface of the inference engine hardware module is hardwired to the input interface of the intelligent decision-making module.

[0012] As a further solution, the feature management module calculates feature vectors based on real-time channel data. The feature vectors include: channel temperature sensor readings, current I / O supply voltage, hash value of channel physical number, phase value of the last successful calibration of the channel, and timestamp since the last calibration.

[0013] As a further solution, the intelligent decision-making module generates phase delay configuration instructions for the target channel based on the clock phase prediction value, specifically as follows: The intelligent decision-making module receives the predicted phase value and confidence level output by the inference engine hardware module, and determines whether the predicted phase value is reliable based on the confidence level. If reliable, the predicted phase value is sent to the phase execution module; the phase execution module calculates the corresponding IDELAYE2 configuration parameters and verifies them based on the predicted phase value using a preset IDELAYE2 tap value-delay time mapping table; according to the address of the target channel and the verified IDELAYE2 configuration parameters, a specific register write command packet conforming to the FPGA configuration bus protocol is generated.

[0014] As a further step, after generating a specific register write command packet conforming to the FPGA configuration bus protocol, the following is also included: The command packet is sent to the corresponding control register of the IDELAYE2 module of the target channel through the configuration network inside the FPGA. After the sending is completed, the phase execution module triggers a loading signal to make the new clock phase delay value take effect immediately, so as to lock the sampling clock phase of the SD card data input path at the predicted optimal position. After the phase configuration is completed, the system sends the CMD19 command to the SD card again, uses the newly locked phase sampling tuning data block, and matches the received data with the standard pattern stored in the local matching unit; if the match is successful, the calibration is confirmed to be complete; if the match fails, the calibration is marked as abnormal and a recalibration or full scan rollback process is triggered.

[0015] As a further step, the machine learning model update process is triggered when any of the following conditions are met: Condition 1: The cumulative number of newly calibrated samples exceeds the preset number; Condition 2: There are more than N consecutive instances where the prediction confidence is high but the verification fails; Condition 3: The system has been running continuously for longer than the predetermined time.

[0016] In other embodiments, the following technical solutions are adopted: A machine learning-based collaborative calibration method for clock phase of multi-channel SD cards includes: In the software development environment, a lightweight machine learning model is trained using historical calibration data, and the pre-trained machine learning model is automatically converted into RTL code using the HLS tool to generate a customized inference engine hardware module. Feature vectors are calculated based on real-time channel data and written into the inference engine hardware module; The inference engine hardware module outputs predicted clock phase and confidence level based on the feature vectors written in real time; The phase delay configuration command for the target channel is generated based on the clock phase prediction value.

[0017] As a further embodiment, the feature vector includes: channel temperature sensor readings, current I / O supply voltage, hash value of channel physical number, phase value of the last successful calibration of the channel, and timestamp since the last calibration.

[0018] Compared with the prior art, the beneficial effects of the present invention are: (1) The customized inference engine implemented by the present invention through HLS completely eliminates the additional control overhead, bus interface and storage level required by general processors or dedicated AI acceleration cores. With minimal lookup table, register and on-chip memory resource consumption, it achieves hardware inference with nanosecond-level deterministic latency, which is unmatched by software or general IP solutions.

[0019] (2) The inference engine generated by this invention is a "bare metal" hardware module (i.e., a hardware module that does not run any operating system, does not embed any CPU soft core, does not use any software middleware, exists directly in the form of hardware logic gates, and is directly connected to the surrounding hardware modules through physical signal lines). It can be directly inserted into the control data stream of the central intelligent scheduler and interact directly with the state machine, feature extraction logic, etc. through hardware signals, eliminating the communication delay and scheduling uncertainty of system-level chips or soft core processors, and making the system more integrated.

[0020] (3) The HLS process of this invention allows engineers to perform collaborative optimization in multiple dimensions such as algorithm structure, data bit width, parallelism, and pipeline depth, and to tailor it to specific prediction models and FPGA platforms, thereby pursuing the optimal prediction speed and accuracy under given resource constraints.

[0021] Other features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the machine learning collaborative calibration system for multi-channel SD card clock phase in an embodiment of the present invention; Figure 2 This is a flowchart of the machine learning collaborative calibration method for the clock phase of a multi-channel SD card in an embodiment of the present invention. Detailed Implementation

[0023] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0024] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0025] Terminology Explanation: IDELAYE2: Dedicated hardware located near each I / O pin that can finely delay individual signals input to that pin.

[0026] CMD19 is a dedicated tuning command in the SD card protocol. Its core function is to allow the SD card to send a known, fixed data pattern (tuning pattern) to the host in high-speed mode. This enables the host to calibrate its data sampling points, ensuring accurate reading of subsequent high-speed data.

[0027] Verification Tuning Pattern: This refers to a known, fixed 64-byte data sequence used by the host to calibrate its own sampling clock during the initialization process of the SD card in high-speed mode (such as UHS-I SDR104).

[0028] HLS is an abbreviation for High-Level Synthesis; it is a technology that automatically converts algorithms described in high-level programming languages ​​(such as C / C++ / SystemC) into hardware description languages ​​(such as Verilog / VHDL).

[0029] Python is a high-level, interpreted, general-purpose programming language.

[0030] RTL stands for Register Transfer Level. In the fields of digital circuit design and FPGA development, RTL is a way to describe digital circuits using hardware description languages ​​(such as Verilog / VHDL).

[0031] Vivado: Xilinx's FPGA integrated development environment, used for hardware design, synthesis, placement and routing, and bitstream generation.

[0032] Scikit-learn: An open-source machine learning library in the Python ecosystem, with built-in algorithms such as decision trees and random forests, often used for training and validating small-scale models.

[0033] Xilinx Vitis HLS: High-Level Synthesis (HLS) toolchain, which can automatically convert C / C++ / OpenCL code into RTL hardware descriptions and ultimately map them onto FPGA logic resources.

[0034] Example 1 In one or more embodiments, a machine learning collaborative calibration system for the clock phase of a multi-channel SD card is disclosed. By using HLS technology, a trained lightweight machine learning model is directly compiled and synthesized into a registerable transport-level hardware description logic, forming a customized inference engine with equal status to other hardware modules in the system. This achieves nanosecond-level prediction latency and extremely low FPGA logic resource consumption, making it a calibration scheme that combines intelligence, real-time performance, and resource economy. It overcomes the problems of low efficiency, poor adaptability, and excessive hardware resource overhead when introducing intelligent algorithms in existing calibration methods.

[0035] The following section uses the Xilinx Vitis HLS toolchain to provide a detailed explanation of the specific implementation of the machine learning collaborative calibration system for the clock phase of a multi-channel SD card in this embodiment.

[0036] Combination Figure 1 The multi-channel SD card clock phase machine learning collaborative calibration system specifically includes: (1) Feature management module, used to calculate feature vectors based on real-time channel data and write them into the inference engine hardware module.

[0037] In this embodiment, the feature vector F consists of the following elements: channel temperature sensor reading T (16-bit quantization), current I / O supply voltage V (12-bit quantization), hash value ID of channel physical number (6 bits), phase value P_hist of the last successful calibration of the channel (7 bits), and timestamp Δt (16 bits) since the last calibration.

[0038] All of the above features have undergone normalization preprocessing before being input into the inference engine.

[0039] (2) The inference engine hardware module is used to output the predicted clock phase and confidence level based on the feature vector written in real time; and transmit the prediction results to the intelligent decision module. In the software development environment, a lightweight machine learning model is trained using historical calibration data, and the pre-trained machine learning model is automatically converted into RTL code using the HLS tool to generate a customized inference engine hardware module.

[0040] In this embodiment, the lightweight machine learning model can be a decision tree model or a small fully connected neural network, etc., to extract feature vectors from historical calibration data, construct a training dataset, and train the lightweight machine learning model.

[0041] Historical calibration data consists of a series of records showing "under what environmental conditions, and to what final value IDELAYE2 was adjusted." The environmental conditions refer to the input feature vector, and the final IDELAYE2 value is the output label to be learned. By learning from these historical records, the model can predict where to adjust IDELAYE2 based on the current environment.

[0042] As a concrete example, in Python, a lightweight gradient boosting tree model is trained using Scikit-learn. Dedicated tools like hls4ml are then used to convert the machine learning model parameters, originally described as floating-point numbers (e.g., 0.3125), into low-bit integers (e.g., 8-bit integers 40). This allows the model to run efficiently on an FPGA—integer operations are much faster than floating-point operations, require fewer hardware resources, consume less power, and suffer minimal loss in prediction accuracy. Thus, with almost no loss of algorithmic accuracy, a simple configuration file can convert a floating-point model into a low-bit-width integer model, achieving extreme computational speed and resource efficiency on an FPGA.

[0043] Import the converted model into HLS. The HLS tool will automatically generate highly optimized RTL code based on the model structure. Key design constraints include: ① Expand the prediction loop to achieve single-cycle or pipeline prediction.

[0044] In HLS (High-Level Synthesis) code, the reasoning logic of machine learning models is typically represented by a loop structure. For example, for a decision tree model, it is necessary to traverse every decision node of every tree; for a neural network, it is necessary to traverse every neuron of every layer.

[0045] The HLS tool copies the loop body N_NODES copies, each of which is executed independently. Comparisons of all nodes are completed in parallel within the same clock cycle, enabling the inference process to be completed within a single clock cycle or a very small number of pipeline stages.

[0046] ② Store the weights and threshold parameters of the machine learning model in the memory blocks inside the FPGA chip.

[0047] In HLS code, model weights, thresholds, and other constants are typically defined as arrays, which are mapped to the on-chip Block RAM of the FPGA, rather than being implemented using LUTs or distributed RAM.

[0048] FPGA's Base RAM (BRAM) is a hard-core module specifically designed for data storage, offering large capacity (up to 36Kb per block) and fast access speed (synchronized with the logic clock). Placing read-only weights / thresholds into the BRAM frees up valuable LUTs and FFs, allowing them to be used by control logic, state machines, and other components requiring greater flexibility. The read / write power consumption of BRAM is significantly lower than that of distributed RAM built with LUTs of the same capacity. In large-scale multi-channel systems, this helps control overall power consumption. BRAM has built-in address decoding and read / write control logic, seamlessly interfacing with the access interface generated by HLS, eliminating the need for additional complex memory management circuitry.

[0049] ③ Define the feature vector input interface and clock phase output interface of the machine learning model as a stream interface or register interface of type ap_uint<bit width> (an unsigned integer of arbitrary bit width) to interface with surrounding logic.

[0050] Add the inference engine .v module file output by the HLS tool to the Vivado project in the main project. Vivado is a Xilinx development tool that allows machine learning models to be added to Xilinx-based FPGAs. In the top-level design, directly instantiate this module and connect its input or output ports to the output interface of the feature management module and the input interface of the intelligent decision module via hardware wiring.

[0051] (3) Intelligent decision-making module, used to generate phase delay configuration instructions for the target channel based on the clock phase prediction value; (4) Phase execution module, which generates a new clock phase delay value based on the phase delay configuration instruction, so as to lock the sampling clock phase of the SD card data input path at the predicted optimal position; and calibrates the new clock phase delay value after the phase configuration is completed.

[0052] In this embodiment, each SD channel includes a local matching unit, an SD controller, a phase adjustment module containing IDELAYE2, and a channel real-time data collection module.

[0053] Specifically, the phase adjustment module including IDELAYE2 uses Xilinx's built-in IDELAYE2 primitives to configure the signal delay value by receiving the delay value input from the phase execution module, thus achieving the delay of the received signal. Each SD card channel is equipped with an SD controller, and each controller interacts with the SD card of the corresponding channel for command and data exchange. The local matching unit sends a CMD19 command to the SD card, uses the newly locked phase sampling tuning data block, and matches the received data with the standard pattern stored in the local matching unit; if the match is successful, the calibration is confirmed to be complete; if the match fails, the calibration is marked as abnormal, and a recalibration or full scan rollback process is triggered. The channel real-time data collection module collects channel temperature sensor readings, current I / O supply voltage, hash value of the channel physical number, and the phase value of the last successfully calibrated channel in real time, and transmits them to the feature management module.

[0054] The feature management module, inference engine hardware module, intelligent decision-making module, and phase execution module together constitute the central intelligent scheduler. In this embodiment, the feature management module obtains target channel information in real time, calculates feature vector F, and then writes the calculated feature vector F into the input register of the inference engine hardware module in the next clock cycle. The inference engine hardware module is a dedicated computing module formed by converting a lightweight machine learning model into hardware logic through the HLS tool.

[0055] After receiving the feature vector F, the inference engine hardware module starts the calculation. After a predetermined fixed number of clock cycles, it obtains the prediction results of the clock phase and confidence level, and stores the prediction results in the output register.

[0056] The intelligent decision-making module reads the prediction results from the output registers of the inference engine hardware module and generates instructions accordingly. The entire process is driven by a hardware state machine, without any software interrupts, thread scheduling, or bus transmission delays.

[0057] The core of the machine learning collaborative calibration system for multi-channel SD card clock phase in this embodiment lies in accurately and in real-time mapping the digital prediction values ​​output by the machine learning inference engine to the control of the physical delay unit (IDELAYE2). This process is completed by the phase execution module within the central intelligent scheduler, and the specific implementation process is as follows: S1. Predicted value reception and transformation: The intelligent decision-making module receives the predicted phase value P_pred (usually an integer, such as "19") and confidence level from the inference engine. The intelligent decision-making module determines the reliability of the predicted value based on the confidence level (e.g., a confidence level above 80% can be directly considered high confidence, indicating a reliable phase value). If reliable, the predicted phase value P_pred is sent to the phase execution module.

[0058] S2. Range Mapping and Verification: The phase execution module has a pre-defined mapping table of IDELAYE2 tap values ​​and delay times. The predicted phase value P_pred is compared with this mapping table to calculate the corresponding IDELAYE2 configuration parameters.

[0059] At the same time, boundary checks will be performed on the IDELAYE2 configuration parameters to ensure that they are within the valid configurable range of the IDELAYE2 unit (such as 0-31).

[0060] The predicted phase value P_pred is the phase number output by the machine learning inference engine. Its value range is consistent with the IDELAYE2 tap value, but there may be a fixed offset between the two caused by factors such as PCB trace differences and temperature drift. A preset mapping table within the phase execution module records the offset of each channel, used to convert P_pred into the actual physical tap value that should be written to the IDELAYE2 module configuration register. After boundary verification, the converted configuration parameters are written to the IDELAYE2 module of the target channel via the configuration bus, triggering a load signal to make the new delay value take effect immediately, thereby achieving precise adjustment of the sampling clock phase.

[0061] S3. Generate configuration command: The phase execution module generates a specific register write command packet that conforms to the FPGA configuration bus protocol based on the address of the target channel and the verified IDELAYE2 configuration parameters.

[0062] S4. Distribute configuration and lock phase: The command packet is sent to the corresponding control register (such as IDELAY_VALUE) of the IDELAYE2 module of the target channel through the configuration network inside the FPGA.

[0063] After the write operation is complete, the phase execution module triggers a load signal, making the new delay value take effect immediately. At this point, the sampling clock phase of the SD card data input path is locked at the predicted optimal position, and then the correctness of the downsampling at this phase point is verified by CMD19.

[0064] Specifically, after the phase configuration is complete, the system sends the CMD19 command to the SD card again, using the newly locked phase sampling tuning data block, and matches the received data with the standard pattern stored in the local matching unit. If the match is successful, the calibration is confirmed to be complete; if the match fails, the calibration is marked as abnormal, and a recalibration or full scan rollback process is triggered.

[0065] As a further implementation, the system triggers the model update process when any of the following conditions are met: Condition 1: The cumulative number of newly calibrated samples exceeds the preset number (e.g., 1000). Condition 2: There are more than N consecutive instances where the prediction confidence is high but the verification fails; N is a set value, such as N=5; Condition 3: The system has been running continuously for more than the predetermined time (e.g., 24 hours).

[0066] Compared to traditional static calibration methods (where the model's behavior remains fixed once deployed), this embodiment constructs an automatically triggered online learning loop based on the above conditions: the system continuously accumulates data, detects anomalies, and periodically refreshes the model during use, adapting to dynamic factors such as equipment aging, seasonal environmental changes, and batch differences without manual intervention, significantly improving the robustness of the calibration system throughout its entire lifecycle.

[0067] The system in this embodiment achieves extremely short and deterministic latency from intelligent prediction to physical adjustment. The entire process is completed by hardware logic, and the phase reconfiguration of a single channel can usually be completed within tens of clock cycles, realizing high-speed and accurate multi-channel collaborative calibration.

[0068] On a Xilinx Kintex-7 FPGA, implementing a gradient boosting model with 20 trees for 16-channel prediction, after HLS optimization, requires approximately: Logic units: Approximately 1200 LUTs; Storage unit: Approximately 10 Block RAM (36Kb); Operating latency: 15 clock cycles (150 nanoseconds at a 100MHz system clock); It can be seen that the resource consumption of the entire process is far less than that of a microprocessor soft core, and the latency is deterministic and knowable, perfectly meeting the real-time requirements of a high-speed testing system.

[0069] Example 2 In one or more embodiments, a machine learning-based collaborative calibration method for the clock phase of a multi-channel SD card is disclosed, combining... Figure 2 Specifically, it includes the following process: S101: In a software development environment, a lightweight machine learning model is trained using historical calibration data and then fixed-point quantization is performed. Fixed-point quantization refers to the engineering process of converting floating-point precision model parameters (weights, thresholds, etc.) trained in the Python environment into a low-precision representation of a specific number of points (such as 8-bit or 16-bit integers). This conversion is done automatically using specialized tools such as hls4ml.

[0070] Using the high-level synthesis tool HLS, pre-trained machine learning models are automatically converted into RTL code, generating customized inference engine hardware modules. The inference engine hardware module is used as a hardware IP and integrated with the central intelligent scheduler logic and channel control logic in the FPGA project.

[0071] S102: Calculate feature vectors based on real-time channel data and write them into the inference engine hardware module; During system operation, real-time feature vectors are sent to the inference engine through the hardware data path; The feature vector F includes the following elements: channel temperature sensor reading, current I / O supply voltage, hash value of channel physical number, phase value of the last successful calibration of the channel, and timestamp since the last calibration.

[0072] S103: The inference engine hardware module outputs predicted clock phase and confidence level based on the feature vectors written in real time; The inference engine hardware module outputs the predicted clock phase and confidence level within a very short and deterministic clock cycle based on the received feature vector.

[0073] S104: Generate phase delay configuration instruction for the target channel based on the clock phase prediction value.

[0074] Based on the prediction results, the subsequent simplified scan, physical delay mapping, result verification, and learning update process are executed.

[0075] It should be noted that the specific implementation methods of the above steps are exactly the same as those in Example 1, and will not be described in detail again.

[0076] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A machine learning-based collaborative calibration system for clock phase of a multi-channel SD card, characterized in that, include: The feature management module is used to calculate feature vectors based on real-time channel data and write them into the inference engine hardware module; The inference engine hardware module is used to output predicted clock phase and confidence based on real-time written feature vectors and transmit the prediction results to the intelligent decision module. In the software development environment, a lightweight machine learning model is trained using historical calibration data, and the pre-trained machine learning model is automatically converted into RTL code using the HLS tool to generate a customized inference engine hardware module. The intelligent decision-making module is used to generate phase delay configuration instructions for the target channel based on the clock phase prediction value; The phase execution module is used to generate a new clock phase delay value based on the phase delay configuration command, so as to lock the sampling clock phase of the SD card data input path at the predicted optimal position; and to calibrate the new clock phase delay value after the phase configuration is completed.

2. The machine learning collaborative calibration system for multi-channel SD card clock phase as described in claim 1, characterized in that, When using HLS tools to automatically convert pre-trained machine learning models into RTL code, the following design constraints apply: Expand the prediction loop to achieve single-cycle or pipeline prediction; The weights and threshold parameters of the machine learning model are stored in the memory blocks inside the FPGA chip. Define the feature vector input interface and clock phase output interface of the machine learning model as a stream interface or register interface of type ap_uint<bit width> to interface with surrounding logic.

3. The machine learning collaborative calibration system for multi-channel SD card clock phase as described in claim 1, characterized in that, Generate a customized inference engine hardware module, specifically: The RTL code output by the HLS tool is encapsulated into an IP core format recognizable by Vivado and added to the Vivado project in the main project.

4. The machine learning collaborative calibration system for multi-channel SD card clock phase as described in claim 1, characterized in that, The input interface of the inference engine hardware module is connected to the output interface of the feature management module via a hardwire; the output interface of the inference engine hardware module is connected to the input interface of the intelligent decision-making module via a hardwire.

5. The machine learning collaborative calibration system for multi-channel SD card clock phase as described in claim 1, characterized in that, The feature management module calculates feature vectors based on real-time channel data. The feature vectors include: channel temperature sensor readings, current I / O supply voltage, hash value of channel physical number, phase value of the last successful calibration of the channel, and timestamp since the last calibration.

6. The machine learning collaborative calibration system for multi-channel SD card clock phase as described in claim 1, characterized in that, The intelligent decision-making module generates phase delay configuration instructions for the target channel based on the clock phase prediction value, specifically: The intelligent decision-making module receives the predicted phase value and confidence level output by the inference engine hardware module, and determines whether the predicted phase value is reliable based on the confidence level. If reliable, the predicted phase value is sent to the phase execution module; the phase execution module calculates the corresponding IDELAYE2 configuration parameters and verifies them based on the predicted phase value using a preset IDELAYE2 tap value-delay time mapping table; according to the address of the target channel and the verified IDELAYE2 configuration parameters, a specific register write command packet conforming to the FPGA configuration bus protocol is generated.

7. The machine learning collaborative calibration system for multi-channel SD card clock phase as described in claim 6, characterized in that, After generating a specific register write command packet conforming to the FPGA configuration bus protocol, it also includes: The command packet is sent to the corresponding control register of the IDELAYE2 module of the target channel through the configuration network inside the FPGA. After the sending is completed, the phase execution module triggers a loading signal to make the new clock phase delay value take effect immediately, so as to lock the sampling clock phase of the SD card data input path at the predicted optimal position. After the phase configuration is completed, the system sends the CMD19 command to the SD card again, uses the newly locked phase sampling tuning data block, and matches the received data with the standard pattern stored in the local matching unit; if the match is successful, the calibration is confirmed to be complete; if the match fails, the calibration is marked as abnormal and a recalibration or full scan rollback process is triggered.

8. The machine learning collaborative calibration system for multi-channel SD card clock phase as described in claim 1, characterized in that, Also includes: The machine learning model update process is triggered when any of the following conditions are met: Condition 1: The cumulative number of newly calibrated samples exceeds the preset number; Condition 2: There are more than N consecutive instances where the prediction confidence is high but the verification fails; Condition 3: The system has been running continuously for longer than the predetermined time.

9. A machine learning-based collaborative calibration method for clock phase of a multi-channel SD card, characterized in that, include: In the software development environment, a lightweight machine learning model is trained using historical calibration data, and the pre-trained machine learning model is automatically converted into RTL code using the HLS tool to generate a customized inference engine hardware module. Feature vectors are calculated based on real-time channel data and written into the inference engine hardware module; The inference engine hardware module outputs predicted clock phase and confidence level based on the feature vectors written in real time; The phase delay configuration command for the target channel is generated based on the clock phase prediction value.

10. The machine learning collaborative calibration method for clock phase of a multi-channel SD card as described in claim 9, characterized in that, The feature vector includes: channel temperature sensor readings, current I / O supply voltage, hash value of channel physical number, phase value of the last successful calibration of the channel, and timestamp since the last calibration.

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