Parameterized canny edge detection accelerator based on spinalhdl and generation method

Abstract

The application provides a parameterized Canny edge detection accelerator based on SpinalHDL and a generation method, and belongs to the technical field of integrated circuit design and image processing. The application aims to solve the problems of poor design flexibility, low reuse rate and long iteration cycle of the existing Canny edge detection hardware accelerator. The accelerator comprises: a unified parameter configuration module for encapsulating configurable parameters; a plurality of configurable hardware module generators for dynamically generating submodules such as grayscale conversion, filtering and noise reduction, gradient extraction, non-maximum suppression and edge lag connection by using the SpinalHDL high-level language characteristics; a standard bus interface and top-level control logic; and a FIFO cache module integrated at the minimum data bit width. The agile generation method realizes rapid design space exploration through three steps of parameter definition, hardware automatic generation and verification exploration. The application can generate Canny accelerators with different performance points through parameterization configuration, significantly improves the design flexibility and reusability, shortens the development cycle, and greatly saves the storage resources.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design and image processing technology, and in particular to a parameterized Canny edge detection accelerator and generation method based on SpinalHDL. Background Technology

[0002] The Canny edge detection algorithm is widely recognized as one of the best edge detection algorithms due to its excellent noise resistance and high positioning accuracy, and is widely used in fields such as industrial inspection, autonomous driving, and medical imaging. However, the algorithm is complex and computationally intensive, making it difficult to meet the real-time processing requirements of high-resolution images on a CPU platform. Therefore, Field Programmable Gate Arrays (FPGAs) or Application-Specific Integrated Circuits (ASICs) are often used for hardware acceleration.

[0003] The existing Canny edge detection hardware accelerator design has the following main shortcomings: 1) Poor design flexibility: Most existing designs are implemented using traditional hardware description languages ​​such as Verilog / VHDL or high-level synthesis (HLS) tools, and their parameters (such as image size, filter kernel size, gradient operator type, etc.) are usually fixed during design. When the application scenario changes, a large amount of RTL code needs to be manually modified and resynthesized, resulting in long design iteration cycles and an inability to quickly adapt to diverse requirements.

[0004] 2) Low code reusability: Accelerator designs with different parameter configurations (such as Gaussian filters of different sizes and different types of gradient operators) often require writing independent hardware modules. The lack of a unified and reusable generation framework leads to a large workload in design and difficulty in maintenance.

[0005] 3) Difficulty in design space exploration: The Canny algorithm involves numerous parameters (such as the standard deviation of Gaussian filtering σ, dual thresholds, gradient operator selection, etc.), whose combinations constitute a huge design space. Existing research lacks an agile method that can systematically and quickly generate different configurations and evaluate their performance (resources, power consumption, frame rate).

[0006] Therefore, there is an urgent need for a Canny edge detection hardware accelerator design scheme that can be quickly configured, efficiently generated, and flexibly optimized. Summary of the Invention

[0007] The main objective of this invention is to propose a parameterized Canny edge detection accelerator, generation method, storage medium, and program product based on SpinalHDL, in order to solve the problems of poor design flexibility, low reusability, and long iteration cycle of existing Canny edge detection hardware accelerators, and to achieve a hardware accelerator design that can be quickly configured, efficiently generated, and with a performance trade-off.

[0008] To achieve the above objectives, one aspect of this invention proposes a parameterized Canny edge detection accelerator based on SpinalHDL, comprising: The unified parameter configuration module is constructed as the top-level configuration class of SpinalHDL, which is used to encapsulate and manage multiple configurable parameters of the accelerator. Multiple configurable hardware module generators utilize the high-level language features of SpinalHDL to dynamically generate hardware sub-modules with different structures and algorithms based on parameters in the unified parameter configuration module, and achieve standardized interface interconnection; the multiple configurable hardware module generators include at least: a configurable grayscale conversion module generator, a configurable filtering and noise reduction module generator, a configurable gradient extraction module generator, a configurable nonmaximum suppression module generator, and a configurable edge hysteresis connection module generator; The accelerator integrates a standard bus interface and top-level control logic, including an AXI-Lite slave interface and an AXI-Stream interface, as well as a state machine for coordinating data and control flows. The FIFO buffer module is integrated at the point where the data width of the accelerator pipeline is minimized, and is used to decouple the timing of input and output.

[0009] In some embodiments, the configurable parameters encapsulated by the unified parameter configuration module include one or more of the following: data bit width, maximum image size, grayscale conversion algorithm type, filtering and noise reduction algorithm type and parameters, gradient extraction operator type, non-maximum suppression window size, and edge hysteresis connection iteration number.

[0010] In some embodiments, the configurable grayscale conversion module generator selectively generates grayscale conversion hardware logic implemented using the mean method, weighted average method (YUV), or extreme value method according to configuration parameters. The configurable filtering and noise reduction module generator dynamically generates Gaussian filter kernel coefficients with different window sizes and standard deviations according to configuration parameters, and generates hardware calculation logic for Gaussian filtering, mean filtering, or median filtering; and supports cascading multiple small-sized Gaussian filters to achieve an equivalent large-sized Gaussian filtering effect. The configurable gradient extraction module generator selectively generates hardware logic for gradient calculation and direction quantization of Roberts operator, Prewitt operator, 3×3 Sobel operator or 5×5 Sobel operator according to configuration parameters. The configurable nonmaximum suppression module generator generates nonmaximum suppression hardware logic with an adjustable window size (N×N) according to configuration parameters; The configurable edge hysteresis connection module generator generates edge hysteresis connection hardware logic based on an iterative pipeline structure with a specified number of iterations according to configuration parameters.

[0011] In some embodiments, in the standard bus interface and top-level control logic, the AXI-Lite slave interface is used to communicate with an external CPU to receive configuration parameters, and the AXI-Stream interface is used for the input and output of high-speed image data streams.

[0012] In some embodiments, the FIFO cache module is integrated after the dual threshold and edge hysteresis connection module, wherein the data bit width is reduced to the bit width of the edge type code.

[0013] To achieve the above objectives, another aspect of this invention proposes an agile generation method for a parameterized Canny edge detection accelerator based on SpinalHDL, comprising the following steps: S1. Parameter definition: Define a top-level configuration class in the SpinalHDL environment, define all configurable parameters in the top-level configuration class, set default values ​​and perform validity checks; S2. Hardware Generation: The SpinalHDL compiler reads the parameters in the top-level configuration class and uses the advanced features of conditional and loop functions in the Scala language to selectively instantiate multiple hardware module generators to dynamically generate the corresponding Verilog RTL code; wherein the multiple hardware module generators include at least: a configurable grayscale conversion module generator, a configurable filtering and noise reduction module generator, a configurable gradient extraction module generator, a configurable nonmaximum suppression module generator, and a configurable edge hysteresis connection module generator; S3. Verification and Exploration: By modifying the parameters in the top-level configuration class, accelerator instances with different configurations can be quickly generated and synthesized and tested on the FPGA to evaluate their resource consumption, maximum operating frequency and image processing performance, thereby enabling rapid exploration of the design space.

[0014] In some embodiments, step S2 further includes: calculating integer Gaussian kernel coefficients on the computer side based on the configured Gaussian window size and Gaussian standard deviation during compilation by the SpinalHDL compiler.

[0015] In some embodiments, step S2 further includes: dynamically generating an edge hysteresis connection hardware module with N levels of iterative connections using a for loop based on the configured edge hysteresis connection iteration number N.

[0016] In some embodiments, the agile generation method further includes: automatically instantiating the FIFO buffer module at the point of minimum data width in the accelerator pipeline in the generated Verilog RTL code, so as to decouple the timing of input and output.

[0017] To achieve the above objectives, another aspect of the present invention proposes an electronic device including the parameterized Canny edge detection accelerator described above, or for implementing the agile generation method described above.

[0018] To achieve the above objectives, another aspect of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described above.

[0019] To achieve the above objectives, another aspect of the present invention provides a computer program product, including a computer program that, when executed by a processor, implements the method described above.

[0020] Compared with the prior art, the present invention has the following advantages and beneficial effects: 1) Extremely high design flexibility and reusability: Through a unified parameter configuration class, designers do not need to modify any hardware description code; they can generate Canny accelerators suitable for different scenarios (such as switching from high-precision, high-resource-consumption mode to low-precision, low-power mode) simply by changing parameters. Different algorithm options (such as various filtering and gradient operators) are encapsulated as generators, achieving a high degree of hardware module reusability.

[0021] 2) Significantly shortened development cycle: By utilizing the agile design method of SpinalHDL, the process of "parameter configuration - automatic hardware generation" is realized, avoiding the tedious manual RTL modification and debugging in traditional methods, greatly shortening the iteration cycle from algorithm to hardware, and supporting rapid design space exploration.

[0022] 3) Optimize hardware resource consumption: This invention innovatively places the FIFO cache at the point of minimum data width (edge ​​type code, only 1-2 bits), saving over 90% of storage resources compared to caching 24 bits of RGB image data at the input or output. Simultaneously, by parameterizing the iteration number of edge lag connections, unnecessary hardware overhead is avoided.

[0023] 4) Flexible trade-off between performance and resources: By adjusting parameters (such as data bit width, convolution kernel size, number of iterations, etc.), a flexible trade-off can be made between detection accuracy, processing speed (frame rate FPS) and hardware resources (lookup tables LUTs, block random access memory BRAM, digital signal processing units DSPs) to adapt to different application requirements from low-cost embedded systems to high-performance computing platforms. Attached Figure Description

[0024] Figure 1This is a schematic diagram of the top-level structure of the parameterized Canny edge detection accelerator in an embodiment of the present invention.

[0025] Figure 2 This is a flowchart of the agile generation method in an embodiment of the present invention.

[0026] Figure 3 This is a schematic diagram of the state control logic of the accelerator main body in an embodiment of the present invention.

[0027] Figure 4 This is a schematic diagram illustrating the configurable parameter selection in the parameterized Canny edge detection accelerator in this embodiment of the invention. Detailed Implementation

[0028] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0029] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0030] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0031] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0032] See Figure 1This embodiment provides a parameterized Canny edge detection accelerator based on SpinalHDL, including: a unified parameter configuration module, multiple configurable hardware module generators, a standard bus interface and top-level control logic, and a FIFO cache module, as detailed below: Unified Parameter Configuration Module: A top-level configuration class is built based on SpinalHDL classes to encapsulate and manage all configurable parameters of the accelerator. These configurable parameters include: data bit width, maximum image size, grayscale conversion algorithm type, filtering and denoising algorithm type and parameters, gradient extraction operator type, non-maximum suppression window size, and number of edge hysteresis connection iterations.

[0033] Multiple configurable hardware module generators: Utilizing the high-level language features of SpinalHDL (such as if-else conditional statements and for loops), these generators dynamically generate sub-modules with different structures and algorithms based on parameters in the unified parameter configuration module, and achieve standardized interface interconnection. The sub-modules include: 1) Configurable grayscale conversion module generator: Based on configuration parameters, it selectively generates hardware logic implemented using the mean method, weighted average method (YUV), or extreme value method.

[0034] 2) Configurable filter and noise reduction module generator: Dynamically generates modules with different window sizes (e.g., 3x3, 5x7, 7x7) and different standard deviations based on configuration parameters. It generates Gaussian filter kernel coefficients and generates hardware calculation logic for Gaussian filtering, mean filtering, or median filtering; it supports cascading multiple small-sized Gaussian filters to achieve an equivalent large-sized Gaussian filtering effect.

[0035] 3) Configurable gradient extraction module generator: Based on configuration parameters, selectively generate hardware logic for gradient calculation and direction quantization of Roberts operator, Prewitt operator, 3×3 Sobel operator or 5×5 Sobel operator.

[0036] 4) Configurable Nonmaximum Suppression Module Generator: Generates nonmaximum suppression hardware logic with an adjustable window size (N×N) based on configuration parameters.

[0037] 5) Configurable edge hysteresis connection module generator: Generates edge hysteresis connection hardware logic based on an iterative pipeline structure with a specified number of iterations according to configuration parameters.

[0038] Standard bus interface and top-level control logic: The accelerator integrates an AXI-Lite slave interface at the top level for communicating with an external CPU to receive configuration parameters; it also integrates an AXI-Stream interface for high-speed image data stream input and output. The top-level control logic implements a state machine to coordinate data flow and control flow.

[0039] FIFO buffer module: Integrated at the point of minimum data width in the accelerator pipeline (i.e., after the dual-threshold and edge-hysteresis connection module), it is used to decouple the timing of input and output. The data stored in this FIFO buffer module is edge-type code, with a bit width of only 1-2 bits.

[0040] like Figure 2 As shown, this embodiment also provides an agile generation method for the parameterized Canny edge detection accelerator described above, including the following steps: S1. Parameter definition: Define all configurable parameters in the top-level configuration class, set default values ​​and perform validity checks.

[0041] S2. Hardware Generation: The SpinalHDL compiler reads the parameters in the top-level configuration class and uses the advanced features of the Scala language, such as conditions and loops, to selectively instantiate the above hardware module generators and dynamically generate the corresponding Verilog RTL code.

[0042] In one embodiment, step S2 specifically includes the following steps: S21. Calculate the integerized Gaussian kernel coefficients at compile time (computer side) based on the configured Gaussian window size and Gaussian standard deviation. S22. Based on the configured number of edge hysteresis connection iterations N, dynamically generate an edge hysteresis connection hardware module with N levels of iterative connections using a for loop. S23. Automatically instantiate the FIFO cache module at the location with the smallest data width.

[0043] S3. Verification and Exploration: By modifying the parameters in the top-level configuration class, accelerator instances with different configurations can be quickly generated and synthesized and tested on the FPGA to evaluate their resource consumption, maximum operating frequency and image processing performance, thus enabling rapid exploration of the design space.

[0044] Below, in conjunction with Figure 3 , Figure 4 The present invention provides a detailed description and explanation of the embodiments of the invention, along with specific application examples.

[0045] Example 1 In this embodiment, a parameterized Canny edge detection accelerator based on SpinalHDL, as described in this embodiment of the invention, was implemented and verified based on the Xilinx Artix-7 series XC7A200T FPGA platform.

[0046] I. Parameter Configuration First, define a top-level configuration class in the SpinalHDL environment and set the following parameters: dataWidth: Int = 8 (data width) maxWidth: Int = 720, maxHeight: Int = 540 (maximum image size) grayType: String = "yuv" (YUV weighted grayscale conversion) filterType: String = "gaussian" (Gaussian filter) gaussianWindowSize: Int = 5, (Gaussian kernel size 5×5) GaussianSigma: Double = 1.0 (Gaussian filter standard deviation σ = 1.0) gaussianScaleBits: Int = 8 (Gaussian kernel scaling factor) edgeDetectorType: String = "3x3sobel" (3×3 Sobel gradient operator) hysteresisConnectorNum: Int = 50 (edge ​​connection iterations 50 times) II. Hardware Generation Run the SpinalHDL compiler. The compiler reads the above configuration and first calculates the integerized 5×5 Gaussian kernel coefficients at compile time (on the computer) based on the Gaussian window size and Gaussian standard deviation, for example: [[1, 3, 6, 3, 1], [3, 7, 11, 7, 3], [6, 11, 14, 11, 6], [3, 7, 11, 7, 3], [1, 3, 6, 3, 1]] Then, based on the configuration parameters, the YUV grayscale conversion module generator, the 5×5 Gaussian filter module, and the 3×3 Sobel gradient module are instantiated using Scala's if-else statements. Specifically, a for loop is used to dynamically generate an edge hysteresis connection module with 50 iterative connections based on hysteresisConnectorNum = 50. Finally, a complete Verilog RTL file optimized for the above configuration is automatically generated. This RTL file can be directly used in subsequent FPGA or ASIC implementation processes.

[0047] III. Results and Parameter Tuning After integration, the accelerator in this configuration occupies approximately 9.5% of the FPGA's LUTs, 2.3% of the registers, and 17.8% of the BRAM, and theoretically achieves a frame rate of 257 FPS for processing 720*540 images at a 100MHz system clock.

[0048] To explore higher performance, the configuration was modified to gaussianWindowSize = 3 and hysteresisConnectorNum = 10, and SpinalHDL was re-run to generate new hardware. After the new design was implemented on the FPGA, resource consumption was significantly reduced (LUTs decreased to approximately 3000), the maximum operating frequency increased to 162.5MHz, and the theoretical frame rate exceeded 400FPS, demonstrating the agility and flexibility of this invention.

[0049] Example 2 This embodiment is basically the same as Embodiment 1, except for the parameter configuration of the grayscale conversion module. Changing grayType to "mean" generates hardware logic for grayscale conversion using the mean method; changing grayType to "extremum" generates hardware logic for grayscale conversion using the extreme value method. Accelerators for different grayscale conversion algorithms can be obtained without modifying any other code.

[0050] Example 3 This embodiment is basically the same as Embodiment 1, except for the parameter configuration of the filtering and noise reduction module. Changing `filterType` to "median" generates median filtering hardware logic; changing `gaussianWindowSize` to 7 generates 7×7 Gaussian filtering hardware logic; and changing `gaussianSigma` to 1.5 generates 7×7 Gaussian filter kernel coefficients with a standard deviation of 1.5. Furthermore, by setting the `cascade` parameter, multiple 3×3 Gaussian filter modules can be cascaded to achieve an equivalent 5×5 or larger Gaussian filtering effect, thereby saving multiplier resources.

[0051] Example 4 This embodiment is basically the same as Embodiment 1, except for the parameter configuration of the gradient extraction module. Changing edgeDetectorType to "prewitt" generates the Prewitt operator gradient calculation logic; changing it to "roberts" generates the Roberts operator logic; changing it to "5x5sobel" generates the 5×5 Sobel operator logic.

[0052] Example 5 This embodiment is basically the same as Embodiment 1, except for the window size of the non-maximum suppression module. By modifying the nmsWindowSize parameter, non-maximum suppression logic with a 3×3, 5×5, or 7×7 window can be generated to adapt to edge detection requirements of different widths.

[0053] Example 6 This embodiment is essentially the same as Embodiment 1, except for the number of iterations in the edge hysteresis connection module. Based on the maximum edge length in the target image, hysteresisConnectorNum is set to 10, 20, 50, or 100. More iterations result in a more complete connection, but also increase hardware resources and latency. The parametric design of this invention simplifies this trade-off.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art can make some modifications or alterations to the disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the scope of the present invention.

Claims

1. A parameterized Canny edge detection accelerator based on SpinalHDL, characterized in that, include: The unified parameter configuration module is constructed as the top-level configuration class of SpinalHDL, which is used to encapsulate and manage multiple configurable parameters of the accelerator. Multiple configurable hardware module generators utilize the high-level language features of SpinalHDL to dynamically generate hardware sub-modules with different structures and algorithms based on parameters in the unified parameter configuration module, and achieve standardized interface interconnection; the multiple configurable hardware module generators include at least: a configurable grayscale conversion module generator, a configurable filtering and noise reduction module generator, a configurable gradient extraction module generator, a configurable nonmaximum suppression module generator, and a configurable edge hysteresis connection module generator; The accelerator integrates a standard bus interface and top-level control logic, including an AXI-Lite slave interface and an AXI-Stream interface, as well as a state machine for coordinating data and control flows. The FIFO buffer module is integrated at the point where the data width of the accelerator pipeline is minimized, and is used to decouple the timing of input and output.

2. The parameterized Canny edge detection accelerator according to claim 1, characterized in that, The configurable parameters encapsulated in the unified parameter configuration module include one or more of the following: data bit width, maximum image size, grayscale conversion algorithm type, filtering and noise reduction algorithm type and parameters, gradient extraction operator type, non-maximum suppression window size, and edge hysteresis connection iteration number.

3. The parameterized Canny edge detection accelerator according to claim 1, characterized in that, The configurable grayscale conversion module generator selectively generates grayscale conversion hardware logic implemented using the mean method, weighted average method, or extreme value method according to the configuration parameters. The configurable filtering and noise reduction module generator dynamically generates Gaussian filter kernel coefficients with different window sizes and standard deviations according to configuration parameters, and generates hardware calculation logic for Gaussian filtering, mean filtering, or median filtering; and supports cascading multiple small-sized Gaussian filters to achieve an equivalent large-sized Gaussian filtering effect. The configurable gradient extraction module generator selectively generates hardware logic for gradient calculation and direction quantization of Roberts operator, Prewitt operator, 3×3 Sobel operator or 5×5 Sobel operator according to configuration parameters. The configurable nonmaximum suppression module generator generates nonmaximum suppression hardware logic with an adjustable window size according to configuration parameters. The configurable edge hysteresis connection module generator generates edge hysteresis connection hardware logic based on an iterative pipeline structure with a specified number of iterations according to configuration parameters.

4. The parameterized Canny edge detection accelerator according to claim 1, characterized in that, In the standard bus interface and top-level control logic, the AXI-Lite slave interface is used to communicate with an external CPU to receive configuration parameters, and the AXI-Stream interface is used for the input and output of high-speed image data streams.

5. The parameterized Canny edge detection accelerator according to claim 1, characterized in that, The FIFO cache module is integrated after the dual threshold and edge hysteresis connection module, wherein the data bit width is reduced to the bit width of the edge type code.

6. An agile generation method for a parameterized Canny edge detection accelerator based on SpinalHDL, characterized in that, Includes the following steps: S1. Parameter definition: Define a top-level configuration class in the SpinalHDL environment, define all configurable parameters in the top-level configuration class, set default values ​​and perform validity checks; S2. Hardware Generation: The SpinalHDL compiler reads the parameters in the top-level configuration class and uses the advanced features of Scala language, such as conditions and loops, to selectively instantiate multiple hardware module generators to dynamically generate the corresponding Verilog RTL code. The plurality of hardware module generators include at least: a configurable grayscale conversion module generator, a configurable filtering and noise reduction module generator, a configurable gradient extraction module generator, a configurable nonmaximum suppression module generator, and a configurable edge hysteresis connection module generator; S3. Verification and Exploration: By modifying the parameters in the top-level configuration class, accelerator instances with different configurations can be quickly generated and synthesized and tested on the FPGA to evaluate their resource consumption, maximum operating frequency and image processing performance, thereby enabling rapid exploration of the design space.

7. The agile generation method according to claim 6, characterized in that, Step S2 also includes: during compilation by the SpinalHDL compiler, calculating the integer Gaussian kernel coefficients on the computer based on the configured Gaussian window size and Gaussian standard deviation.

8. The agile generation method according to claim 6, characterized in that, Step S2 also includes: dynamically generating an edge hysteresis hardware module with N levels of iterative connections using a for loop based on the configured edge hysteresis connection iteration number N.

9. The agile generation method according to claim 6, characterized in that, The agile generation method further includes: in the generated Verilog RTL code, automatically instantiating the FIFO buffer module at the point where the data width of the accelerator pipeline is minimum, in order to decouple the timing of input and output.

10. An electronic device, characterized in that, Includes the parameterized Canny edge detection accelerator as described in any one of claims 1-5, or is used to implement the agile generation method as described in any one of claims 6-9.

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