Electronic device, method for generating semiconductor pattern image, and electronic system

Abstract

An electronic device, a method for generating a semiconductor pattern image, and an electronic system are provided. The electronic device includes one or more processors including processing circuitry and a memory including one or more storage media storing instructions that, when executed by the one or more processors individually or collectively, cause the electronic device to: convert a patterning vulnerability to a first vector; convert a design rule to a second vector; and generate one or more pattern images that satisfy the patterning vulnerability and the design rule based on the first vector and the second vector.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0016188, filed with the Korean Intellectual Property Office on February 7, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to methods, apparatus, and systems for generating semiconductor pattern images. More specifically, this disclosure relates to apparatus, methods, and systems for generating semiconductor pattern images that include receiving design rules and patterning vulnerabilities to generate semiconductor pattern images. Background Technology

[0003] Typical methods for generating semiconductor pattern images allow engineers to directly create candidate sets of semiconductor pattern images for semiconductor process simulation, or these candidate sets can be obtained using rule-based methods.

[0004] When directly generating candidate sets of semiconductor pattern images, the quality deviation of the results (reduced diversity) can be large depending on the manufacturer's expertise, and the generation rate can be inefficient (low diversity and high cost and high fidelity). Rule-based methods can set an upper limit on diversity based on the complexity of the rules used to design semiconductor patterns (medium diversity and medium cost and low fidelity). Furthermore, semiconductor pattern images generated according to rule-based methods can have low accuracy / fidelity.

[0005] In other words, the quality of patterning candidate sets typically depends on the engineer's expertise. Furthermore, fabricating semiconductor pattern image candidate sets can often result in slow manufacturing rates, which can be costly to implement. Additionally, limitations may exist on the diversity of fabricable semiconductor pattern images due to the complexity of the rules employed in typical rule-based methods, which can be based on the inherent complexity of the rules. Summary of the Invention

[0006] The present invention is provided to introduce, in a simplified form, the selection of concepts further described in the detailed embodiments below. The present invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter.

[0007] In one general aspect, an electronic device is provided herein, the electronic device comprising: one or more processors including a processing circuit system; and a memory including one or more storage media storing instructions, the instructions, when executed individually or jointly by the one or more processors, causing the electronic device to: convert a patterned vulnerability into a first vector; convert a design rule into a second vector; and generate one or more patterned images satisfying the patterned vulnerability and the design rule based on the first vector and the second vector.

[0008] The process of converting patterned vulnerability into a first vector may include: determining a first weak score from the patterned vulnerability using a patterned vulnerability estimation index, which is one of a process variation band (PVB) and a normalized image log slope (NILS); and calculating a vector value corresponding to the determined first weak score.

[0009] The process of calculating the vector value may include: defining multiple levels by quantizing one or more level weak scores, wherein the one or more level weak scores are defined as continuous values; defining a codebook including multiple level vector values ​​corresponding to the multiple levels; and determining a first weak score and a corresponding first vector based on the codebook.

[0010] The process of defining multiple levels may include: defining an unknown level in response to the absence of patterned vulnerability, to generate a default vector as the vector value.

[0011] The process of converting patterned vulnerabilities into a first vector may include: simultaneously receiving multiple proposed weak scores as multiple patterned vulnerabilities, the multiple proposed weak scores being created using multiple patterned vulnerability estimation metrics.

[0012] Executing the instructions causes the electronic device to: receive design rules for corresponding polygons included in the one or more pattern images; and project the design rules onto a predetermined dimension to generate a second vector.

[0013] The generated process may include: generating multiple polygons that each satisfy a design rule; and generating a pattern defined by the arrangement of the multiple polygons and reflecting patterning vulnerability.

[0014] The processing may include: using an artificial intelligence-based image generation model to generate the one or more pattern images.

[0015] The generated processing may include: using a diffusion model to generate one or more patterned images from random noise that satisfy pattern vulnerability and design rules.

[0016] In one general aspect, a processor-implemented method is provided herein, the method comprising: converting received patterned vulnerability into a first vector; converting received design rules into a second vector; and using the first and second vectors to generate one or more patterned images that satisfy the patterned vulnerability and the design rules.

[0017] The steps of converting received patterned vulnerabilities may include: determining a first weak score from the received patterned vulnerabilities using a patterned vulnerability estimation index, which is one of process variation band (PVB) and normalized image log slope (NILS); and calculating a vector value corresponding to the determined first weak score.

[0018] The calculation steps may include: defining multiple levels by quantizing one or more level weak scores, wherein the multiple level weak scores are defined as continuous values; defining a codebook including multiple level vector values ​​corresponding to the multiple levels; and determining a first weak score and a corresponding first vector based on the codebook.

[0019] The steps of defining multiple levels may include: defining an unknown level in response to no patterned vulnerability received, to generate a default vector as the vector value.

[0020] The step of converting the received patterned vulnerabilities into a first vector may include: simultaneously receiving multiple proposed weak scores as multiple received patterned vulnerabilities, the multiple proposed weak scores being created using multiple patterned vulnerability estimation metrics.

[0021] The step of converting the received design rules into a second vector may include: receiving design rules for corresponding polygons to be included in the one or more pattern images; and projecting the design rules along a predetermined dimension to generate the second vector.

[0022] The generation steps may include: generating multiple polygons that each satisfy the received design rules; and generating a pattern defined by the arrangement of the multiple polygons and reflecting patterning vulnerability.

[0023] The generation steps may include: using an artificial intelligence-based image generation model to generate the one or more pattern images.

[0024] The generation steps may include: using a diffusion model to generate one or more pattern images from random noise that satisfy the received patterned vulnerability and the received design rules.

[0025] In one general aspect, a system is provided herein comprising: a semiconductor pattern image generator configured to generate semiconductor pattern images, the semiconductor pattern image generator including an artificial intelligence model for generating a patterning candidate set, the patterning candidate set including at least one pattern image satisfying design rules and patterning vulnerabilities; and a simulator for performing process simulations using the patterning candidate set, the system being configured to adjust process variables in response to the results of the simulation.

[0026] A semiconductor pattern image generator may include: one or more processors, including a processing circuit system; a memory, including one or more storage media storing instructions, which, when executed individually or jointly by the one or more processors, cause the semiconductor pattern image generator to: convert patterning vulnerability into a first vector; convert design rules into a second vector; generate one or more pattern images that satisfy the patterning vulnerability and the design rules based on the first and second vectors; and generate one or more semiconductor pattern images using an artificial intelligence-based model. Attached Figure Description

[0027] Figure 1 An example process for generating a semiconductor patterned image is shown according to one or more embodiments.

[0028] Figure 2 An example apparatus for generating semiconductor patterned images is shown according to one or more embodiments.

[0029] Figure 3 Illustrations according to one or more embodiments Figure 2 Example patterned vulnerability embedder.

[0030] Figure 4 Illustrations according to one or more embodiments Figure 2 Example design rule embedder.

[0031] Figure 5 Example inputs and outputs are shown according to one or more embodiments.

[0032] Figure 6A and Figure 6B An example apparatus for generating semiconductor patterned images is shown according to one or more embodiments.

[0033] Figure 7 An example method for generating a semiconductor patterned image according to one or more embodiments is shown.

[0034] Figure 8 An example electronic device according to one or more embodiments is shown.

[0035] Throughout the accompanying drawings and detailed embodiments, unless otherwise described or provided, the same or similar reference numerals shall be understood to denote the same or similar elements, features, and structures. The drawings may not be to scale, and for clarity, illustration, and convenience, the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated. Detailed Implementation

[0036] The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding the disclosure of this application. For example, the order of operations and / or the sequence of operations described herein are merely examples, and are not limited to the order of operations and / or the sequence of operations set forth herein, except that they must occur in a specific order, but may be changed as will become apparent upon understanding the disclosure of this application. As another example, the order of operations and / or the sequence of operations may be performed in parallel, except that at least a portion of the order of operations and / or the sequence of operations must occur in a specific order (e.g., a particular order). Furthermore, for clarity and brevity, descriptions of features known upon understanding the disclosure of this application may be omitted.

[0037] The features described herein may be embodied in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein have been provided only to illustrate some of the many possible ways in which the methods, apparatus, and / or systems described herein will be clear upon understanding the disclosure of this application. The use of the term “may” in relation to examples or embodiments (e.g., regarding what an example or embodiment may include or implement) indicates the existence of at least one example or embodiment that includes or implements such a feature, and not all examples are limited thereto. The terms “example,” “embodiment,” and “example embodiment” are used herein with the same meaning (e.g., the phrase “in one example” has the same meaning as “in one embodiment” and “in an example embodiment”), and “one or more examples” has the same meaning as “one or more embodiments” and “one or more example embodiments.” Furthermore, each of the multiple or all individually described “example,” “embodiment,” “example embodiment,” and “example,” “embodiment,” “example embodiment” may be combined and included in any combination of the same embodiment.

[0038] Although terms such as “first,” “second,” and “third,” or A, B, (a), (b), etc., may be used herein to describe various components, assemblies, regions, layers, or parts, these components, assemblies, regions, layers, or parts should not be limited by these terms. For example, each of these terms is not used to define the nature, order, or sequence of the corresponding component, assembly, region, layer, or part, but only to distinguish the corresponding component, assembly, region, layer, or part from other components, assemblies, regions, layers, or parts. Therefore, without departing from the teaching of the examples described herein, the first component, first assembly, first region, first layer, or first part mentioned in the examples may also be referred to as the second component, second assembly, second region, second layer, or second part.

[0039] As used in conjunction with the various exemplary embodiments disclosed, any use of the terms "module" or "unit" refers to hardware and / or processing hardware, and is interchangeable with other terms (e.g., "logic," "logic block," "part," or "circuit system"), the hardware and / or processing hardware being configured to implement software and / or firmware to configure such processing hardware to perform corresponding operations. As a non-limiting example, an application-defined integrated circuit (ASIC) may be referred to as an application-defined integrated module. As another non-limiting example, a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) may be referred to as a field-programmable gate cell or an application-specific integrated cell, respectively. In one non-limiting example, such software may include components such as software components, object-oriented software components, class components, and may include processor task components, processes, functions, attributes, procedures, subroutines, and software segments. The software may also include program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. In another non-limiting example, such software may be executed by one or more central processing units (CPUs) of an electronic device or a secure multimedia card.

[0040] The terminology used herein is for describing various examples only and is not intended to limit the disclosure. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well. As a non-limiting example, the terms “comprising,” “including,” and “having” specify the presence of the stated features, quantities, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof, or alternatives to the stated features, quantities, operations, components, elements, and / or combinations thereof. Furthermore, while one embodiment may describe the presence of features, quantities, operations, components, elements, and / or combinations thereof specified by the terms “comprising,” “including,” and “having,” other embodiments may exist where one or more of the stated features, quantities, operations, components, elements, and / or combinations thereof are absent.

[0041] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains and specifically in the context of understanding the disclosure of this application. Unless expressly defined herein, terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as the term in the context of the relevant field and specifically in the context of the disclosure of this application, and shall not be interpreted in an idealized or overly formal sense.

[0042] Figure 1 An example process for generating a semiconductor patterned image is shown according to one or more embodiments.

[0043] Reference Figure 1 A system (or electronic system) for generating semiconductor pattern images may include a device 100 for generating semiconductor pattern images (also referred to as a semiconductor pattern image generating device 100 or semiconductor pattern image generator 100) and a simulator 200.

[0044] The device 100 can generate a patterning candidate group 40, which includes at least one pattern image 30 that satisfies the input design rules and the patterning vulnerability.

[0045] When design rules and patterning vulnerabilities are input, device 100 can generate patterned candidate groups 40 that satisfy the design rules and patterning vulnerabilities.

[0046] In one example, simulator 200 may receive a generated patterned candidate group 40 and may use the patterned candidate group 40 to perform semiconductor process simulation.

[0047] Simulator 200 can output simulation results 50 by repeating semiconductor process simulations.

[0048] A system for generating semiconductor pattern images can use the apparatus 100 for generating semiconductor pattern images and the simulation results 50 obtained by simulator 200 to adjust process variables (e.g., process variable 1 to process variable n, where n is an integer greater than 1) through feedback.

[0049] A system capable of generating semiconductor pattern images can use adjusted process variables to repeat semiconductor process simulations and determine the effectiveness of the process.

[0050] Figure 2 An example apparatus for generating semiconductor patterned images is shown according to one or more embodiments.

[0051] Reference Figure 1 and Figure 2 The device 100 can execute program code or instructions loaded on at least one memory device via at least one processor.

[0052] For example, device 100 may be implemented as will be referred to below. Figure 8 The electronic device 900 is described in more detail. At least one processor may correspond to the processor 910 of the electronic device 900, and at least one memory device may correspond to the memory 930 of the electronic device 900.

[0053] The program code or instructions can be executed by at least one processor and can generate at least one patterned image that satisfies design rules and patterning vulnerabilities as input to a patterning candidate group for semiconductor process simulation.

[0054] Reference Figure 2 In a non-restrictive example, Figure 1 The device 100 for generating semiconductor patterned images may include a patterned vulnerability embedder (or patterned vulnerability embedding module) 110, a design rule embedder (or design rule embedding module) 120, and an image generator (or image generation module) 130.

[0055] In one example, patterned vulnerability embedder 110 may receive patterned vulnerabilities (e.g., patterned vulnerability 10) and convert the patterned vulnerability into a first vector. For example, patterned vulnerability 10 may be an estimation metric used to predict the patterned effectiveness of an actual process based on process simulations of a design. That is, patterned vulnerability 10 may be a metric used to determine the success status (e.g., the degree or level of success) of simulation results. Patterned vulnerability 10 may be calculated using various metrics including process variation bands (PVB), normalized image log slope (NILS), etc.

[0056] In one example, the patterned vulnerability embedder 110 may receive patterned vulnerability 10. Next, the patterned vulnerability 10 may be evaluated as a score (e.g., a weak score) for use in the model using one or more patterned vulnerability estimation metrics (such as PVB or NILS metrics). That is, as described in more detail below, the patterned vulnerability 10 may be converted into a weak score based on the metric so that it can be used by the neural network model. For example, the weak score may be an indicator value that follows the results of PVB or NILS. Upon receiving a weak score, the patterned vulnerability embedder 110 may convert the weak score into a vector value (e.g., a first vector).

[0057] In other words, the patterned vulnerability embedder 110 can receive patterned vulnerability 10, which can then be evaluated as a weak score using a patterned vulnerability estimation metric, and the vector value corresponding to the weak score can be computed. For example, in Figure 2 In the diagram, an example value for a weak fraction (i.e., in the patterned fragility 10 element) is shown as a value of 13.3.

[0058] The patterned vulnerability embedder 110 can provide a first vector to the artificial intelligence model of the image generator 130 as input.

[0059] In one example, the patterned vulnerability embedder 110 may simultaneously receive corresponding weak scores using multiple patterned vulnerability estimation metrics as patterned vulnerabilities. That is, the patterned vulnerability embedder 110 may receive a first weak score based on PVB and a second weak score based on NILS.

[0060] In one example, design rule embedder 120 can receive design rules and convert them into a second vector. Design rule 20 can represent one or more rules regarding the arrangement and form of design polygons. Design rule 20 can represent the minimum conditions that allow patterning in the process.

[0061] For example, design rule 20 may be a reference that will be physically observed through polygons in a semiconductor pattern image, which is required for successful patterning, and may include the length of the polygons (e.g., height and width) and the position of the polygons (e.g., the X and Y coordinates of the center of the polygons), as well as the corresponding gaps between the polygons (e.g., top space, bottom space, right space, left space, and channel information).

[0062] The design rule embedder 120 can convert design rules for the corresponding polygon into vector values ​​(e.g., a second vector). The design rule embedder 120 can provide the second vector as input to the artificial intelligence model of the image generator 130.

[0063] Upon receiving the first vector and the second vector, the image generator 130 can generate one or more patterned images 30 that satisfy pattern fragility and design rules.

[0064] Image generator 130 may include various types of artificial intelligence-based image generation models. For example, image generator 130 may include diffusion models (DM), generative adversarial network (GAN) models, variational autoencoder (VAE) models, and autoregressive models (Am).

[0065] For example, image generator 130 can use a diffusion model to generate at least one patterned image from random noise that satisfies patterning vulnerability and design rules. Patterning vulnerability and design rules can be provided to semiconductor patterned image generation apparatus 100 for evaluation, for example, by patterning vulnerability embedder 110, to create one or more weakness scores. For example, image generator 130 can generate at least one patterned image that satisfies the first weakness score and the second weakness score, calculated based on various patterning vulnerabilities according to different patterning vulnerability estimation metrics.

[0066] Image generator 130 can generate polygons that each satisfy design rules. Image generator 130 can generate patterns defined by the arrangement of polygons and reflecting patterning fragility.

[0067] In other words, the corresponding pattern image may include polygons with patterns that satisfy pattern fragility and meet design rules.

[0068] Figure 3 Illustrations according to one or more embodiments Figure 2 Example patterned vulnerability embedder.

[0069] Reference Figure 3 In a non-limiting example, the patterned vulnerability embedder 110 may include a fractional quantizer 111 and a fractional book 112.

[0070] In one example, fraction quantizer 111 can quantize weak fractions that are presented as continuous values ​​and can define classes.

[0071] For example, PVB-based weak fractions can have a range of 0 to 14. The fraction quantizer 111 can quantize weak fractions from 0 to 14 and can define levels in a range of values ​​from 1 to 8.

[0072] For example, when a PVB-based weak fraction 13.3 is input, the fraction quantizer 111 can define the patterned vulnerability of the PVB-based weak fraction 13.3 as level 8.

[0073] The fractional quantizer 111 can also define unknown levels. Unknown levels can be used when there is an instruction or expectation not to use the received patterned vulnerability, or when the patterned vulnerability has not yet been received. The fractional quantizer 111 can define another unknown level (the other unknown level is level 0) as a level other than levels 1 through 8. When no indicator of patterned vulnerability is input to the image generator 130, the fractional quantizer 111 can determine the patterned vulnerability as an unknown level.

[0074] In one example, the codebook 112 can define a codebook including vector values ​​corresponding to the levels. For example, when receiving patterned vulnerability based on PVB and defining weak scores as levels 0 to 8, the codebook 112 can generate a codebook including vector values ​​corresponding to levels 0 to 8. In one example, the codebook 112 can generate a codebook including vector values ​​corresponding to levels 0 to k (where k is an integer greater than 0), and the vector space corresponding to the codebook can be represented as... (in, (Represents the dimension of the vector space).

[0075] The fractional quantizer 112 can determine a first vector corresponding to a weak fraction based on the generated codebook. For example, when the patterned vulnerability of the input is 13.3, the fractional quantizer 111 can assign a level of 8, and the fractional quantizer 112 can determine a first vector corresponding to level 8, which can then be provided to the image generator 130. In one example, the fractional quantizer 112 can determine a default vector corresponding to an unknown level (e.g., level 0), and this default vector can be provided to the image generator 130.

[0076] Figure 4 Illustrations according to one or more embodiments Figure 2 Example design rule embedder.

[0077] Reference Figure 4 In a non-limiting example, the design rule embedder 120 may include the design rule projector 121.

[0078] In one example, the design rule embedder 120 may receive design rules for polygons included in a pattern image. The design rule projector 121 may project the received design rules in a predetermined dimension and may generate a second vector. For example, the design rule projector 121 may have m samples and may receive design rules represented in d-dimensional space (e.g., the vector space corresponding to the design rules may be represented as...). ).

[0079] The design rule projector 121 can be represented as a matrix W and can perform the transformation of the mapping data of the input design rules in a high-dimensional (or low-dimensional) feature space. The design rule projector 121 can transform the second vector output as a representation of a new dimension ( A new vector space (e.g., In the design rule projector 121, the second vector can be provided as input to the artificial intelligence model of the image generator 130.

[0080] Figure 5 Example inputs and outputs are shown according to one or more embodiments.

[0081] Reference Figure 5 In a non-restrictive example, patterned vulnerability 11 can be input as a PVB-based weak score 13. The input design rule 21 may include the spacing (or gap) between polygons and the position of each polygon POL1.

[0082] The generated pattern image 31 can satisfy the input pattern fragility 11 and the input design rule 21 for the included polygon POL2.

[0083] Figure 6A and Figure 6B An example apparatus for generating semiconductor patterned images is shown according to one or more embodiments.

[0084] Reference Figure 6A In a non-limiting example, an apparatus 100-1 is shown for generating semiconductor pattern images while ignoring patterning vulnerabilities and inputting design rules.

[0085] When design rules are entered independently, the pattern image generation device 100-1 can use an unknown level 61 (e.g., level 0) as input to the patterned vulnerability embedder 110.

[0086] Reference Figure 6B In a non-limiting example, an apparatus 100-2 is shown for generating a semiconductor pattern image when design rules are ignored and patterning vulnerabilities are input to generate a pattern image.

[0087] When patterning vulnerability is input independently, the apparatus 100-2 for generating semiconductor pattern images can use unknown information 62 (e.g., -1) predefined in the design rule embedder 120 as input (e.g., as input to the artificial intelligence model of the image generator 130).

[0088] Figure 7 An example method for generating a semiconductor patterned image according to one or more embodiments is shown. Figure 7 The method for generating semiconductor pattern images can be derived from Figure 2 The device 100, which generates semiconductor pattern images, performs the operation.

[0089] Reference Figure 7 In a non-limiting example, in method 700, in operation S710, a device (e.g., device 100) having semiconductor patterned image generation can receive a specific fraction of patterned vulnerability and can convert the patterned vulnerability into a first vector that will be input into an artificial intelligence model.

[0090] The device can receive patterned vulnerabilities, shown as a first weak score, using patterned vulnerability estimation metrics including process variation bands (PVB) and normalized image log slope (NILS). A vector value corresponding to the received first weak score can be generated. The device can define a level by quantizing the weak scores, shown as continuous values.

[0091] In one example, the device can define an unknown level to use when ignoring received patterned vulnerabilities.

[0092] The device can define a codebook including vector values ​​corresponding to the grades. A first vector corresponding to the first weak score can be determined based on the codebook.

[0093] In one example, the device can simultaneously receive corresponding weak scores as patterned vulnerabilities using multiple patterned vulnerability estimation metrics.

[0094] In one example, during operation S720, a device for generating semiconductor pattern images (e.g., device 100) can receive design rules for at least one polygon and can convert those design rules into a second vector that will be input into an artificial intelligence model. The design rules for the respective polygons may be included in at least one pattern image.

[0095] In one example, the device can project the received design rules along a predetermined dimension and generate a second vector. In operation S730, the first and second vectors can be input into an artificial intelligence model, which can generate at least one patterned image that satisfies pattern fragility and the design rules.

[0096] In one example, an apparatus for generating semiconductor pattern images (e.g., apparatus 100) can generate polygons that satisfy design rules and can generate patterns defined by the arrangement of polygons that reflect patterning vulnerabilities. The apparatus can use an artificial intelligence-based image generation model to generate at least one pattern image. For example, a diffusion model can be used to generate at least one pattern image that satisfies patterning vulnerabilities and design rules from random noise.

[0097] Figure 8 An example electronic device according to one or more embodiments is shown.

[0098] Reference Figure 8 In a non-limiting example, an electronic device and method for generating semiconductor pattern images (e.g., method 700) may be implemented using electronic device 900.

[0099] Electronic device 900 may include at least one of a processor 910, a memory 930, a user interface input device 940, a user interface output device 950, and a storage device 960, each communicating with bus 920. Electronic device 900 may include a network interface 970 electrically connected to network 90. ​​Network interface 970 can send signals to or receive signals from other components via network 90.

[0100] Processor 910 can be configured to execute a program or application to configure processor 910 to control electronic device 900 to perform one or more operations and / or methods involving providing position codes to a neural network. Processor 910 can be implemented as various types of devices (such as microcontroller unit (MCU), application processor (AP), central processing unit (CPU), graphics processing unit (GPU), or neural processor (NPU)) and can be any semiconductor device for executing instructions stored in memory 930 or storage device 960. Processor 910 can be implemented with reference to... Figures 1 to 7 The functions and methods described.

[0101] Memory 930 may include computer-readable instructions. Processor 910 may be configured to execute computer-readable instructions (such as computer-readable instructions stored in memory 930), and by executing computer-readable instructions, processor 910 may be configured to perform one or more or any combination of the operations and / or methods described herein. Memory 930 and storage device 960 may include various types of volatile or non-volatile storage media. For example, memory may include read-only memory (ROM) 931 and random access memory (RAM) 932. In one example, memory 930 may be located internally or externally to processor 910 and may be connected to processor 910 by various known means.

[0102] In one example, at least some of the elements or functions of the apparatus, method, and system for generating semiconductor pattern images can be implemented using a program or software executed by electronic device 900, and the program or software can be stored in a computer-readable medium.

[0103] In one example, at least some elements or functions of the apparatus, method, and system for generating semiconductor patterned images can be implemented using the hardware or circuitry of the electronic device 900, and can also be implemented using additional hardware or circuitry electrically connected to the electronic device 900.

[0104] The electronic device, memory, processor, neural network, device 100, patterned vulnerability embedder 110, design rule embedder 120, image generator 130, electronic device 900, processor 910, memory 930, user interface input device 940, user interface output device 950, storage device 960, and network interface 970 described herein (including those related to...) Figures 1 to 8The description of the hardware components (as described above) is implemented or represents a hardware component. Examples of hardware components that can be used to perform the operations described in this application, as described above or in addition to those described above, include, where appropriate, controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components performing the operations described in this application are implemented by computing hardware (e.g., by one or more processors or computers). A processor or computer may be implemented by one or more processing elements (such as logic gate arrays, controllers and arithmetic logic units (ALUs), digital signal processors (DSPs), microcomputers, programmable logic controllers, field-programmable gate arrays (FPGAs), programmable logic arrays (PLUs), microprocessors, or any other means or combination of means configured to respond to and execute instructions (e.g., code or encoding) in a defined manner to achieve a desired result). In one example, the processor or computer includes one or more memories storing instructions or software executed by the processor or computer, or connected to one or more memories storing instructions or software executed by the processor or computer. Hardware components implemented by a processor or computer can execute instructions or software (such as an operating system (OS) and one or more software applications running on the OS) to perform the operations described in this application. Hardware components can also access, manipulate, process, create, and store data in response to the execution of instructions or software. For simplicity, the singular terms "processor" or "computer" may be used in the description of the examples described in this application; however, in other examples, multiple processors or computers may be used, or a processor or computer may include multiple processing elements, or multiple types of processing elements, or both, and therefore while some references to a single processor or computer may be made, such references are also intended to refer to multiple processors or computers. For example, a single hardware component, or two or more hardware components, may be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components may be implemented by one or more processors, or a processor and a controller, and one or more other hardware components may be implemented by one or more other processors, or additional processors and additional controllers. One or more processors, or a processor and a controller, may implement a single hardware component, or two or more hardware components. As described above, or in addition to the above description, the example hardware components may have any one or more different processing configurations, examples of which include a single processor, a discrete processor, a parallel processor, a single instruction single data (SISD) multiprocessing, a single instruction multiple data (SIMD) multiprocessing, multiple instruction single data (MISD) multiprocessing, and multiple instruction multiple data (MIMD) multiprocessing.Therefore, the reference to a processor herein refers to a processing circuit system (e.g., a circuit system including one or more processing element circuits). One or more processors including a processing circuit system also refers to each processor including a processing circuit system, and some or all of one or more processors including the same processing circuit system. Furthermore, by way of non-limiting example, processor(s) and controller(s) do not represent human processing or human control, but rather represent hardware components as described herein by way of non-limiting example.

[0105] Figures 1 to 8 The above and about Figures 1 to 8 The methods for performing the operations described in this application are executed by computing hardware (e.g., one or more processors or a computer), which, as described above, is implemented as instructions (e.g., computer or processor / processing device readable instructions) or software for performing the operations performed by the methods described in this application. For example, a single operation or two or more operations may be performed by a single processor, or two or more processors, or a processor and a controller. One or more operations may be performed by one or more processors, or a processor and a controller, and one or more other operations may be performed by one or more other processors, or additional processors and additional controllers. One or more processors, or a processor and a controller, may perform a single operation, or two or more operations. As a non-limiting example, references to processors or one or more processors configured to perform two or more operations indicate processors or two or more processors configured to jointly perform all of the two or more operations, and configurations where two or more processors respectively perform any corresponding one of the two or more operations (e.g., corresponding one or more processors are configured to perform each of the two or more operations, or any corresponding combination of one or more processors is configured to perform any corresponding combination of two or more operations). Similarly, a reference to a processor-implemented method is a reference to a method executed by one or more processors or other processing or computing hardware of a device or system.

[0106] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above may be written as computer programs, code segments, or other executable instructions or any combination thereof to individually or collectively instruct or configure one or more processors or computers to operate as a machine or special-purpose computer to perform operations performed by the hardware components and methods described above. In one example, the instructions or software include machine code (such as machine code generated by a compiler) that is directly executed by one or more processors or computers. In another example, the instructions or software include high-level code that is executed by one or more processors or computers using an interpreter. The instructions or software may be written using any programming language based on the block diagrams and flowcharts shown in the accompanying drawings and the corresponding description herein, which disclose algorithms for performing operations performed by the hardware components and methods described above.

[0107] Instructions or software used to control computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above, as well as any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media, and are therefore not the signal itself. Thus, references to storage media herein refer to storage media hardware, not to transient media or the signal itself. Examples of non-transitory computer-readable storage media, as described above or in addition to the above description, include one or more of any of the following: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disc storage, hard disk drive (HDD), solid-state drive (SSD), flash memory, card-type storage (such as multimedia cards or microcards (e.g., Secure Digital (SD) or Extreme Digital (XD))), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state drive, and / or any other device configured to store instructions or software and any associated data, data files, and data structures in a non-transitory manner, and to provide instructions or software and any associated data, data files, and data structures to one or more processors or computers, such that one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed across a networked computer system, such that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner by one or more processors or computers.

[0108] While this disclosure includes specific examples, it will be clear upon understanding this disclosure that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered for descriptive purposes only and not for limiting purposes. The description of features or aspects in each example is to be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and / or if components in the described system, architecture, apparatus, or circuit are combined in a different manner and / or replaced or supplemented by other components or their equivalents.

[0109] Therefore, in addition to the above and all the figures disclosed, the scope of the disclosure also includes the claims and their equivalents (i.e., all variations within the scope of the claims and their equivalents shall be interpreted as included in the disclosure).

Claims

1. An electronic device comprising: One or more processors; as well as The memory includes one or more storage media storing instructions that, when executed individually or jointly by the one or more processors, cause the one or more processors to: Transform patterned vulnerability into a first vector; Transform the design rules into a second vector; and One or more patterned images that satisfy pattern fragility and design rules are generated based on the first and second vectors.

2. The electronic device as claimed in claim 1, wherein, The process of converting patterned vulnerabilities into first vectors includes: The first weak score is determined from patterned vulnerability using a patterned vulnerability estimation index, which is one of the process variation band and the normalized image logarithmic slope; and The vector value corresponding to the first weak fraction is calculated and determined, and is taken as the first vector.

3. The electronic device as claimed in claim 2, wherein, The operation of calculating the vector value includes: Multiple levels are defined by quantifying one or more weak level scores, which are defined as continuous values; The definition includes a codebook containing multiple level vector values ​​corresponding to the multiple levels; and The vector value corresponding to the first weak fraction is determined based on the codebook.

4. The electronic device as claimed in claim 3, wherein, Defining multiple levels of processing includes: In response to the absence of patterned vulnerability, an unknown level is defined to generate a default vector as the vector value.

5. The electronic device as claimed in claim 1, wherein, The process of converting patterned vulnerabilities into a first vector includes: simultaneously receiving multiple proposed weak scores as multiple patterned vulnerabilities, the multiple proposed weak scores being created using multiple patterned vulnerability estimation metrics.

6. The electronic device as claimed in claim 1, wherein, The instructions, when executed individually or jointly by the one or more processors, cause the one or more processors to: Receive design rules for the corresponding polygons included in the one or more pattern images, and The design rules are projected along a predetermined dimension to generate a second vector.

7. The electronic device as claimed in claim 1, wherein, The process of generating the one or more pattern images includes: Generate multiple polygons that each satisfy the design rules, and Generate multiple patterns defined by the arrangement of the multiple polygons and reflecting patterning vulnerability.

8. The electronic device according to any one of claims 1 to 7, wherein, The process of generating the one or more pattern images includes: The one or more pattern images are generated using an artificial intelligence-based image generation model.

9. The electronic device as claimed in claim 8, wherein, The process of generating the one or more pattern images includes: The diffusion model is used to generate one or more patterned images from random noise that satisfy pattern fragility and design rules.

10. A method for generating a semiconductor pattern image, the method comprising: The received patterned vulnerability is converted into a first vector; Convert the received design rules into a second vector; as well as Generate one or more patterned images that satisfy pattern fragility and design rules using the first and second vectors.

11. The method of claim 10, wherein, The steps to convert the received patterned vulnerability into a first vector include: A first weakness score is determined from the received patterned vulnerability using a patterned vulnerability estimation metric, which is one of the process variation band and the normalized image logarithmic slope; and The vector value corresponding to the first weak fraction is calculated and determined, and is taken as the first vector.

12. The method of claim 11, wherein, The steps for calculating the vector value include: Multiple levels are defined by quantifying one or more weak level scores, which are defined as continuous values; The definition includes a codebook containing multiple level vector values ​​corresponding to the multiple levels; and The vector value corresponding to the first weak fraction is determined based on the codebook.

13. The method of claim 12, wherein, The steps to define multiple levels include: An unknown level is defined in response to the absence of a patterned vulnerability, and a default vector is generated as the vector value.

14. The method of claim 10, wherein, The steps to convert the received patterned vulnerability into a first vector include: Simultaneously, multiple suggested weak scores are received as multiple received patterned vulnerabilities, which are created using multiple patterned vulnerability estimation metrics.

15. The method of claim 10, wherein, The operation of converting the received design rules into a second vector includes: Receive design rules for corresponding polygons included in the one or more pattern images; and The design rules are projected along a predetermined dimension to generate a second vector.

16. The method of claim 10, wherein, The steps for generating the one or more pattern images include: Generate multiple polygons that each satisfy the received design rules, and Generate multiple patterns defined by the arrangement of the multiple polygons and reflecting patterning vulnerability.

17. The method of any one of claims 10 to 16, wherein, The steps for generating the one or more pattern images include: The one or more pattern images are generated using an artificial intelligence-based image generation model.

18. The method of claim 17, wherein, The steps for generating the one or more pattern images include: The diffusion model is used to generate one or more pattern images from random noise that satisfy the received patterned vulnerability and the received design rules.

19. An electronic system comprising: A semiconductor pattern image generator is configured to generate semiconductor pattern images. The semiconductor pattern image generator includes an artificial intelligence model for generating a patterning candidate set, which includes at least one pattern image that satisfies design rules and patterning vulnerabilities. as well as A simulator used to perform process simulations using patterned candidate sets. The semiconductor pattern image generator is further configured to adjust process variables in response to the results of the simulation.

20. The electronic system as claimed in claim 19, in, The semiconductor pattern image generator includes: One or more processors; and The memory includes one or more storage media storing instructions that, when executed individually or jointly by the one or more processors, cause the semiconductor pattern image generator to: Transform patterned vulnerability into a first vector; Transform the design rules into a second vector; One or more pattern images satisfying pattern fragility and design rules are generated based on the first and second vectors; and One or more semiconductor pattern images are generated using an artificial intelligence-based model.

Images