Display module and electronic device including the same

Abstract

A display module and an electronic device including the same are disclosed. The display module includes a gate driving circuit and a plurality of pixels. The gate driving circuit includes a plurality of stages electrically connected with the plurality of pixels. A first stage among the plurality of stages receives a high signal having a first potential, a low signal having a second potential lower than the first potential, and a first clock signal. The first stage includes a first charging unit, a first inverting unit, a first main boost unit, a first main output unit, and a first sub output unit. The first charging unit includes a first main capacitor disposed between a first upper charging node and a first lower charging node. The first inverting unit transfers the high signal to a first output node or electrically connects the first lower charging node to the first output node according to the first clock signal.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2025-0014177, filed on February 5, 2025, and all benefits derived therefrom, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display module and an electronic device including the display module. More specifically, this disclosure relates to a display module in which power consumption for generating a clock signal is reduced and the operating speed of the gate drive circuit is increased, and an electronic device including the display module. Background Technology

[0003] The display module includes a gate drive circuit and multiple pixels. The gate drive circuit provides gate control signals, and the multiple pixels are controlled based on the gate control signals. The gate drive circuit is controlled by various electrical signals, including clock signals, high signals, and low signals.

[0004] In conventional technology, gate drive circuits use a portion of a clock signal to generate the gate control signal. To improve the resolution of the display module or to increase the operating speed of the gate drive circuit, a clock signal with a larger amplitude may be required. Consequently, generating a clock signal with a larger amplitude can lead to increased power consumption. Summary of the Invention

[0005] The purpose of this disclosure is to provide a display module in which a gate control signal is generated using high and low signals instead of a clock signal itself with a larger amplitude, thereby reducing the power consumption associated with generating the clock signal, and an electronic device including the display module.

[0006] This disclosure provides a display module, which, according to an embodiment, may include a gate driving circuit and a plurality of pixels. The gate driving circuit may include a plurality of stages electrically connected to the plurality of pixels. Among the plurality of stages, a first stage may receive a high signal having a first potential, a low signal having a second potential lower than the first potential, and a first clock signal.

[0007] The first stage may include a first charging unit, a first inverting unit, a first main boost unit, a first main output unit, and a first auxiliary output unit. The first charging unit may include a first main capacitor disposed between a first upper charging node and a first lower charging node. The first inverting unit may transmit a high signal to the first output node or electrically connect the first lower charging node to the first output node based on a first clock signal. The first main boost unit may transmit a low signal to the first upper charging node according to the potential of the first output node.

[0008] The first main output unit can provide a first non-inverting output signal to at least one of a plurality of pixels based on the potential of the first output node. The first sub-output unit can provide a first inverting output signal to at least one of a plurality of pixels based on the potential of the first output node and the potential of the first non-inverting output signal. One of the first non-inverting output signal and the first inverting output signal can be a high signal, and the other can be a low signal.

[0009] In one embodiment, the first charging unit may charge the first main capacitor with an amount of charge corresponding to the potential difference between a high signal and a low signal, based on one of an initialization signal and a carry signal, and a first clock signal. The carry signal may be an electrical signal received from a stage other than the first stage among a plurality of stages.

[0010] In an embodiment, the first main output unit may include a first upper main output transistor and a first lower main output transistor. The first upper main output transistor and the first lower main output transistor can be controlled according to the potential of the first output node, such that one of the first upper main output transistor and the other is turned off. The first sub-output unit may include a first upper sub-output transistor and a first lower sub-output transistor. The first upper sub-output transistor can be controlled by the potential of a first non-inverting output signal and provides a high signal as a first inverting output signal. The first lower sub-output transistor can be controlled by the potential of the first output node and provides a low signal as a first inverting output signal.

[0011] In an embodiment, among multiple stages, a second stage can receive a high signal, a low signal, and a second clock signal. The second stage may include a second charging unit, a second inverting unit, a second main boost unit, a second main output unit, and a second sub-output unit. The second charging unit may include a second main capacitor disposed between a second upper charging node and a second lower charging node. The second inverting unit may transmit a high signal to a second output node or electrically connect a second lower charging node to a second output node based on the second clock signal. The second main boost unit may transmit a low signal to a second upper charging node based on the potential of the second output node. The second main output unit may provide a second non-inverted output signal to at least one of a plurality of pixels based on the potential of the second output node. The second sub-output unit may provide a second inverted output signal to at least one of a plurality of pixels based on the potential of the second output node and the potential of the second non-inverted output signal. One of the second non-inverted output signal and the second inverted output signal may be a high signal, and the other may be a low signal. The first stage may further include a first main initialization unit, which may provide a high signal to a first lower charging node based on one of the second non-inverted output signal and the second inverted output signal.

[0012] In an embodiment, the first clock signal and the second clock signal may have different phases relative to each other.

[0013] In an embodiment, a level initialization signal may be further provided to the first level. The first level may further include a first sub-initialization unit, which may transmit a high signal to the first next charging node based on the level initialization signal.

[0014] In this embodiment, the first clock signal may be an electrical signal that oscillates between a first potential and a second potential. The duration for which the potential of the first clock signal is held at the first potential may be shorter than the duration for which the potential of the first clock signal is held at the second potential.

[0015] In one embodiment, the first stage may further include a first secondary boost unit comprising a first secondary capacitor. The first secondary capacitor may be disposed between the first charging node and the first secondary boost node. The first secondary boost node may be electrically connected to the first inverting unit. According to a first clock signal, the first secondary capacitor may be charged or the first secondary boost node may be electrically connected to the first output node.

[0016] A display module according to another embodiment of this disclosure may include a gate driving circuit and a plurality of pixels. The gate driving circuit may include a plurality of stages electrically connected to the plurality of pixels. Among the plurality of stages, a first stage may include a first upper output terminal, a first carry terminal, a first high-potential terminal, a first low-potential terminal, a first clock terminal, a first input terminal, a first upper input transistor, a first lower input transistor, a first main capacitor, a first lower inverting transistor, a first upper inverting transistor, a first main boost transistor, a first upper main output transistor, and a first lower main output transistor.

[0017] The first upper output terminal can transmit a first non-inverting output signal to at least one of a plurality of pixels. The first carry terminal can be electrically connected to a first upper charging node and a second stage among a plurality of stages. The first high-potential terminal can receive a high signal having a first potential. The first low-potential terminal can receive a low signal having a second potential lower than the first potential. The first clock terminal can receive a first clock signal. The first input terminal can receive one of an initialization signal and a carry signal. The carry signal can be an electrical signal received from a stage other than the first stage among a plurality of stages.

[0018] The first upper-input transistor can be turned on or off based on a first clock signal. The first upper-input transistor can be positioned between a first high-potential terminal and a first upper-charge node. The first lower-input transistor can be turned on or off based on the potential of the first input terminal. The first lower-input transistor can be positioned between a first lower-charge node (insulated from the first upper-charge node) and a first low-potential terminal.

[0019] The first main capacitor can be disposed between the first upper input transistor and the first lower input transistor. The first lower inverting transistor can be turned on or off based on the potential of the first clock terminal. The first lower inverting transistor can be disposed between the first lower charging node and the first output node.

[0020] The first upper-inverting transistor can be turned on or off based on the potential of the first clock terminal. The first upper-inverting transistor can be disposed between the first lower-inverting transistor and the first high-potential terminal. The first main boost transistor can be turned on or off according to the potential of the first output node. The first main boost transistor can be disposed between the first low-potential terminal and the first charging node.

[0021] The first upper main output transistor can be turned on or off according to the potential of the first output node. The first upper main output transistor can be positioned between the first high-potential terminal and the first upper output terminal. The first lower main output transistor can be turned on or off according to the potential of the first output node. The first lower main output transistor can be positioned between the first low-potential terminal and the first upper output terminal.

[0022] According to embodiments of this disclosure, the display module may further include a first lower output terminal, a first upper sub-output transistor, and a first lower sub-output transistor. The first lower output terminal can transmit a first inverted output signal to at least one of a plurality of pixels. The first upper sub-output transistor can be turned on or off based on the potential of the first non-inverted output signal. The first upper sub-output transistor can be disposed between a first high-potential terminal and the first lower output terminal. The first lower sub-output transistor can be turned on or off based on the potential of the first output node. The first lower sub-output transistor can be disposed between a first low-potential terminal and the first lower output terminal.

[0023] In an embodiment, one of the first upper main output transistor and the first lower main output transistor may be an NMOS transistor, and the other may be a PMOS transistor.

[0024] In this embodiment, the first upper main output transistor and the first lower main output transistor can be controlled according to the potential of the first output node, such that one of the first upper main output transistor and the first lower main output transistor is turned on while the other is turned off. One of the first non-inverting output signal and the first inverting output signal can be a high signal, and the other can be a low signal.

[0025] In an embodiment, the second stage may include a second upper output terminal, a second lower output terminal, a second high-potential terminal, a second low-potential terminal, a second clock terminal, a second input terminal, a second upper input transistor, a second lower input transistor, a second main capacitor, a second lower inverting transistor, a second upper inverting transistor, a second main boost transistor, a second upper main output transistor, a second lower main output transistor, a second upper secondary output transistor, and a second lower secondary output transistor.

[0026] The second upper output terminal can transmit the second non-inverting output signal to at least one of the multiple pixels. The second lower output terminal can transmit the second inverting output signal to at least one of the multiple pixels. The second high-level terminal can receive a high signal. The second low-level terminal can receive a low signal. The second clock terminal can receive a second clock signal.

[0027] The second input terminal can be electrically connected to the first carry terminal of the first stage. The second upper input transistor can be turned on or off based on the second clock signal. The second upper input transistor can be located between the second high-potential terminal and the second upper charging node. The second lower input transistor can be turned on or off based on the potential of the second input terminal. The second lower input transistor can be located between the second lower charging node, which is electrically insulated from the second upper charging node, and the second low-potential terminal.

[0028] The second main capacitor can be disposed between the second upper input transistor and the second lower input transistor. The second lower inverting transistor can be turned on or off based on the potential of the second clock terminal. The second lower inverting transistor can be disposed between the second lower charging node and the second output node. The second upper inverting transistor can be turned on or off based on the potential of the second clock terminal. The second upper inverting transistor can be disposed between the second lower inverting transistor and the second high-potential terminal.

[0029] The second main boost transistor can be turned on or off according to the potential of the second output node. The second main boost transistor can be positioned between the second low-potential terminal and the second upper charging node. The second upper main output transistor can be turned on or off according to the potential of the second output node. The second upper main output transistor can be positioned between the second high-potential terminal and the second upper output terminal. The second lower main output transistor can be turned on or off according to the potential of the second output node. The second lower main output transistor can be positioned between the second low-potential terminal and the second upper output terminal.

[0030] The second upper sub-output transistor can be turned on or off based on the potential of the second non-inverting output signal. The second upper sub-output transistor can be positioned between the second high-potential terminal and the second lower output terminal. The second lower sub-output transistor can be turned on or off according to the potential of the second output node. The second lower sub-output transistor can be positioned between the second low-potential terminal and the second lower output terminal.

[0031] The first stage may further include a first main initialization terminal and a first main initialization transistor. The first main initialization terminal may be electrically connected to one of the second upper output terminal and the second lower output terminal. The first main initialization transistor may be turned on or off based on the potential of the first main initialization terminal. The first main initialization transistor may be located between the first lower charging node and the first high-potential terminal.

[0032] In an embodiment, the first clock signal and the second clock signal may have different phases relative to each other.

[0033] In this embodiment, the first clock signal can be an electrical signal that oscillates between a first potential and a second potential. The duration for which the potential of the first clock signal is held at the first potential can be shorter than the duration for which the potential of the first clock signal is held at the second potential. The second clock signal can also be an electrical signal that oscillates between the first potential and the second potential. The duration for which the potential of the second clock signal is held at the first potential can be shorter than the duration for which the potential of the second clock signal is held at the second potential.

[0034] In an embodiment, the first stage may further include a first secondary initialization terminal and a first secondary initialization transistor. The first secondary initialization terminal may receive a stage initialization signal. The first secondary initialization transistor may be turned on or off based on the potential of the first secondary initialization terminal. The first secondary initialization transistor may be disposed between a first lower charging node and a first high-potential terminal.

[0035] In one embodiment, the first stage may further include a first secondary capacitor. The first secondary capacitor may be disposed between the first upper charging node and the first upper inverting transistor.

[0036] Another aspect of this disclosure provides an electronic device, which, according to an embodiment, may include a display module, a processor, a memory, and a power module. The display module may be configured to emit light. The processor may be configured to control the display module. The memory may be configured to store data necessary for the operation of the display module or the processor. The power module may be configured to generate or supply power.

[0037] The display module may include a gate driving circuit and multiple pixels. The gate driving circuit may include multiple stages electrically connected to the multiple pixels. Among the multiple stages, a first stage may receive a high signal having a first potential, a low signal having a second potential lower than the first potential, and a first clock signal.

[0038] The first stage may include a first charging unit, a first inverting unit, a first main boost unit, a first main output unit, and a first auxiliary output unit. The first charging unit may include a first main capacitor disposed between a first upper charging node and a first lower charging node. The first inverting unit may transmit a high signal to the first output node or electrically connect the first lower charging node to the first output node based on a first clock signal. The first main boost unit may transmit a low signal to the first upper charging node according to the potential of the first output node.

[0039] The first main output unit can provide a first non-inverting output signal to at least one of a plurality of pixels based on the potential of the first output node. The first sub-output unit can provide a first inverting output signal to at least one of a plurality of pixels based on the potential of the first output node and the potential of the first non-inverting output signal. One of the first non-inverting output signal and the first inverting output signal can be a high signal, and the other can be a low signal.

[0040] In this embodiment, the first main output unit may include a first upper main output transistor and a first lower main output transistor. The first upper main output transistor and the first lower main output transistor can be controlled according to the potential of the first output node, such that one of the first upper main output transistor and the first lower main output transistor is turned on, while the other is turned off. The first sub-output unit may include a first upper sub-output transistor and a first lower sub-output transistor. The first upper sub-output transistor can provide a high signal as a first inverted output signal based on the potential of the first non-inverted output signal. The first lower sub-output transistor can provide a low signal as a first inverted output signal based on the potential of the first output node.

[0041] In one embodiment, the first stage may further include a first secondary boost unit comprising a first secondary capacitor. The first secondary capacitor may be disposed between the first charging node and the first secondary boost node. The first secondary boost node may be electrically connected to the first inverting unit. According to a first clock signal, the first secondary capacitor may be charged or the first secondary boost node may be electrically connected to the first output node.

[0042] According to embodiments of this disclosure, a gate control signal is generated using high and low signals instead of a clock signal with a larger amplitude, thereby providing a display module for generating clock signals with reduced power consumption and an electronic device including such a display module. Attached Figure Description

[0043] These and / or other features will become apparent and more readily understood from the following description of embodiments in conjunction with the accompanying drawings, in which:

[0044] Figure 1This is an example block diagram illustrating a display module according to an embodiment of the present disclosure;

[0045] Figure 2A This is an example circuit diagram illustrating the equivalent circuit of the i-th pixel according to an embodiment of the present disclosure;

[0046] Figure 2B This is an example block diagram illustrating a gate drive circuit according to an embodiment of the present disclosure;

[0047] Figure 3A and Figure 3B These are example circuit diagrams of the first and second levels according to embodiments of the present disclosure;

[0048] Figure 3C This is an example waveform diagram of a clock signal according to an embodiment of the present disclosure;

[0049] Figure 4 This is an example timing diagram illustrating the operation of the first and second levels according to embodiments of the present disclosure;

[0050] Figures 5A to 5C This is an example circuit diagram illustrating the operation of the first level according to an embodiment of the present disclosure;

[0051] Figure 6A and Figure 6B These are example circuit diagrams of the first and second levels according to embodiments of the present disclosure;

[0052] Figure 7 This is an example timing diagram illustrating the operation of the first and second levels according to embodiments of the present disclosure;

[0053] Figures 8A to 8C This is an example circuit diagram illustrating the operation of the first and second levels according to embodiments of the present disclosure;

[0054] Figure 9A and Figure 9B This is an example block diagram illustrating a gate drive circuit according to an embodiment of the present disclosure;

[0055] Figure 10A and Figure 10B This is an example circuit diagram illustrating the equivalent circuit of the i-th pixel according to an embodiment of the present disclosure;

[0056] Figure 11A This is an example block diagram illustrating an electronic device according to an embodiment of the present disclosure; and

[0057] Figure 11B The figures illustrate various electronic devices according to embodiments of the present disclosure. Detailed Implementation

[0058] Reference will now be made in detail to specific embodiments illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. These embodiments may have many forms and arrangements, but this disclosure should in no way be construed as limited to the described embodiments. Rather, this disclosure should be construed as encompassing all forms, arrangements, equivalents, and substitutions covered by the technical concept and scope of this disclosure. Accordingly, only exemplary embodiments are described herein with reference to the accompanying drawings to explain the features of this disclosure.

[0059] Identical or similar reference numerals refer to identical or similar elements. Furthermore, in the accompanying drawings, the thickness, scale, and dimensions of these elements may not be drawn to exact scale and may be exaggerated in order to effectively interpret the technical features associated with them. Therefore, this disclosure should not be limited to the thickness, scale, or dimensions illustrated in the drawings. The term "and / or" should include a combination of the listed items that can be defined by the relevant elements, or any one of the listed items.

[0060] Terms such as “first” and “second” can be used to describe various components, but these components should not be limited by these terms. The terms used herein are intended to distinguish one component from others. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this disclosure. Singular terms may include plural forms unless otherwise specified.

[0061] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, “a,” “the,” and “at least one” do not indicate a limitation on quantity but are intended to include both singular and plural forms unless the context clearly indicates otherwise. For example, “an element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limited to “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the listed associated items. It will be further understood that, when used in this application, the terms “comprising” and / or variations thereof, or “including” and / or variations thereof, indicate the presence of the described features, areas, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, or components.

[0062] The term "substantially" as used in this document means approximately or actually. The term "substantially equal" means approximately equal or actually equal. The term "substantially identical" means approximately identical or actually identical. The term "substantially perpendicular" means approximately perpendicular or actually perpendicular. The term "substantially parallel" means approximately parallel or actually parallel.

[0063] The terms “high signal” (or alternatively, “high voltage level”) and “low signal” (or alternatively, “low voltage level”) are relative terms describing voltage levels. For example, the terms “high signal” (or alternatively, “high voltage level”) and “low signal” (or alternatively, “low voltage level”) may refer, based on transistor type (e.g., P-type or N-type, etc.), to the level of voltage that, when applied to the transistors described herein, can activate the transistor (e.g., turn the transistor on (“ON”)) or deactivate the transistor (e.g., turn the transistor off (“OFF”)).

[0064] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having meanings consistent with their meanings in the relevant art and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0065] It should be understood that the various embodiments of this disclosure and the terminology used therein are not intended to limit the technical features set forth herein to particular embodiments, but rather to include various changes, equivalents, or substitutions for corresponding embodiments. Regarding the description of the drawings, similar reference numerals may be used to refer to similar or related elements. It should be understood that the singular form of a noun corresponding to an item may include one or more of that item, unless the relevant context clearly indicates otherwise. As used herein, each of the phrases such as “A or B,” “at least one of A and B,” “A, B, or C,” and “at least one of A, B, and C” may include any one or all possible combinations of the items listed together in the corresponding phrases within these phrases.

[0066] Expressions such as “comprising” or “including” are intended to identify features, quantities, steps, operations, elements, parts, or combinations thereof, and should not be construed as excluding any possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, parts, or combinations thereof.

[0067] Figure 1 This is an example block diagram illustrating a display module DM according to an embodiment of the present disclosure. (Reference) Figure 1The display module DM may include a display panel DP, a signal control circuit SCC, a gate drive circuit GDC, a light emission control circuit ECC, and a data drive circuit DCC. Here, n is a natural number greater than 0. In this embodiment, the display module DM can be applied to small and medium-sized display devices. For example, small and medium-sized display devices may be any of tablet computers, built-in displays of home appliances, smartwatches, and smartphones. In another embodiment, the display module DM can be applied to large display devices, which may be any of televisions, monitors, and electronic billboards.

[0068] The display panel DP may include a plurality of pixels PX1 to PXn. Each of the plurality of pixels PX1 to PXn may be configured to emit light. Specifically, the (i-1)th pixel PXi-1, the ith pixel PXi, and the (i+1)th pixel PXi+1 may each be any one of the plurality of pixels PX1 to PXn. Here, i is a natural number equal to or greater than 1 and equal to or less than n.

[0069] The signal control circuit SCC can be configured to control at least one of the gate drive circuit GDC, the data drive circuit DCC, and the light emission control circuit ECC. The signal control circuit SCC can be configured to receive image data (e.g., video data signals) and control signals (e.g., input control signals) from an external graphics control unit (not shown). The control signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The vertical synchronization signal may be a signal that distinguishes frame segments, while the horizontal synchronization signal may be a signal that distinguishes horizontal segments (i.e., a line separation signal).

[0070] In an embodiment, the signal control circuit SCC may be a timing controller. However, the signal control circuit SCC of this disclosure is not limited to this, and the signal control circuit SCC may be any circuit capable of controlling at least one of the gate drive circuit GDC, the data drive circuit DCC, and the light emission control circuit ECC.

[0071] The gate drive circuit GDC can be configured to receive control signals from the signal control circuit SCC and provide gate control signals GS to multiple pixels PX1 to PXn.

[0072] In this embodiment, the gate drive circuit GDC can be formed simultaneously with the pixels PX1 to PXn using a thin-film process. For example, the gate drive circuit GDC can be implemented in the form of an oxide semiconductor TFT gate (OSG) driver circuit or an amorphous silicon TFT gate (ASG) driver circuit.

[0073] The light emission control circuit ECC can be configured to receive control signals from the signal control circuit SCC and provide the light emission control signal EM to multiple pixels PX1 to PXn.

[0074] The data drive circuit DCC can be configured to receive control signals from the signal control circuit SCC and provide data signals DS to multiple pixels PX1 to PXn.

[0075] The display module DM according to embodiments of this disclosure may further include an input sensing drive circuit (not shown). The input sensing drive circuit and the signal control circuit SCC may be mounted on a printed circuit board (PCB). The input sensing drive circuit may be configured to process signals corresponding to user touch input and signals corresponding to pressure applied from an external source. For example, the PCB may be a flexible printed circuit board (FPCB).

[0076] Figure 2A This is an example circuit diagram illustrating the equivalent circuit of the i-th pixel PXi according to an embodiment of the present disclosure. Figure 2B This is an example block diagram illustrating a gate drive circuit GDC according to an embodiment of the present disclosure.

[0077] refer to Figure 1 , Figure 2A and Figure 2B The gate control signal GS may include multiple non-inverting output signals NSG1 to NSGn and multiple inverting output signals ISG1 to ISGn.

[0078] Each of the plurality of pixels PX1 to PXn may include a light-emitting diode (LD) and a pixel circuitry PC. The structure of the pixel PX in this disclosure is not limited to... Figure 2A The structure is illustrated in the figure. In other embodiments, the pixel PX can be implemented in various configurations that enable the light-emitting diode LD to emit light.

[0079] The pixel circuit PC may include a compensation capacitor CCP and multiple transistors T1 to T7. The pixel circuit PC may be configured to control the amount of current flowing through the light-emitting diode LD in response to a data signal DS. The pixel circuit PC may include at least one oxide thin-film transistor and / or at least one low-temperature polycrystalline silicon (LTPS) thin-film transistor.

[0080] A light-emitting diode (LD) can be configured to emit light at a predetermined brightness in response to the amount of current supplied from the pixel circuit PC. For this purpose, the potential of the first power supply ELVDD can be set higher than the potential of the second power supply ELVSS. For example, the LD can be an organic light-emitting diode (OLED).

[0081] Each of the transistors T1 to T7 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). In this specification, one of the input electrode and the output electrode may be referred to as the first electrode, and the other may be referred to as the second electrode.

[0082] The first electrode of the first transistor T1 can be electrically connected to the first power supply ELVDD via the fifth transistor T5, and the second electrode of the first transistor T1 can be electrically connected to the anode electrode of the light-emitting diode LD via the sixth transistor T6. The first transistor T1 can be configured to control the amount of current flowing through the light-emitting diode LD based on the potential of the control electrode.

[0083] The second transistor T2 can be disposed between the data line DL and the first electrode of the first transistor T1. The second transistor T2 can be electrically connected to the i-th non-inverting output line NSLi, and can be turned on by the i-th non-inverting output signal NSGi to electrically connect the data line DL to the first electrode of the first transistor T1.

[0084] Despite Figure 2A The diagram illustrates that the control electrode of the second transistor T2 is electrically connected to the i-th non-inverting output line NSL1, but this disclosure is not limited to this configuration. In embodiments, for example, the control electrode of the second transistor T2 may be electrically connected to any one of the multiple non-inverting output lines NSL1 to NSLn or any one of the multiple inverting output lines ISL1 to ISLn.

[0085] A third transistor T3 can be disposed between the second electrode of the first transistor T1 and the control electrode of the first transistor T1. The control electrode of the third transistor T3 can be electrically connected to the i-th inverting output line ISLi, and the first electrode of the third transistor T3 can be electrically connected to the control electrode of the first transistor T1. The third transistor T3 can be turned on by the i-th inverting output signal ISGi to electrically connect the second electrode of the first transistor T1 to the control electrode of the first transistor T1. Accordingly, when the third transistor T3 is turned on, the first transistor T1 can operate as a diode.

[0086] although Figure 2A The description shows that the control electrode of the third transistor T3 is electrically connected to the i-th inverting output line ISL1, but this disclosure is not limited to this configuration. In embodiments, for example, the control electrode of the third transistor T3 may be electrically connected to any one of the multiple non-inverting output lines NSL1 to NSLn or any one of the multiple inverting output lines ISL1 to ISLn.

[0087] The fourth transistor T4 can be positioned between the compensation capacitor CCP and the initialization power line INL. The control electrode of the fourth transistor T4 can be electrically connected to the (i-1)th non-inverting output line NSLi-1. The fourth transistor T4 can be turned on by the (i-1)th non-inverting output signal NSGi-1 to provide the initialization voltage VINT to the first electrode of the third transistor T3.

[0088] although Figure 2A The diagram illustrates that the control electrode of the fourth transistor T4 is electrically connected to the (i-1)th non-inverting output line NSL1-1, but this disclosure is not limited to this configuration. In embodiments, for example, the control electrode of the fourth transistor T4 may be electrically connected to any one of the multiple non-inverting output lines NSL1 to NSLn or any one of the multiple inverting output lines ISL1 to ISLn.

[0089] The fifth transistor T5 can be electrically connected between the first power supply line PL1 and the first electrode of the first transistor T1. The control electrode of the fifth transistor T5 can be electrically connected to the light emission control line EML, which provides the light emission control signal EM.

[0090] The sixth transistor T6 can be connected between the second electrode of the first transistor T1 and the anode electrode of the light-emitting diode LD. The control electrode of the sixth transistor T6 can be electrically connected to the light-emitting control line EML that provides the light-emitting control signal EM.

[0091] The seventh transistor T7 can be positioned between the initialization power line INL and the anode of the light-emitting diode LD. The control electrode of the seventh transistor T7 can be electrically connected to the (i+1)th non-inverting output line NSL1+1, which provides the (i+1)th non-inverting output signal NSGi+1. The seventh transistor T7 can be turned on by the (i+1)th non-inverting output signal NSGi+1 to transmit the initialization voltage VINT to the anode of the light-emitting diode LD.

[0092] The seventh transistor T7 can be configured to improve the black level performance of pixel PX. Specifically, when the seventh transistor T7 is turned on, the parasitic capacitor (not shown) of the light-emitting diode LD can be discharged. Accordingly, the light emission of the light-emitting diode LD due to leakage current during black brightness realization can be suppressed. Therefore, the black level performance of the display module DM can be enhanced.

[0093] although Figure 2A The diagram illustrates that the control electrode of the seventh transistor T7 is electrically connected to the (i+1)th non-inverting output line NSL1+1, but this disclosure is not limited to this configuration. In embodiments, for example, the control electrode of the seventh transistor T7 may be electrically connected to any one of the multiple non-inverting output lines NSL1 to NSLn or any one of the multiple inverting output lines ISL1 to ISLn.

[0094] The compensation capacitor CCP can be placed between the first power line PL1 and the control electrode of the first transistor T1. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 can be determined by the amount of charge stored in the compensation capacitor CCP.

[0095] In the embodiments, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be an oxide thin-film transistor or a low-temperature polycrystalline silicon (LTPS) thin-film transistor.

[0096] refer to Figure 2B The gate drive circuit (GDC) may include multiple stages STG1 to STGn. The multiple stages STG1 to STGn may be connected sequentially to each other and electrically connected to multiple pixels PX1 to PXn through multiple non-inverting output lines NSL1 to NSLn and multiple inverting output lines ISL1 to ISLn.

[0097] Multiple stages STG1 to STGn can be configured to receive a stage initialization signal ESR, a low signal LSG, a high signal HSG, multiple clock signals CLK1, CLK2, CLK3, and an initialization signal FLM. The stage initialization signal ESR, low signal LSG, high signal HSG, multiple clock signals CLK1, CLK2, CLK3, and initialization signal FLM can be provided from the signal control circuit SCC. In another embodiment, at least some of the stage initialization signal ESR, low signal LSG, high signal HSG, multiple clock signals CLK1, CLK2, CLK3, and initialization signal FLM can be omitted.

[0098] Each of the multiple stages STG1 to STGn may include an upper output terminal TOT, a lower output terminal BOT, a carry terminal CRT, a high-level terminal HPT, a low-level terminal LPT, a clock terminal CKT, an input terminal IPT, a main initialization terminal INT, a secondary initialization terminal EST, a charging unit CHG, an inverting unit INV, a main boost unit MBS, a main output unit MOP, a secondary output unit SOP, a main initialization unit MIN, and a secondary initialization unit SIN.

[0099] Figure 3A This is an example circuit diagram of the first-stage STG1 according to an embodiment of the present disclosure. Figure 3B This is an example circuit diagram of the second-level STG2 according to an embodiment of the present disclosure. Figure 3C The diagram illustrates example waveforms of clock signals CLK1, CLK2, and CLK3 according to embodiments of the present disclosure.

[0100] refer to Figure 3AAmong the multiple STG1 to STGn stages, the first STG1 stage can receive a high signal HSG, a low signal LSG, and a first clock signal CLK1. The first STG1 stage may include a first upper output terminal TOT1, a first lower output terminal BOT1, a first carry terminal CRT1, a first high potential terminal HPT1, a first low potential terminal LPT1, a first clock terminal CKT1, a first input terminal IPT1, a first main initialization terminal INT1, a first secondary initialization terminal EST1, a first charging unit CHG1, a first inverting unit INV1, a first main boost unit MBS1, a first main output unit MOP1, a first secondary output unit SOP1, a first main initialization unit MIN1, and a first secondary initialization unit SIN1.

[0101] In this embodiment, at least some of the following components may be omitted: first upper output terminal TOT1, first lower output terminal BOT1, first carry terminal CRT1, first high potential terminal HPT1, first low potential terminal LPT1, first clock terminal CKT1, first input terminal IPT1, first main initialization terminal INT1, first secondary initialization terminal EST1, first charging unit CHG1, first inverting unit INV1, first main boost unit MBS1, first main output unit MOP1, first secondary output unit SOP1, first main initialization unit MIN1, and first secondary initialization unit SIN1.

[0102] The first upper output terminal TOT1 can be configured to transmit a first non-inverting output signal NSG1 to at least one of a plurality of pixels PX1 to PXn. In an embodiment, Figure 2A The second transistor T2 shown in the figure can be turned on or off by the first non-inverting output signal NSG1.

[0103] The first lower output terminal BOT1 can be configured to transmit the first inverted output signal ISG1 to at least one of a plurality of pixels PX1 to PXn. In an embodiment, Figure 2A The third transistor T3 shown in the figure can be turned on or off by the first inverted output signal ISG1.

[0104] The first carry terminal CRT1 can be electrically connected to the first up-charging node TND1 and the second stage STG2 among the multiple stages STG1 to STGn. The potential of the first up-charging node TND1 can be transmitted to the second input terminal IPT2 through the first carry terminal CRT1.

[0105] refer to Figure 3CThe first high-potential terminal HPT1 can be configured to receive a high signal HSG having a first potential V1, and the first low-potential terminal LPT1 can be configured to receive a low signal LSG having a second potential V2 lower than the first potential V1. In one embodiment, the first potential V1 can be between +4V and +12V, while the second potential V2 can be between -4V and -12V. In another embodiment, the first potential V1 and the second potential V2 can be adjusted according to the application or desired outcome.

[0106] The first clock terminal CKT1 can be configured to receive the first clock signal CLK1.

[0107] The first input terminal IPT1 can be configured to receive the initialization signal FLM. In an embodiment, the input terminal IPTi of the i-th stage STGi can be configured to receive either the initialization signal FLM or the (i-1)-th carry signal CRSi-1. The (i-1)-th carry signal CRSi-1 can be an electrical signal provided by the (i-1)-th stage STGi-1 among multiple stages STG1 to STGn. Specifically, the potential of the (i-1)-th carry signal CRSi-1 can be equal to the potential of the upper charging node TNDi-1 of the (i-1)-th stage STGi-1.

[0108] The first main initialization terminal INT1 can be electrically connected to one of the second upper output terminal TOT2 and the second lower output terminal BOT2.

[0109] The first initialization terminal EST1 can be configured to receive the stage initialization signal ESR. The stage initialization signal ESR can be an electrical signal used to initialize multiple stages STG1 to STGn.

[0110] The first charging unit CHG1 may include a first upper input transistor TRA1, a first main capacitor MCP1, and a first lower input transistor TRB1. The first charging unit CHG1 may be controlled by one of an initialization signal FLM and a first carry signal CRS1, and by a first clock signal CLK1, to charge the first main capacitor MCP1 with an amount of charge corresponding to the potential difference between a high signal HSG and a low signal LSG. The first carry signal CRS1 may be an electrical signal received from a stage other than the first stage STG1 among multiple stages STG1 to STGn.

[0111] The first upper-input transistor TRA1 can be located between the first high-potential terminal HPT1 and the first upper-charge node TND1. The first upper-input transistor TRA1 can be configured to turn on or off in response to the first clock signal CLK1.

[0112] The first lower input transistor TRB1 can be disposed between the first lower charging node BND1, which is electrically insulated from the first upper charging node TND1, and the first low-potential terminal LPT1. The first lower input transistor TRB1 can be configured to be turned on or off based on the potential of the first input terminal IPT1.

[0113] The first main capacitor MCP1 can be located between the first upper charging node TND1 and the first lower charging node BND1.

[0114] The first inverting unit INV1 may include a first lower inverting transistor TRC1 and a first upper inverting transistor TRD1. The first inverting unit INV1 may be controlled by a first clock signal CLK1 to either transmit a high signal HSG to the first output node OND1, or to electrically connect the first lower charging node BND1 to the first output node OND1.

[0115] The first down-inverting transistor TRC1 can be located between the first down-charge node BND1 and the first output node OND1. The first down-inverting transistor TRC1 can be configured to be turned on or off based on the potential of the first clock terminal CKT1.

[0116] The first upper-inverting transistor TRD1 can be disposed between the first lower-inverting transistor TRC1 and the first high-potential terminal HPT1. The first upper-inverting transistor TRD1 can be configured to be turned on or off based on the potential of the first clock terminal CKT1.

[0117] The first main boost unit MBS1 may include a first main boost transistor TRE1. The first main boost unit MBS1 may be configured to transmit a low signal LSG to a first up-charge node TND1 based on the potential of the first output node OND1.

[0118] The first main boost transistor TRE1 can be located between the first low-potential terminal LPT1 and the first up-charge node TND1. The first main boost transistor TRE1 can be configured to be turned on or off based on the potential of the first output node OND1.

[0119] The first main output unit MOP1 can be configured to provide a first non-inverting output signal NSG1 to at least one of a plurality of pixels PX1 to PXn based on the potential of the first output node OND1. The first main output unit MOP1 may include a first upper main output transistor TRF1 and a first lower main output transistor TRG1.

[0120] The first upper main output transistor TRF1 can be located between the first high-potential terminal HPT1 and the first upper output terminal TOT1. The first upper main output transistor TRF1 can be configured to be turned on or off based on the potential of the first output node OND1.

[0121] The first lower main output transistor TRG1 can be disposed between the first low-potential terminal LPT1 and the first upper output terminal TOT1. The first lower main output transistor TRG1 can be configured to be turned on or off based on the potential of the first output node OND1. In an embodiment, the first lower main output transistor TRG1 can be an N-type metal-oxide-semiconductor (NMOS) transistor (e.g., an N-channel MOSFET).

[0122] In this embodiment of the disclosure, the first upper main output transistor TRF1 and the first lower main output transistor TRG1 can be controlled to make one turn on and the other turn off according to the potential of the first output node OND1.

[0123] In an embodiment, one of the first upper main output transistor TRF1 and the first lower main output transistor TRG1 may be an NMOS transistor (N-channel MOSFET), while the other may be a P-type metal-oxide-semiconductor (PMOS) transistor (e.g., a P-channel MOSFET).

[0124] The first sub-output unit SOP1 can be configured to provide a first inverted output signal ISG1 to at least one of a plurality of pixels PX1 to PXn based on the potential of the first output node OND1 and the potential of the first non-inverted output signal NSG1. The first sub-output unit SOP1 may include a first upper sub-output transistor TRH1 and a first lower sub-output transistor TRI1.

[0125] The first upper sub-output transistor TRH1 can be disposed between the first high-potential terminal HPT1 and the first lower output terminal BOT1. The first upper sub-output transistor TRH1 can be configured to provide a high signal HSG as the first inverted output signal ISG1 based on the potential of the first non-inverting output signal NSG1.

[0126] The first lower sub-output transistor TRI1 can be disposed between the first low-potential terminal LPT1 and the first lower output terminal BOT1. The first lower sub-output transistor TRI1 can be configured to provide a low signal LSG as the first inverted output signal ISG1 based on the potential of the first output node OND1.

[0127] In the embodiment, one of the first non-inverting output signal NSG1 and the first inverting output signal ISG1 can be a high signal HSG, and the other of the first non-inverting output signal NSG1 and the first inverting output signal ISG1 can be a low signal LSG.

[0128] The first main initialization unit MIN1 and the first secondary initialization unit SIN1 can be configured to discharge the first main capacitor MCP1. In other words, the first main initialization unit MIN1 and the first secondary initialization unit SIN1 can be configured to initialize the first-stage STG1 to prevent faults.

[0129] The first main initialization unit MIN1 may include a first main initialization transistor TRJ1. The first main initialization unit MIN1 may be configured to provide a high signal HSG to a first lower charging node BND1 in response to one of a second non-inverting output signal NSG2 and a second inverting output signal ISG2.

[0130] The first main initialization transistor TRJ1 can be located between the first lower charging node BND1 and the first high-potential terminal HPT1. The first main initialization transistor TRJ1 can be configured to be turned on or off based on the potential of the first main initialization terminal INT1.

[0131] The first initialization unit SIN1 can be configured to transmit a high signal HSG to the first lower charging node BND1 in response to the initialization signal ESR. The first initialization unit SIN1 may include a first initialization transistor TRK1.

[0132] The first initialization transistor TRK1 can be configured to be turned on or off based on the potential of the first initialization terminal EST1, and can be located between the first lower charging node BND1 and the first high-potential terminal HPT1.

[0133] Each of the following transistors can be a PMOS transistor (P-channel MOSFET) or an NMOS transistor (N-channel MOSFET): the first upper input transistor TRA1, the first lower input transistor TRB1, the first lower inverting transistor TRC1, the first upper inverting transistor TRD1, the first main boost transistor TRE1, the first upper main output transistor TRF1, the first lower main output transistor TRG1, the first upper secondary output transistor TRH1, the first lower secondary output transistor TRI1, the first main initialization transistor TRJ1, and the first secondary initialization transistor TRK1.

[0134] In this embodiment of the disclosure, the first upper input transistor TRA1, the first lower input transistor TRB1, the first upper inverting transistor TRD1, the first main boost transistor TRE1, the first upper main output transistor TRF1, the first upper secondary output transistor TRH1, the first lower secondary output transistor TRI1, the first main initialization transistor TRJ1, and the first secondary initialization transistor TRK1 can be PMOS transistors (P-channel MOSFETs), while the first lower inverting transistor TRC1 and the first lower main output transistor TRG1 can be NMOS transistors (N-channel MOSFETs).

[0135] refer to Figure 3B The second stage STG2 among the multiple stages STG1 to STGn can be configured to receive the high signal HSG, the low signal LSG, and the second clock signal CLK2.

[0136] The second stage STG2 may include the second upper output terminal TOT2, the second lower output terminal BOT2, the second carry terminal CRT2, the second high potential terminal HPT2, the second low potential terminal LPT2, the second clock terminal CKT2, the second input terminal IPT2, the second main initialization terminal INT2, the second secondary initialization terminal EST2, the second charging unit CHG2, the second inverting unit INV2, the second main boost unit MBS2, the second main output unit MOP2, the second secondary output unit SOP2, the second main initialization unit MIN2, and the second secondary initialization unit SIN2.

[0137] The second upper output terminal TOT2 can be configured to transmit the second non-inverting output signal NSG2 to at least one of the plurality of pixels PX1 to PXn. The second lower output terminal BOT2 can be configured to provide the second inverting output signal ISG2 to at least one of the plurality of pixels PX1 to PXn.

[0138] The second high-level terminal HPT2 can be configured to receive a high signal HSG. The second low-level terminal LPT2 can be configured to receive a low signal LSG. The second clock terminal CKT2 can be configured to receive a second clock signal CLK2. The second input terminal IPT2 can be electrically connected to the first carry terminal CRT1 of the first stage STG1.

[0139] The second charging unit CHG2 may include a second upper input transistor TRA2, a second main capacitor MCP2, and a second lower input transistor TRB2. The second inverting unit INV2 may include a second lower inverting transistor TRC2 and a second upper inverting transistor TRD2. The second main boost unit MBS2 may include a second main boost transistor TRE2. The second main output unit MOP2 may include a second upper main output transistor TRF2 and a second lower main output transistor TRG2. The second sub-output unit SOP2 may include a second upper sub-output transistor TRH2 and a second lower sub-output transistor TRI2. Further descriptions of the second stage STG2 are related to... Figure 3A The descriptions are essentially the same, and therefore omitted.

[0140] refer to Figure 3CIn this embodiment of the disclosure, each of the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 can be an electrical signal that oscillates between a first potential V1 and a second potential V2. In this embodiment, the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 can have different phases relative to each other. In other words, the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 can be different in phase relative to each other.

[0141] Figure 4 This is an example timing diagram illustrating the operation of the first-stage STG1 and the second-stage STG2. The duration TM1 for which the first clock signal CLK1 is held at the first potential V1 can be shorter than the duration TM2 for which the first clock signal CLK1 is held at the second potential V2. The duration TM3 for which the second clock signal CLK2 is held at the first potential V1 can be shorter than the duration TM4 for which the second clock signal CLK2 is held at the second potential V2. The duration TM5 for which the third clock signal CLK3 is held at the first potential V1 can be shorter than the duration TM6 for which the third clock signal CLK3 is held at the second potential V2.

[0142] Figures 5A to 5C This is an example circuit diagram illustrating the operation of the first-stage STG1. In the first level time interval H1 (see...) Figure 4 In this process, the first main capacitor MCP1 can be charged. See below for reference. Figure 4 and Figure 5A This describes the operation of the first-level STG1 in the first-level time period H1.

[0143] The first clock terminal CKT1 receives the first clock signal CLK1, and the first input terminal IPT1 receives the start signal FLM. When both the first clock signal CLK1 and the start signal FLM have a second potential V2 during the first horizontal period H1, the first upper input transistor TRA1 is turned on to transmit the high signal HSG to the first upper charging node TND1, and the first lower input transistor TRB1 is turned on to transmit the low signal LSG to the first lower charging node BND1. Accordingly, the first main capacitor MCP1 is charged with a charge corresponding to the potential difference between the high signal HSG and the low signal LSG. That is, when a voltage corresponding to the difference between the first potential V1 and the second potential V2 (i.e., V1-V2) is applied to the first main capacitor MCP1, the first main capacitor MCP1 is charged.

[0144] The first upper inverting transistor TRD1 turns on in response to the first clock signal CLK1 and transmits the high signal HSG to the first output node OND1, and the first output node OND1 may have a first potential V1. Due to the potential of the first output node OND1, each of the first lower main output transistor TRG1 and the first upper secondary output transistor TRH1 is turned on.

[0145] Accordingly, the first-stage STG1 provides the low signal LSG as the first non-inverting output signal NSG1 to at least one of the plurality of pixels PX1 to PXn via the first upper output terminal TOT1. In addition, the first-stage STG1 provides the high signal HSG as the first inverting output signal ISG1 to at least one of the plurality of pixels PX1 to PXn via the first lower output terminal BOT1.

[0146] Second level time period H2 (see Figure 4 In this process, due to the voltage applied to the first main capacitor MCP1, the potential of the first output node OND1 can change from the first potential V1 to the third potential V3. In the following text, refer to... Figure 4 and Figure 5B This describes the operation of the first-level STG1 and the second-level STG2 in the second-level time period H2.

[0147] When both the first clock signal CLK1 and the start signal FLM have a first potential V1 during the second horizontal time period H2, the first upper input transistor TRA1 and the first lower input transistor TRB1 are turned off, and the first lower inverting transistor TRC1 is turned on. Since the first lower inverting transistor TRC1 is turned on to electrically connect the first lower charging node BND1 to the first output node OND1, the potential of the first lower charging node BND1 is transferred to the first output node OND1. As a result, the potential of the first output node OND1 changes to a second potential V2.

[0148] Subsequently, once the first main boost transistor TRE1 is turned on based on the potential of the first output node OND1, the low signal LSG is transmitted to the first up-charging node TND1, which changes the potential of the first up-charging node TND1 from the first potential V1 to the second potential V2 and changes the potentials of the first down-charging node BND1 and the first output node OND1 to the third potential V3.

[0149] The third potential V3 is equal to the second potential V2 minus the difference between the first potential V1 and the second potential V2. Therefore, the third potential V3 can be expressed as 2 × V2 - V1. In an embodiment, the first potential V1 can be between +4V and +12V, the second potential V2 can be between -4V and -12V, and the third potential V3 can be between -36V and -12V.

[0150] Each of the first upper main output transistor TRF1 and the first lower secondary output transistor TRI1 is turned on based on the potential of the first output node OND1. The first output node OND1 has a third potential V3, the absolute value of which is greater than the absolute values ​​of the first potential V1 and the second potential V2.

[0151] Therefore, when the third potential V3 is applied to the first output node OND1, the first upper main output transistor TRF1 and the first lower sub-output transistor TRI1 can be turned on more quickly compared to when the first potential V1 or the second potential V2 is applied to the first output node OND1. In other words, using this disclosure, the operating speed of the gate drive circuit GDC can be improved because the electrical signals used to turn on the first upper main output transistor TRF1 and the first lower sub-output transistor TRI1 are amplified.

[0152] The first-stage STG1 provides a first non-inverting output signal NSG1 to at least one of a plurality of pixels PX1 to PXn through the first upper output terminal TOT1, and provides a first inverting output signal ISG1 to at least one of a plurality of pixels PX1 to PXn through the first lower output terminal BOT1.

[0153] Furthermore, the low signal LSG, acting as the first carry signal CRS1, is transmitted to the second input terminal IPT2 of the second stage STG2 via the first carry terminal CRT1, thereby charging the second main capacitor MCP2 of the second stage STG2. The charging process of the second main capacitor MCP2 of the second stage STG2 in the second horizontal time period H2 is substantially the same as the charging process of the first main capacitor MCP1 in the first horizontal time period H1, therefore a detailed description thereof will be omitted.

[0154] One of the first non-inverting output signal NSG1 and the first inverting output signal ISG1 can be a high signal HSG, and the other can be a low signal LSG. That is, the first inverting output signal ISG1 can be an electrical signal that is the inverted version of the first non-inverting output signal NSG1. Therefore, using this disclosure, a gate drive circuit GDC capable of simultaneously outputting an inverted electrical signal (hereinafter, inverted signal) and a non-inverted electrical signal (hereinafter, non-inverted signal) can be provided. In this application, one of the first non-inverting output signal NSG1 and the first inverting output signal ISG1 can be an inverted signal, and the other can be a non-inverted signal.

[0155] In the third level period H3 (see...) Figure 4 In the second stage STG2, the second main capacitor MCP2 can be charged, and the first main capacitor MCP1 of the first stage STG1 can be discharged. That is, when the second stage STG2 is operating, the first stage STG1 can be initialized. See below for reference. Figure 4 and Figure 5C This describes the operation of the first-level STG1 and the second-level STG2 in the third-level time period H3.

[0156] The process by which the second-stage STG2 provides the second non-inverting output signal NSG2 and the second inverting output signal ISG2 in the third level time period H3 is substantially the same as the process by which the first-stage STG1 provides the first non-inverting output signal NSG1 and the first inverting output signal ISG1 in the second level time period H2, and therefore a detailed description thereof will be omitted.

[0157] The first main initialization terminal INT1 receives the second inverted output signal ISG2 of the second stage STG2. The first main initialization transistor TRJ1 is turned on based on the potential of the first main initialization terminal INT1, and the first upper input transistor TRA1 is turned on based on the potential of the first clock signal CLK1. As a result, the potentials of the first upper charging node TND1 and the first lower charging node BND1 change to the first potential V1, and the first main capacitor MCP1 is discharged. That is, the first stage STG1 can be initialized by the second stage STG2.

[0158] The first upper inverting transistor TRD1 turns on in response to the first clock signal CLK1 and transmits the high signal HSG to the first output node OND1, and the first output node OND1 may have a first potential V1. Based on the potential of the first output node OND1, each of the first lower main output transistor TRG1 and the first upper secondary output transistor TRH1 turns on.

[0159] Accordingly, the first-stage STG1 provides the low signal LSG as the first non-inverting output signal NSG1 to at least one of the plurality of pixels PX1 to PXn via the first upper output terminal TOT1. In addition, the first-stage STG1 provides the high signal HSG as the first inverting output signal ISG1 to at least one of the plurality of pixels PX1 to PXn via the first lower output terminal BOT1.

[0160] although Figure 3A , Figure 5A , Figure 5B and Figure 5C The illustration shows the first main initialization terminal INT1 receiving the second inverted output signal ISG2, but this is an example, and the embodiments disclosed herein are not limited thereto. In another embodiment, the first main initialization terminal INT1 may receive the second non-inverted output signal NSG2.

[0161] In conventional techniques, a portion of the clock signal is used as the output signal of the gate drive circuit. In this disclosure, instead of the clock signal CLK, the high signal HSG and the low signal LSG are used as the output signals of the gate drive circuit GDC, and the clock signal CLK is used only in a limited manner to control the gate drive circuit GDC. Accordingly, compared to clock signals in conventional techniques, the clock signal CLK of this disclosure can have a smaller amplitude or a shorter duration. Therefore, using this disclosure, the power consumption required to generate the clock signal CLK can be reduced, and the gate control signal GS can be stably provided independent of the resistance of the wiring used to supply the clock signal CLK.

[0162] Figure 6A and Figure 6B These are example circuit diagrams of the first-stage STG1-1 and the second-stage STG2-1 according to embodiments of the present disclosure.

[0163] Figure 6A The first stage STG1-1 may further include a first sub-boost unit SBS1, which in Figure 3A It does not exist in the first level STG1. (See reference) Figure 6A The first boost unit SBS1 may include a first capacitor SCP1 and a first boost transistor TRL1.

[0164] The first secondary capacitor SCP1 can be configured to amplify the electrical signal used to turn off the first upper main output transistor TRF1 and the first lower secondary output transistor TRI1. (See later...) Figure 7 It is described in detail.

[0165] The first secondary capacitor SCP1 can be electrically connected to the first secondary boost node SND1 and the first inverting unit INV1. The first secondary capacitor SCP1 can be located between the first charging node TND1 and the first secondary boost node SND1. Depending on the first clock signal CLK1, the first secondary capacitor SCP1 can be charged or can be electrically connected to the first output node OND1.

[0166] The first sub-boost transistor TRL1 can be disposed between the first high-potential terminal HPT1 and the first sub-boost node SND1. The first sub-boost transistor TRL1 can be configured to be turned on based on the potential of the first low-potential terminal LPT1 to electrically connect the first high-potential terminal HPT1 to the first sub-boost node SND1.

[0167] Figure 6B The second stage STG2-1 can further include a second sub-boost unit SBS2, which in Figure 3B It does not exist in the second-level STG2. (See reference) Figure 6BThe second boost unit SBS2 may include a second capacitor SCP2 and a second boost transistor TRL2. Further descriptions and references to the second boost unit SBS2 are available. Figure 6A The descriptions are essentially the same, and therefore omitted.

[0168] Figure 7 This is an example timing diagram illustrating the operations of the first-level STG1-1 and the second-level STG2-1. Figures 8A to 8C This is an example circuit diagram illustrating the operation of the first-stage STG1-1.

[0169] During the first level period H1, the first main capacitor MCP1 can be charged. (Referring to the following text...) Figure 7 and Figure 8A Describe in detail the operation of the first-level STG1-1 in the first level time period H1.

[0170] The first clock terminal CKT1 receives the first clock signal CLK1, and the first input terminal IPT1 receives the start signal FLM. During the first horizontal period H1, when both the first clock signal CLK1 and the start signal FLM have a second potential V2, the first upper input transistor TRA1 is turned on to transmit the high signal HSG to the first upper charging node TND1, and the first lower input transistor TRB1 is turned on to transmit the low signal LSG to the first lower charging node BND1. Accordingly, the first main capacitor MCP1 can be charged with an amount of charge corresponding to the potential difference between the high signal HSG and the low signal LSG. That is, the first main capacitor MCP1 can be charged when a voltage corresponding to the difference between the first potential V1 and the second potential V2 (i.e., V1-V2) is applied to it.

[0171] The first upper inverting transistor TRD1 is turned on in response to the first clock signal CLK1 to transmit the high signal HSG to the first output node OND1. The potential of the first output node OND1 causes the first lower main output transistor TRG1 and the first upper secondary output transistor TRH1 to turn on.

[0172] Accordingly, the first-stage STG1-1 provides the low signal LSG as the first non-inverting output signal NSG1 to at least one of the plurality of pixels PX1 to PXn through the first upper output terminal TOT1. In addition, the first-stage STG1-1 provides the high signal HSG as the first inverting output signal ISG1 to at least one of the plurality of pixels PX1 to PXn through the first lower output terminal BOT1.

[0173] During the second horizontal period H2, due to the voltage applied to the first main capacitor MCP1, the potential of the first output node OND1 can change from the first potential V1 to the third potential V3, and the first secondary capacitor SCP1 can be charged. References will be made below. Figure 7 and Figure 8B To describe in detail the operation of the first-level STG1-1 and the second-level STG2-1 in the second-level time period H2.

[0174] During the second horizontal time period H2, when both the first clock signal CLK1 and the start signal FLM have a first potential V1, the first upper input transistor TRA1 and the first lower input transistor TRB1 are turned off, and the first lower inverting transistor TRC1 is turned on. Since the first lower inverting transistor TRC1 is turned on to electrically connect the first lower charging node BND1 to the first output node OND1, the potential of the first lower charging node BND1 can be transferred to the first output node OND1. Accordingly, the potential of the first output node OND1 can change to a second potential V2.

[0175] Subsequently, once the first main boost transistor TRE1 is turned on based on the potential of the first output node OND1, the low signal LSG is transmitted to the first up-charging node TND1, thereby changing the potential of the first up-charging node TND1 to the second potential V2, and changing the potentials of both the first down-charging node BND1 and the first output node OND1 to the third potential V3.

[0176] The first upper main output transistor TRF1 and the first lower secondary output transistor TRI1 are turned on based on the potential of the first output node OND1. The first stage STG1-1 provides a first non-inverting output signal NSG1 to at least one of the plurality of pixels PX1 to PXn through the first upper output terminal TOT1, and provides a first inverting output signal ISG1 to at least one of the plurality of pixels PX1 to PXn through the first lower output terminal BOT1.

[0177] Furthermore, since the low signal LSG is transmitted to the first up-charging node TND1 and the high signal HSG is transmitted to the first sub-boost node SND1, the first sub-capacitor SCP1 is charged with a charge corresponding to the potential difference between the high signal HSG and the low signal LSG. In other words, the first sub-capacitor SCP1 is charged with a charge corresponding to the difference between the first potential V1 and the second potential V2.

[0178] Furthermore, the low signal LSG, acting as the first carry signal CRS1, is transmitted to the second input terminal IPT2 of the second stage STG2-1 via the first carry terminal CRT1. Correspondingly, the second main capacitor MCP2 of the second stage STG2-1 is charged. Since the charging process of the second main capacitor MCP2 of the second stage STG2-1 during the second horizontal time period H2 is substantially the same as the charging process of the first main capacitor MCP1 during the first horizontal time period H1, a detailed description thereof will be omitted.

[0179] During the third level period H3, the second main capacitor MCP2 of the second stage STG2-1 can be charged, the first main capacitor MCP1 of the first stage STG1-1 can be discharged, and the first upper main output transistor TRF1 and the first lower sub-output transistor TRI1 of the first stage STG1-1 can be turned off. References will be made below. Figure 7 and Figure 8C Describe in detail the operation of the first-level STG1-1 in the third-level time period H3.

[0180] When the first clock signal CLK1 has a second potential V2, the first upper-inverting transistor TRD1 is turned on, and therefore, the first secondary boost node SND1 is electrically connected to the first output node OND1. Accordingly, the potential of the first upper-inverting node TND1 changes from the second potential V2 to the first potential V1, and the potential of the first secondary boost node SND1 changes from the first potential V1 to the fourth potential V4.

[0181] The first upper inverting transistor TRD1 is turned on in response to the first clock signal CLK1 to transmit the high signal HSG to the first output node OND1. Each of the first lower main output transistor TRG1 and the first upper secondary output transistor TRH1 is turned on based on the potential of the first output node OND1.

[0182] Accordingly, the first-stage STG1-1 provides the low signal LSG as the first non-inverting output signal NSG1 to at least one of the plurality of pixels PX1 to PXn through the first upper output terminal TOT1. In addition, the first-stage STG1-1 provides the high signal HSG as the first inverting output signal ISG1 to at least one of the plurality of pixels PX1 to PXn through the first lower output terminal BOT1.

[0183] Based on the fourth potential V4 of the first secondary boost node SND1, the first upper main output transistor TRF1 and the first lower secondary output transistor TRI1 are turned off, and the absolute value of the fourth potential V4 can be greater than the absolute value of the first potential V1.

[0184] Therefore, when the fourth potential V4 is applied to the first sub-boost node SND1, the first upper main output transistor TRF1 and the first lower sub-output transistor TRI1 can be turned off more quickly compared to when the first potential V1 or the second potential V2 is applied to the first sub-boost node SND1. In other words, using this disclosure, since the electrical signals used to turn off the first upper main output transistor TRF1 and the first lower sub-output transistor TRI1 are amplified, the operating speed of the gate drive circuit GDC can be improved.

[0185] Furthermore, the second main capacitor MCP2 of the second stage STG2-1 is charged. Subsequently, the process by which the second stage STG2-1 provides the second non-inverting output signal NSG2 and the second inverting output signal ISG2 in the third level time period H3 is substantially the same as the process by which the first stage STG1-1 provides the first non-inverting output signal NSG1 and the first inverting output signal ISG1 in the second level time period H2, and therefore a detailed description thereof will be omitted.

[0186] Furthermore, the first main capacitor MCP1 of the first stage STG1-1 is discharged. The first main initialization terminal INT1 receives the second inverted output signal ISG2 of the second stage STG2-1. Based on the potential of the first main initialization terminal INT1, the first main initialization transistor TRJ1 is turned on, and based on the potential of the first clock signal CLK1, the first upper input transistor TRA1 is turned on. Accordingly, the potential of each of the first upper charging node TND1 and the first lower charging node BND1 changes to the first potential V1, causing the first main capacitor MCP1 to be discharged. That is, the first stage STG1-1 can be initialized by the second stage STG2-1.

[0187] Figure 9A This is an example block diagram illustrating a gate drive circuit GDC-1 according to an embodiment of the present disclosure. (See reference) Figure 9A In this embodiment of the disclosure, the third clock signal CLK3 can be omitted. The first stage STG1 and the second stage STG2 can each be one of multiple stages STG1 to STGn.

[0188] The first-stage STG1 can be configured to receive a first clock signal CLK1, and the second-stage STG2 can be configured to receive a second clock signal CLK2, wherein the first clock signal CLK1 and the second clock signal CLK2 can have different phases relative to each other. That is, although Figure 2B The multiple stages STG1 to STGn can be configured to receive three clock signals CLK1, CLK2, and CLK3 that have different phases relative to each other, but Figure 9A Multiple stages STG1 to STGn can be configured to receive two clock signals CLK1 and CLK2 that have different phases relative to each other.

[0189] Figure 9B This is an example block diagram illustrating a gate drive circuit GDC-2 according to an embodiment of the present disclosure. (See reference...) Figure 9B In this embodiment of the disclosure, multiple stages STG1 to STGn can be configured to further receive a fourth clock signal CLK4. The first to fourth clock signals CLK1 to CLK4 may have different phases relative to each other. The first stage STG1, the second stage STG2, the third stage STG3, and the fourth stage STG4 may each be one of the multiple stages STG1 to STGn.

[0190] The first-level STG1 can be configured to receive the first clock signal CLK1, the second-level STG2 can be configured to receive the second clock signal CLK2, the third-level STG3 can be configured to receive the third clock signal CLK3, and the fourth-level STG4 can be configured to receive the fourth clock signal CLK4. That is to say, although... Figure 2B The multiple stages STG1 to STGn can be configured to receive three clock signals CLK1, CLK2, and CLK3 that have different phases relative to each other, but Figure 9B The multiple stages STG1 to STGn can be configured to receive four clock signals CLK1, CLK2, CLK3, and CLK4 that have different phases relative to each other.

[0191] In this embodiment, the fourth clock signal CLK4 can be an electrical signal that oscillates between a first potential V1 and a second potential V2. The fourth clock signal CLK4, the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 can have different phases relative to each other. In this embodiment, the duration for which the fourth clock signal CLK4 is held at the first potential V1 can be shorter than the duration for which the fourth clock signal CLK4 is held at the second potential V2.

[0192] Figure 10A and Figure 10B This is an example circuit diagram of the equivalent circuit of the i-th pixel PXi according to an embodiment of the present disclosure. In an embodiment of the present disclosure, at least some of the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 can be controlled by the i-th non-inverting output signal NSGi or the i-th inverting output signal ISGi.

[0193] refer to Figure 10A The i-th pixel PXi may include a light-emitting diode (LD) and a pixel circuit (PC).

[0194] exist Figure 2AIn the pixel circuit PC, the second transistor T2 can be controlled by the i-th non-inverting output signal NSGi, and the third transistor T3, which is a P-channel MOSFET (PMOS), can be controlled by the i-th inverting output signal ISGi. Figure 10A In the pixel circuit PC, the third transistor T3 is an N-channel MOSFET (NMOS), and both the second transistor T2 and the third transistor T3 can be controlled by the i-th non-inverting output signal NSGi.

[0195] although Figure 10A The illustration shows that the second transistor T2 and the third transistor T3 are controlled by the i-th non-inverting output signal NSGi, but this is just an example, and the pixel circuit PC of this disclosure is not limited thereto. In another embodiment of this disclosure, the second transistor T2 and the third transistor T3 may be controlled by the i-th inverting output signal ISGi.

[0196] refer to Figure 10B The i-th pixel PXi may include a light-emitting diode (LD) and a pixel circuit (PC). Figure 2A In the pixel circuit PC, the second transistor T2 of the N-channel MOSFET (NMOS) can be controlled by the i-th non-inverting output signal NSGi, and the third transistor T3 can be controlled by the i-th inverting output signal ISGi. Figure 10B In the pixel circuit PC, the second transistor T2 is a P-channel MOSFET (PMOS), and both the second transistor T2 and the third transistor T3 can be controlled by the i-th inverted output signal ISGi.

[0197] In the case where the pixel circuit PC includes both N-channel MOSFETs (NMOS) and P-channel MOSFETs (PMOS), in order to control the NMOS transistors and PMOS transistors, both inverted and non-inverted signals are provided to the pixel circuit PC.

[0198] In conventional gate drive circuits, a single stage provides only one of the inverted and non-inverted signals. Because the inverted and non-inverted signals are provided in different stages, timing discrepancies may occur between pixels. In contrast, the gate drive circuit GDC of this disclosure allows a single stage to provide both inverted and non-inverted signals. Because both inverted and non-inverted signals are provided in a single stage, the operating time of each pixel can be uniformly controlled.

[0199] although Figure 10BThe illustration shows that the second transistor T2 and the third transistor T3 are controlled by the i-th inverted output signal ISGi, but this is just an example, and the pixel circuit PC of this disclosure is not limited thereto. In another embodiment of this disclosure, the second transistor T2 and the third transistor T3 may be controlled by the i-th non-inverted output signal NSGi.

[0200] Figure 11A This is an example block diagram illustrating an electronic device ED according to an embodiment of the present disclosure. (See reference) Figure 11A According to the embodiments, the electronic device ED may include a display module DM, a processor PR, a memory MM, and a power module PM.

[0201] The processor PR may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. The processor PR may be configured to provide a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4 to the gate drive circuit GDC.

[0202] The memory MM may contain data and information stored therein to support the operation of the processor PR or the display module DM. When the processor PR executes an application stored in the memory MM, video data signals and / or input control signals may be transmitted to the display module DM, and the display module DM may be configured to process the received signals and output image information through a display screen.

[0203] The power module PM may include a power supply module such as a power adapter or battery device, and a power conversion module configured to convert the power supplied by the power supply module into power for supporting the operation of the electronic device ED. The power module PM may be configured to provide a high signal HSG and a low signal LSG to the gate drive circuit GDC.

[0204] At least one of the aforementioned components of the electronic device ED may be included in the display device. In some aspects, some of the independent modules that are functionally included in a single module may be incorporated into the display device, while other independent modules may be provided separately from the display device. For example, the display device may include a display module DM according to the embodiments described herein, while the processor PR, memory MM, and power module PM may be provided as components of other devices within the electronic device ED besides the display device.

[0205] Figure 11B The illustrations depict various electronic devices (EDs) according to embodiments of the present disclosure. (Reference) Figure 11BThe various electronic devices ED that include the display module DM according to embodiments of the present disclosure may include image display electronic devices (such as smartphone APP1, tablet computer APP2, laptop computer APP3, television APP4, and desktop monitor APP5) and wearable electronic devices that include the display module DM (such as smart glasses APP6, head-mounted display APP7, and smartwatch APP8). Furthermore, the display module DM can also be applied to vehicle electronic devices APP9 and APP9-1 to APP9-4 (such as instrument panels, central information displays (CID) located on the center console or dashboard, or interior mirror displays).

[0206] Although specific embodiments of this disclosure have been described herein, it will be appreciated by anyone skilled in the art to which this disclosure pertains that various modifications and combinations can be made to this disclosure without departing from the technical spirit and scope of this disclosure as defined in the claims. Furthermore, it should be understood that the disclosed embodiments are not intended to limit this disclosure, and all technical ideas within the claims and their equivalents should be construed as being included within the scope of this disclosure.

Claims

1. A display module, comprising: Multiple pixels; as well as Gate drive circuit, in, The gate driving circuit includes multiple stages electrically connected to the plurality of pixels. The first stage of the plurality of stages receives a high signal having a first potential, a low signal having a second potential lower than the first potential, and a first clock signal. The first level includes: The first charging unit includes a first main capacitor disposed between the first upper charging node and the first lower charging node; The first inverting unit, based on the first clock signal, transmits the high signal to the first output node or electrically connects the first lower charging node to the first output node; The first main boost unit transmits the low signal to the first upper charging node based on the potential of the first output node; A first main output unit, based on the potential of the first output node, provides a first non-inverting output signal to at least one of the plurality of pixels; and The first sub-output unit provides a first inverted output signal based on the potential of the first output node and the potential of the first non-inverting output signal, and One of the first non-inverting output signal and the first inverting output signal is the high signal, and the other of the first non-inverting output signal and the first inverting output signal is the low signal.

2. The display module according to claim 1, wherein, The first charging unit, in response to one of an initialization signal and a carry signal, and the first clock signal, charges the first main capacitor with an amount of charge corresponding to the potential difference between the high signal and the low signal, and The carry signal is an electrical signal received from a stage other than the first stage among the plurality of stages.

3. The display module according to claim 1, wherein, The first main output unit includes a first upper main output transistor and a first lower main output transistor. Based on the potential of the first output node, one of the first upper main output transistor and the first lower main output transistor is turned on, while the other of the first upper main output transistor and the first lower main output transistor is turned off. The first sub-output unit includes a first upper sub-output transistor and a first lower sub-output transistor, and The first upper sub-output transistor is controlled by the potential of the first non-inverting output signal and provides a high signal as the first inverting output signal based on the potential of the first non-inverting output signal, and the first lower sub-output transistor is controlled by the potential of the first output node and provides a low signal as the first inverting output signal based on the potential of the first output node.

4. The display module according to claim 1, wherein, The second stage of the plurality of stages receives the high signal, the low signal, and the second clock signal, and The second level includes: The second charging unit includes a second main capacitor disposed between the second upper charging node and the second lower charging node; The second inverting unit, based on the second clock signal, transmits the high signal to the second output node or electrically connects the second lower charging node to the second output node; The second main boost unit transmits the low signal to the second up-charging node based on the potential of the second output node; The second main output unit, based on the potential of the second output node, provides a second non-inverting output signal to at least one of the plurality of pixels; and The second sub-output unit, based on the potential of the second output node and the potential of the second non-inverting output signal, provides a second inverting output signal to at least one of the plurality of pixels, wherein one of the second non-inverting output signal and the second inverting output signal is the high signal, and the other of the second non-inverting output signal and the second inverting output signal is the low signal. in, The first stage further includes a first main initialization unit, and The first main initialization unit provides the high signal to the first lower charging node based on one of the second non-inverted output signal and the second inverted output signal.

5. The display module according to claim 4, wherein, The first clock signal and the second clock signal have different phases relative to each other.

6. The display module according to claim 1, wherein, The first stage is further provided with a stage initialization signal, and The first stage further includes a first sub-initialization unit, which transmits the high signal to the first lower charging node based on the stage initialization signal.

7. The display module according to claim 1, wherein, The first clock signal is an electrical signal that oscillates between the first potential and the second potential, and The duration for which the potential of the first clock signal is held at the first potential is shorter than the duration for which the potential of the first clock signal is held at the second potential.

8. The display module according to claim 1, wherein, The first stage further includes a first boost unit comprising a first secondary capacitor. The first auxiliary capacitor is disposed between the first upper charging node and the first auxiliary boost node, and The first boost node is electrically connected to the first inverting unit. Specifically, according to the first clock signal, the first secondary capacitor is charged or the first secondary boost node is electrically connected to the first output node.

9. A display module, comprising: Multiple pixels; as well as Gate drive circuit, in, The gate driving circuit includes multiple stages electrically connected to the plurality of pixels, and The first level among the plurality of levels includes: The first upper output terminal transmits a first non-inverting output signal to at least one of the plurality of pixels; The first input terminal is electrically connected to the first charging node and the second stage among the plurality of stages; The first high-potential terminal is configured to receive a high signal having a first potential. The first low-potential terminal is configured to receive a low signal having a second potential that is lower than the first potential; The first clock terminal is configured to receive a first clock signal; The first input terminal is configured to receive one of an initialization signal and a carry signal, wherein the carry signal is an electrical signal received from a stage other than the first stage among the plurality of stages. The first upper input transistor is disposed between the first high potential terminal and the first upper charging node, and is turned on or off in response to the first clock signal; The first lower input transistor is disposed between the first lower charging node, which is insulated from the first upper charging node, and the first low-potential terminal, and is turned on or off based on the potential of the first input terminal. A first main capacitor is disposed between the first upper input transistor and the first lower input transistor; The first inverting transistor is disposed between the first charging node and the first output node, and is turned on or off based on the potential of the first clock terminal; The first upper inverting transistor is disposed between the first lower inverting transistor and the first high-potential terminal, and is turned on or off based on the potential of the first clock terminal; The first main boost transistor is disposed between the first low-potential terminal and the first charging node, and is turned on or off based on the potential of the first output node. A first upper main output transistor is disposed between the first high-potential terminal and the first upper output terminal, and is turned on or off based on the potential of the first output node; and The first lower main output transistor is disposed between the first low-potential terminal and the first upper output terminal, and is turned on or off based on the potential of the first output node.

10. The display module according to claim 9, further comprising: The first lower output terminal transmits the first inverted output signal to at least one of the plurality of pixels; The first upper sub-output transistor is disposed between the first high-potential terminal and the first lower output terminal, and is turned on or off based on the potential of the first non-inverting output signal; as well as The first lower sub-output transistor is disposed between the first low-potential terminal and the first lower output terminal, and is turned on or off based on the potential of the first output node.

11. The display module according to claim 9, wherein, One of the first upper main output transistor and the first lower main output transistor is an N-type metal-oxide-semiconductor transistor, and The other of the first upper main output transistor and the first lower main output transistor is a P-type metal-oxide-semiconductor transistor.

12. The display module according to claim 9, wherein, The first upper main output transistor and the first lower main output transistor are controlled based on the potential of the first output node such that one of the first upper main output transistor and the first lower main output transistor is turned on, and the other of the first upper main output transistor and the first lower main output transistor is turned off. One of the first non-inverting output signal and the first inverting output signal is the high signal, and the other of the first non-inverting output signal and the first inverting output signal is the low signal.

13. The display module according to claim 12, wherein, The second level includes: The second upper output terminal transmits the second non-inverting output signal to at least one of the plurality of pixels; The second lower output terminal transmits the second inverted output signal to at least one of the plurality of pixels; The second high-potential terminal is configured to receive the high signal; The second low-potential terminal is configured to receive the low signal; The second clock terminal is configured to receive a second clock signal; The second input terminal is electrically connected to the first carry terminal of the first stage; The second upper input transistor is disposed between the second high potential terminal and the second upper charging node, and is turned on or off in response to the second clock signal; The second lower input transistor is disposed between the second lower charging node, which is insulated from the second upper charging node, and the second low-potential terminal, and is turned on or off based on the potential of the second input terminal; The second main capacitor is disposed between the second upper input transistor and the second lower input transistor; The second lower inverting transistor is disposed between the second lower charging node and the second output node, and is turned on or off based on the potential of the second clock terminal; The second upper inverting transistor is disposed between the second lower inverting transistor and the second high-potential terminal, and is turned on or off based on the potential of the second clock terminal; The second main boost transistor is disposed between the second low-potential terminal and the second upper-charge node, and is turned on or off based on the potential of the second output node; The second upper main output transistor is disposed between the second high potential terminal and the second upper output terminal, and is turned on or off based on the potential of the second output node; The second lower main output transistor is disposed between the second low potential terminal and the second upper output terminal, and is turned on or off based on the potential of the second output node; The second upper sub-output transistor is disposed between the second high-potential terminal and the second lower output terminal, and is turned on or off based on the potential of the second non-inverting output signal; and The second lower sub-output transistor is disposed between the second low-potential terminal and the second lower output terminal, and is turned on or off based on the potential of the second output node. The first level further includes: The first main initialization terminal is electrically connected to one of the second upper output terminal and the second lower output terminal; and A first main initialization transistor is disposed between the first lower charging node and the first high-potential terminal, and is turned on or off based on the potential of the first main initialization terminal.

14. The display module according to claim 13, wherein, The first clock signal and the second clock signal have different phases relative to each other.

15. The display module according to claim 13, wherein, The first clock signal is an electrical signal that oscillates between a first potential and a second potential, and the duration for which the potential of the first clock signal is maintained at the first potential is shorter than the duration for which the potential of the first clock signal is maintained at the second potential. The second clock signal is an electrical signal that oscillates between the first potential and the second potential, and the duration for which the potential of the second clock signal is held at the first potential is shorter than the duration for which the potential of the second clock signal is held at the second potential.

16. The display module according to claim 13, wherein, The first level further includes: The first initialization terminal is configured as the receiver initialization signal; and A first initialization transistor is disposed between the first lower charging node and the first high-potential terminal, and is turned on or off based on the potential of the first initialization terminal.

17. The display module according to claim 16, wherein, The first stage further includes a first secondary capacitor disposed between the first upper charging node and the first upper inverting transistor.

18. An electronic device comprising: The display module according to any one of claims 1 to 17 is configured to emit light; The processor is configured to control the display module; A memory having data stored therein for the operation of the display module or the processor; as well as The power module is configured to generate or supply power.

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