Gate driving circuit, display panel and driving method of display panel

Abstract

Embodiments of the present application disclose a gate drive circuit, a display panel and a driving method of the display panel. The gate drive circuit comprises a plurality of cascaded gate drive units. An output control module is arranged between an output end of each gate drive unit and a gate line. The output control module is used for outputting a high resistance state when a fault enable signal is received, so as to isolate the gate drive unit and the corresponding gate line. The scheme can isolate the gate drive unit with a failure in a single row on a single side, greatly improves the display unevenness of the entire display panel caused by the failure of the gate drive circuit on a single side, and the other rows and the gate drive circuit on the other side can be normally used, thereby maximizing the effective driving capacity of the panel and significantly improving the product yield.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a gate driving circuit, a display panel, and a driving method for the display panel. Background Technology

[0002] As display panels become larger and larger in size and resolution, a dual-side driving design is usually adopted, in which gate driving circuits set on the left and right sides of the display panel simultaneously provide gate driving signals to the pixel circuits in the same row, so as to ensure that the gate driving signals have sufficient driving force.

[0003] When a gate drive unit in the gate drive circuit malfunctions due to process defects, electrostatic discharge, or device aging (such as a short circuit or open circuit), it will cause abnormal display of pixels in that row. Related technologies typically employ a method of completely shutting down the entire gate drive circuit for single-sided driving. This reduces the driving force of the gate drive circuit and results in insufficient time for the gate drive signal output to the panel, leading to uneven brightness across the entire screen and reduced product yield. Summary of the Invention

[0004] This invention provides a gate driving circuit, a display panel, and a driving method for the display panel to solve the problem of yield loss caused by the forced shutdown of the entire gate driving circuit due to a single-row gate driving unit failure.

[0005] According to one aspect of the present invention, a gate driving circuit is provided, comprising a plurality of cascaded gate driving units, wherein an output control module is provided between the output terminal of each stage of the gate driving unit and the gate line, the output control module being used to output a high impedance state when a fault enable signal is received, so as to isolate the gate driving unit of the same stage from the corresponding gate line.

[0006] Optionally, the gate drive circuit further includes a combinational logic unit; The input terminal of the combinational logic unit is connected to the output terminal of the gate driving unit, the first output terminal of the combinational logic unit is connected to the input terminal of the output control module, the second output terminal of the combinational logic unit is connected to the control terminal of the output control module, the output terminal of the output control module is connected to the gate line, the combinational logic unit is used to perform logical operations on the output signal of the gate driving unit, output a gate driving signal from its own first output terminal, and output the fault enable signal from its own second output terminal according to the received row fault configuration signal; The combinational logic unit is further configured to output a non-fault enable signal from its second output terminal according to the received row non-fault configuration signal, and the output control module is further configured to turn on according to the non-fault enable signal. The row fault configuration signal is used to characterize the row address and fault configuration information corresponding to the gate driving unit with a fault, and the row non-fault configuration signal is used to characterize the row address and non-fault configuration information corresponding to the gate driving unit without a fault.

[0007] Optionally, the gate drive circuit further includes a combinational logic unit; The input terminal of the combinational logic unit is connected to the output terminal of the gate driving unit, the output terminal of the combinational logic unit is connected to the input terminal of the output control module, the output terminal of the output control module is connected to the gate line, the combinational logic unit is used to perform logical operations on the output signal of the gate driving unit and output the gate driving signal, and the output control module uses the row fault configuration signal connected to its own control terminal as the fault enable signal. The output control module is also used to use the row non-fault configuration signal accessed by its own control terminal as a non-fault enable signal, and to turn on according to the non-fault enable signal. The row fault configuration signal is used to characterize the row address and fault configuration information corresponding to the gate driving unit with a fault, and the row non-fault configuration signal is used to characterize the row address and non-fault configuration information corresponding to the gate driving unit without a fault.

[0008] Optionally, the output control module includes a tri-state gate, the input of which is connected to the combinational logic unit, the output of which is connected to the gate line, and the control terminal of which is connected to the fault enable signal or the non-fault enable signal. The tri-state gate outputs a high-impedance state in response to the fault enable signal or turns on in response to the non-fault enable signal.

[0009] Optionally, a drive buffer may be further included in the connection path between any one of the combinational logic units and the output control module. The input terminal of the drive buffer is connected to the combinational logic unit, and the output terminal of the drive buffer is connected to the input terminal of the output control module.

[0010] According to another aspect of the present invention, a display panel is provided, including two sets of gate driving circuits as provided in any embodiment of the present invention. The first set of gate driving circuits and the second set of gate driving circuits are respectively located on opposite sides of the display panel. The output terminal of the output control module corresponding to the Nth level gate driving unit in the first set of gate driving circuits is connected to the same gate line as the output terminal of the output control module corresponding to the Nth level gate driving unit in the second set of gate driving circuits, where N is an integer greater than or equal to 1.

[0011] Optionally, the gate driving circuit further includes a combinational logic unit, the input terminal of which is connected to the output terminal of the gate driving unit, the first output terminal of which is connected to the input terminal of the output control module, the second output terminal of which is connected to the control terminal of the output control module, and the output terminal of the output control module is connected to the gate line. The display panel further includes a display driver chip and an address decoder. The address decoder is used to decode the row address output by the display driver chip, and to determine whether there is a gate driving unit marked as faulty based on the decoded row address. It also transmits a row fault configuration signal to the combinational logic unit corresponding to the gate driving unit marked as faulty, and transmits a row non-fault configuration signal to the combinational logic unit corresponding to the gate driving unit not marked as faulty. Alternatively, the input terminal of the combinational logic unit is connected to the output terminal of the gate driving unit, the output terminal of the combinational logic unit is connected to the input terminal of the output control module, the output terminal of the output control module is connected to the gate line, and the address decoder is used to transmit a row fault configuration signal to the output control module corresponding to the gate driving unit that is marked as faulty, and to transmit a row non-fault configuration signal to the output control module corresponding to the gate driving unit that is not marked as faulty.

[0012] Optionally, the display panel includes a display area and a non-display area that is at least partially disposed around the display area, wherein the first set of gate driving circuits, the second set of gate driving circuits, the display driver chip, and the address decoder are all located in the non-display area; The display panel also includes a plurality of pixel circuits located within the display area, and the gate line is connected to the pixel circuits.

[0013] According to another aspect of the present invention, a driving method for a display panel is provided. The display panel includes two sets of gate driving circuits, each gate driving circuit including a plurality of cascaded gate driving units. An output control module is disposed between each stage of the gate driving unit and a gate line. The output terminal of the output control module corresponding to the Nth stage of the gate driving unit in the first set of gate driving circuits is connected to the same gate line as the output terminal of the output control module corresponding to the Nth stage of the gate driving unit in the second set of gate driving circuits, where N is an integer greater than or equal to 1. The driving method for the display panel includes: The output control module outputs a high-impedance state when it receives a fault enable signal, thus isolating the gate drive unit of this stage from the corresponding gate line.

[0014] Optionally, the display panel further includes a display driver chip and an address decoder, and the gate driving circuit further includes a combinational logic unit. The input terminal of the combinational logic unit is connected to the output terminal of the gate driving unit, the first output terminal of the combinational logic unit is connected to the input terminal of the output control module, and the second output terminal of the combinational logic unit is connected to the control terminal of the output control module. The driving method for the display panel further includes: The address decoder is controlled to decode the row address data sent by the display driver chip and output a row configuration signal to the combinational logic unit; the row configuration signal includes a row fault configuration signal and / or a row non-fault configuration signal. The control module that outputs a high-impedance state when it receives a fault enable signal, isolating the gate drive unit of this stage from the corresponding gate line, includes: The combinational logic units marked as fault rows in the first group of gate drive circuits and the second group of gate drive circuits are respectively controlled to output fault enable signals according to the row fault configuration signals. The output control module outputs a high impedance state according to the fault enable signals to isolate the gate drive unit of this stage from the corresponding gate line.

[0015] Optionally, the driving method for the display panel further includes: The combinational logic units in the first group of gate drive circuits and the second group of gate drive circuits that are not marked as faulty rows output non-fault enable signals according to the row non-fault configuration signal. The output control module turns on according to the non-fault enable signal, thus turning on the gate drive unit and the corresponding gate line of this stage.

[0016] The technical solution provided by this invention isolates the faulty gate drive unit from its corresponding gate line by setting an output control module on the output side of each cascaded gate drive unit. This output control module outputs a high-impedance state upon receiving a fault enable signal. In a dual-sided driven display panel, when a fault occurs in a row of gate drive units on one side of the gate drive circuit, only the corresponding output control module needs to be set to a high-impedance state to block the transmission of the gate drive signal, without shutting down the entire gate drive circuit on that side. Furthermore, the gate line connected to the output control module in the high-impedance state is not affected by the signal input from the high-impedance output control module, ensuring the stability of the signal on that gate line. In high-resolution display panels, such as 2.5K or 4K and above resolution panels, the display difference caused by changing the driving force of a single row from dual-sided to single-sided driving is not perceptible to the human eye. Compared to shutting down the entire single-sided gate drive circuit, this significantly improves product yield. This solution can isolate the faulty gate drive unit on only one side and one row, which greatly improves the uneven display problem caused by the failure of the gate drive circuit on one side of the entire display panel. The other rows that are not faulty and the gate drive circuit on the other side can be used normally, thus preserving the effective driving capability of the panel to the greatest extent and significantly improving the product yield.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention; Figure 7 A flowchart illustrating a driving method for a display panel provided in an embodiment of the present invention; Figure 8 A flowchart of another display panel driving method provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention, with reference to... Figure 1 The gate drive circuit 10 includes multiple cascaded gate drive units 101. Each stage of the gate drive unit 101 has an output control module 102 between its output terminal and the gate line GL. The output control module 102 is used to output a high impedance state when a fault enable signal is received, so as to isolate the current stage of the gate drive unit 101 from the corresponding gate line GL.

[0023] Display panels typically include a gate drive circuit 10 and a pixel circuit. The gate drive circuit generates a gate drive signal and transmits the gate drive signal to the pixel circuit through the gate line GL to control the on / off state of the transistors in the pixel circuit. The pixel circuit drives the light-emitting element to emit light, thereby realizing the display function.

[0024] Figure 2This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, with reference to... Figure 1 and Figure 2 The display panel includes two sets of gate driving circuits, namely a first set of gate driving circuit 11 and a second set of gate driving circuit 12. The same level gate driving unit 101 in the first set of gate driving circuit 11 and the second set of gate driving circuit 12 is connected to the same gate line DL. When the display panel is working normally, the first set of gate driving circuit 11 and the second set of gate driving circuit 12 work together to provide gate driving signals to the same row of pixel circuits, thereby realizing bilateral driving.

[0025] In this embodiment, the output terminal of each stage gate driving unit 101 of each group of gate driving circuits 10 is connected to an output control module 102. When a fault occurs in a certain stage of the gate driving circuit 10, the output control module 102 can be enabled to output a high-impedance state, isolating the faulty gate driving unit 101 from the gate line GL, thereby blocking the transmission of the gate driving signal to the corresponding gate line GL. This prevents the faulty unit from pulling up or down the potential of the gate line GL, avoiding its abnormal output from adversely affecting the display. For the gate driving unit 101 that has not failed, the corresponding output control module 102 is turned on to transmit the gate driving signal normally to the corresponding gate line GL.

[0026] In the event of a single-side, single-row gate drive unit 101 failure, existing technologies typically use an enable signal to shut down all gate drive units 101 on the side containing the faulty row, switching the display panel to a single-side drive mode driven only by the gate drive circuit 10 on the other side. While this repair method isolates the fault, it causes the drive load on the other side to double instantaneously, affecting display uniformity and forcing all normally functioning gate drive units 101 in the gate drive circuit 10 on the side containing the faulty row to stop operating. This significantly reduces the success rate of display panel repair and the final yield. For high-resolution, large-size panels, single-side drive often fails to meet charging requirements, potentially leading to product degradation or even scrapping, reducing expected profits.

[0027] The technical solution provided by this invention provides an output control module 102 on the output side of each cascaded gate drive unit 101. By controlling the output control module 102 to output a high-impedance state when a fault enable signal is received, the faulty gate drive unit 101 is isolated from the corresponding gate line GL. In a dual-sided driven display panel, when a fault occurs in a row of gate drive units 101 in a gate drive circuit 10 on one side, only the corresponding output control module 102 needs to be set to a high-impedance state to block the transmission of the gate drive signal, without shutting down the entire gate drive circuit 10 on that side. Furthermore, the gate line GL connected to the output control module 102 in the high-impedance state will not be affected by the signal input to the output control module 102 in the high-impedance state, ensuring the stability of the signal on that gate line GL. In high-resolution display panels, such as 2.5K or 4K and above resolution display panels, the display difference caused by the change from dual-sided driving to single-sided driving is not perceptible to the human eye during use. Compared to shutting down the entire single-sided gate drive circuit 10, this significantly improves the product yield. This solution can isolate the faulty gate drive unit 101 on only one side and one row, which greatly improves the uneven display problem caused by the failure of the gate drive circuit on one side of the entire display panel. Other unfaulty rows and the gate drive circuit 10 on the other side can be used normally, thus preserving the effective driving capability of the panel to the greatest extent and significantly improving the product yield.

[0028] Figure 3 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention, with reference to... Figure 3 Optionally, based on the above embodiments, the gate drive circuit 10 further includes a combinational logic unit 103.

[0029] The input terminal of combinational logic unit 103 is connected to the output terminal of gate driving unit 101. The first output terminal of combinational logic unit 103 is connected to the input terminal of output control module 102. The second output terminal of combinational logic unit 103 is connected to the control terminal of output control module 102. The output terminal of output control module 102 is connected to gate line GL. Combinational logic unit 103 is used to perform logical operations on the output signal of gate driving unit 101, output a gate driving signal from its first output terminal, and output a fault enable signal from its second output terminal according to the received row fault configuration signal.

[0030] The combinational logic unit 103 is also used to output a non-fault enable signal from its second output terminal according to the received row non-fault configuration signal, and the output control module 102 is also used to turn on according to the non-fault enable signal.

[0031] Specifically, the combinational logic unit 103 receives the row configuration signal FA and outputs a fault enable signal or a non-fault enable signal based on the received row configuration signal FA. The row configuration signal contains the row address corresponding to each level of gate drive unit 101, as well as the configuration information (e.g., high level or low level) to be given to the combinational logic unit 103 corresponding to that row gate drive unit 101. The output control module 102 turns off in response to the fault enable signal or turns on in response to the non-fault enable signal. The row configuration signal includes a row fault configuration signal and a row non-fault configuration signal. The row fault configuration signal is used to characterize the row address and fault configuration information corresponding to the gate drive unit with a fault, and the row non-fault configuration signal is used to characterize the row address and non-fault configuration information corresponding to the gate drive unit without a fault.

[0032] In this embodiment, the configuration information refers to the control signal used to control the output control module 102. For example, the configuration information includes fault configuration information and non-fault configuration information. A low level of the control signal represents fault configuration information, and a high level of the control signal represents non-fault configuration information. That is, the row configuration signal includes the row address of each level of gate drive unit 101 and the control signal corresponding to the output control module to which each level of gate drive unit 101 is connected.

[0033] Optionally, in this embodiment, the row configuration signal FA can be an address transmitted from the display driver chip, decoded, and returned to the gate drive circuit. The row configuration signal FA contains the row address and configuration information. By configuring the combinational logic unit 103, when both the input row address and fault configuration information point to the current row, the combinational logic unit 103 corresponding to the current row outputs a fault enable signal to the control terminal of the corresponding output control module 102, thereby controlling the output control module 102 to isolate the gate drive signal transmission to the gate line GL. When both the input row address and non-fault configuration information point to the current row, the combinational logic unit 103 corresponding to the current row outputs a non-fault enable signal to the corresponding output control module 102, thereby controlling the output control module 102 to allow the gate drive signal transmission to the gate line GL.

[0034] Figure 4 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention, with reference to... Figure 4 The row configuration signal can also be directly transmitted to the control terminal of the output control module 102 without going through the logic operation of the combinational logic unit 103. The control terminal of the output control module 102 is connected to the row configuration signal FA.

[0035] Specifically, the input terminal of the combinational logic unit 103 is connected to the output terminal of the gate driving unit 101, the output terminal of the combinational logic unit 103 is connected to the input terminal of the output control module 102, and the output terminal of the output control module 102 is connected to the gate line GL. The combinational logic unit 103 is used to perform logical operations on the output signal of the gate driving unit 101 and output the gate driving signal. The output control module 102 uses the row fault configuration signal connected to its own control terminal as the fault enable signal. The output control module 102 is also used to use the row non-fault configuration signal connected to its own control terminal as the non-fault enable signal and turn on according to the non-fault enable signal.

[0036] In this embodiment, the output control module 102 directly responds to the row configuration signal FA received from its own control terminal to enable output. For example, if the row configuration signal FA is a row fault configuration signal, the output control module 102 uses the received row fault configuration signal as a fault enable signal and directly enables the high-impedance output state. If the row configuration signal FA is a row non-fault configuration signal, the output control module 102 uses the received row non-fault configuration signal as a non-fault enable signal, and its output is determined by its own input.

[0037] Here, the input position of the row configuration signal FA is related to the internal structure of the combinational logic unit and also to the type of the row configuration signal FA. The specific design can be carried out according to the actual situation.

[0038] In one optional implementation of this embodiment, the output control module 102 includes a tri-state gate. The input terminal of the tri-state gate is connected to the combinational logic unit 103, and the output terminal of the tri-state gate is connected to the gate line GL. The control terminal of the tri-state gate is connected to a fault enable signal or a non-fault enable signal. The tri-state gate outputs a high-impedance state in response to the fault enable signal and turns on in response to the non-fault enable signal.

[0039] The tri-state gate has three output states: logic 1 (high level), logic 0 (low level), and high impedance. When the control terminal of the tri-state gate is low, its output is in the high impedance state regardless of its input terminal; when the control terminal of the tri-state gate is high, its output is either logic 1 or logic 0, depending on the input state.

[0040] When the tri-state gate connected to the Nth-level gate driving unit 101 in a certain group of gate driving circuits 10 is in a high-impedance state, regardless of how the output signal of the Nth-level gate driving unit 101 changes, the level of the corresponding gate line GL is completely determined by the Nth-level gate driving unit 101 in another group of gate driving circuits 10. For example, when the Nth-level gate driving unit 101 (corresponding to the Nth row of pixels) in the first group of gate driving circuits 11 malfunctions, the row address of the gate driving unit 101 in the group of gate driving circuits 10 is sent by the display driver chip. The gate driving circuit 10 obtains the faulty row address information of the gate driving unit 101, and controls the corresponding tri-state gate to be in a high-impedance state through the combinational logic unit 103 of the corresponding row, thereby cutting off (turning off) the Nth-level gate driving unit 101 in the first group of gate driving circuits 11, and the corresponding gate line GL is driven by the Nth-level gate driving unit 101 in the second group of gate driving circuits 12.

[0041] In this embodiment, the fault enable signal or the non-fault enable signal is only used to control the tri-state gate. Since the tri-state gate is located at the rear end of the gate drive unit 101, the fault enable signal or the non-fault enable signal will not affect the cascade carry signal between the cascaded gate drive units 101 in the gate drive circuit 10, so as to ensure that the cascade relationship between the non-fault rows is not affected.

[0042] Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention, with reference to... Figure 5 Based on the above embodiments, optionally, a drive buffer 104 may be further included in the connection path between any combinational logic unit 103 and the output control module 102. The input terminal of the drive buffer 104 is connected to the combinational logic unit 103, and the output terminal of the drive buffer 104 is connected to the input terminal of the output control module 102. The drive buffer 104 is used to improve the driving capability of the gate drive signal to ensure the working stability of the display panel.

[0043] Optionally, the specific structure of the gate driving unit 101 can be found in the description in the relevant art, and will not be repeated here.

[0044] The technical solution provided by the embodiments of the present invention isolates only the faulty gate driving unit 101 on that side and row by combining the logic unit 103 and the output control module 102, while retaining the normal operation of all other gate driving units 101 on that side, thereby maximizing the preservation of the effective driving capability of the display panel and improving the product delivery yield.

[0045] Optionally, embodiments of the present invention also provide a display panel, which includes two sets of gate driving circuits as provided in any of the above embodiments. This display panel can be applied to electronic devices with display functions, such as mobile phones, tablets, televisions, and computers. (Refer to the references...) Figure 1 and Figure 2 The first group of gate driving circuits 11 and the second group of gate driving circuits 12 are located on opposite sides of the display panel. The output terminal of the output control module 102 corresponding to the Nth level gate driving unit 101 in the first group of gate driving circuits 11 is connected to the same gate line GL as the output terminal of the output control module 102 corresponding to the Nth level gate driving unit 101 in the second group of gate driving circuits 12. N is an integer greater than or equal to 1.

[0046] Figure 6 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 3 and Figure 6 The gate driving circuit 10 also includes a combinational logic unit 103. The input terminal of the combinational logic unit 103 is connected to the output terminal of the gate driving unit 101. The first output terminal of the combinational logic unit 103 is connected to the input terminal of the output control module 102. The second output terminal of the combinational logic unit 103 is connected to the control terminal of the output control module 102. The output terminal of the output control module 102 is connected to the gate line GL. The display panel also includes a display driver chip 20 and an address decoder 30. The address decoder 30 is used to decode the row address output by the display driver chip 20, and to determine whether there is a gate driving unit 101 marked with a fault based on the decoded row address. It also transmits a row fault configuration signal to the combinational logic unit 103 corresponding to the gate driving unit 101 marked with a fault, and transmits a row non-fault configuration signal to the combinational logic unit 103 corresponding to the gate driving unit 101 not marked with a fault.

[0047] Specifically, the address decoder 30 can decode the address input from the display driver chip 20 and send it to the corresponding row for control via the combinational logic unit 103. For example, if the total number of rows in the pixel circuit is 2000, the display driver chip will output a 22-bit data after power-on. This 22-bit data will be divided into two parts: <0:10> and <11:21>, corresponding to the first group of gate driving circuits 11 and the second group of gate driving circuits 12, respectively. After receiving this 22-bit data, the address decoder 30 will decode these two groups of 11-bit data, corresponding to each stage of the gate driving unit 101 in the first group of gate driving circuits 11 and the second group of gate driving circuits 12, respectively. If the fault behavior is row 1024 in the first group of gate drive circuits 11, the address decoder 30 will pull the 1024th data in <0:10> low (fault configuration information) and write it into the combinational logic unit 103 corresponding to row 1024 in the first group of gate drive circuits 11, so as to control the tri-state gate corresponding to that row to output a high impedance state, while the other gate drive units 101 normally conduct the corresponding tri-state gates (non-fault configuration information). At this time, the logic of the gate drive signal in row 1024 is driven unilaterally by the second gate drive circuit 12.

[0048] Alternatively, refer to Figure 4 and Figure 6 The input terminal of the combinational logic unit 103 is connected to the output terminal of the gate driving unit 101, the output terminal of the combinational logic unit 103 is connected to the input terminal of the output control module 102, and the output terminal of the output control module 102 is connected to the gate line GL. The address decoder 30 is used to transmit a row fault configuration signal to the output control module 102 corresponding to the gate driving unit 101 that is marked as faulty, and to transmit a row non-fault configuration signal to the output control module 102 corresponding to the gate driving unit 101 that is not marked as faulty.

[0049] The technical solution provided by this invention, in the event of damage to a single-side, single-row gate driving unit 101, decodes the row address transmitted from the display driver chip 20 using the address decoder 30, determines the row address and configuration information of the marked faulty gate driving unit 101, and uses the combinational logic unit 103 to set the corresponding tri-state gate to a high-impedance state to block the transmission of the gate driving signal to the gate line GL. This achieves isolation of the faulty gate driving unit 101 on only one side and one row, without needing to cut off the entire side's gate driving circuit 10, which improves display uniformity and shipment yield, and reduces costs. Furthermore, the combined design of the combinational logic unit 103, the address decoder 30, and the display driver chip 20 allows for software or hardware configuration of fault isolation at the module level or even at the end-user end, increasing repair flexibility and improving product yield.

[0050] Continue to refer to Figure 6 Optionally, the display panel includes a display area AA and a non-display area NA that is at least partially surrounding the display area AA. The first set of gate driving circuits 11, the second set of gate driving circuits 12, the display driver chip 20, and the address decoder 30 are all located in the non-display area NA. For example, the non-display area NA includes a left border area, a right border area, a top border area, and a bottom border area. The first set of gate driving circuits 11 can be located in the left border area, the second set of gate driving circuits 12 can be located in the right border area, and the address decoder 30 and the display driver chip 20 can be located in the bottom border area. The gate driving circuits 10 on the left and right sides work together to provide gate driving signals to the same row of pixel circuits simultaneously, ensuring the uniformity of charging and the reliability of driving, which is especially suitable for large-size display panels.

[0051] Optionally, the display panel also includes multiple pixel circuits located within the display area AA, with gate lines GL connected to the pixel circuits.

[0052] Optionally, the present invention also provides a driving method for a display panel, which can be applied to the display panel provided in any of the above embodiments. Figure 7 A flowchart of a display panel driving method provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 7 and Figure 1 The driving method includes: S110, When the control output module receives a fault enable signal, it outputs a high impedance state to isolate the gate drive unit of this stage from the corresponding gate line.

[0053] The technical solution provided by this invention provides an output control module 102 on the output side of each cascaded gate drive unit 101. By controlling the output control module 102 to output a high-impedance state when a fault enable signal is received, the faulty gate drive unit 101 is isolated from the corresponding gate line GL. In a dual-side driven display panel, when a fault occurs in a row of gate drive units 101 in a gate drive circuit 10 on one side, only the corresponding output control module 102 needs to be set to a high-impedance state to block the transmission of the gate drive signal, without shutting down the entire gate drive circuit 10 on that side. Furthermore, the gate line GL connected to the output control module 102 in the high-impedance state will not be affected by the signal input to the output control module 102 in the high-impedance state, ensuring the stability of the signal on that gate line GL. In high-resolution display panels, such as 2.5K or 4K and above resolution display panels, the display difference caused by the change from dual-side driving to single-side driving is not perceptible to the human eye during use. Compared to shutting down the entire single-side gate drive circuit, this significantly improves the product yield. This solution can isolate the faulty gate drive unit 101 on only one side and one row, which greatly improves the uneven display problem caused by the failure of the gate drive circuit on one side of the entire display panel. Other unfaulty rows and the gate drive circuit 10 on the other side can be used normally, thus preserving the effective driving capability of the panel to the greatest extent and significantly improving the product yield.

[0054] Figure 8 A flowchart of another display panel driving method provided in an embodiment of the present invention is shown in the reference. Figure 6 and Figure 8 The driving method provided in this embodiment includes: S210, the control address decoder decodes the row address data sent by the display driver chip and outputs row configuration signals to the combinational logic unit; the row configuration signals include row fault configuration signals and / or row non-fault configuration signals.

[0055] Before the display panel is lit, the display driver chip 20 sends the fault row address of the gate driving unit 101. The address decoder 30 decodes the row fault address sent by the display driver chip 20 and confirms whether there is a row address marked as faulty. The address decoder 30 outputs the corresponding row configuration signal according to the received row address data.

[0056] S1101: Control the combinational logic units marked as fault rows in the first group of gate drive circuits and the second group of gate drive circuits respectively to output fault enable signals according to the row fault configuration signals. The output control module outputs a high impedance state according to the fault enable signals to isolate the gate drive unit of this stage from the corresponding gate line.

[0057] Combination Figure 3 The address decoder 30 outputs the decoded faulty row address to the combinational logic unit 103 for that row. For the faulty row, the control combinational logic unit 103 sends a fault enable signal to the tri-state gate according to the row configuration signal, causing the tri-state gate to be in a high-impedance state to isolate the local gate drive unit 101 from the corresponding gate line GL. Here, the row configuration signal of the faulty row contains fault configuration information.

[0058] S1102: Control the combinational logic units in the first group of gate drive circuits and the second group of gate drive circuits that are not marked as faulty rows to output non-fault enable signals according to the row non-fault configuration signals. The output control module turns on according to the non-fault enable signals, and turns on the gate drive unit of this stage and the corresponding gate line.

[0059] Combination Figure 3 The address decoder 30 outputs the decoded non-faulty row address to the combinational logic unit 103 of that row. For a non-faulty row, the control combinational logic unit 103 sends a non-faulty enable signal to the tri-state gate according to the row configuration signal, causing the tri-state gate to conduct, thereby allowing the gate drive signal to be transmitted to the corresponding gate line GL, and the display panel performs bilateral driving. Here, the row configuration signal of the non-faulty row contains non-faulty configuration information.

[0060] In this embodiment, when the Nth row marked as a faulty row is scanned, the combinational logic unit 103 corresponding to the Nth row in the first group of gate driving circuits 11 determines that the row is faulty and controls the tri-state gate of the Nth row in the first group of gate driving circuits 11 to output a high-impedance state, so that the output of the Nth level gate driving unit 101 in the first group of gate driving circuits 11 is disconnected from the gate line GL, and the Nth level gate driving unit 101 in the second group of gate driving circuits 12 outputs normally.

[0061] When scanning to other rows (such as row N+1), the combinational logic unit 103 corresponding to row N+1 in the first group of gate driving circuits 11 determines that the row is not faulty and controls the tri-state gate of row N+1 in the first group of gate driving circuits 11 to be turned on, so that the gate driving unit 101 of stage N+1 in the first group of gate driving circuits 11 outputs normally, and the gate driving unit 101 of stage N in the second group of gate driving circuits 12 outputs normally, realizing bilateral driving. The above steps are repeated until all rows are scanned.

[0062] The specific working principle of the display panel can be found in the relevant descriptions in the above embodiments, and will not be repeated here.

[0063] Optionally, for the scheme where the row configuration signal FA output by the address decoder 30 is directly transmitted to the control terminal of the output control module 102, the specific working principle can be referred to the relevant descriptions in the above embodiments, and will not be repeated here.

[0064] The technical solution provided in this embodiment, in a dual-sided driven display panel, allows for the setting of the coordinates of the faulty row in a gate driving unit 101 within the gate driving circuit 10 on one side when a fault occurs. This coordinates are then sent to the address decoder 30, which locates the faulty row and sends a control signal to the output control module 102 of that row. This causes the module to output a high-impedance state, blocking the transmission of the gate driving signal, without needing to shut down the entire gate driving circuit 10 on that side. Furthermore, the gate line GL connected to the output control module 102 in the high-impedance state is not affected by the signal input to the high-impedance output control module 102, ensuring the stability of the signal on that gate line GL.

[0065] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0066] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gate driving circuit, characterized in that, It includes multiple cascaded gate driving units. Each stage of the gate driving unit has an output control module between its output terminal and the gate line. The output control module is used to output a high impedance state when a fault enable signal is received, so as to isolate the gate driving unit of this stage from the corresponding gate line.

2. The gate driving circuit according to claim 1, characterized in that, The gate drive circuit also includes a combinational logic unit; The input terminal of the combinational logic unit is connected to the output terminal of the gate driving unit, the first output terminal of the combinational logic unit is connected to the input terminal of the output control module, the second output terminal of the combinational logic unit is connected to the control terminal of the output control module, the output terminal of the output control module is connected to the gate line, the combinational logic unit is used to perform logical operations on the output signal of the gate driving unit, output a gate driving signal from its own first output terminal, and output the fault enable signal from its own second output terminal according to the received row fault configuration signal; The combinational logic unit is further configured to output a non-fault enable signal from its second output terminal according to the received row non-fault configuration signal, and the output control module is further configured to turn on according to the non-fault enable signal. The row fault configuration signal is used to characterize the row address and fault configuration information corresponding to the gate driving unit with a fault, and the row non-fault configuration signal is used to characterize the row address and non-fault configuration information corresponding to the gate driving unit without a fault.

3. The gate driving circuit according to claim 1, characterized in that, The gate drive circuit also includes a combinational logic unit; The input terminal of the combinational logic unit is connected to the output terminal of the gate driving unit, the output terminal of the combinational logic unit is connected to the input terminal of the output control module, the output terminal of the output control module is connected to the gate line, the combinational logic unit is used to perform logical operations on the output signal of the gate driving unit and output the gate driving signal, and the output control module uses the row fault configuration signal connected to its own control terminal as the fault enable signal. The output control module is also used to use the row non-fault configuration signal accessed by its own control terminal as a non-fault enable signal, and to turn on according to the non-fault enable signal. The row fault configuration signal is used to characterize the row address and fault configuration information corresponding to the gate driving unit with a fault, and the row non-fault configuration signal is used to characterize the row address and non-fault configuration information corresponding to the gate driving unit without a fault.

4. The gate driving circuit according to claim 2 or 3, characterized in that, The output control module includes a tri-state gate. The input of the tri-state gate is connected to the combinational logic unit, and the output of the tri-state gate is connected to the gate line. The control terminal of the tri-state gate is connected to the fault enable signal or the non-fault enable signal. The tri-state gate outputs a high-impedance state in response to the fault enable signal, or turns on in response to the non-fault enable signal.

5. The gate driving circuit according to claim 2 or 3, characterized in that, The connection path between any one of the combinational logic units and the output control module also includes a drive buffer, the input of which is connected to the combinational logic unit, and the output of which is connected to the input of the output control module.

6. A display panel, characterized in that, It includes two sets of gate driving circuits as described in any one of claims 1-5, wherein the first set of gate driving circuits and the second set of gate driving circuits are respectively located on opposite sides of the display panel, and the output terminal of the output control module corresponding to the Nth level gate driving unit in the first set of gate driving circuits is connected to the same gate line as the output terminal of the output control module corresponding to the Nth level gate driving unit in the second set of gate driving circuits, where N is an integer greater than or equal to 1.

7. The display panel according to claim 6, characterized in that, The gate driving circuit further includes a combinational logic unit. The input terminal of the combinational logic unit is connected to the output terminal of the gate driving unit. The first output terminal of the combinational logic unit is connected to the input terminal of the output control module. The second output terminal of the combinational logic unit is connected to the control terminal of the output control module. The output terminal of the output control module is connected to the gate line. The display panel further includes a display driver chip and an address decoder. The address decoder is used to decode the row address output by the display driver chip, and to determine whether there is a gate driving unit marked with a fault based on the decoded row address. It also transmits a row fault configuration signal to the combinational logic unit corresponding to the gate driving unit marked with a fault, and transmits a row non-fault configuration signal to the combinational logic unit corresponding to the gate driving unit not marked with a fault. Alternatively, the input terminal of the combinational logic unit is connected to the output terminal of the gate driving unit, the output terminal of the combinational logic unit is connected to the input terminal of the output control module, the output terminal of the output control module is connected to the gate line, and the address decoder is used to transmit a row fault configuration signal to the output control module corresponding to the gate driving unit that is marked as faulty, and to transmit a row non-fault configuration signal to the output control module corresponding to the gate driving unit that is not marked as faulty.

8. The display panel according to claim 7, characterized in that, The display panel includes a display area and a non-display area that is at least partially arranged around the display area, wherein the first group of gate driving circuits, the second group of gate driving circuits, the display driver chip and the address decoder are all located in the non-display area; The display panel also includes a plurality of pixel circuits located within the display area, and the gate line is connected to the pixel circuits.

9. A driving method for a display panel, characterized in that, The display panel includes two sets of gate driving circuits, each gate driving circuit including multiple cascaded gate driving units. Each stage of the gate driving unit is provided with an output control module between it and the gate line. The output terminal of the output control module corresponding to the Nth stage of the gate driving unit in the first set of gate driving circuits is connected to the same gate line as the output terminal of the output control module corresponding to the Nth stage of the gate driving unit in the second set of gate driving circuits, where N is an integer greater than or equal to 1. The driving method for the display panel includes: The output control module outputs a high-impedance state when it receives a fault enable signal, thus isolating the gate drive unit of this stage from the corresponding gate line.

10. The driving method for a display panel according to claim 9, characterized in that, The display panel further includes a display driver chip and an address decoder. The gate driving circuit further includes a combinational logic unit. The input terminal of the combinational logic unit is connected to the output terminal of the gate driving unit. The first output terminal of the combinational logic unit is connected to the input terminal of the output control module. The second output terminal of the combinational logic unit is connected to the control terminal of the output control module. The driving method for the display panel further includes: The address decoder is controlled to decode the row address data sent by the display driver chip and output a row configuration signal to the combinational logic unit; the row configuration signal includes a row fault configuration signal and / or a row non-fault configuration signal. The control module that outputs a high-impedance state when it receives a fault enable signal, isolating the gate drive unit of this stage from the corresponding gate line, includes: The combinational logic units marked as fault rows in the first group of gate drive circuits and the second group of gate drive circuits are respectively controlled to output fault enable signals according to the row fault configuration signals. The output control module outputs a high impedance state according to the fault enable signals to isolate the gate drive unit of this stage from the corresponding gate line.

11. The driving method for a display panel according to claim 10, characterized in that, The driving method for the display panel further includes: The combinational logic units in the first group of gate drive circuits and the second group of gate drive circuits that are not marked as faulty rows output non-fault enable signals according to the row non-fault configuration signal. The output control module turns on according to the non-fault enable signal, thus turning on the gate drive unit and the corresponding gate line of this stage.

Images