Array substrate, display panel and display device

Abstract

The application provides an array substrate, a display panel and a display device. The array substrate comprises a plurality of longitudinally spaced scan lines, a plurality of transversely spaced data lines, a voltage compensation line and a plurality of pixel units arranged in an array. The scan lines are connected with a row of pixel units, the data lines are connected with a column of pixel units, and each pixel unit comprises a pixel capacitor and a compensation unit. The compensation unit is connected with the pixel capacitor, and the voltage compensation line is connected with the compensation unit in a column of pixel units. The compensation unit in the nth row of pixel units is connected with the nth+m scan line, and the compensation unit in the nth+m row of pixel units is connected with the nth scan line. Thus, the problem of electric leakage is solved, and the display effect is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] With the smallest pixel driving unit of OLED displays, such as Figure 1 As shown, T1 is a data control switch, responsible for charging and discharging the capacitor; T2 is a drive control TFT, responsible for controlling the current reaching the OLED, thereby controlling the brightness of the OLED; and T3 is a sensing TFT, used to detect the current flowing through T2 or the potential of the anode of the OLED device, thereby calculating the threshold voltage of T2.

[0003] However, T1 is not an ideal device and will exhibit leakage current when switched off, such as... Figure 2 As shown, Figure 2 Given the characteristic range of T1, it can be seen that no matter what the gate voltage Vg is, Id (the current between the source and drain) is not zero. This causes the ideal device, which was originally intended to have no leakage, to have continuous leakage in practice, resulting in inaccurate screen display. Summary of the Invention

[0004] This invention mainly provides an array substrate, a display panel, and a display device, which can solve the T1 leakage problem and improve the display effect.

[0005] To solve the above-mentioned technical problems, the first technical solution adopted by the present invention is: to provide an array substrate, including: multiple vertically spaced scan lines, multiple horizontally spaced data lines, voltage compensation lines, and multiple pixel units arranged in an array; wherein, the scan lines are connected to a row of pixel units, the data lines are connected to a column of pixel units, and the pixel unit includes: a pixel capacitor and a compensation unit, the compensation unit is connected to the pixel capacitor, and the voltage compensation line is connected to the compensation unit in a column of pixel units; The compensation unit in the pixel unit of the nth row is connected to the (n+m)th scan line, and the compensation unit in the pixel unit of the (n+m)th row is connected to the nth scan line.

[0006] In one embodiment, the compensation unit includes: a compensation switch; The first terminal of the compensation switch is connected to the voltage compensation line, and the second terminal of the compensation switch is connected to the pixel capacitor. In the pixel unit of the nth row, the control terminal of the compensation switch is connected to the (n+m)th scan line; in the pixel unit of the (n+m)th row, the control terminal of the compensation switch is connected to the nth scan line.

[0007] In one embodiment, each pixel unit further includes: Light-emitting elements; The voltage writing unit has a voltage receiving terminal connected to a data line for the voltage writing unit corresponding to a column of pixel units, a control terminal connected to a scan line for the voltage writing unit corresponding to a row of pixel units, and a voltage writing terminal connected to the pixel capacitor of the pixel unit for the voltage writing unit corresponding to each pixel unit. The driving unit has a voltage receiving terminal that receives the power supply voltage and is connected to the first terminal of the pixel capacitor. The control terminal of the driving unit is connected to the second terminal of the pixel capacitor, and the voltage driving terminal of the driving unit is connected to the light-emitting element. The reset detection unit has its voltage detection terminal connected to the detection line, its control terminal connected to the corresponding scan line, and its voltage output terminal connected to the light-emitting element.

[0008] In one embodiment, in response to enabling the nth scan line, the voltage writing unit in the nth row pixel unit is in a working state, and the data line charges the pixel capacitor in the nth row pixel unit using the data voltage; and the compensation unit in the (n+m)th row pixel unit is in a working state, and the voltage compensation line performs voltage compensation for the pixel capacitor in the (n+m)th row pixel unit using the first compensation voltage; at the same time, the reset detection unit in the nth row pixel unit is in a working state, and performs reset detection on the nth row pixel unit.

[0009] In one embodiment, the first compensation voltage is the data voltage of the pixel unit in the (n+m)th row of the previous frame of the current display frame.

[0010] In one embodiment, in response to enabling the (n+m)th scan line, the voltage writing unit in the (n+m)th row pixel unit is in an active state, and the data line charges the pixel capacitor in the (n+m)th row pixel unit using the data voltage; and the compensation unit in the nth row pixel unit is in an active state, and the voltage compensation line performs voltage compensation for the pixel capacitor in the nth row pixel unit using the second compensation voltage; at the same time, the reset detection unit in the (n+m)th row pixel unit is in an active state, and performs reset detection on the (n+m)th row pixel unit.

[0011] In one embodiment, the second compensation voltage is the data voltage of the nth row pixel unit of the current display frame.

[0012] In one embodiment, m is determined based on the number of rows of pixel units on the array substrate; where m∈[1, P / 2]; or, m=P / 2, where P is the number of rows of pixel units on the array substrate.

[0013] To solve the above-mentioned technical problems, the second technical solution adopted by the present invention is to provide a display panel, including an array substrate of any one of the above-mentioned components.

[0014] To solve the above-mentioned technical problems, the third technical solution adopted by the present invention is: to provide a display device, comprising: An array substrate, wherein the array substrate comprises any one of the array substrates described above; A driving circuit for driving the array substrate.

[0015] The beneficial effects of this invention are as follows: Unlike existing technologies, the array substrate provided by this invention includes: multiple vertically spaced scan lines, multiple horizontally spaced data lines, voltage compensation lines, and multiple pixel units arranged in an array. Each scan line is connected to a row of pixel units, and each data line is connected to a column of pixel units. Each pixel unit includes a pixel capacitor and a compensation unit, with the compensation unit connected to the pixel capacitor. The voltage compensation line is connected to the compensation unit in a column of pixel units. Furthermore, the compensation unit in the nth row of pixel units is connected to the (n+m)th scan line, and the compensation unit in the (n+m)th row of pixel units is also connected to the nth scan line. Because the compensation unit in the nth row of pixel units is connected to the (n+m)th scan line, compensation can be simultaneously provided for the (n+m)th row of pixel units during scanning charging and discharging, thereby solving the leakage problem and improving the display effect. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of the smallest pixel driving unit in OLED in related technologies; Figure 2 This is a schematic diagram of the characteristic range of T1; Figure 3 A schematic diagram of the structure of an embodiment of the array substrate provided in this application; Figure 4 This is a schematic diagram of the structure of a second embodiment of the array substrate provided in this application; Figure 5 A schematic diagram illustrating the scanning of the nth row and the compensation of the (n+m)th row of the array substrate provided in this application; Figure 6 A schematic diagram illustrating the scanning of the (n+m)th row and the compensation of the nth row of the array substrate provided in this application; Figure 7 A schematic diagram of the structure of the third embodiment of the array substrate provided in this application; Figure 8A schematic diagram of the structure of an embodiment of the display panel provided in this application; Figure 9 This is a schematic diagram of an embodiment of the display device provided in this application.

[0018] Explanation of reference numerals in the attached drawings: Array substrate 10, Scan line Gate, Data line Data, Voltage compensation line D, Pixel unit 11, Pixel capacitor C, Compensation unit 111, Compensation switch T4, Light-emitting element OLED, Voltage writing unit 112, Driving unit 113, Reset detection unit 114, First transistor T1, Second transistor T2, Third transistor T3, First switch Q1, Second switch Q2, Third switch Q3, Fourth switch Q4, Fifth switch Q5, Sixth switch Q6, Power supply voltage ELVDD, Display panel 30, Display device 40, Driving circuit 20. Detailed Implementation

[0019] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0020] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0021] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, "more" in this article means two or more objects.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0023] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0024] To enable those skilled in the art to better understand the technical solution of the present invention, the display device provided by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] See Figure 3 , Figure 3The diagram below shows the structure of the first embodiment of the array substrate provided in this application. The array substrate 10 includes multiple vertically spaced scan lines Gate (Gate1, Gate2, Gate3...), multiple horizontally spaced data lines Data (Data1, Data2, Data3...), voltage compensation lines D (D1, D2, D3...), and multiple pixel units 11 arranged in an array. The scan lines Gate are connected to a row of pixel units 11, and the data lines Data are connected to a column of pixel units 11.

[0026] Combination Figure 4 Pixel unit 11 includes a pixel capacitor C and a compensation unit 111. The compensation unit 111 is connected to the pixel capacitor C, and the voltage compensation line D is connected to the compensation unit 111 in a column of pixel units 11. Specifically, in this embodiment, the compensation unit 111 in the nth row of pixel units 11 is connected to the (n+m)th scan line Gate n+m, and the compensation unit 111 in the (n+m)th row of pixel units 11 is connected to the nth scan line Gate n. Thus, when the pixel units in the nth row are scanning and charging / discharging, compensation can be simultaneously provided for the pixel units in the (n+m)th row, thereby solving the leakage problem and improving the display effect.

[0027] In one specific embodiment, the compensation unit 111 includes a compensation switch T4. The first path terminal of the compensation switch T4 is connected to the voltage compensation line D, and the second path terminal of the compensation switch T4 is connected to the pixel capacitor C. In the pixel unit 11 of the nth row, the control terminal of the compensation switch T4 is connected to the (n+m)th scan line Gate n+m. In the pixel unit 11 of the (n+m)th row, the control terminal of the compensation switch T4 is connected to the nth scan line Gate n.

[0028] like Figure 4As shown, each pixel unit 11 further includes: an OLED light-emitting element, a voltage writing unit 112, a driving unit 113, and a reset detection unit 114. Specifically, the voltage receiving terminal of the voltage writing unit 112 corresponding to a column of pixel units 11 is connected to a data line Data, the control terminal of the voltage writing unit 112 corresponding to a row of pixel units 11 is connected to a scan line Gate, and the voltage writing terminal of the voltage writing unit 112 corresponding to each pixel unit 11 is connected to the pixel capacitor C of the pixel unit 11. The voltage receiving terminal of the driving unit 113 receives the power supply voltage ELVDD and is connected to the first terminal of the pixel capacitor C. The control terminal of the driving unit 113 is connected to the second terminal of the pixel capacitor C, and the voltage driving terminal of the driving unit 113 is connected to the OLED light-emitting element. The voltage detection terminal of the reset detection unit 114 is connected to the sensor line Sensor, the control terminal of the reset detection unit 114 is connected to the corresponding scan line Gate, and the voltage output terminal of the reset detection unit 114 is connected to the OLED light-emitting element.

[0029] like Figure 4 The pixel unit 11 shown includes a voltage writing unit 112 comprising a first transistor T1. The first path terminal of the first transistor T1 (i.e., the voltage receiving terminal of the voltage writing unit 112) is connected to the data line Data. The second path terminal of the first transistor T1 (i.e., the voltage writing terminal of the voltage writing unit 112) is connected to the second terminal of the pixel capacitor C. The control terminal of the first transistor T1 (i.e., the control terminal of the voltage writing unit 112) is connected to a scan line Gate.

[0030] The driving unit 113 includes a second transistor T2. The first path terminal of the second transistor T2 (i.e. the voltage receiving terminal of the driving unit 113) receives the power supply voltage ELVDD and is connected to the first terminal of the pixel capacitor C. The second path terminal of the second transistor T2 (i.e. the voltage driving terminal of the driving unit 113) is connected to the light-emitting element OLED. The control terminal of the second transistor T2 (i.e. the control terminal of the driving unit 113) is connected to the second terminal of the pixel capacitor C.

[0031] The reset detection unit 114 includes a third transistor T3. The first path terminal of the third transistor T3 (i.e., the voltage detection terminal of the reset detection unit 114) is connected to the detection line Sensor. The second path terminal of the third transistor T3 (i.e., the voltage output terminal of the reset detection unit 114) is connected to the light-emitting element OLED. The control terminal of the third transistor T3 (the control terminal of the reset detection unit 114) is connected to the corresponding scan line Gate.

[0032] In one specific embodiment, for the nth row pixel unit 11, the control terminal of the first transistor T1 is connected to the nth scan line Gate n, and the control terminal of the third transistor T3 is also connected to the nth scan line Gate n.

[0033] Specifically, when scanning the nth row, in response to the nth scan line Gate n being enabled, the voltage writing unit 112 in the nth row pixel unit 11 is in working state. At this time, the first transistor T1 is turned on, and the data line Data uses the data voltage Vdata to charge the pixel capacitor C in the nth row pixel unit 11. Simultaneously, the reset detection unit 114 in the nth row pixel unit 11 is in working state, and the third transistor T3 is turned on to perform reset detection on the nth row pixel unit 11. Since the control terminal of the compensation switch T4 in the (n+m)th row pixel unit 11 is connected to the nth scan line Gate n, when the nth scan line Gate n is enabled, the compensation unit 111 in the (n+m)th row pixel unit 11 is in working state. At this time, the compensation switch T4 is turned on, and the voltage compensation line D uses the first compensation voltage Vd1 to perform voltage compensation on the pixel capacitor C in the (n+m)th row pixel unit 11.

[0034] Specifically, in combination Figure 5 During the reset phase, the sensor is low, the nth scan line Gate n is enabled, and the third transistor T3 is turned on, pulling down the potential of the anode of the OLED in the nth row pixel unit 11 to clear residual charge from the previous frame and avoid ghosting and crosstalk. Simultaneously, the scan activation phase begins. Because the nth scan line Gate n is enabled, the first transistor T1 is turned on, selecting the current pixel unit 11, and the data line Data prepares to input the data voltage Vdata. During the charging phase, the data line Data inputs the data voltage Vdata to charge the pixel capacitor C. Furthermore, the scan activation phase of the nth row and the leakage compensation phase of the (n+m)th row pixel unit occur simultaneously. Because the nth scan line Gate n is enabled, the compensation switch T4 of the (n+m)th row pixel unit is turned on, and the voltage compensation line D uses the first compensation voltage Vd1 to compensate the pixel capacitor C in the (n+m)th row pixel unit 11. Then, the light-emitting stage begins. The voltage across the pixel capacitor C remains constant, and the source voltage of the second transistor T2 is raised by the power supply voltage ELVDD. At this time, the second transistor T2 is turned on, and the light-emitting element OLED continues to emit light.

[0035] Understandably, during the scan of the nth row, the first transistor T1, the second transistor T2, and the third transistor T3 in the nth row will be turned on, and the compensation switch T4 in the (n+m)th row will be turned on.

[0036] When scanning the (n+m)th row, in response to the (n+m)th scan line Gate n+m being enabled, the voltage writing unit 112 in the (n+m)th row pixel unit 11 is in working state. At this time, the first transistor T1 is turned on, and the data line Data charges the pixel capacitor C in the (n+m)th row pixel unit 11 using the data voltage Vdata. Simultaneously, the reset detection unit 114 in the (n+m)th row pixel unit 11 is in working state, and the third transistor T3 is turned on to perform reset detection on the (n+m)th row pixel unit 11. Since the compensation unit 111 in the nth row pixel unit 11 is connected to the (n+m)th scan line Gate n+m, when the (n+m)th scan line Gate n+m is enabled, the compensation unit 111 in the nth row pixel unit 11 is in working state. At this time, the compensation switch T4 is turned on, and the voltage compensation line D uses the second compensation voltage Vd2 to perform voltage compensation on the pixel capacitor C in the nth row pixel unit 11.

[0037] Specifically, in combination Figure 6 During the reset phase, the sensor is at a low level, the (n+m)th scan line Gate n is enabled, and the third transistor T3 is turned on, pulling down the potential of the anode of the OLED light-emitting element in the (n+m)th row pixel unit 11 to clear residual charge from the previous frame and avoid ghosting and crosstalk. Simultaneously, the scan activation phase begins. Since the (n+m)th scan line Gate n+m is enabled, the first transistor T1 is turned on, selecting the current pixel unit 11, and the data line Data prepares to input the data voltage Vdata. During the charging phase, the data line Data inputs the data voltage Vdata to charge the pixel capacitor C. Furthermore, the scan activation phase of the (n+m)th row and the leakage compensation phase of the nth row pixel unit occur simultaneously. Since the (n+m)th scan line Gate n+m is enabled, the compensation switch T4 of the nth row pixel unit is turned on, and the voltage compensation line D uses the second compensation voltage Vd2 to compensate the pixel capacitor C in the nth row pixel unit 11. Then, the light-emitting stage begins. The voltage across the pixel capacitor C remains constant, and the source voltage of the second transistor T2 is raised by the power supply voltage ELVDD. At this time, the second transistor T2 is turned on, and the light-emitting element OLED continues to emit light.

[0038] Understandably, during the scan of the nth row, the first transistor T1, the second transistor T2, and the third transistor T3 in the (n+m)th row will be turned on, and the compensation switch T4 in the nth row will also be turned on.

[0039] In one specific embodiment, the first compensation voltage Vd1 is the data voltage Vdata of the (n+m)th row pixel unit 11 in the previous frame of the current display frame. The second compensation voltage Vd2 is the data voltage Vdata of the nth row pixel unit in the current display frame.

[0040] It is understandable that when charging the nth row pixel unit 11, voltage compensation is simultaneously performed on the (n+m)th row pixel unit 11, and vice versa. Therefore, for the nth row pixel unit 11, charging comes first, followed by compensation; while for the (n+m)th row pixel unit 11, compensation comes first, followed by charging. Thus, for the nth row pixel unit 11, the leakage after charging is the data voltage Vdata of the current display frame. Therefore, the second compensation voltage Vd2 used when compensating the nth row pixel unit 11 is the data voltage Vdata of the nth row pixel unit in the current display frame. For the (n+m)th row pixel unit 11, the leakage before charging is the data voltage Vdata of the previous frame. Therefore, the first compensation voltage Vd1 used when compensating the (n+m)th row pixel unit 11 is the data voltage Vdata of the (n+m)th row pixel unit 11 in the previous frame of the current display frame. This ensures the effectiveness of the compensation.

[0041] In one embodiment, m is determined based on the number of rows of pixel units 11 on the array substrate 10. In a specific embodiment, m ∈ [1, P / 2]; or, m = P / 2, where P is the number of rows of pixel units on the array substrate.

[0042] It should be noted that when the data line Data is charging and discharging the nth row, the voltage compensation line D will perform charge compensation on the (n+m)th row at the position of the (n+m)th row; when the data line Data is charging and discharging the (n+m)th row, the voltage compensation line D will perform charge compensation on the (n+m)th row at the position of the nth row. Assuming a resolution of 2400×1080, the number of rows of pixel unit 11 is 1080, where m∈[1,540]. When m=1, when charging the 1st row, compensation will be performed on the 2nd row; when charging the 2nd row, compensation will be performed on the 1st and 3rd rows; when charging the 3rd row, compensation will be performed on the 2nd and 4th rows, and so on. When charging the 1079th row, compensation will be performed on the 1078th and 1080th rows, and when charging the 1080th row, compensation will be performed on the 1079th row. Therefore, when m=1, the first and last rows are compensated once, while rows 2 through 1079 are compensated twice. When m=3, rows 1, 2, 3, and rows 1078, 1079, and 1080 are each compensated once, while the remaining rows are compensated twice. When m=540, all rows are compensated once. Therefore, when m=P / 2, all pixel units are compensated uniformly, improving compensation uniformity and further ensuring display quality.

[0043] In another embodiment, if the resolution is 3200×1440, then the number of rows of pixel unit 11 is 1440, where m∈[1,720], and in a specific embodiment, m=720.

[0044] In another embodiment, the solution of this application can be applied to... Figure 1 In addition to the 3T1C circuit structure shown, it can also be applied to... Figure 7 In the circuit structure shown. Specifically, Figure 7 The circuit structure shown includes a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, a fifth switch Q5, a sixth switch Q6, a pixel capacitor C, and an OLED light-emitting element. The fourth switch Q4 is the driving switch. The first switch Q1, second switch Q2, third switch Q3, fifth switch Q5, and sixth switch Q6 are all switching transistors. The fourth switch Q4 is used to determine the driving current of the pixel driving circuit 100, and the OLED light-emitting element emits light in response to the driving current.

[0045] Any one of the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the sixth switch Q6 can be a low-temperature polycrystalline silicon thin-film switch, an oxide semiconductor thin-film switch, or an amorphous silicon thin-film switch, and the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the sixth switch Q6 include at least one of the following: a low-temperature polycrystalline silicon thin-film switch, an oxide semiconductor thin-film switch, and an amorphous silicon thin-film switch.

[0046] One of the third switch Q3 and the sixth switch Q6 is a P-type thin-film switch and the other is an N-type thin-film switch, and the third switch Q3 and the sixth switch Q6 share a single control signal.

[0047] In this embodiment, the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, and the sixth switch Q6 are all oxide semiconductor thin-film switches. Specifically, the sixth switch Q6 is a P-type thin-film switch that conducts at a low level, while the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, and the fifth switch Q5 are all N-type thin-film switches that conduct at a high level. Combining P-type and N-type thin-film switches in the pixel driving circuit 100 allows the third switch Q3 and the sixth switch Q6 to share a single control signal, reducing the amount of control signal used. Furthermore, the fifth switch Q5 and the first switch Q1 share a single control signal, again reducing the amount of control signal used and simplifying the circuit.

[0048] In this configuration, the gate of the first switching transistor Q1 is connected to the scan line Gate, the drain is connected to the data line Data, and the source is electrically connected to the first node A. The first switching transistor Q1 is used to transmit the data voltage Vdata on the data line Data to the first node A in response to the enable signal of the scan line Gate.

[0049] The gate of the second switch Q2 is connected to the first control signal S1, its drain is connected to the second node B, and its source is connected to the source of the third switch Q3 and the drain of the fourth switch Q4. The second switch Q2 is used to transmit the power signal ELVDD to the second node B or transmit the signal from the second node B to the drain of the fourth switch Q4 in response to the first control signal S1.

[0050] The gate of the third switch Q3 is connected to the second control signal S2, the drain is connected to the power supply signal ELVDD, and the source is connected to the drain of the fourth switch Q4. The third switch Q3 is used to transmit the power supply signal ELVDD to the drain of the fourth switch Q4 in response to the second control signal S2.

[0051] The gate of the fourth switch Q4 is connected to the second node B, and the source is connected to the third node E. The fourth switch Q4 is used to transmit the driving current to the light-emitting element OLED or to transmit the signal from the second node B to the third node E.

[0052] The gate of the fifth switch Q5 is connected to the data line Data, the source is connected to node E, and the drain is connected to node A. The fifth switch Q5 is used to transmit the signal from node A to node E.

[0053] The gate of the sixth switch Q6 is connected to the second control signal S2, the source is grounded, and the drain is connected to the third node E.

[0054] One end of the pixel capacitor C is electrically connected to the first node A, and the other end is electrically connected to the second node B.

[0055] The anode of the OLED light-emitting element is connected to the third node E, and the cathode is grounded.

[0056] It should be noted that the first switch Q1 serves as the voltage writing unit. Specifically, Figure 7 The pixel unit shown further includes a compensation switch T4 and a voltage compensation line D. The first path terminal of the compensation switch T4 is connected to the voltage compensation line D, and the second path terminal of the compensation switch T4 is connected to the first node A. In the nth row, the control terminal of the first switch Q1 is connected to the scan line Gatan, and the control terminal of the compensation switch T4 is connected to the scan line Gatan n+m. In the mth row, the control terminal of the first switch Q1 is connected to the scan line Gatan n+m, and the control terminal of the compensation switch T4 is connected to the scan line Gatan n.

[0057] In this way, when the pixel unit in the nth row is scanned for charging and discharging, the pixel unit in the (n+m)th row can be compensated at the same time, thereby solving the leakage problem and improving the display effect.

[0058] In other embodiments, the compensation switch T4 of this application may also be set in other types of pixel units, and there is no specific limitation.

[0059] See Figure 8 , Figure 8 This is a schematic diagram of a structure of a display panel according to an embodiment of the present application. The display panel 30 specifically includes the array substrate 10 of any of the above embodiments. The array substrate 10 can realize the functions and effects of the array substrate 10 described above.

[0060] See Figure 9 , Figure 9 This is a schematic diagram of a structure of an embodiment of the display device provided in this application. The display device 40 provided in this application includes an array substrate 10 and a driving circuit 20. The array substrate 10 includes any of the array substrates 10 described above. The array substrate 10 can realize the functions and effects of the array substrate 10 described above. The driving circuit 20 is used to drive the array substrate 10.

[0061] Specifically, the driving circuit 20 includes a gate driving circuit, a source driving circuit, a timing control circuit, a power management circuit, etc.

[0062] The above are merely embodiments of the present invention and do not limit the scope of patent protection of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. An array substrate, characterized in that, include: Multiple vertically spaced scan lines, multiple horizontally spaced data lines, voltage compensation lines, and multiple pixel units arranged in an array; wherein, the scan lines are connected to a row of pixel units, the data lines are connected to a column of pixel units, and each pixel unit includes a pixel capacitor and a compensation unit, the compensation unit being connected to the pixel capacitor, and the voltage compensation line being connected to the compensation unit in a column of pixel units; Wherein, the compensation unit in the pixel unit of the nth row is connected to the (n+m)th scan line, and the compensation unit in the pixel unit of the (n+m)th row is connected to the nth scan line.

2. The array substrate according to claim 1, characterized in that, The compensation unit includes: a compensation switch; The first path terminal of the compensation switch is connected to the voltage compensation line, and the second path terminal of the compensation switch is connected to the pixel capacitor. In the pixel unit of the nth row, the control terminal of the compensation switch is connected to the (n+m)th scan line. In the pixel unit of the (n+m)th row, the control terminal of the compensation switch is connected to the nth scan line.

3. The array substrate according to claim 2, characterized in that, Each pixel unit further includes: Light-emitting elements; The voltage writing unit has a voltage receiving terminal connected to a data line for the voltage writing unit corresponding to a column of pixel units, a control terminal connected to a scan line for the voltage writing unit corresponding to a row of pixel units, and a voltage writing terminal connected to the pixel capacitor of the pixel unit for the voltage writing unit corresponding to each pixel unit. The driving unit has a voltage receiving terminal that receives a power supply voltage and is connected to the first terminal of the pixel capacitor, a control terminal that is connected to the second terminal of the pixel capacitor, and a voltage driving terminal that is connected to the light-emitting element. A reset detection unit is provided, wherein the voltage detection terminal of the reset detection unit is connected to the detection line, the control terminal of the reset detection unit is connected to the corresponding scan line, and the voltage output terminal of the reset detection unit is connected to the light-emitting element.

4. The array substrate according to claim 3, characterized in that, In response to the enabling of the nth scan line, the voltage writing unit in the nth row of pixel units is in a working state, and the data line charges the pixel capacitor in the nth row of pixel units using the data voltage; and the compensation unit in the (n+m)th row of pixel units is in a working state, and the voltage compensation line performs voltage compensation for the pixel capacitor in the (n+m)th row of pixel units using the first compensation voltage; at the same time, the reset detection unit in the nth row of pixel units is in a working state, and performs reset detection on the nth row of pixel units.

5. The array substrate according to claim 4, characterized in that, The first compensation voltage is the data voltage of the pixel unit in the (n+m)th row of the previous frame of the current display frame.

6. The array substrate according to claim 3, characterized in that, In response to the enabling of the (n+m)th scan line, the voltage writing unit in the (n+m)th row pixel unit is in a working state, and the data line charges the pixel capacitor in the (n+m)th row pixel unit using the data voltage; and the compensation unit in the nth row pixel unit is in a working state, and the voltage compensation line performs voltage compensation for the pixel capacitor in the nth row pixel unit using the second compensation voltage; at the same time, the reset detection unit in the (n+m)th row pixel unit is in a working state, and performs reset detection on the (n+m)th row pixel unit.

7. The array substrate according to claim 6, characterized in that, The second compensation voltage is the data voltage of the nth row pixel unit of the current display frame.

8. The array substrate according to claim 1, characterized in that, m is determined based on the number of rows of pixel units on the array substrate; Where m∈[1,P / 2]; or m=P / 2, where P is the row number of pixel units on the array substrate.

9. A display panel, characterized in that, include: The array substrate according to any one of claims 1 to 8.

10. A display device, characterized in that, include: An array substrate, wherein the array substrate comprises the array substrate according to any one of claims 1 to 8; A driving circuit for driving the array substrate.

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