Pixel circuit, driving method thereof and display panel

Abstract

The application relates to the technical field of display, and particularly discloses a pixel circuit, a driving method thereof and a display panel, which comprise a data writing module, a coupling module, a driving module and a threshold compensation module. In a data writing stage, the data writing module transmits a data signal to a first node according to a first scanning signal. The coupling module is connected between the first node and a second node, and is used for coupling a potential change at the first node to the second node. The control end of the driving module is connected with the second node. The threshold compensation module is used for turning on the connection between the control end of the driving module and the second node according to a second scanning signal at least in the data writing stage. The first initialization module is used for transmitting a first initialization signal to the first end of the driving module according to a third scanning signal. Part of a stage before the data writing stage and / or part of a stage after the data writing stage of the third scanning signal is configured as the turn-on level of the first initialization module. The pixel circuit solves the ghosting problem by initializing the first end of the driving module.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel circuit and its driving method, and a display panel. Background Technology

[0002] With the continuous development of display technology, the application range of display panels is becoming increasingly wide, and people's requirements for display panels are also getting higher and higher. Organic Light Emitting Display (OLED) flat panel display devices are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide application range, becoming the mainstream display device. However, the display performance of OLED products still needs improvement. Summary of the Invention

[0003] Therefore, it is necessary to provide a pixel circuit and its driving method, as well as a display panel, to address the issue of the need to improve the performance of existing display products.

[0004] A pixel circuit, comprising:

[0005] The data writing module is connected to the first node and is used to transmit data signals to the first node according to the first scan signal during the data writing stage; A coupling module, connected between the first node and the second node, is used to couple the potential change at the first node to the second node; A drive module, the control terminal of which is connected to the second node, is used to output drive signals; A threshold compensation module is connected between the control terminal and the second terminal of the drive module, and is used to connect the control terminal and the second terminal of the drive module according to the second scan signal at least during the data writing phase. A first initialization module is connected to the first end of the driving module and is used to transmit a first initialization signal to the first end of the driving module according to the third scan signal. The third scanning signal is configured to be at the on level of the first initialization module during a portion of the phases before and / or after the data writing phase.

[0006] In one possible implementation, the driving module includes a first transistor, the gate of the first transistor serving as the control terminal of the driving module, the first electrode of the first transistor serving as the first terminal of the driving module, and the second electrode of the first transistor serving as the second terminal of the driving module.

[0007] In one possible implementation, the data writing module includes a second transistor, the gate of the second transistor being connected to the first scan signal as the control terminal of the data writing module, the first electrode of the second transistor being connected to the data signal as the first terminal of the data writing module, and the second electrode of the second transistor being connected to the first node as the second terminal of the data writing module.

[0008] In one possible implementation, the threshold compensation module includes a third transistor, the gate of which serves as the control terminal of the threshold compensation module and is connected to the second scan signal, the first electrode of which serves as the first terminal of the threshold compensation module and is connected to the control terminal of the driving module, and the second electrode of which serves as the second terminal of the threshold compensation module and is connected to the second terminal of the driving module.

[0009] In one possible implementation, the first initialization module includes a fourth transistor, the gate of which serves as the control terminal of the first initialization module and is connected to the third scan signal, the first terminal of which serves as the first terminal of the first initialization module and is connected to the first initialization signal, and the second terminal of which serves as the second terminal of the first initialization module and is connected to the first terminal of the driving module.

[0010] In one possible implementation, the coupling module includes a first capacitor, with a first terminal of the first capacitor connected to the first node as a first end of the coupling module, and a second terminal of the first capacitor connected to the second node as a second end of the coupling module.

[0011] In one possible implementation, the pixel circuit further includes: A first light-emitting control module is connected between a first power line and a first end of the driving module, and is used to turn on or off the connection between the first power line and the first end of the driving module according to a third scanning signal.

[0012] In one possible implementation, when the third scan signal is configured to be the on level of the first initialization module, the first light emission control module is turned off according to the third scan signal; when the third scan signal is configured to be the off level of the first initialization module, the first light emission control module is turned on according to the third scan signal.

[0013] In one possible implementation, the first light-emitting control module includes a fifth transistor, the gate of which serves as the control terminal of the first light-emitting control module and is connected to the third scan signal, the first electrode of which serves as the first terminal of the first light-emitting control module and is connected to the first power line, and the second electrode of which serves as the second terminal of the first light-emitting control module and is connected to the first terminal of the driving module.

[0014] In one possible implementation, the pixel circuit further includes: The second light-emitting control module is connected between the second end of the driving module and the first end of the light-emitting device, and is used to turn on or off the connection between the second end of the driving module and the first end of the light-emitting device according to the light-emitting control signal.

[0015] In one possible implementation, the second light-emitting control module includes a sixth transistor, the gate of which serves as the control terminal of the second light-emitting control module and is connected to the light-emitting control signal, the first electrode of which serves as the first terminal of the second light-emitting control module and is connected to the second terminal of the driving module, and the second electrode of which serves as the second terminal of the second light-emitting control module and is connected to the light-emitting device.

[0016] In one possible implementation, the pixel circuit further includes: The second initialization module is connected to the first end of the light-emitting device and is used to transmit the second initialization signal to the first end of the light-emitting device according to the third scanning signal.

[0017] In one possible implementation, the on-level of the second initialization module is the same as the on-level of the first initialization module, and the off-level of the second initialization module is the same as the off-level of the first initialization module.

[0018] In one possible implementation, the second initialization module includes a seventh transistor, the gate of which serves as the control terminal of the second initialization module and is connected to the third scan signal, the first terminal of which serves as the first terminal of the second initialization module and is connected to the second initialization signal, and the second terminal of which serves as the second terminal of the second initialization module and is connected to the first terminal of the light-emitting device.

[0019] In one possible implementation, the first initialization signal is the same as the second initialization signal.

[0020] In one possible implementation, the first initialization signal is less than zero.

[0021] In one possible implementation, the pixel circuit further includes: The third initialization module is connected to the first node and is used to transmit the third initialization signal to the first node according to the first scan signal.

[0022] In one possible implementation, when the first scan signal is configured to be the on level of the data writing module, the third initialization module is turned off according to the third scan signal; when the first scan signal is configured to be the off level of the data writing module, the third initialization module is turned on according to the third scan signal.

[0023] In one possible implementation, the third initialization module includes an eighth transistor, the gate of which serves as the control terminal of the third initialization module and is connected to the first scan signal, the first terminal of which serves as the first terminal of the third initialization module and is connected to the third initialization signal, and the second terminal of which serves as the second terminal of the third initialization module and is connected to the first node.

[0024] In one possible implementation, the pixel circuit includes a write frame in one working cycle. The write frame includes a first initialization phase. In the first initialization phase, the first initialization module transmits the first initialization signal to the first terminal of the driving module according to the third scan signal. The second initialization module transmits the second initialization signal to the first terminal of the light-emitting device according to the third scan signal. The second light-emitting control module connects the second terminal of the driving module and the first terminal of the light-emitting device according to the light-emitting control signal. The threshold compensation module connects the control terminal of the driving module and the second terminal of the driving module according to the second scan signal. The third initialization module transmits the third initialization signal to the first node according to the first scan signal.

[0025] In one possible implementation, after the first initialization phase, the write frame includes a data write phase, in which the data write module transmits the data signal to the first node according to the first scan signal, the first light emission control module connects the first power line to the first end of the drive module according to the third scan signal, and the threshold compensation module connects the control end of the drive module to the second end of the drive module according to the second scan signal.

[0026] In one possible implementation, after the data writing phase, the write frame includes a second initialization phase, in which the first initialization module transmits the first initialization signal to the first end of the driving module according to the third scan signal, the second initialization module transmits the second initialization signal to the first end of the light-emitting device according to the third scan signal, and the third initialization module transmits the third initialization signal to the first node according to the first scan signal.

[0027] In one possible implementation, after the second initialization phase, the write frame includes a light emission phase, in which the third initialization module transmits the third initialization signal to the first node according to the first scan signal, the first light emission control module connects the first power line to the first end of the driving module according to the third control signal, and the second light emission control module connects the second end of the driving module to the first end of the light emission device according to the light emission control signal.

[0028] In one possible implementation, the pixel circuit further includes a hold frame in one operating cycle, wherein the levels of the first scan signal and the second scan signal are configured as the cutoff levels of the data writing module and the threshold compensation module in the hold frame.

[0029] In one possible implementation, the timing waveform of the third scan signal in the write frame is the same as the timing waveform in the hold frame, and the timing waveform of the light emission control signal in the write frame is the same as the timing waveform in the hold frame.

[0030] A driving method for a pixel circuit, used to drive a pixel circuit as described in any of the above embodiments, wherein a working cycle of the pixel circuit includes a write frame, the write frame including at least a first initialization phase, a data writing phase, a second initialization phase, and a light emission phase, the driving method comprising: In the first initialization phase, the level of the first scan signal is configured to a first level, the level of the second scan signal is configured to a second level, and the level of the third scan signal is configured to the second level; During the data writing phase, the level of the first scan signal is configured to the second level, the level of the second scan signal is configured to the second level, and the level of the third scan signal is configured to the first level; In the second initialization phase, the level of the first scan signal is configured to the first level, the level of the second scan signal is configured to the first level, and the level of the third scan signal is configured to the second level; During the light emission stage, the level of the first scan signal is configured to the first level, the level of the second scan signal is configured to the first level, and the level of the third scan signal is configured to the first level; Wherein, the first level is lower than the second level.

[0031] In one possible implementation, the driving method further includes: During the first initialization phase, the level of the light emission control signal is configured to the first level; During the data writing phase, the level of the light emission control signal is configured to the second level; In the second initialization phase, the level of the light emission control signal is configured to the second level; During the light emission phase, the level of the light emission control signal is configured to the first level.

[0032] In one possible implementation, the pixel circuit further includes a hold frame in one operating cycle, and the driving method further includes: in the hold frame, configuring the level of the first scan signal and the level of the second scan signal to the first level.

[0033] In one possible implementation, the timing waveform of the third scan signal in the write frame is the same as the timing waveform in the hold frame, and the timing waveform of the light emission control signal in the write frame is the same as the timing waveform in the hold frame.

[0034] A display panel includes pixel circuitry as described in any of the above embodiments. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of the first pixel circuit provided in the embodiments of this application; Figure 2 A schematic diagram of the circuit structure of a first pixel circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of the second pixel circuit provided in the embodiments of this application; Figure 4 A schematic diagram of the circuit structure of the second pixel circuit provided in the embodiments of this application; Figure 5This is a schematic diagram of the structure of the third pixel circuit provided in the embodiments of this application; Figure 6 A schematic diagram of the circuit structure of the third pixel circuit provided in the embodiments of this application; Figure 7 This is a schematic diagram of the structure of the fourth pixel circuit provided in the embodiments of this application; Figure 8 A schematic diagram of the circuit structure of the fourth pixel circuit provided in the embodiments of this application; Figure 9 This is a schematic diagram of the signal timing of a pixel circuit during frame writing, provided in an embodiment of this application. Figure 10 This is a schematic diagram of the signal timing of a pixel circuit in the write frame and the hold frame provided in an embodiment of this application; Figure 11 This is a flowchart illustrating the driving method of the pixel circuit in one embodiment of this application. Detailed Implementation

[0037] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0039] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0040] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0041] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0042] Figure 1 This is a schematic diagram of the structure of a first pixel circuit provided in an embodiment of this application. In one possible implementation, the pixel circuit may include a driving module 110, a data writing module 120, a threshold compensation module 130, a first initialization module 140, and a coupling module 210.

[0043] The data writing module 120 can be connected to the first node N1. The data writing module 120 can be configured to transmit the data signal Vdata to the first node N1 according to the first scan signal S1 during the data writing phase. In some specific embodiments, the first end of the data writing module 120 can be connected to a data line, which can transmit the data signal Vdata to the first end of the data writing module 120. The control end of the data writing module 120 can be connected to the first scan line, which can transmit the first scan signal S1 to the control end of the data writing module 120. The second end of the data writing module 120 can be connected to the first node N1, so that the data writing module 120 can transmit the data signal Vdata to the first node N1 according to the control of the first scan signal S1. Further, the first scan signal S1 can be output by a gate-in-panel (GIP) circuit located in the non-display area (often also called the bezel area) of the array substrate.

[0044] The coupling module 210 is connected between the first node N1 and the second node N2. The coupling module 210 can be used to couple the potential change at the first node N1 to the second node N2. For example, when the first node N1 experiences a potential change and the second node N2 is floating or connected to a high-impedance node, the coupling module 210 can couple the potential change at the first node N1 to the second node N2, that is, the coupling module 210 can couple the data signal Vdata into the second node N2.

[0045] The control terminal of the driving module 110 is connected to the second node N2. The driving module 110 can be located between the first power line and the light-emitting device 220. The driving module 110 can be used to output driving signals. The first power line can output a first power signal ELVDD to the pixel circuit to provide the voltage required for operation. The light-emitting device 220 can be connected between the second terminal of the driving module 100 and the second power line. The second power line can provide a second power signal ELVSS to the second terminal of the light-emitting device 220.

[0046] In this embodiment, the first power line is used to transmit a first power signal ELVDD, and the second power line is used to transmit a second power signal ELVSS. In one feasible implementation, the first power signal ELVDD is greater than the second power signal ELVSS. For example, the first power signal ELVDD can be a positive voltage, and the second power signal ELVSS can be a negative voltage.

[0047] A threshold compensation module 130 can be connected between the control terminal and the second terminal of the drive module 110. The threshold compensation module 130 can be configured to connect the control terminal and the second terminal of the drive module 110 at least during the data writing phase according to the second scan signal S2. In some specific embodiments, the first terminal of the threshold compensation module 130 can be connected to the control terminal of the drive module 110. The control terminal of the threshold compensation module 130 can be connected to a second scan line, which can transmit the second scan signal S2 to the control terminal of the threshold compensation module 130. The second terminal of the threshold compensation module 130 can be connected to the second terminal of the drive module 110, so that the drive module 110 can connect or disconnect the connection between the control terminal and the second terminal according to the control of the second scan signal S2. Further, the second scan signal S2 can also be output by a shift register unit located in the non-display area of ​​the array substrate.

[0048] The first initialization module 140 can be connected to the first terminal of the driving module 110. The first initialization module 140 can be configured to transmit the first initialization signal Vref1 to the first terminal of the driving module 110 according to the third scan signal S3. In some specific embodiments, the first terminal of the first initialization module 140 can be connected to a first initialization signal line, and the first initialization signal line can transmit the first initialization signal Vref1 to the first terminal of the first initialization module 140. The control terminal of the first initialization module 140 can be connected to the third scan signal S3, and the second terminal of the first initialization module 140 can be connected to the first terminal of the driving module 110, so that the first initialization module 140 can transmit the first initialization signal Vref1 to the first terminal of the driving module 110 according to the third scan signal S3. Further, the third scan signal S3 can also be output by a shift register unit located in the non-display area of ​​the array substrate.

[0049] Specifically, the level of the third scan signal S3 is configured as the conduction level of the first initialization module 140 during a portion of the phase before and / or after the data writing phase. That is, the first initialization module 140 is turned on during a portion of the phase before and / or after the data writing phase, and transmits the first initialization signal Vref1 to the first terminal of the driver module 110, thereby resetting the first terminal of the driver module 110 using the first initialization signal Vref1.

[0050] The hysteresis effect in TFTs (Thin Film Transistors) refers to the inconsistency in the current-voltage (IV) characteristic curves of thin film transistors in the scanning direction (forward or reverse), forming a "hysteresis loop." At the interface between the gate insulating layer and the active layer (the core region of channel conduction), there exists a high density of interface states (Dit). These energy levels are located within the semiconductor bandgap and can act as traps for charge carriers. These traps can capture or release charge carriers (mainly electrons or holes) with a certain probability, but their response speed cannot keep up with changes in the gate voltage, thus creating electrical memory. When there are defects at the interface between the gate insulating layer and the active layer, the IV curves during forward and reverse scans will not overlap. Simply put, when the gate voltage scans from low to high and then returns, the drain current measured at the same voltage does not coincide. During a forward scan, a positive voltage Vgs is applied first, attracting electrons to the interface between the gate insulating layer and the active layer. Some electrons are trapped, attracting holes in the channel, increasing the channel carrier concentration, making the device easier to turn on, and forward biasing Vth. Conversely, the same analysis can be performed. It is evident that the TFT hysteresis effect is not only related to the current bias state of the device, but also affected by the bias state of the device at the previous moment, thus leading to the image retention problem.

[0051] The inventors discovered through research that in existing technologies, the DTFT (Drive Transistor) remains in a biased state for extended periods, causing a shift in the DTFT Vth. Furthermore, during the light-emitting phase, the DTFT bias stress differs between black and white states, resulting in image retention during grayscale transitions. This application addresses this issue by initializing the first terminal of the drive module 110 with a first initialization signal Vref1 before and / or after data writing, and by using the reverse voltage first initialization signal Vref1 to release stress in the drive module 110, periodically releasing trapped charges, stabilizing the threshold voltage Vth of the drive module 110, and thus reducing image retention.

[0052] In the pixel circuit provided in this application, before and / or after data writing, the first initialization module 140 transmits the first initialization signal Vref1 to the first terminal of the driving module 110. The first initialization module 140 is used as a reverse voltage to relieve stress on the driving module 110, reducing the probability of a shift in the threshold voltage Vth of the driving module 110, thereby improving the image retention problem. During the data writing stage, the data writing module 120 transmits the data signal Vdata to the first node N1. When a potential change occurs at the first node N1, and the second node N2 is floating or connected to a high-impedance node, the coupling module 210 can couple the potential change at the first node N1 to the second node N2. Simultaneously, when the threshold compensation module 130 conducts the control terminal and the second terminal of the driving module 110, threshold compensation of the driving module 110 can be achieved, writing the threshold information of the driving module 110 into the second node N2. Thus, before emission, the potential at the second node N2 contains both threshold information and data information. Therefore, the above pixel circuit can achieve fast data writing and high-frequency driving through coupling. Meanwhile, by compensating for the threshold voltage of the driving module 110, the impact of differences in TFT device characteristics on the driving effect can be reduced, and the display uniformity can be improved.

[0053] The new circuit architecture formed by the driver module 110, data writing module 120, threshold compensation module 130, first initialization module 140 and coupling module 210, along with the coordination of various signal timings, can realize functions such as resetting each node in the circuit and threshold compensation for the driver module 110, thereby achieving the technical effects of improving image retention, crosstalk and enhancing brightness uniformity.

[0054] In embodiments of this disclosure, a transistor can refer to a device that includes at least a gate, a drain, and a source. In this disclosure, the first terminal of a transistor can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. In embodiments of this disclosure, the first and second terminals of all or some transistors can be interchanged as needed.

[0055] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-level is high and the off-level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. Furthermore, the on-level and off-level in the embodiments of this invention are general terms; the on-level refers to any level that enables the transistor to conduct, and the off-level refers to any level that enables the transistor to turn off / become off.

[0056] Figure 2 This is a schematic diagram of the circuit structure of a first pixel circuit provided in an embodiment of this application. In one possible implementation, the driving module 110 may include a first transistor M1, the gate of which can serve as the control terminal of the driving module 110. The first electrode of the first transistor M1 can serve as the first terminal of the driving module 110, and the second electrode of the first transistor M1 can serve as the second terminal of the driving module 110. More specifically, the first electrode of the first transistor M1 can be the source S, and the second electrode of the first transistor M1 can be the drain D.

[0057] In one possible implementation, the data writing module 120 may include a second transistor M2. The gate of the second transistor M2 may be connected to the first scan signal S1 as the control terminal of the data writing module 120. The first terminal of the second transistor M2 may be connected to the data signal Vdata as the first terminal of the data writing module 120. The second terminal of the second transistor M2 may be connected to the first node N1 as the second terminal of the data writing module 120.

[0058] In one possible implementation, the threshold compensation module 130 may include a third transistor M3. The gate of the third transistor M3 can be connected to the second scan signal S2 as the control terminal of the threshold compensation module 130. The first terminal of the third transistor M3 can be connected to the control terminal of the driving module 110 as the first terminal of the threshold compensation module 130, and the second terminal of the third transistor M3 can be connected to the second terminal of the driving module 110 as the second terminal of the threshold compensation module 130. More specifically, the first terminal of the third transistor M3 is connected to the gate G of the first transistor M1, and the second terminal of the third transistor M3 is connected to the second terminal of the first transistor M1.

[0059] In one possible implementation, the first initialization module 140 may include a fourth transistor M4. The gate of the fourth transistor M4 can be used as the control terminal of the first initialization module 140 to connect to the third scan signal S3. The first terminal of the fourth transistor M4 can be used as the first terminal of the first initialization module 140 to connect to the first initialization signal line to connect to the first initialization signal Vref1. The second terminal of the fourth transistor M4 can be used as the second terminal of the first initialization module 140 to connect to the first terminal of the driving module 11. More specifically, the second terminal of the fourth transistor M4 can be connected to the first terminal S of the first transistor M1.

[0060] In one possible implementation, the coupling module 210 may include a first capacitor C1. The first terminal of the first capacitor C1 can be connected to the first node N1 as the first end of the coupling module 210, and the second terminal of the first capacitor C1 can be connected to the second node N2 as the second end of the coupling module 210. More specifically, the first capacitor C1 and the second terminal of the second transistor M2 are connected to the first node N1, and the second terminal of the first capacitor C1, the gate G of the first transistor M1, and the first terminal of the third transistor M1 are connected to the second node N2.

[0061] Figure 3 This is a schematic diagram of a second pixel circuit provided in an embodiment of this application. In one embodiment, the pixel circuit may further include a first light-emitting control module 150. The first light-emitting control module 150 may be connected between the first power line and the first end of the driving module 110. The first light-emitting control module 150 may be configured to turn on or off the connection between the first power line and the first end of the driving module 110 according to the third scan signal S3.

[0062] In one possible implementation, when the third scan signal S3 is configured to be at the on level of the first initialization module 140, the first light-emitting control module 150 is turned off according to the third scan signal; when the third scan signal S3 is configured to be at the off level of the first initialization module 140, the first light-emitting control module 150 is turned on according to the third scan signal S3. That is, the on level of the first initialization module 140 is the off level of the first light-emitting control module 150, and the off level of the first initialization module 140 is the on level of the first light-emitting control module 150. Both the first initialization module 140 and the first light-emitting control module 150 are controlled by the third scan signal S3, and they will not be turned on simultaneously.

[0063] Figure 4This is a schematic diagram of the circuit structure of a second pixel circuit provided in an embodiment of this application. In one possible implementation, the first light-emitting control module 150 may include a fifth transistor M5. The gate of the fifth transistor M5 can be used as the control terminal of the first light-emitting control module 150 and connected to the third scan signal S3. The first terminal of the fifth transistor M5 can be used as the first terminal of the first light-emitting control module 150 and connected to the first power supply line. The second terminal of the fifth transistor M5 can be used as the second terminal of the first light-emitting control module 150 and connected to the first terminal of the driving module 110. More specifically, the second terminal of the fifth transistor M5 can be connected to the first terminal S of the first transistor M1.

[0064] In one possible implementation, the fourth transistor M4 and the fifth transistor M5 are of different device types. For example, the fourth transistor M4 is an N-type transistor and the fifth transistor M5 is a P-type transistor; or, the fourth transistor M4 is a P-type transistor and the fifth transistor M5 is an N-type transistor. Alternatively, the fourth transistor M4 may be an LTPS P-type transistor and the fifth transistor M5 may be an IGZO N-type transistor; or, the fourth transistor M4 may be an IGZO N-type transistor and the fifth transistor M5 may be an LTPS P-type transistor.

[0065] In one possible implementation, the light-emitting device 220 may include a light-emitting diode (OLED) D1. The OLED (Organic Light-Emitting Diode) may include an anode and a cathode, with the anode of the OLED D1 serving as the first terminal of the light-emitting device 220 and the cathode serving as the second terminal. When a driving signal output from the driving module 110 is transmitted to the OLED D1, the OLED D1 can emit light with a brightness corresponding to the driving signal.

[0066] Figure 5 This is a schematic diagram of the structure of a third pixel circuit provided in an embodiment of this application. In one possible implementation, the pixel circuit may further include a second light emission control module 160 and a second initialization module 170.

[0067] The second light-emitting control module 160 can be connected between the second end of the driving module 110 and the first end of the light-emitting device 220. The second light-emitting control module 160 is configured to turn on or off the connection between the second end of the driving module 110 and the first end of the light-emitting device 220 according to the light-emitting control signal EM. Further, the light-emitting control signal EM can also be output by a shift register unit located in the non-display area of ​​the array substrate. In some specific embodiments, the first end of the second light-emitting control module 160 can be connected to the second end of the driving module 110, the control end of the second light-emitting control module 160 can be connected to a light-emitting control signal line to receive the light-emitting control signal EM, and the second end of the second light-emitting control module 160 can be connected to the first end of the light-emitting device 220.

[0068] The second initialization module 170 can be connected to the first end of the light-emitting device 220. The second initialization module 170 is configured to transmit the second initialization signal Vref2 to the first end of the light-emitting device 220 according to the third scan signal S3. In some specific embodiments, the first end of the second initialization module 170 can be connected to the second initialization signal line to receive the second initialization signal Vref2, the control end of the second initialization module 170 can be connected to the third scan line to receive the third scan signal S3, and the second end of the second initialization module 170 can be connected to the first end of the light-emitting device 220.

[0069] In one possible implementation, the on-level of the second initialization module 170 is the same as the on-level of the first initialization module 140, and the off-level of the second initialization module 170 is the same as the off-level of the first initialization module 140. That is, when the first initialization module 140 is on, the second initialization module 170 is also on; when the first initialization module 140 is off, the second initialization module 170 is also off. Both the first initialization module 140 and the second initialization module 170 are controlled by the third scan signal S3, and both are on and off simultaneously.

[0070] Figure 6 This is a schematic diagram of the circuit structure of a third pixel circuit provided in an embodiment of this application. In one possible implementation, the second light-emitting control module 160 may include a sixth transistor M6. The gate of the sixth transistor M6 can be used as the control terminal of the second light-emitting control module 160 to connect to the light-emitting control signal EM. The first terminal of the sixth transistor M6 can be used as the first terminal of the second light-emitting control module 160 and connected to the second terminal of the driving module 110. The second terminal of the sixth transistor M6 can be used as the second terminal of the second light-emitting control module 160 and connected to the first terminal of the light-emitting device 220. More specifically, the first terminal of the sixth transistor M6 is connected to the second terminal D of the first transistor M1, and the second terminal of the sixth transistor M6 is connected to the anode of the light-emitting diode D1.

[0071] The second initialization module 170 may include a seventh transistor M7. The gate of the seventh transistor M7 can serve as the control terminal of the second initialization module 170, the first terminal of the seventh transistor M7 can serve as the first terminal of the second initialization module 170, and the second terminal of the seventh transistor M7 can serve as the second terminal of the second initialization module 170. The gate of the seventh transistor M7 can be connected to a fourth control signal EM1, the first terminal of the seventh transistor M7 can be connected to a second initialization signal Vref2, and the second terminal of the seventh transistor M7 can be the anode of a light-emitting diode D1.

[0072] When the second initialization module 170, the second light emission control module 160, and the threshold compensation module 130 are simultaneously turned on, the second initialization signal Vref2 can be transmitted sequentially through the second initialization module 170, the second light emission control module 160, and the threshold compensation module 130 to the control terminal of the drive module 110. At this time, the second initialization signal Vref2 can sequentially adjust the potentials at the first terminal of the light-emitting device 220, the second terminal of the drive module 110, the control terminal of the drive module 110, and the second terminal of the first capacitor C1 to Vref2, thereby resetting the aforementioned points.

[0073] In one possible implementation, the fourth transistor M4 and the seventh transistor M7 can be of the same device type. For example, both the fourth transistor M4 and the fifth transistor M5 can be LTPS N-type transistors; or, both the fourth transistor M4 and the fifth transistor M5 can be LTPS P-type transistors. The fourth transistor M4 and the seventh transistor M7 can also be of different device types. For example, the fourth transistor M4 can be an LTPS N-type transistor, and the fifth transistor M5 can be an IGZO N-type transistor; or, the fourth transistor M4 can be an IGZO N-type transistor, and the fifth transistor M5 can be an LTPS N-type transistor.

[0074] In one possible implementation, the first initialization signal Vref1 and the second initialization signal Vref2 can be the same. That is, the same reset voltage can be used to reset the first terminal of the driving module 110, the first terminal of the light-emitting device 220, the second terminal of the driving module 110, the control terminal of the driving module 110, and the second terminal of the first capacitor C1, so as to solve the influence of the residual potential of the previous display frame on the subsequent light emission, and to ensure the accuracy of threshold compensation and the stability of the picture.

[0075] In one possible implementation, the first initialization signal Vref1 can be a voltage less than zero. Since the first terminal of the driving module 110 is connected to ELVDD for a long time (such as during the light emission stage), the threshold voltage of the driving module 110 can be stabilized and the image retention problem can be improved by using the negative first initialization signal Vref1 as a reverse voltage to relieve stress on the driving module 110.

[0076] Figure 7 This is a schematic diagram of the structure of a fourth pixel circuit provided in an embodiment of this application. In one possible implementation, the pixel circuit may further include a third initialization module 180, which is connected to the first node N1. The third initialization module 180 may be configured to transmit a third initialization signal Vref3 to the first node N1 according to the first scan signal S1. In some specific embodiments, the first end of the third initialization module 180 may be connected to a third initialization signal line to receive the third initialization signal Vref3, the control end of the third initialization module 180 may be connected to the first scan signal S1, and the second end of the third initialization module 180 may be connected to the first node N1.

[0077] In one possible implementation, when the first scan signal S1 is configured to be at the on level of the data writing module 120, the third initialization module 180 is turned off according to the first scan signal S1; when the first scan signal S1 is configured to be at the off level of the data writing module 120, the third initialization module 180 is turned on according to the first scan signal S1. That is, the on level of the data writing module 120 is the off level of the third initialization module 180, and the off level of the data writing module 120 is the on level of the third initialization module 180. Both the data writing module 120 and the third initialization module 180 are controlled by the first scan signal S1, and they will not be turned on simultaneously.

[0078] Figure 8 The circuit structure diagram of the fourth pixel circuit provided in the embodiment of this application is shown. In one possible implementation, the third initialization module 180 may include an eighth transistor M8. The gate of the eighth transistor M8 can be used as the control terminal of the third initialization module 180 and connected to the first scan signal S1. The first terminal of the eighth transistor M8 can be used as the first terminal of the third initialization module 180 and connected to the third initialization signal line to access the third initialization signal Vref3. The second terminal of the eighth transistor M8 can be used as the second terminal of the third initialization module 180 and connected to the first node N1.

[0079] In one possible implementation, the second transistor M2 and the eighth transistor M8 are of different device types. For example, the second transistor M2 is an N-type transistor and the eighth transistor M8 is a P-type transistor; or, the second transistor M2 is a P-type transistor and the eighth transistor M8 is an N-type transistor. Alternatively, the second transistor M2 may be an LTPS P-type transistor and the eighth transistor M8 may be an IGZO N-type transistor; or, the second transistor M2 may be an IGZO N-type transistor and the eighth transistor M8 may be an LTPS P-type transistor.

[0080] In one possible implementation, the pixel circuit includes at least one of a metal-oxide-semiconductor (MOD) transistor and a low-temperature polysilicon (LTPS) transistor. The LTP transistor is a transistor fabricated using low-temperature polysilicon as the active semiconductor layer; the MOD transistor is a transistor fabricated using metal-oxide-semiconductor as the active semiconductor layer. The LTP transistor can be a P-type transistor or an N-type transistor, and the MOD transistor can be an N-type transistor.

[0081] The metal oxide material can be, for example, at least one of IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), and IZTO (Indium Zinc Tin Oxide). When the pixel circuit includes both metal oxide transistors and low-temperature polycrystalline silicon transistors, it can be a circuit fabricated using LTPO (Low Temperature Poly Silicon-Oxide) technology. LTPO is a hybrid OLED backplane technology that combines LTPS (Low Temperature Polycrystalline Silicon) and IGZO.

[0082] In one possible implementation, Figure 8 The pixel circuit shown is an 8T1C structure, in which the first transistor M1 is a DTFT (Driver Thin Film Transistor), and the remaining transistors are STFTs (Switch Thin Film Transistors). Specifically, the first transistor M1, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 are P-type transistors, while the second transistor M2, the third transistor M3, the fourth transistor M4, and the seventh transistor M7 are N-type transistors.

[0083] In one possible implementation, the pixel circuit may include at least a write frame in one operating cycle, which is a phase for updating pixel data. The operation of one write frame may include a first initialization phase t1, a data writing phase t2, a second initialization phase t3, and a light emission phase t4.

[0084] Figure 9 This is a schematic diagram of the signal timing of a pixel circuit during frame writing, provided in one embodiment of this application. It can be applied to, for example... Figure 8 The pixel circuit shown in this embodiment is combined with Figure 8 and Figure 9 The working process of the pixel circuit in one embodiment of this application during frame writing is described in detail, but it should not be construed as limiting the scope of the invention. In this embodiment, the first transistor M1, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 in the pixel circuit are P-type transistors, with a low conduction level VGL and a high cutoff level VGH; the second transistor M2, the third transistor M3, the fourth transistor M4, and the seventh transistor M7 are N-type transistors, with a high conduction level VGH and a low cutoff level VGL.

[0085] The second terminal of the second transistor M2, the second terminal of the eighth transistor M8, and the first terminal of the first capacitor C1 are connected to the first node N1. The gates of both the second transistor M2 and the eighth transistor M8 are connected to the first scan signal S1. The first terminal of the second transistor M2 is connected to the data signal Vdata, and the first terminal of the eighth transistor M8 is connected to the third initialization signal Vref3. The first terminal S of the first transistor M1 is connected to the second terminals of the fourth transistor M4 and the fifth transistor M5, respectively. The gates of both the fourth transistor M4 and the fifth transistor M5 are connected to the third scan signal S3. The first terminal of the fourth transistor M4 is connected to the first initialization signal Vref1, and the first terminal of the fifth transistor M5 is connected to the first power supply line. The gate G of the first transistor M1, the first terminal of the third transistor M3, and the second terminal of the first capacitor C1 are connected to the second node N2. The gate of the third transistor M3 is connected to the second scan signal S2, and the second terminal of the third transistor M3 is connected to the second terminal D of the first transistor M1 and the first terminal of the sixth transistor M6. The gate of the sixth transistor M6 is connected to the light-emitting control signal EM, and the second terminal of the sixth transistor M6 is connected to the second terminal of the seventh transistor M7 and the anode of the light-emitting diode D1. The gate of the seventh transistor M7 is connected to the third scan signal S3, and the first terminal of the seventh transistor M7 is connected to the second initialization signal Vref2. The cathode of the light-emitting diode D1 is connected to the second power supply line.

[0086] In the first initialization phase t1, the level of the first scan signal S1 is the first level, the level of the second scan signal S2 is the second level, and the level of the third scan signal S3 is the second level. In this embodiment, the first level can refer to a low level VGL, and the second level can refer to a high level VGH, that is, the first level is less than the second level. The second transistor M2 is turned off according to the low level of the first scan signal S1, and the eighth transistor M8 is turned on according to the low level of the first scan signal S1. The third transistor M3 is turned on according to the high level of the second scan signal S2, the fourth transistor M4 and the seventh transistor M7 are turned on according to the high level of the third scan signal S3, and the fifth transistor M5 is turned off according to the high level of the third scan signal S3. In addition, the level of the light emission control signal EM is the first level (low level VGL). The sixth transistor M6 is turned on according to the low level of the light emission control signal EM.

[0087] After the fourth transistor M4 is turned on, it transmits the first initialization signal Vref1 to the first terminal S of the first transistor M1, thereby initializing the first terminal S of the first transistor M1. The potential at the first terminal S of the first transistor M1 becomes Vs = Vref1. After the eighth transistor M8 is turned on, it transmits the third initialization signal Vref3 to the first node N1, thereby initializing the first node N1. At this time, the potential at the first node N1 is VN1 = Vref3. After the seventh transistor M7 is turned on, it transmits the second initialization signal Vref2 to the anode of the light-emitting diode D1. At the same time, the sixth transistor M6 turns on the second terminal D of the first transistor M1 and the anode of the light-emitting diode D1, and the third transistor M3 turns on the gate of the first transistor M1 and the second terminal of the first transistor M1. Thus, the second initialization signal Vref2 is transmitted sequentially through the sixth transistor M6 and the third transistor M3 to the gate of the first transistor M1. The second initialization signal Vref2 simultaneously initializes the anode of LED D1, the second terminal D of first transistor M1, the gate G of first transistor M1, and the second terminal of first capacitor C1. At this time, the potential at the gate G of first transistor M1 is Vg = Vref2. In the first initialization stage t1, the initialization of each node in the pixel circuit can be realized, and the stress on first transistor M1 before writing can also be relieved.

[0088] In one possible implementation, after the first initialization phase t1, the write frame may include a data write phase t2. In the data write phase t2, the level of the first scan signal S1 is a second level (high level VGH), the level of the second scan signal S2 is a second level, and the level of the third scan signal S3 is a first level (low level VGL). The second transistor M2 is turned on according to the high level of the first scan signal S1, and the eighth transistor M8 is turned off according to the high level of the first scan signal S1. The third transistor M3 is turned on according to the high level of the second scan signal S2, the fourth transistor M4 and the seventh transistor M7 are turned off according to the low level of the third scan signal S3, and the fifth transistor M5 is turned on according to the low level of the third scan signal S3. Additionally, the level of the light emission control signal EM is a second level (high level VGH). The sixth transistor M6 is turned off according to the high level of the light emission control signal EM.

[0089] During the data writing phase t2, the second transistor M2 transmits the data signal Vdata to the first node N1. At this time, the potential at the first node N1 is VN1 = Vdata. After the fifth transistor M5 is turned on, the first power signal ELVDD transmitted on the first power line is transmitted to the first terminal S of the first transistor M1. Since the potential at the gate G of the first transistor M1 was Vg = Vref2 during the first initialization phase t1, the first transistor M1 meets the conduction condition and is turned on. Simultaneously, the third transistor M3 turns on the gate and second terminal of the first transistor M1. Therefore, the first power signal ELVDD is transmitted sequentially through the fifth transistor M5, the first transistor M1, and the third transistor M3 to the gate of the first transistor M1. When the potential at the gate G of the first transistor M1 is charged to ELVDD - |Vth|, the first transistor M1 is turned off. At this time, the potentials at the gate G and drain D of the first transistor M1 are both ELVDD - |Vth|. In addition, since the sixth transistor M6 is turned off, the light-emitting device D1 does not emit light.

[0090] In the data writing stage t2 provided in this application, the difference compared to the data writing stage of related prior art is that, in the data writing stage t2 of this application, the data signal Vdata is written to the first node N1, rather than directly to the gate G of the first transistor M1. Simultaneously, in the data writing stage t2, the first power supply signal ELVDD can be used to achieve threshold compensation for the first transistor M1. After the third transistor M3 is turned on, the first transistor M1 is in a diode-connected state, causing the threshold information to be written to the potential at the gate G of the first transistor M1.

[0091] In one possible implementation, after the data writing phase t2, the write frame may include a second initialization phase t3. In the second initialization phase t3, the level of the first scan signal S1 is a first level (low level VGL), the level of the second scan signal S2 is a first level, and the level of the third scan signal S3 is a second level (high level VGH). The second transistor M2 is turned off according to the low level of the first scan signal S1, and the eighth transistor M8 is turned on according to the low level of the first scan signal S1. The third transistor M3 is turned off according to the low level of the second scan signal S2, the fourth transistor M4 and the seventh transistor M7 are turned on according to the high level of the third scan signal S3, and the fifth transistor M5 is turned off according to the high level of the third scan signal S3. Additionally, the level of the light emission control signal EM is a second level (high level VGH). The sixth transistor M6 is turned off according to the high level of the light emission control signal EM.

[0092] In the second initialization phase t3, the eighth transistor M8 transmits the third initialization signal Vref3 to the first node N1, causing a potential change at the first node N1 from Vdata to Vref3. Simultaneously, since the third transistor M3 is off, the second node N1 is in a floating state. The potential at the second terminal of the first capacitor C1 changes synchronously with the potential at its first terminal, meaning the first capacitor C1 couples the potential change at the first node N1 to the second node N2. The potential at the gate G of the first transistor M1 becomes VG = ELVDD - |Vth| - Vdata + Vref3. The fourth transistor M4 again transmits the first initialization signal Vref1 to the first terminal S of the first transistor M1, achieving stress relief for the first transistor M1 after writing.

[0093] In the second initialization stage t3 provided in this application, the difference compared to the initialization stage of related prior art is that, in the second initialization stage t3 of this application, the data signal Vdata is coupled to the gate G of the first transistor M1 using the first capacitor C1, enabling data writing at an extremely fast speed. Threshold compensation in the pixel circuit is separated from the data writing process, thus the threshold compensation time is adjustable and unaffected by the data writing time. This allows for sufficient threshold compensation of the driving module 110, ensuring uniformity even with high-frequency driving. Simultaneously, the negative first initialization signal Vref1 is again used as the reverse voltage of the first transistor M1 for stress relief, preventing the first transistor M1 from being under negative bias stress for a long time and causing threshold drift, thus more effectively improving the image retention problem.

[0094] In related technologies, when a driving transistor operates in the on state (e.g., gate potential Vg=1V, source potential ELVDD=4.6V, Vgs=-3.6V) for an extended period, the number of holes near point S increases, making it easier for interface layer traps to capture these holes, resulting in a negative shift in the threshold voltage Vth of the first transistor M1. In this application, a negative first initialization signal Vref1 is transmitted to the first terminal S of the first transistor M1 during the first initialization phase t1 and the second initialization phase t3, respectively. At this time, assuming the gate potential Vg=1V and the source potential Vs=-3V of the first transistor M1, then Vgs=4V. That is, a reverse voltage stress (positive gate voltage) is applied to the first transistor M1 to restore the threshold voltage drift. The pixel circuit provided in this application transmits the negative first initialization signal Vref1 to the first electrode S of the first transistor M1 twice, which can more fully realize the stress release of the first transistor M1. At the same time, the time of the two initialization stages is adjustable, which has a better effect on improving the threshold drift of the first transistor M1 and better ensures the stability of the threshold voltage Vth of the first transistor M1.

[0095] In one possible implementation, after the second initialization phase t3, the write frame may include a light-emitting phase t4. In the light-emitting phase t4, the level of the first scan signal S1 is a first level (low level VGL), the level of the second scan signal S2 is a first level, and the level of the third scan signal S3 is a first level. The second transistor M2 is turned off according to the low level of the first scan signal S1, and the eighth transistor M8 is turned on according to the low level of the first scan signal S1. The third transistor M3 is turned off according to the low level of the second scan signal S2, the fourth transistor M4 and the seventh transistor M7 are turned off according to the low level of the third scan signal S3, and the fifth transistor M5 is turned on according to the low level of the third scan signal S3. Additionally, the level of the light-emitting control signal EM is a first level. The sixth transistor M6 is turned on according to the low level of the light-emitting control signal EM.

[0096] During the light-emitting phase t4, the first transistor M1, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 are turned on, while the rest are turned off.

[0097] The first transistor M1 can generate a drive signal based on its gate and source voltages. The drive current output by the first transistor M1 can be calculated as follows: I D =1 / 2 μ C OX (W / L)(Vsg-|Vth|) 2 Where μ is the electron mobility of the first transistor M1, cox is the channel capacitance per unit area of ​​the first transistor M1, W / L is the aspect ratio of the first transistor M1, and Vth is the threshold voltage of the first transistor M1.

[0098] The gate voltage of the first transistor M1 is VG = ELVDD - |Vth| - Vdata + Vref3, and the source voltage of the first transistor M1 is VS = ELVDD. Vsg - |Vth| = Vdata - Vref3, meaning the driving current is a function of (Vdata - Vref3). This function does not include VDD, VSS, or Vth. Therefore, the driving current output by this pixel circuit is not affected by the differences in VDD, VSS, and Vth at different locations on the display panel, indicating good compensation for VDD, VSS, and Vth.

[0099] The drive current I output by the first transistor M1 D The current can be transmitted to the anode of LED D1 via the sixth transistor M6, thus LED D1 responds to the driving current I. D Glowing light.

[0100] Each node of the aforementioned pixel circuit is reset during the first initialization phase t1, and there are no micro-short circuits between signals, effectively improving image retention and reducing power consumption. When compensating for the threshold voltage Vth of the first transistor M1, the compensation time is adjustable, enabling simultaneous compensation of multiple rows of pixel circuits, thus achieving high-frequency driving. During data writing, the data signal Vdata is written to the first node N1, and the first capacitor C1 couples the data signal Vdata to the first transistor M1. Capacitive coupling allows for rapid data writing, making it suitable for high-brightness display scenarios.

[0101] In one possible implementation, the pixel circuit may further include a hold frame in one duty cycle. The hold frame can be a display frame that does not update but only maintains the current image. The combination of the write frame and the hold frame can achieve a dynamic refresh rate and reduce power consumption. Specifically, the pixel circuit can operate at different refresh rates. At a high refresh rate, each display frame is a write frame; at a low refresh rate, at least one display frame can be designed as a write frame, and the other display frames as hold frames. The distinction between high and low refresh rates can be set according to different application requirements. For example, a refresh rate greater than or equal to 120Hz is considered a high refresh rate, and a refresh rate lower than 120Hz is considered a low refresh rate.

[0102] In one possible implementation, the levels of the first scan signal S1 and the second scan signal S2 can be continuously configured to be the cutoff levels of the data writing module 120 and the threshold compensation module 130 during the hold frame, that is, the levels of the first scan signal S1 and the second scan signal S2 can be continuously at the first level (low level VGL) during the hold frame.

[0103] In one possible implementation, the timing waveform of the third scan signal S3 in the write frame is the same as that in the hold frame, and the timing waveform of the light emission control signal EM in the write frame is the same as that in the hold frame.

[0104] Figure 10 This is a schematic diagram of the signal timing of a pixel circuit in the write frame and hold frame provided in one embodiment of this application, which can be applied to, for example... Figure 8 The pixel circuit shown in this embodiment is combined with Figure 8 and Figure 10 The working process of the pixel circuit in one embodiment of this application in holding the frame is described in detail, but it should not be construed as a limitation on the scope of the invention patent.

[0105] In one possible implementation, during at least a portion of the holding frame, the third scan signal S3 is configured to be high, and the fourth transistor M4 is turned on according to the high-level third scan signal S3, transmitting the first initialization signal Vref1 to the first terminal S of the first transistor M1. That is, stress relief is also applied to the first transistor M1 during the holding frame. Simultaneously, the seventh transistor M7 and the eighth transistor M8 are also turned on according to the high-level third scan signal S3. The seventh transistor M7 transmits the second initialization signal Vref2 to the anode of the light-emitting diode D1, and the eighth transistor M8 transmits the third initialization signal Vref3 to the first node N1. The anode of the light-emitting diode D1 is initialized using the second initialization signal Vref2, and the first node N1 is initialized using the third initialization signal Vref3.

[0106] In one possible implementation, during the hold frame, the third scan signal S3 experiences two high-level pulses, i.e., the negative first initialization signal Vref1 is transmitted to the first terminal S of the first transistor M1 twice. The pixel circuit provided in this application utilizes the negative first initialization signal Vref1 in both the write frame and the hold frame to stage stress relief in the first transistor M1, effectively reducing the threshold drift problem of the first transistor M1 and ensuring the stability of the threshold voltage Vth of the first transistor M1.

[0107] In one possible implementation, the holding frame may also include a light-emitting phase after initialization and stress relief. During the light-emitting phase of the holding frame, the first transistor M1, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 are turned on, while the others are turned off. The drive current output by the first transistor M1 according to its gate potential is transmitted through the sixth transistor M6 to the anode of the light-emitting diode D1, thereby causing the light-emitting diode D1 to emit light according to the drive current.

[0108] The pixel circuit provided in this application resets point S of the first transistor M1 twice during the holding frame, effectively adjusting the threshold voltage of the first transistor M1 and improving the ghosting problem. In addition, the anode of the light-emitting diode D1 is also reset using the second initialization signal Vref2, further optimizing the display effect.

[0109] This invention also provides a driving method for driving a pixel circuit as described in any of the above embodiments. One working cycle of the pixel circuit includes a write frame. During the operation of one write frame, the pixel circuit may include a first initialization stage t1, a data writing stage t2, a second initialization stage t3, and a light emission stage t4. Figure 11 This is a flowchart illustrating a pixel circuit driving method in one embodiment of the present application. In one possible implementation, the pixel circuit driving method may include the following steps S100 to S400.

[0110] Step S100: In the first initialization phase, the level of the first scan signal is configured to the first level, the level of the second scan signal is configured to the second level, and the level of the third scan signal is configured to the second level.

[0111] In the embodiments of this application, the first level may refer to a low level VGL, and the second level may refer to a high level VGH. The first level is lower than the second level.

[0112] In the first initialization phase t1, the level of the first scan signal S1 is the first level, the level of the second scan signal S2 is the second level, and the level of the third scan signal S3 is the second level. In this embodiment, the first level can refer to a low level VGL, and the second level can refer to a high level VGH, that is, the first level is less than the second level. The second transistor M2 is turned off according to the low level of the first scan signal S1, and the eighth transistor M8 is turned on according to the low level of the first scan signal S1. The third transistor M3 is turned on according to the high level of the second scan signal S2, the fourth transistor M4 and the seventh transistor M7 are turned on according to the high level of the third scan signal S3, and the fifth transistor M5 is turned off according to the high level of the third scan signal S3.

[0113] In one possible implementation, the level of the light emission control signal EM is a first level (low level VGL). The sixth transistor M6 is turned on according to the low level of the light emission control signal EM.

[0114] In the first initialization phase t1, the fourth transistor M4 transmits the first initialization signal Vref1 to the first terminal S of the first transistor M1, initializing the first terminal S of the first transistor M1. The eighth transistor M8 transmits the third initialization signal Vref3 to the first node N1, initializing the first node N1. The seventh transistor M7 transmits the second initialization signal Vref2 to the anode of the light-emitting diode D1. Simultaneously, the sixth transistor M6 turns on the second terminal D of the first transistor M1 and the anode of the light-emitting diode D1, and the third transistor M3 turns on the gate and the second terminal of the first transistor M1, so that the second initialization signal Vref2 is transmitted sequentially through the sixth transistor M6 and the third transistor M3 to the gate of the first transistor M1. The second initialization signal Vref2 simultaneously initializes the anode of the light-emitting diode D1, the second terminal D of the first transistor M1, the gate G of the first transistor M1, and the second terminal of the first capacitor C1. In the first initialization phase t1, the initialization of each node in the pixel circuit can be realized, and stress relief can also be achieved for the first transistor M1 before writing.

[0115] Step S200: During the data writing stage, the level of the first scan signal is configured to the second level, the level of the second scan signal is configured to the second level, and the level of the third scan signal is configured to the first level.

[0116] During the data writing phase t2, the level of the first scan signal S1 is the second level (high level VGH), the level of the second scan signal S2 is the second level, and the level of the third scan signal S3 is the first level (low level VGL). The second transistor M2 is turned on according to the high level of the first scan signal S1, and the eighth transistor M8 is turned off according to the high level of the first scan signal S1. The third transistor M3 is turned on according to the high level of the second scan signal S2, the fourth transistor M4 and the seventh transistor M7 are turned off according to the low level of the third scan signal S3, and the fifth transistor M5 is turned on according to the low level of the third scan signal S3.

[0117] In one possible implementation, the level of the light emission control signal EM is the second level (high level VGH). The sixth transistor M6 is turned off according to the high level of the light emission control signal EM.

[0118] During the data writing phase t2, the second transistor M2 transmits the data signal Vdata to the first node N1. At this time, the potential at the first node N1 is VN1 = Vdata. The first power supply signal ELVDD is transmitted to the first terminal S of the first transistor M1 through the fifth transistor M5. The first transistor M1 is turned on. Simultaneously, the third transistor M3 turns on the gate and second terminal of the first transistor M1. Therefore, the first power supply signal ELVDD is transmitted to the gate of the first transistor M1 sequentially through the fifth transistor M5, the first transistor M1, and the third transistor M3. At this time, the potentials at the gate G and drain D of the first transistor M1 are both ELVDD - |Vth|. In addition, since the sixth transistor M6 is turned off, the light-emitting device D1 does not emit light.

[0119] Step S300: In the second initialization phase, the level of the first scan signal is configured to the first level, the level of the second scan signal is configured to the first level, and the level of the third scan signal is configured to the second level.

[0120] During the second initialization phase t3, the level of the first scan signal S1 is the first level (low level VGL), the level of the second scan signal S2 is the first level, and the level of the third scan signal S3 is the second level (high level VGH). The second transistor M2 is turned off according to the low level of the first scan signal S1, and the eighth transistor M8 is turned on according to the low level of the first scan signal S1. The third transistor M3 is turned off according to the low level of the second scan signal S2, the fourth transistor M4 and the seventh transistor M7 are turned on according to the high level of the third scan signal S3, and the fifth transistor M5 is turned off according to the high level of the third scan signal S3.

[0121] In one possible implementation, the level of the light emission control signal EM is the second level (high level VGH). The sixth transistor M6 is turned off according to the high level of the light emission control signal EM.

[0122] In the second initialization phase t3, the eighth transistor M8 transmits the third initialization signal Vref3 to the first node N1, causing a potential change at the first node N1 from Vdata to Vref3. Simultaneously, since the third transistor M3 is off, the second node N1 is in a floating state. The potential at the second terminal of the first capacitor C1 changes synchronously with the potential at its first terminal, meaning the first capacitor C1 couples the potential change at the first node N1 to the second node N2. The potential at the gate G of the first transistor M1 becomes VG = ELVDD - |Vth| - Vdata + Vref3. The fourth transistor M4 again transmits the first initialization signal Vref1 to the first terminal S of the first transistor M1, achieving stress relief for the first transistor M1 after writing.

[0123] Step S400: During the light emission stage, the level of the first scan signal is configured to a first level, the level of the second scan signal is configured to a first level, and the level of the third scan signal is configured to a first level.

[0124] During the light-emitting phase t4, the levels of the first scan signal S1, the second scan signal S2, and the third scan signal S3 are all at the first level. The second transistor M2 is turned off according to the low level of the first scan signal S1, and the eighth transistor M8 is turned on according to the low level of the first scan signal S1. The third transistor M3 is turned off according to the low level of the second scan signal S2, the fourth transistor M4 and the seventh transistor M7 are turned off according to the low level of the third scan signal S3, and the fifth transistor M5 is turned on according to the low level of the third scan signal S3.

[0125] In one possible implementation, the level of the light emission control signal EM is a first level. The sixth transistor M6 is turned on according to the low level of the light emission control signal EM.

[0126] During the light-emitting phase t4, transistors M1, M5, M6, and M8 are turned on, while the rest are turned off. Transistor M1 can generate a drive signal based on its gate-source voltage. The drive current I output by transistor M1 is... D The current can be transmitted to the anode of LED D1 via the sixth transistor M6, thus LED D1 responds to the driving current I. D Glowing light.

[0127] When the driving method of the pixel circuit described above is applied to the pixel circuit, each node is reset in the first initialization phase t1, and there is no micro-short circuit between signals, which can effectively improve image retention and reduce power consumption. When compensating the threshold voltage Vth of the first transistor M1, the compensation time for the threshold voltage is adjustable, enabling simultaneous compensation of multiple rows of pixel circuits, thus achieving high-frequency driving. During data writing, the data signal Vdata is written to the first node N1, and the first capacitor C1 couples the data signal Vdata to the first transistor M1. Capacitive coupling enables rapid data writing, which can be applied to high-brightness display scenarios. Furthermore, by transmitting the negative first initialization signal Vref1 twice to the first terminal S of the first transistor M1, the stress on the first transistor M1 is more fully released, resulting in better improvement of the threshold drift of the first transistor M1 and better ensuring the stability of the threshold voltage Vth of the first transistor M1.

[0128] In one possible implementation, the pixel circuit may further include a hold frame in one operating cycle. The levels of the first scan signal S1 and the second scan signal S2 may be continuously configured to be the cutoff levels of the data writing module 120 and the threshold compensation module 130 during the hold frame, that is, the levels of the first scan signal S1 and the second scan signal S2 may be continuously at the first level (low level VGL) during the hold frame.

[0129] In one possible implementation, the timing waveform of the third scan signal S3 in the write frame is the same as that in the hold frame, and the timing waveform of the light emission control signal EM in the write frame is the same as that in the hold frame.

[0130] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple steps or stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0131] This invention also provides a display panel that may include the pixel circuits described in any of the above embodiments. The display panel may include one or more sets of pixel circuits. The pixel circuits may be configured to generate driving signals and use these driving signals to drive the light-emitting units to emit light. This display panel can be applied to any product or component with display functionality, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc. This invention does not impose any special limitations on these categories.

[0132] This invention also provides a display device, which may include the pixel circuit described in any of the above embodiments. The display device may include one or more sets of pixel circuits. The pixel circuits may be configured to generate driving signals and use these driving signals to drive the light-emitting units to emit light. Similarly, this display device can be applied to any product or component with display functionality, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc. This invention does not impose any special limitations on these categories.

[0133] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0134] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0135] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A pixel circuit, characterized in that, include: The data writing module is connected to the first node and is used to transmit data signals to the first node according to the first scan signal during the data writing stage; A coupling module, connected between the first node and the second node, is used to couple the potential change at the first node to the second node; A drive module, the control terminal of which is connected to the second node, is used to output drive signals; A threshold compensation module is connected between the control terminal and the second terminal of the drive module, and is used to connect the control terminal and the second terminal of the drive module according to the second scan signal at least during the data writing phase. A first initialization module is connected to the first end of the driving module and is used to transmit a first initialization signal to the first end of the driving module according to the third scan signal. The third scanning signal is configured to be at the on level of the first initialization module during a portion of the phases before and / or after the data writing phase.

2. The pixel circuit according to claim 1, characterized in that, The driving module includes a first transistor, the gate of the first transistor serves as the control terminal of the driving module, the first electrode of the first transistor serves as the first terminal of the driving module, and the second electrode of the first transistor serves as the second terminal of the driving module. Preferably, the data writing module includes a second transistor, the gate of the second transistor serves as the control terminal of the data writing module and is connected to the first scan signal, the first electrode of the second transistor serves as the first terminal of the data writing module and is connected to the data signal, and the second electrode of the second transistor serves as the second terminal of the data writing module and is connected to the first node. Preferably, the threshold compensation module includes a third transistor, the gate of the third transistor is connected to the second scan signal as the control terminal of the threshold compensation module, the first electrode of the third transistor is connected to the control terminal of the driving module as the first terminal of the threshold compensation module, and the second electrode of the third transistor is connected to the second terminal of the driving module as the second terminal of the threshold compensation module. Preferably, the first initialization module includes a fourth transistor, the gate of the fourth transistor is connected to the third scan signal as the control terminal of the first initialization module, the first terminal of the fourth transistor is connected to the first initialization signal as the first terminal of the first initialization module, and the second terminal of the fourth transistor is connected to the first terminal of the driving module as the second terminal of the first initialization module. Preferably, the coupling module includes a first capacitor, the first terminal of the first capacitor is connected to the first node as the first end of the coupling module, and the second terminal of the first capacitor is connected to the second node as the second end of the coupling module.

3. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: A first light-emitting control module is connected between a first power line and a first end of the driving module, and is used to turn on or off the connection between the first power line and the first end of the driving module according to a third scanning signal. Preferably, when the third scan signal is configured to be the on level of the first initialization module, the first light emission control module is turned off according to the third scan signal; when the third scan signal is configured to be the off level of the first initialization module, the first light emission control module is turned on according to the third scan signal. Preferably, the first light-emitting control module includes a fifth transistor, the gate of the fifth transistor is connected to the third scan signal as the control terminal of the first light-emitting control module, the first electrode of the fifth transistor is connected to the first power line as the first terminal of the first light-emitting control module, and the second electrode of the fifth transistor is connected to the first terminal of the driving module as the second terminal of the first light-emitting control module.

4. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: The second light-emitting control module is connected between the second end of the driving module and the first end of the light-emitting device, and is used to turn on or off the connection between the second end of the driving module and the first end of the light-emitting device according to the light-emitting control signal; Preferably, the second light-emitting control module includes a sixth transistor, the gate of the sixth transistor serves as the control terminal of the second light-emitting control module and is connected to the light-emitting control signal, the first electrode of the sixth transistor serves as the first terminal of the second light-emitting control module and is connected to the second terminal of the driving module, and the second electrode of the sixth transistor serves as the second terminal of the second light-emitting control module and is connected to the light-emitting device. Preferably, the pixel circuit further includes: The second initialization module is connected to the first end of the light-emitting device and is used to transmit the second initialization signal to the first end of the light-emitting device according to the third scanning signal; Preferably, the on-level of the second initialization module is the same as the on-level of the first initialization module, and the off-level of the second initialization module is the same as the off-level of the first initialization module. Preferably, the second initialization module includes a seventh transistor, the gate of the seventh transistor is connected to the third scan signal as the control terminal of the second initialization module, the first terminal of the seventh transistor is connected to the second initialization signal as the first terminal of the second initialization module, and the second terminal of the seventh transistor is connected to the first terminal of the light-emitting device as the second terminal of the second initialization module. Preferably, the first initialization signal is the same as the second initialization signal; Preferably, the first initialization signal is less than zero.

5. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: The third initialization module is connected to the first node and is used to transmit the third initialization signal to the first node according to the first scan signal; Preferably, when the first scan signal is configured to be the on level of the data writing module, the third initialization module is turned off according to the third scan signal; when the first scan signal is configured to be the off level of the data writing module, the third initialization module is turned on according to the third scan signal. Preferably, the third initialization module includes an eighth transistor, the gate of the eighth transistor is connected to the first scan signal as the control terminal of the third initialization module, the first terminal of the eighth transistor is connected to the third initialization signal as the first terminal of the third initialization module, and the second terminal of the eighth transistor is connected to the first node as the second terminal of the third initialization module.

6. The pixel circuit according to claim 1, characterized in that, The pixel circuit includes a write frame in one working cycle. The write frame includes a first initialization phase. In the first initialization phase, the first initialization module transmits the first initialization signal to the first terminal of the driving module according to the third scan signal. The second initialization module transmits the second initialization signal to the first terminal of the light-emitting device according to the third scan signal. The second light-emitting control module connects the second terminal of the driving module and the first terminal of the light-emitting device according to the light-emitting control signal. The threshold compensation module connects the control terminal of the driving module and the second terminal of the driving module according to the second scan signal. The third initialization module transmits the third initialization signal to the first node according to the first scan signal. Preferably, after the first initialization phase, the write frame includes a data write phase. In the data write phase, the data write module transmits the data signal to the first node according to the first scan signal, the first light emission control module connects the first power line to the first end of the drive module according to the third scan signal, and the threshold compensation module connects the control end of the drive module to the second end of the drive module according to the second scan signal. Preferably, after the data writing stage, the write frame includes a second initialization stage. In the second initialization stage, the first initialization module transmits the first initialization signal to the first end of the driving module according to the third scan signal, the second initialization module transmits the second initialization signal to the first end of the light-emitting device according to the third scan signal, and the third initialization module transmits the third initialization signal to the first node according to the first scan signal. Preferably, after the second initialization phase, the write frame includes a light emission phase, in which the third initialization module transmits the third initialization signal to the first node according to the first scan signal, the first light emission control module connects the first power line to the first end of the driving module according to the third control signal, and the second light emission control module connects the second end of the driving module to the first end of the light emission device according to the light emission control signal.

7. The pixel circuit according to claim 6, characterized in that, The pixel circuit also includes a hold frame in one working cycle, wherein the levels of the first scan signal and the second scan signal are configured as the cutoff levels of the data writing module and the threshold compensation module in the hold frame; Preferably, the timing waveform of the third scan signal in the write frame is the same as the timing waveform in the hold frame, and the timing waveform of the light emission control signal in the write frame is the same as the timing waveform in the hold frame.

8. A driving method for a pixel circuit, characterized in that, For driving a pixel circuit as described in any one of claims 1 to 7, wherein a write frame is included in one operating cycle of the pixel circuit, and the write frame includes at least a first initialization phase, a data writing phase, a second initialization phase, and a light emission phase, the driving method comprising: In the first initialization phase, the level of the first scan signal is configured to a first level, the level of the second scan signal is configured to a second level, and the level of the third scan signal is configured to the second level; During the data writing phase, the level of the first scan signal is configured to the second level, the level of the second scan signal is configured to the second level, and the level of the third scan signal is configured to the first level; In the second initialization phase, the level of the first scan signal is configured to the first level, the level of the second scan signal is configured to the first level, and the level of the third scan signal is configured to the second level; During the light emission stage, the level of the first scan signal is configured to the first level, the level of the second scan signal is configured to the first level, and the level of the third scan signal is configured to the first level. Wherein, the first level is lower than the second level.

9. The driving method for the pixel circuit according to claim 8, characterized in that, The driving method further includes: During the first initialization phase, the level of the light emission control signal is configured to the first level; During the data writing phase, the level of the light emission control signal is configured to the second level; In the second initialization phase, the level of the light emission control signal is configured to the second level; During the light-emitting phase, the level of the light-emitting control signal is configured to the first level; Preferably, the pixel circuit further includes a hold frame in one working cycle, and the driving method further includes: in the hold frame, configuring the level of the first scan signal and the level of the second scan signal to the first level; Preferably, the timing waveform of the third scan signal in the write frame is the same as the timing waveform in the hold frame, and the timing waveform of the light emission control signal in the write frame is the same as the timing waveform in the hold frame.

10. A display panel, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 7.

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