Backlight alignment timing control method for avoiding liquid crystal flipping interference

Abstract

The application discloses a backlight alignment timing control method for avoiding liquid crystal flip interference, and the method comprises the following steps: setting a brightness duty cycle threshold for a PWM dimming signal, wherein the high level signal duration corresponding to the duty cycle corresponding to the brightness duty cycle threshold is less than or equal to the liquid crystal steady state duration T0; when the signal duty cycle of the PWM dimming signal is less than or equal to the brightness duty cycle threshold, the PWM dimming signal adopts a first alignment mode for alignment; when the signal duty cycle of the PWM dimming signal is greater than the brightness duty cycle threshold, the PWM dimming signal adopts at least one second alignment mode for alignment.

Description

Technical Field

[0001] This invention relates to the field of LED backlight control technology, and in particular to a backlight alignment timing control method that avoids liquid crystal flipping interference. Background Technology

[0002] In order to prevent adverse phenomena such as ion migration and image retention caused by the liquid crystal medium being subjected to a unidirectional DC electric field for a long time during the driving process of the liquid crystal display device, the polarity of the pixel voltage needs to be periodically reversed according to a preset timing sequence.

[0003] Current LED backlight control mainly employs a fixed head-alignment or tail-alignment timing strategy, using the Vsync signal as the frame synchronization signal and performing liquid crystal flipping line by line. The transmittance change curve of the liquid crystal layer during the liquid crystal molecule flipping process consists of the following stages: rising region, stable plateau region, and falling region. At the beginning of the frame, the liquid crystal pixel voltage is in the rising establishment phase; at the end of the frame, near the liquid crystal polarity flipping point, both the beginning and end of the frame have a timing margin and are not illuminated. Because the response of the liquid crystal molecules requires time, the pixel transmittance is unstable at this time, displaying a "transitional state."

[0004] If the LED is lit during the transition state, the human eye will see blurry edges and motion blur. However, lighting the backlight in the steady state area of ​​the liquid crystal can avoid blurry or motion blur. Only when the LED is lit during the period when the pixel transparency is completely stable can the brightness output of each frame be ensured to be consistent and uneven brightness be avoided.

[0005] For high refresh rate LCD screens, it takes about 1-5ms for the liquid crystal to stabilize after the initial flip-up. For regular refresh rates (below 120Hz), each frame has at least 3ms to stabilize the output brightness. However, for high refresh rates (above 240Hz), it is difficult to achieve the same 3ms stable brightness output.

[0006] like Figure 1As shown, when driving LEDs with a high brightness duty cycle (large brightness duty ratio), the rising edge of the LED output exceeds the steady-state duration T of the liquid crystal (the optimal brightness range of the LED). If the dimming duty cycle signal is still specified using the tail-alignment mode, the leading edge of the LED dimming pulse will fall into the rising transition region where the transmittance is unstable. The real-time fluctuation of the liquid crystal transmittance directly causes abnormal grayscale and poor color shift in the image. To avoid the display defects caused by LEDs in the transition region, the existing solution can only narrow the lamp-on duration by compressing the LED lamp-on duty cycle. The shortened lamp-on duration directly causes a decrease in backlight output power, resulting in low overall screen brightness. In summary, the traditional LED driving control method with fixed alignment mode cannot simultaneously meet the design requirements of high-frequency refresh rate and backlight brightness output. Therefore, a new LED backlight driving method is needed in the existing technology, especially a backlight alignment timing control method that can avoid liquid crystal flip interference. Summary of the Invention

[0007] The technical objective of this invention is to provide a backlight alignment timing control method that avoids interference from liquid crystal flipping. This method addresses the shortcomings of existing technologies where fixed tail alignment of LEDs cannot simultaneously prevent color shift and maintain screen brightness. This invention adaptively switches the backlight alignment mode based on the real-time brightness of the screen. When the brightness is high (the optimal brightness range of the LEDs), a non-tail alignment mode is used for alignment, and when the brightness is low (the optimal brightness range of the LEDs), a tail alignment mode is used for alignment. In high refresh rate applications, this reduces grayscale deviation and color shift caused by liquid crystal polarity flipping, maximizes the effective backlight illumination time, and effectively balances screen display quality and backlight brightness.

[0008] Based on the above technical objectives, the present invention provides a backlight alignment timing control method for avoiding liquid crystal flip-out interference, the method comprising:

[0009] A brightness duty cycle threshold is set for the PWM dimming signal, wherein the duration of the high-level signal corresponding to the duty cycle of the brightness duty cycle threshold is less than or equal to the steady-state duration T0 of the liquid crystal.

[0010] When the duty cycle of the PWM dimming signal is less than or equal to the brightness duty cycle threshold, the PWM dimming signal is aligned using the first alignment mode.

[0011] When the duty cycle of the PWM dimming signal is greater than the brightness duty cycle threshold, the PWM dimming signal is aligned using at least one second alignment mode.

[0012] In one embodiment, the first alignment pattern is a tail alignment pattern relative to the period of the field vertical signal Vsync signal.

[0013] In one embodiment, the first alignment mode is a tail alignment mode relative to the liquid crystal steady-state duration T0.

[0014] In one embodiment, the second alignment mode is a center alignment mode that uses the center point of the liquid crystal steady-state duration T0 as the alignment point.

[0015] This invention also provides another backlight alignment timing control method to avoid liquid crystal flipping interference, the method comprising:

[0016] A first brightness duty cycle threshold is set for the PWM dimming signal, wherein the duration of the high-level signal corresponding to the duty cycle of the first brightness duty cycle threshold is less than or equal to the steady-state duration T0 of the liquid crystal.

[0017] When the duty cycle of the PWM dimming signal is less than or equal to the brightness duty cycle threshold, the PWM dimming signal is aligned using the first alignment mode.

[0018] For the PWM dimming signal, there are also two brightness duty cycle thresholds, from the second to the nth, where n ≥ 3. Each of these thresholds corresponds to an alignment point m. i , 1≦i≦n-1;

[0019] Furthermore, when the duty cycle (Duty) of the PWM dimming signal satisfies: the ith brightness duty cycle threshold ≦ Duty ≦ the (i+1)th brightness duty cycle threshold, the PWM dimming signal will be aligned with point m. i Alignment is performed based on the (i+1)th alignment pattern, where 1 ≦ i ≦ n-1.

[0020] In one embodiment, all alignment points m i All are within the steady-state duration T0 of the liquid crystal.

[0021] In one embodiment, with alignment point m i The alignment pattern based on the (i+1)th alignment point is at alignment point m. i The alignment of the high-level duration T of each cycle of the PWM dimming signal, which is distributed proportionally before and after.

[0022] In one embodiment, the first alignment mode is a tail alignment mode relative to the period of the field vertical signal Vsync signal.

[0023] In one embodiment, the first alignment mode is a tail alignment mode relative to the liquid crystal steady-state duration T0.

[0024] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0026] Figure 1 This is a schematic diagram of LED backlight driving using the tail-aligned mode in existing technology;

[0027] Figure 2 This is a schematic diagram of the backlight alignment timing according to the first embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the backlight alignment timing according to the second embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram showing the proportional distribution of backlight alignment points according to the second embodiment of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And when a second element, component, area, layer, or portion is discussed, it does not imply that the first element, component, area, layer, or portion necessarily exists in this invention.

[0032] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0034] Example 1

[0035] like Figure 2 As shown, the backlight alignment timing control method for avoiding liquid crystal flipping interference of the present invention includes:

[0036] First, a brightness duty cycle threshold is set for the PWM dimming signal. The duration of the high-level signal corresponding to the duty cycle of the brightness duty cycle threshold is less than or equal to the steady-state duration T0 of the liquid crystal. In this embodiment, the duration of the high-level signal corresponding to the duty cycle of the brightness duty cycle threshold is set to be exactly equal to the steady-state duration T0 of the liquid crystal.

[0037] When the duty cycle of the PWM dimming signal is less than or equal to the brightness duty cycle threshold, the PWM dimming signal is aligned using a first alignment mode. In this embodiment, the first alignment mode is a tail alignment mode relative to the period of the vertical signal Vsync. That is, in the first alignment mode, the high-level duration T of each period of the PWM dimming signal is aligned with the end point of each frame of the vertical signal Vsync.

[0038] When the duty cycle of the PWM dimming signal is greater than the brightness duty cycle threshold, the PWM dimming signal is aligned using a second alignment mode. In this embodiment, the second alignment mode is a center alignment mode using the center point of the liquid crystal steady-state duration T0 as the alignment point. That is, in the second alignment mode, the center point of the high-level duration T of each cycle of the PWM dimming signal is aligned with the center point of the liquid crystal steady-state duration T0. Figure 2 As can be seen, when the center point of the liquid crystal steady-state duration T0 is used as the alignment point for signal alignment, the liquid crystal transmittance change Δ2 on the left side of the high-level duration T of each cycle of the PWM dimming signal that exceeds the liquid crystal steady-state duration T0 and the liquid crystal transmittance change Δ3 on the right side that exceeds the liquid crystal steady-state duration T0 are both smaller than the liquid crystal transmittance change Δ1 when tail alignment is used in the prior art. This can improve the grayscale abnormality caused by the change in liquid crystal transmittance under high brightness conditions.

[0039] In this embodiment, when the duration of each cycle of the PWM dimming signal is T PWM When the high-level duration within the cycle is T, the duty cycle of the PWM dimming signal is T / T. PWM In other words, the longer the high-level duration T is, the larger the duty cycle, and the higher the brightness corresponding to the PWM dimming signal.

[0040] In this embodiment, the duration of the high-level signal corresponding to the duty cycle corresponding to the brightness duty cycle threshold is set to be exactly equal to the steady-state duration T0 of the liquid crystal. Those skilled in the art should know that the duration of the high-level signal corresponding to the duty cycle corresponding to the brightness duty cycle threshold can also be set to be slightly less than the steady-state duration T0 of the liquid crystal, which can also achieve the technical objective of this embodiment.

[0041] Example 2

[0042] like Figure 3-4 As shown, the backlight alignment timing control method for avoiding liquid crystal flipping interference of the present invention includes:

[0043] First, a first brightness duty cycle threshold is set for the PWM dimming signal. The duration of the high-level signal corresponding to the duty cycle of the first brightness duty cycle threshold is less than or equal to the liquid crystal steady-state duration T0. In this embodiment, the duration of the high-level signal corresponding to the duty cycle of the brightness duty cycle threshold is set to be exactly equal to the liquid crystal steady-state duration T0.

[0044] When the duty cycle of the PWM dimming signal is less than or equal to the first brightness duty cycle threshold, the PWM dimming signal is aligned using a first alignment mode. In this embodiment, the first alignment mode is a tail alignment mode relative to the period of the vertical signal Vsync. That is, in the first alignment mode, the high-level duration T of each period of the PWM dimming signal is aligned with the end point of each frame of the vertical signal Vsync.

[0045] When the duty cycle of the PWM dimming signal is greater than the first brightness duty cycle threshold and less than or equal to the second brightness duty cycle threshold, the PWM dimming signal is aligned using a second alignment mode. In this embodiment, the second alignment mode is an alignment method in which the high-level duration T of each cycle of the PWM dimming signal is proportionally distributed before and after the first alignment point, based on a first alignment point reference value M1. Figure 4 As shown, when the alignment reference value M is the first alignment point reference value M1, the first alignment point is located at the dividing point where the first half of the liquid crystal steady-state duration T0 has a duration of M1 and the second half has a duration of T0-M1, or at the dividing point where the first half of the duration is a proportional division point of the entire liquid crystal steady-state duration T0 (M1 / T0). This proportional division point is the first alignment point. Simultaneously, the high-level duration T of each cycle of the PWM dimming signal is aligned with the first alignment point. Before the first alignment point, the high-level duration is T×(M1 / T0), and after the first alignment point, the high-level duration is T×[(M1-T0) / T0]. Through this alignment method, when the liquid crystal transmittance change curves on both sides of the liquid crystal steady-state duration T0 are inconsistent, the high-level duration range in the PWM dimming signal can be adjusted to move towards the side where the liquid crystal transmittance change is relatively slower, thereby obtaining a better display effect.

[0046] Similarly, further, when the duty cycle of the PWM dimming signal is greater than the second brightness duty cycle threshold and less than or equal to the third brightness duty cycle threshold, the PWM dimming signal is aligned using the third alignment mode. In this embodiment, the third alignment mode is an alignment method in which the high-level duration T of each cycle of the PWM dimming signal is proportionally distributed before and after the second alignment point, based on the second alignment point reference value M2. Figure 4As shown, when the alignment reference value M is the second alignment point reference value M2, the second alignment point is located at the division point where the first half duration of the liquid crystal steady state duration T0 is M2 and the second half duration is T0 - M2, or at the proportional division point where the first half duration is M2 / T0 of the entire liquid crystal steady state duration T0. This proportional division point is the second alignment point. At the same time, the high-level duration T of each cycle of the PWM dimming signal is aligned based on the second alignment point. In the front part of the second alignment point, the high-level duration is T×(M2 / T0), and in the rear part of the second alignment point, the high-level duration is T×[(M2 - T0) / T0].

[0047] Similarly, further, when the signal duty ratio of the PWM dimming signal is greater than the third brightness duty ratio threshold and less than or equal to the fourth brightness duty ratio threshold, the PWM dimming signal is aligned using the fourth alignment mode. In this embodiment, the fourth alignment mode is an alignment method in which the high-level duration T of each cycle of the PWM dimming signal is proportionally distributed before and after the third alignment point determined by the third alignment point reference value M3. Similarly, as Figure 4 shown, when the alignment reference value M is the third alignment point reference value M3, the second alignment point is located at the division point where the first half duration of the liquid crystal steady state duration T0 is M3 and the second half duration is T0 - M3, or at the proportional division point where the first half duration is M3 / T0 of the entire liquid crystal steady state duration T0. This proportional division point is the third alignment point. At the same time, the high-level duration T of each cycle of the PWM dimming signal is aligned based on the third alignment point. In the front part of the second alignment point, the high-level duration is T×(M3 / T0), and in the rear part of the second alignment point, the high-level duration is T×[(M3 - T0) / T0].

[0048] In this embodiment, the first alignment point reference value M1, the second alignment point reference value M2, and the third alignment point reference value M3 satisfy M1 < M2 < M3. That is, as the duty ratio of the PWM dimming signal corresponding to the brightness increases, the corresponding alignment point moves to the right side of the liquid crystal steady state duration T0. Or when the change in the liquid crystal transmittance around the liquid crystal steady state duration T0 is opposite to Figure 3-4 as shown, it can also be set as M1 > M2 > M3. In short, it is sufficient to meet the requirement in this embodiment that the high-level duration interval in the PWM dimming signal is adjusted to move to the side where the change in the liquid crystal transmittance is relatively slow.

[0049] Further, those skilled in the art should know that only three alignment reference values, namely the first alignment point reference value M1, the second alignment point reference value M2, and the third alignment point reference value M3, are set in this embodiment. According to actual needs, those skilled in the art can set more alignment reference values M to make the alignment timing control more refined.

[0050] In this embodiment, the duration of the high-level signal corresponding to the duty cycle corresponding to the brightness duty cycle threshold is set to be exactly equal to the steady-state duration T0 of the liquid crystal. Those skilled in the art should know that the duration of the high-level signal corresponding to the duty cycle corresponding to the brightness duty cycle threshold can also be set to be slightly less than the steady-state duration T0 of the liquid crystal, which can also achieve the technical objective of this embodiment.

[0051] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A backlight alignment timing control method to avoid liquid crystal flipping interference, characterized in that, The method includes: A brightness duty cycle threshold is set for the PWM dimming signal, wherein the duration of the high-level signal corresponding to the duty cycle of the brightness duty cycle threshold is less than or equal to the steady-state duration T0 of the liquid crystal. When the duty cycle of the PWM dimming signal is less than or equal to the brightness duty cycle threshold, the PWM dimming signal is aligned using the first alignment mode. When the duty cycle of the PWM dimming signal is greater than the brightness duty cycle threshold, the PWM dimming signal is aligned using at least one second alignment mode.

2. The method according to claim 1, characterized in that, The first alignment mode is a tail alignment mode relative to the period of the field vertical signal Vsync signal.

3. The method according to claim 1, characterized in that, The first alignment mode is the tail alignment mode relative to the steady-state duration T0 of the liquid crystal.

4. The method according to claim 1, characterized in that, The second alignment mode is a center alignment mode that uses the center point of the liquid crystal steady-state duration T0 as the alignment point.

5. A backlight alignment timing control method to avoid liquid crystal flipping interference, characterized in that, The method includes: A first brightness duty cycle threshold is set for the PWM dimming signal, wherein the duration of the high-level signal corresponding to the duty cycle of the first brightness duty cycle threshold is less than or equal to the steady-state duration T0 of the liquid crystal. When the duty cycle of the PWM dimming signal is less than or equal to the brightness duty cycle threshold, the PWM dimming signal is aligned using the first alignment mode. For the PWM dimming signal, there are also two brightness duty cycle thresholds, from the second to the nth, where n ≥ 3. Each of these thresholds corresponds to an alignment point m. i , 1≦i≦n-1; Furthermore, when the duty cycle (Duty) of the PWM dimming signal satisfies: the ith brightness duty cycle threshold ≦ Duty ≦ the (i+1)th brightness duty cycle threshold, the PWM dimming signal will be aligned with point m. i Alignment is performed based on the (i+1)th alignment pattern, where 1 ≦ i ≦ n-1.

6. The method according to claim 5, characterized in that, All alignment points m i All are within the steady-state duration T0 of the liquid crystal.

7. The method according to claim 5, characterized in that, Alignment point m i The alignment pattern based on the (i+1)th alignment point is at alignment point m. i The alignment of the high-level duration T of each cycle of the PWM dimming signal, which is distributed proportionally before and after.

8. The method according to claim 5, characterized in that, The first alignment mode is a tail alignment mode relative to the period of the field vertical signal Vsync signal.

9. The method according to claim 5, characterized in that, The first alignment mode is the tail alignment mode relative to the steady-state duration T0 of the liquid crystal.

10. An LED backlight panel, wherein the LED backlight panel is driven to emit light using a backlight alignment timing control method as described in any one of claims 1-9.

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