Drive circuit board, display device, and voltage output method

Abstract

The present disclosure provides a driving circuit board, a display device and a voltage output method. The driving circuit board comprises a voltage conversion circuit configured to obtain a refresh frequency of a display panel, output an off voltage signal to the display panel according to the refresh frequency, and the off voltage signal is configured to control a switching device of a sub-pixel in the display panel to be in an off state. Wherein, the difference between the voltage value of the off voltage signal and the reference off voltage shows an increasing trend with the increase of the refresh frequency.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving circuit board, a display device, and a voltage output method. Background Technology

[0002] With the development of display technology, people have increasingly higher requirements for the quality of display images, leading to the emergence of FreeSync monitors. FreeSync monitors are display devices equipped with FreeSync technology, which dynamically controls the monitor's refresh rate, helping to improve issues such as screen tearing and stuttering. However, during use, it has been found that these monitors exhibit screen flickering when switching refresh rates. Summary of the Invention

[0003] This disclosure provides a driving circuit board, a display device, and a voltage output method through some embodiments, which are beneficial for improving the aforementioned screen flickering phenomenon.

[0004] In a first aspect of this disclosure, a driving circuit board for a display panel is provided, comprising: a voltage conversion circuit configured to acquire a refresh frequency of the display panel and output a shutdown voltage signal to the display panel according to the refresh frequency, the shutdown voltage signal being configured to control switching devices of sub-pixels in the display panel to be in a shutdown state. The difference between the voltage value of the shutdown voltage signal and a reference shutdown voltage increases with increasing refresh frequency.

[0005] In some embodiments, the voltage conversion circuit includes a microprocessor and a voltage adjustment sub-circuit, the voltage adjustment sub-circuit being electrically connected to the microprocessor. The microprocessor is configured to acquire a frame start signal, determine the refresh rate of the display panel based on the frame start signal, and output a voltage control signal to the voltage adjustment sub-circuit based on the refresh rate. The voltage adjustment sub-circuit is configured to output a shutdown voltage signal to the display panel under the control of the voltage control signal.

[0006] In some embodiments, the microprocessor is configured to determine a target frequency level that matches the refresh frequency from N preset frequency levels, and output a voltage control signal corresponding to the target frequency level, where N is an integer greater than or equal to 2, and the voltage control signals corresponding to different frequency levels are different. Specifically, the higher the level of the frequency level, the higher the refresh frequency, and the higher the level of the target frequency level, the greater the difference between the voltage value of the shutdown voltage signal output by the voltage adjustment subcircuit and the reference shutdown voltage.

[0007] In some embodiments, each frequency level corresponds to a refresh frequency, and the refresh frequency corresponding to the (i+1)th frequency level is greater than the refresh frequency corresponding to the ith frequency level, where i is an integer from 1 to N-1; or, each frequency level corresponds to a refresh frequency range, and the minimum value of the refresh frequency range corresponding to the (i+1)th frequency level is greater than the maximum value of the refresh frequency range corresponding to the ith frequency level, where i is an integer from 1 to N-1.

[0008] In some embodiments, the voltage adjustment subcircuit includes a buck-boost converter chip, a first resistor, a second resistor, and at least one resistance adjustment branch. A first terminal of the first resistor and a first terminal of the second resistor are electrically connected to the feedback terminal of the buck-boost converter chip. A second terminal of the first resistor is electrically connected to the voltage output terminal of the voltage adjustment subcircuit, and a second terminal of the second resistor is grounded. The resistance adjustment branch is connected in parallel with the second resistor. The control terminal of the resistance adjustment branch is electrically connected to the microprocessor and configured to adjust the resistance value of the feedback resistor connected to the feedback terminal of the buck-boost converter chip under the control of the voltage control signal, thereby adjusting the turn-off voltage signal output by the voltage output terminal.

[0009] In some embodiments, the resistance adjustment branch includes a third resistor and a first switching device connected in series. The control terminal of the first switching device is electrically connected to the microprocessor to receive the voltage control signal, which is configured to control the switching state of the first switching device.

[0010] In some embodiments, the voltage regulation sub-circuit includes a buck-boost topology circuit. The control terminal of the second switching device in the buck-boost topology circuit is electrically connected to the microprocessor to receive the voltage control signal. The voltage control signal is a pulse width modulation signal, and the duty cycle of the voltage control signal corresponds to different frequency levels. The buck-boost topology circuit is configured to output the shutdown voltage signal based on the input voltage and the duty cycle of the received voltage control signal.

[0011] In some embodiments, the voltage regulation sub-circuit further includes a level converter, the input terminal of which is electrically connected to the microprocessor, and the output terminal of which is electrically connected to the control terminal of the second switching device. The level converter is configured to perform level conversion on the voltage control signal output by the microprocessor and output the level-converted voltage control signal to the control terminal of the second switching device. The high-level voltage of the level-converted voltage control signal is greater than the high-level voltage of the voltage control signal output by the microprocessor.

[0012] In some embodiments, the voltage conversion circuit further includes a sampling sub-circuit, the input terminal of which is electrically connected to the voltage output terminal of the voltage adjustment sub-circuit, and the output terminal of which is electrically connected to the microprocessor. The sampling sub-circuit is configured to sample the off-voltage signal output by the voltage output terminal and feed the sampled voltage back to the microprocessor, so that the microprocessor adjusts the duty cycle of the voltage control signal according to the sampled voltage.

[0013] In some embodiments, the microprocessor is a timing controller.

[0014] In a second aspect of this disclosure, a display device is provided, including a display panel and a driving circuit board provided in the first aspect. The display panel includes a display area and a border area located on at least one side of the display area. The display area is provided with a plurality of pixel units arranged in an array, each pixel unit including a plurality of sub-pixels. The border area is provided with a gate driving circuit, the gate driving circuit including a plurality of cascaded shift registers. The signal output terminal of the shift register is electrically connected to the control terminal of a switching device of at least one row of sub-pixels. The output terminal of the voltage conversion circuit on the driving circuit board is electrically connected to the off-voltage terminal of the shift register.

[0015] In a third aspect of this disclosure, a voltage output method for a display panel is provided, comprising: acquiring a refresh frequency of the display panel; and outputting a shutdown voltage signal to the display panel according to the refresh frequency, the shutdown voltage signal being configured to control switching devices of sub-pixels in the display panel to be in a shutdown state. The difference between the voltage value of the shutdown voltage signal and a reference shutdown voltage increases with increasing refresh frequency.

[0016] The display panel driver circuit board provided in some embodiments of this disclosure, by setting a voltage conversion circuit, can obtain the refresh rate of the display panel and output a shutdown voltage signal to the display panel according to the refresh rate. The difference between the voltage value of the output shutdown voltage signal and the reference shutdown voltage increases with the increase of the refresh rate. This can increase the leakage current speed at high frequencies, reduce the brightness difference between high-frequency and low-frequency conditions, and help improve the screen flickering phenomenon during refresh rate switching.

[0017] The above description is merely an overview of the technical solutions of some embodiments of this disclosure. In order to better understand the technical means of the embodiments of this disclosure and to implement them in accordance with the contents of the specification, and to make the embodiments of this disclosure more obvious and easy to understand, specific implementation methods of some embodiments of this disclosure are given below. Attached Figure Description

[0018] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the embodiments disclosed herein. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0019] Figure 1 A schematic diagram of the structure of an exemplary display module of this disclosure is shown;

[0020] Figure 2 A schematic diagram of an exemplary gate drive circuit is shown.

[0021] Figure 3 A transfer characteristic curve of an exemplary thin-film transistor (TFT) is shown;

[0022] Figure 4 A schematic diagram of the structure of a driver circuit board according to some embodiments of this disclosure is shown;

[0023] Figure 5 A schematic diagram of the structure of a voltage conversion circuit according to some embodiments of the present disclosure is shown;

[0024] Figure 6 Circuit diagrams of voltage regulation sub-circuits according to some embodiments of the present disclosure are shown;

[0025] Figure 7 Schematic diagrams of voltage conversion circuits according to other embodiments of this disclosure are shown;

[0026] Figure 8 Circuit diagrams of buck-boost topologies according to some embodiments of the present disclosure are shown;

[0027] Figure 9 Circuit diagrams of level converters according to some embodiments of the present disclosure are shown;

[0028] Figure 10 A schematic diagram of the structure of a voltage conversion circuit according to some embodiments of the present disclosure is shown;

[0029] Figure 11 A schematic diagram of the structure of a driver circuit board according to other embodiments of this disclosure is shown;

[0030] Figure 12 A flowchart of a voltage output method according to some embodiments of the present disclosure is shown. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0032] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. “At least one” includes one or more cases. The terms “including,” “comprising,” or “contains,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “electrical connection,” “connection,” or “linked,” and similar terms indicate an electrical connection, whether direct or indirect. “*” represents a multiplication sign.

[0033] Figure 1 A schematic diagram of the structure of an exemplary display module of this disclosure is shown. For example... Figure 1 As shown, the display module 1000 includes a display panel 20. The display panel 20 includes a display area AA and a border area NA located on at least one side of the display area AA.

[0034] The display area AA has multiple pixel units P arranged in an array along a first direction and a second direction. Each pixel unit P includes multiple sub-pixels, such as red sub-pixels, green sub-pixels, and blue sub-pixels. The first direction is the pixel row direction, and the second direction is the pixel column direction; the first and second directions intersect. For example, the first direction can be perpendicular to the second direction. Figure 1 The X-axis direction, the second direction can be Figure 1 The Y-axis direction in the diagram.

[0035] like Figure 1 As shown, the display panel 20 may also include multiple scan lines GL and multiple data lines DL. The scan lines GL extend along a first direction, and the data lines DL extend along a second direction. The multiple scan lines GL and multiple data lines DL intersect each other to define multiple pixel areas distributed in an array in the display area AA, and the pixel openings of the sub-pixels are located within the pixel areas.

[0036] When the display panel 20 is a liquid crystal display panel, the pixel arrangement of the display panel 20 can adopt a pixel arrangement method with a Single Gate driving architecture, or a pixel arrangement method with a Dual Gate driving architecture, or a pixel arrangement method with a Triple Gate driving architecture. This disclosure does not limit this.

[0037] Figure 1 The illustration uses a display panel 20 employing a Single Gate driving architecture as an example. Each pixel unit P includes elements along a first direction (e.g., ...). Figure 1 The sub-pixels are arranged along the X-axis (as shown in the image). Each row of sub-pixels corresponds to a grid line GL, and each column of sub-pixels corresponds to a data line DL. These grid lines GL and data lines DL intersect and are used to define sub-pixels within the pixel areas defined in the display area AA.

[0038] For example, in a Dual Gate driving architecture, each sub-pixel includes a long side and a short side. The long side is set along a second direction (e.g., vertical), and the short side is set along a first direction (e.g., horizontal). Sub-pixels in the same column emit the same color. Along the first direction, two adjacent sub-pixels can share a single data line DL. Two gate lines GL are set for each row of sub-pixels. The aforementioned multiple gate lines GL and multiple data lines DL intersect each other, and two sub-pixels are set in each pixel area defined in the display area AA. For example, in a Triple Gate driving architecture, each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel arranged along a second direction (e.g., vertical), which is equivalent to three columns of sub-pixels sharing a single data line DL. The red, green, and blue sub-pixels of the same pixel unit are connected to three different gate lines GL.

[0039] When the display panel 20 is a liquid crystal display panel, the display panel 20 may include an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. The aforementioned plurality of gate lines GL and plurality of data lines DL are disposed on the array substrate. In some embodiments, the array substrate may further include a pixel electrode for each sub-pixel, a common electrode, and a switching device T for controlling each sub-pixel. The switching device T may be, for example, a transistor, such as a thin-film transistor (TFT). Alternatively, other suitable switching devices T may be used, and this disclosure does not limit this. Of course, in other embodiments, the common electrode may also be disposed on the color filter substrate, depending on the actual needs of the product, and this disclosure does not limit this.

[0040] like Figure 1As shown, taking a thin-film transistor (TFT) as an example, the gate (G) of the TFT is electrically connected to the gate line GL, the drain (D) is electrically connected to the data line DL, and the source (S) can be electrically connected to the pixel electrode. For example, when the switch is in the ON state, the data voltage signal transmitted by the data line DL is transmitted to the pixel electrode. The electric field generated between the pixel electrode and the common electrode controls the deflection of the liquid crystal molecules in the liquid crystal layer region corresponding to the sub-pixel, thereby controlling the light emission brightness of the sub-pixel. When the switch is in the OFF state, the liquid crystal molecules do not deflect, and the sub-pixel is in the OFF state.

[0041] In some embodiments, the display module 1000 may further include a gate driving circuit 210 disposed at the bezel area NA of the display panel 20. The gate driving circuit 210 is electrically connected to the gate line GL and configured to output a gate driving signal to the gate line GL. Figure 1 As shown, the gate driving circuit 210 can be, for example, a GOA (Gate Driver on Array) circuit, that is, a gate driving circuit 210 integrated on the array substrate of the display panel 20.

[0042] The gate drive circuit 210 includes multiple cascaded shift registers 211, also referred to as GOA units. The gate drive circuit 210 may include M cascaded groups, each cascaded group including multiple cascaded shift registers 211, where M is an integer greater than or equal to 1. For example, one, two, three, or more cascaded groups can be configured, depending on the actual product requirements; this disclosure does not impose any limitations on this. For example, the shift register 211 may include a first clock signal terminal, a second clock signal terminal, a turn-off voltage terminal, a signal input terminal, a signal output terminal, and a reset terminal. Within the same cascaded group, the signal output terminal of the current stage is electrically connected not only to the corresponding gate line GL, but also to the signal output terminal of the next stage and the reset terminal of the previous stage. The signal input terminal of the first-stage shift register 211 in each cascaded group receives the frame start signal.

[0043] In some embodiments, the display panel 20 further includes clock signal lines and shutdown voltage signal lines disposed in the bezel area NA. For example, the clock signal lines and shutdown voltage signal lines can be disposed in the bezel area NA on the side where the gate driving circuit 210 is located, between the gate driving circuit 210 and the display area AA, or on the side of the gate driving circuit 210 away from the display area AA. The number of clock signal lines can be set according to the needs of the actual product, for example, it can be 2, 4 or 8, etc.

[0044] Figure 2 A schematic diagram of the circuit structure of an exemplary gate drive circuit 210 is shown. Figure 2The example shown uses a gate drive circuit 210 comprising a cascaded group (only the cascaded shift registers 211 from the first to the fourth stage are shown), with two clock signal lines, as an example and not a limitation. Figure 2 As shown, the first clock signal terminal CLK and the second clock signal terminal CLB of each stage shift register 211 are electrically connected to the first clock signal line CK1 and the second clock signal line CK2, respectively, and the turn-off voltage terminal VSS is electrically connected to the turn-off voltage signal line Vss. The signal input terminal Input of the first stage shift register 211 receives the frame start signal STV, the signal output terminal Output is electrically connected to the gate line GL of the corresponding row sub-pixel, and the reset terminal Reset is electrically connected to the signal output terminal Output of the second stage shift register 211; the signal input terminal Input of the second stage shift register 211 is electrically connected to the signal output terminal Output of the first stage shift register 211, the signal output terminal Output is electrically connected to the gate line GL of the corresponding row sub-pixel, and the reset terminal Reset is electrically connected to the signal output terminal Output of the third stage shift register 211; the third... The input terminal of the first-stage shift register 211 is electrically connected to the output terminal of the second-stage shift register 211, and the output terminal of the second-stage shift register 211 is electrically connected to the gate line GL of the corresponding row sub-pixel. The reset terminal is electrically connected to the output terminal of the fourth-stage shift register 211. The input terminal of the fourth-stage shift register 211 is electrically connected to the output terminal of the third-stage shift register 211, and the output terminal of the fourth-stage shift register 211 is electrically connected to the gate line GL of the corresponding row sub-pixel. This process is repeated to achieve the sequential cascading of each stage of the shift register 211.

[0045] In some embodiments, the display module 1000 may further include a source drive circuit disposed at the bezel area NA of the display panel 20. The source drive circuit is electrically connected to the data line DL and configured to output a data voltage signal to the data line DL.

[0046] In some embodiments, the display module 1000 may further include a driving circuit board 10, which is electrically connected to the gate driving circuit 210 and the source driving circuit, respectively, to provide display control signals to the gate driving circuit 210, such as clock signals, frame start signals, and turn-off voltage signals, and to provide display data signals to the source driving circuit. The turn-off voltage signal refers to the voltage signal that maintains the switching device T in the off state; it can also be called a gate turn-off signal. It should be noted that the driving circuit board 10 may include one or more circuit boards, which can be configured according to the needs of the actual product.

[0047] In some embodiments, the display module 1000 may further include a flexible printed circuit board 11 (FPC), and the source driving circuit may include a source driving chip 12 (Source IC). Each source driving chip 12 is disposed on a flexible printed circuit board 11 and is bonded to the display panel 20 through the flexible printed circuit board 11, so that each source driving chip 12 is electrically connected to multiple data lines DL in the display panel 20. Through the flexible printed circuit board 11 bonded to the display panel 20 and the driving circuit board 10 respectively, the display control signal (also known as the GOA signal) output by the driving circuit board 10 is transmitted to the gate driving circuit 210 of the display panel 20, the display data signal output by the driving circuit board 10 is transmitted to the source driving chip 12, and the data voltage signal output by the source driving chip 12 is transmitted to the data lines DL in the display panel 20, thereby driving the display panel 20 to display an image.

[0048] It should be noted that the number of source driver chips 12 can be one or more (such as 4, 6, or 8), depending on the size and resolution requirements of the actual product. Figure 1 The example shown uses four examples and is not intended as a limitation.

[0049] It should be noted that, Figure 1 The gate drive circuit 210 and data drive chip shown in the diagram, along with the positional relationship of the gate line GL and data line DL within the display panel 20, are merely examples. The actual arrangement can be designed as needed. For instance, it can be as follows: Figure 1 The diagram shows that gate drive circuits 210 are set in the left and right bezel areas NA of the display panel 20, i.e., a dual-sided drive architecture is adopted. Alternatively, it can be... Figure 1 The left or right bezel area NA of the display panel 20 is provided with a gate drive circuit 210, that is, a single-sided drive architecture is adopted.

[0050] To improve issues like screen tearing and stuttering, FreeSync technology was developed to dynamically control the monitor's refresh rate. For example, the refresh rate adjustment range can be 48–75Hz, or 48–120Hz, depending on the specific product requirements. However, in actual use, it has been found that monitors equipped with FreeSync technology exhibit screen flickering during frequency switching. One reason for this is that at lower frequencies, the switching devices of each sub-pixel have relatively longer off-times, resulting in more leakage current and a darker image; while at higher frequencies, the switching devices of each sub-pixel have relatively shorter off-times, resulting in less leakage current and a brighter image. Therefore, screen flickering occurs during frequency switching.

[0051] Figure 3 A transfer characteristic curve of an exemplary thin-film transistor (TFT) is shown. Figure 3 In the graph, the horizontal axis Vgs represents the gate-source voltage (GS voltage) of the TFT, and the vertical axis Ids represents the leakage current. Figure 4 It can be seen that the leakage current Ids is the smallest when Vgs is about -8V. The greater the difference from -8V, the larger the leakage current Ids becomes.

[0052] In this paper, the turn-off voltage that makes the leakage current of the switching device of the sub-pixel at or close to the minimum value is called the reference turn-off voltage (that is, it can be considered as the optimal turn-off voltage).

[0053] In related technologies, the shutdown voltage is set by software and controls the digital power supply to generate a fixed voltage value. Typically, the shutdown voltage is configured to match the aforementioned reference shutdown voltage to minimize leakage current in the switching devices of the sub-pixels. In this case, the leakage current rate of the switching devices is the same whether the screen refresh rate is switched to a high frequency or a low frequency. However, because the shutdown time of the switching devices is shorter at high frequencies than at low frequencies, there is relatively less leakage current, resulting in a brighter image and causing screen flickering during frequency switching.

[0054] Based on this, this disclosure proposes a scheme to dynamically adjust the shutdown voltage according to the refresh rate of the display panel 20. By increasing the voltage difference between the shutdown voltage signal at high frequency and the reference shutdown voltage signal, the leakage current speed at high frequency is increased, and the brightness difference between the screen under high frequency conditions and low frequency conditions is reduced, thereby improving the screen flickering phenomenon when switching refresh rates.

[0055] This disclosure provides a driver circuit board for a display panel 20 in some embodiments. Figure 4 A schematic diagram of the structure of a driver circuit board according to some embodiments of this disclosure is shown, such as... Figure 4 As shown, the driving circuit board 10 includes a voltage conversion circuit 100 configured to acquire the refresh frequency of the display panel 20 and output a shutdown voltage signal to the display panel 20 according to the refresh frequency. The shutdown voltage signal is configured to control the switching devices of the sub-pixels in the display panel 20 to be in a shutdown state.

[0056] The difference between the voltage value of the turn-off voltage signal and the reference turn-off voltage increases with the increase of the refresh frequency. It should be noted that this increasing trend includes both gradual and stepwise increases.

[0057] In this way, when the refresh rate switches from low frequency to high frequency, the voltage conversion circuit 100 can adjust the shutdown voltage signal output to the display panel 20, so that the difference between the voltage value of the shutdown voltage signal and the reference shutdown voltage increases, thereby increasing the leakage current speed. When the refresh rate switches from high frequency to low frequency, the difference between the voltage value of the shutdown voltage signal and the reference shutdown voltage decreases, thereby reducing the leakage current speed. This reduces the brightness difference between the screen under high frequency conditions and low frequency conditions, and improves the screen flickering phenomenon when switching refresh rates.

[0058] Figure 5 A schematic diagram of the structure of a voltage conversion circuit 100 according to some embodiments of this disclosure is shown. For example... Figure 5 As shown, in some embodiments, the voltage conversion circuit 100 may include a microprocessor 110 (Microcontroller Unit, abbreviated as MCU) and a voltage adjustment sub-circuit 120, the voltage adjustment sub-circuit 120 being electrically connected to the microprocessor 110. The microprocessor 110 is configured to acquire a frame start signal, determine the refresh frequency of the display panel 20 based on the frame start signal, and output a voltage control signal to the voltage adjustment sub-circuit 120 according to the refresh frequency. The voltage adjustment sub-circuit 120 is configured to output a shutdown voltage signal to the display panel 20 under the control of the voltage control signal.

[0059] The refresh rate refers to the number of times the screen scans per second. For example, a refresh rate of 60Hz means 60 scans per second. The Frame Start Signal (STV) is the start signal for a single frame of an image. For example, the STV frequency can be the same as the refresh rate, transitioning to an active level (usually active high) once per scan cycle to initiate scanning of the current frame. Therefore, the current refresh rate of the display panel 20 can be determined by counting the number of pulses in the STV within one second.

[0060] In some embodiments, the driver circuit board 10 further includes a timing controller IC (TCON IC). In some embodiments, the microprocessor 110 can be a timing controller, which is equivalent to multiplexing the timing controller, so that in addition to performing its original timing control function, the timing control chip can also obtain the refresh frequency based on the generated frame start signal, and output the voltage control signal to the voltage adjustment sub-circuit 120 according to the refresh frequency. Of course, in other embodiments, the microprocessor 110 can also be set independently of the timing controller, and this disclosure does not limit this.

[0061] In some embodiments, N different frequency levels can be pre-configured in the microprocessor 110. Higher frequency levels correspond to higher refresh rates, and different frequency levels correspond to different voltage control signals. N is an integer greater than or equal to 2. For example, when N = 2, two frequency levels are configured, which can be a high-frequency level and a low-frequency level; when N = 3, three frequency levels are configured, which can be a high-frequency level, a mid-frequency level, and a low-frequency level. Of course, more frequency levels can be further subdivided, and the number of frequency levels can be set according to the refresh rate adjustment needs of the actual product.

[0062] For example, the microprocessor 110 can be configured to determine a target frequency level from the N different frequency levels that matches the refresh rate of the display panel 20, and output a voltage control signal corresponding to the target frequency level. The higher the level of the target frequency level, the greater the difference between the voltage value of the shutdown voltage signal output by the voltage adjustment sub-circuit 120 and the reference shutdown voltage, and the faster the leakage current speed.

[0063] In some embodiments, the voltage value of the shutdown voltage signal corresponding to the lowest frequency level can be equal to the reference shutdown voltage. It should be noted that "equal to" here includes both exact and approximate equality; approximate equality means that the deviation between the two is within an acceptable error range. This helps reduce leakage current at low frequencies, thus improving the aforementioned screen flickering phenomenon while minimizing leakage.

[0064] In some embodiments, each frequency level can correspond to a refresh frequency, and the refresh frequency corresponding to the (i+1)th frequency level is greater than the refresh frequency corresponding to the ith frequency level, where i is an integer from 1 to N-1.

[0065] For example, consider two frequency levels: a high-frequency level and a low-frequency level. The low-frequency level corresponds to a refresh rate of 60Hz, and the high-frequency level corresponds to a refresh rate of 120Hz. When the microprocessor 110 detects a refresh rate of 60Hz, it outputs a first voltage control signal to the voltage adjustment sub-circuit 120 to control the voltage adjustment sub-circuit 120 to output a first shutdown voltage signal. When it detects a refresh rate switch from 60Hz to 120Hz (i.e., a switch from low frequency to high frequency), it outputs a second voltage control signal to the voltage adjustment sub-circuit 120 to control the voltage adjustment sub-circuit 120 to output a second shutdown voltage signal, thus achieving two different shutdown voltage signals for high and low frequencies. The difference between the voltage value of the second shutdown voltage signal and the reference shutdown voltage is greater than the difference between the voltage value of the first shutdown voltage signal and the reference shutdown voltage. For example, the voltage value of the first shutdown voltage signal can be equal to the reference shutdown voltage.

[0066] In other embodiments, each frequency level can correspond to a refresh frequency range, where the minimum value of the refresh frequency range corresponding to the (i+1)th frequency level is greater than the maximum value of the refresh frequency range corresponding to the ith frequency level, and i is an integer from 1 to N-1. In this case, the microprocessor 110 can match the current refresh frequency of the display panel 20 with each refresh frequency range to determine the target frequency level. Therefore, when the target frequency level of the refresh frequency changes, the microprocessor adjusts the voltage control signal output to the voltage adjustment sub-circuit 120, thereby adjusting the shutdown voltage signal output by the voltage adjustment sub-circuit 120.

[0067] For example, the adjustable refresh rate range of the display panel 20 is 48 to 120 Hz. Taking the two-level frequency settings as an example, the refresh rate range corresponding to the low-frequency setting can be greater than or equal to 48 Hz and less than or equal to 60 Hz, while the refresh rate range corresponding to the high-frequency setting can be greater than 60 Hz and less than or equal to 120 Hz. When the microprocessor 110 detects a refresh rate greater than or equal to 48 Hz and less than or equal to 60 Hz, it outputs a first voltage control signal to the voltage adjustment sub-circuit 120 to control the voltage adjustment sub-circuit 120 to output a first shutdown voltage signal. When it detects a switch from the low-frequency setting to the high-frequency setting, i.e., a refresh rate greater than 60 Hz and less than or equal to 120 Hz, it outputs a second voltage control signal to the voltage adjustment sub-circuit 120 to control the voltage adjustment sub-circuit 120 to output a second shutdown voltage signal, thereby achieving the use of two different shutdown voltage signals for high and low frequencies.

[0068] like Figure 5 As shown, the voltage regulation sub-circuit 120 includes a voltage input terminal VIN, a control terminal CTR, and a voltage output terminal VOUT. The control terminal CTR receives the voltage control signal mentioned above, and the voltage output terminal VOUT outputs a turn-off voltage signal.

[0069] Figure 6 A circuit diagram of a voltage regulation sub-circuit 120 according to some embodiments of this disclosure is shown. For example... Figure 6As shown, the voltage regulation sub-circuit 120 may include a buck-boost converter chip 201, a first resistor R1, a second resistor R2, and at least one resistance regulation branch 202. The buck-boost converter chip 201 may include an input power terminal Vin, a switching terminal SW, a shutdown terminal SHDN, a feedback terminal NFB, and a ground terminal GND. The first end of the first resistor R1 and the first end of the second resistor R2 are electrically connected to the feedback terminal NFB of the buck-boost converter chip 201. The second end of the first resistor R1 is electrically connected to the voltage output terminal VOUT, and the second end of the second resistor R2 is grounded. The resistance regulation branch 202 is connected in parallel with the second resistor R2. The control terminal of the resistance regulation branch 202 serves as the control terminal CTR of the voltage regulation sub-circuit 120 and is electrically connected to the microprocessor 110. It is configured to adjust the resistance value of the feedback resistor connected to the feedback terminal of the buck-boost converter chip 201 under the control of a voltage control signal, thereby adjusting the shutdown voltage signal output by the voltage output terminal VOUT.

[0070] It should be noted that the aforementioned at least one resistor adjustment branch 202 can be one resistor adjustment branch 202 or more resistor adjustment branches 202, depending on the number of frequency levels mentioned above. If the second resistor R2 is connected in parallel with n resistor adjustment branches 202, then a maximum of 2 n The shutdown voltage signal is grouped, where n is an integer greater than or equal to 1. This allows for the subdivision of the refresh rate and shutdown voltage signal as needed, which is beneficial for improving the display effect.

[0071] Figure 6 Taking a resistor adjustment branch 202 as an example, under the control of the voltage control signal, the resistance value of the feedback resistor is two, so that two different turn-off voltage signals can be output from the voltage output terminal VOUT.

[0072] like Figure 6 As shown, the resistance adjustment branch 202 includes a third resistor R3 and a first switching device Q1 connected in series. The first end of the third resistor R3 is electrically connected to the first connection terminal of the first switching device Q1, and the second end of the third resistor R3 is grounded. The second connection terminal of the first switching device Q1 is electrically connected to the feedback terminal NFB, and the control terminal of the first switching device Q1 (i.e., the control terminal of the aforementioned resistance adjustment branch 202) is electrically connected to the microprocessor 110 to receive a voltage control signal and control the on / off state between the first and second connection terminals according to the voltage control signal. In this case, the voltage control signal is configured to control the switching state of the first switching device Q1, that is, to control the conduction and shutdown of the first switching device Q1 through the high and low levels of the voltage control signal. For example, the first switching device Q1 can be a transistor, such as a P-type transistor, or an N-type transistor; this disclosure does not limit this.

[0073] It should be noted that when multiple resistance adjustment branches 202 are connected in parallel with the second resistor R2, the voltage control signal includes multiple sub-control signals. The control terminal of the first switching device Q1 in each resistance adjustment branch 202 is electrically connected to an output port (such as a general-purpose input / output port, abbreviated as GPIO) of the microprocessor 110, and receives a sub-control signal, thereby realizing independent control of the first switching device Q1 in each resistance adjustment branch 202.

[0074] like Figure 6 As shown, the voltage regulation sub-circuit 120 may further include a first inductor L1, a second inductor L2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a first diode D1. The input power terminal Vin and the stop terminal SHDN of the buck-boost converter chip 201, the first terminal of the first capacitor C1, and the first terminal of the first inductor L1 are electrically connected to the voltage input terminal VIN of the voltage regulation sub-circuit 120. The second terminal of the first capacitor C1 and the ground terminal GND of the buck-boost converter chip 201 are grounded, for example, they can be electrically connected to the ground terminal of the driver circuit board 10. The second terminal of the first inductor L1 and the first terminal of the second capacitor C2 can be electrically connected to the switching terminal SW of the buck-boost converter chip 201. The second terminal of the second capacitor C2 is electrically connected to the anode of the first diode D1 and the first terminal of the second inductor L2, respectively, and the cathode of the first diode D1 is grounded. The second terminal of the second inductor L2 is electrically connected to the voltage output terminal VOUT. The third capacitor C3 is connected in parallel with the first resistor R1. That is, the first terminal of the third capacitor C3 is electrically connected to the feedback terminal NFB, and the second terminal is electrically connected to the voltage output terminal VOUT. The first terminal of the fourth capacitor is electrically connected to the voltage output terminal VOUT, and the second terminal is grounded.

[0075] Taking a two-level frequency range, namely low frequency and high frequency, as an example, the second resistor R2 is connected in parallel as follows: Figure 6 The diagram shows a resistor adjustment branch 202. For example, when the refresh rate of the display panel 20 is at a low frequency, the first switching device Q1 is in the off state, and the feedback resistor connected to the feedback terminal of the buck-boost converter chip 201 is the second resistor R2. At this time, the voltage value VSS1 of the first turn-off voltage signal output by the voltage output terminal VOUT of the voltage adjustment sub-circuit 120 can be determined according to the following formula (1).

[0076]

[0077] In equation (1), V NFB This indicates the voltage value at the feedback terminal NFB of the buck-boost converter chip 201. The actual value is determined based on the specific buck-boost converter chip model used. For example, V... NFBIt can be -1.23V; R1 represents the resistance value of the first resistor R1, and R2 represents the resistance value of the second resistor R2.

[0078] When the refresh rate of the display panel 20 is at the high frequency level, the first switching device Q1 is in the conducting state, and the feedback resistor connected to the feedback terminal of the buck-boost converter chip 201 is the parallel resistance of the second resistor R2 and the third resistor R3. At this time, the voltage value VSS2 of the second turn-off voltage signal output by the voltage output terminal VOUT of the voltage adjustment sub-circuit 120 can be determined according to the following formula (2).

[0079]

[0080] In equation (2), R1 represents the resistance value of the first resistor R1, and R2 / / R3 represents the parallel resistance value of the second resistor R2 and the third resistor R3.

[0081] For example, with a reference shutdown voltage of -8V, V NFB With a voltage of -1.23V, VSS1 can be set to -8V and VSS2 to -9V by selecting the values ​​of the first resistor R1, the second resistor R2, and the third resistor R3. For example, the first resistor R1 can be 55 kΩ, the second resistor R2 can be 10 kΩ, and the third resistor R3 can be 70 kΩ.

[0082] Figure 7 A schematic diagram of the structure of a voltage conversion circuit 100 according to other embodiments of this disclosure is shown. For example... Figure 7 As shown, in some embodiments, the voltage control signal is a pulse width modulation (PWM) signal, and the voltage adjustment sub-circuit 120 may include a buck-boost topology 301. The buck-boost topology 301 includes a second switching device Q2. The control terminal of the second switching device Q2 serves as the control terminal CTR of the voltage adjustment sub-circuit 120 and is electrically connected to the microprocessor 110 to receive the voltage control signal, i.e., the PWM signal. The buck-boost topology 301 is configured to output a shutdown voltage signal based on the input voltage and the duty cycle of the received voltage control signal. Different frequency levels correspond to different duty cycles of the voltage control signal, resulting in different voltage values ​​for the output shutdown voltage signal.

[0083] In some embodiments, the second switching device Q2 can be a transistor, for example, a power transistor or a power MOSFET, and this disclosure does not limit it.

[0084] Figure 8 Circuit diagrams of buck-boost topologies according to some embodiments of the present disclosure are shown. Figure 8In the buck-boost topology 301 shown, the second switching device Q2 is a P-type transistor. For example... Figure 7 As shown, the buck-boost topology circuit 301 may include a second switching device Q2, a fourth resistor R4, a second diode D2, a third inductor L3, a fifth capacitor C5, and a sixth capacitor C6. The first terminal of the second switching device Q2 and the first terminal of the fifth capacitor C5 are electrically connected to the voltage input terminal VIN of the voltage regulation sub-circuit 120. The second terminal of the second switching device Q2 and the first terminal of the third inductor L3 are electrically connected to the cathode of the second diode D2. The control terminal of the second switching device Q2 is electrically connected to the microprocessor 110, and controls the switching between the first and second terminals via a voltage control signal. The anode of the second diode D2, the first terminal of the sixth capacitor C6, and the first terminal of the fourth resistor are electrically connected to the voltage output terminal VOUT of the voltage regulation sub-circuit 120. The second terminals of the fifth capacitor C5, the third inductor L3, the sixth capacitor C6, and the fourth resistor R4 are grounded. Of course, in other embodiments, the buck-boost topology circuit 301 may also employ other suitable circuits, and this disclosure does not limit this.

[0085] For example, when the second switching device Q2 is a P-type transistor, the second switching device Q2 is turned on when the voltage control signal is low and turned off when the voltage control signal is high. If the duty cycle of the voltage control signal is represented as H and the duty cycle of the buck-boost topology circuit 301 is represented as D, then D = 1 - H.

[0086] The voltage value VSS of the turn-off voltage signal output by the voltage output terminal VOUT of the voltage regulation sub-circuit 120 can be determined by the following formula (3), where Vin represents the voltage input by the voltage input terminal VIN.

[0087]

[0088] Taking the two-level frequency settings, namely low frequency and high frequency, as an example, when the microprocessor 110 detects that the refresh rate of the display panel 20 is at the low frequency setting, it outputs a first voltage control signal to the voltage adjustment sub-circuit 120, controlling the voltage output terminal VOUT of the voltage adjustment sub-circuit 120 to output a first shutdown voltage signal VSS1. When the refresh rate of the display panel 20 is at the high frequency setting, it outputs a second voltage control signal to the voltage adjustment sub-circuit 120, controlling the voltage output terminal VOUT of the voltage adjustment sub-circuit 120 to output a second shutdown voltage signal VSS2.

[0089] For example, with a reference turn-off voltage of -8V and Vin of 12V, the duty cycle H of the first voltage control signal can be... Accordingly, the duty cycle D of the buck-boost topology circuit 301 is This controls the first shutdown voltage signal VSS1 output from the voltage output terminal VOUT of the voltage regulation sub-circuit 120 to be -8V; the duty cycle H of the second voltage control signal can be... Accordingly, the duty cycle D of the buck-boost topology circuit 301 is This controls the second shutdown voltage signal VSS2 output from the voltage output terminal VOUT of the voltage regulator circuit 120 to be -9V.

[0090] Considering the limited driving capability of some microprocessors 110, in order to more reliably drive the second switching device Q2 in the buck-boost topology circuit 301, such as Figure 7 As shown, the voltage regulation sub-circuit 120 may further include a level converter 302. The input terminal of the level converter 302 is electrically connected to the microprocessor 110, and the output terminal is electrically connected to the control terminal of the second switching device Q2. The level converter 302 is configured to perform level conversion on the voltage control signal output by the microprocessor 110, and output the level-converted voltage control signal to the control terminal of the second switching device Q2. The high-level voltage of the converted voltage control signal is greater than the high-level voltage of the voltage control signal output by the microprocessor 110.

[0091] For example, the voltage control signal output by the microprocessor 110 is a PWM signal of 0V and 3.3V, that is, the high level voltage is 3.3V and the low level voltage is 0V. This PWM signal can be input to the level converter 302 to be converted into a PWM signal of 0V and 12V, so as to improve the driving capability of the voltage control signal and ensure the normal driving of the second switching device Q2 in the buck-boost topology circuit 301.

[0092] Figure 9 Circuit diagrams of level converters according to some embodiments of this disclosure are shown. For example... Figure 9As shown, the level converter 302 may include a gate driver chip 320 and a seventh capacitor C7. The input terminal IN of the gate driver chip 320 is electrically connected to the microprocessor 110 to receive the voltage control signal. The output terminal OUT of the gate driver chip 320 is electrically connected to the control terminal of the second switching device Q2 in the buck-boost topology circuit 301. For ease of distinction, the voltage control signal input to the input terminal IN of the gate driver chip 320 is represented as TR1, and the level-converted voltage control signal output from the output terminal OUT of the gate driver chip 320 is represented as TR2. The power supply terminal VDD and the unused terminal NC of the gate driver chip 320 are electrically connected to the power supply voltage terminal Vdd. The first terminal of the seventh capacitor C7 is electrically connected to the power supply terminal VDD of the gate driver chip 320, and the second terminal of the seventh capacitor C7 and the ground terminal GND of the gate driver chip 320 are grounded. For example, when it is necessary to convert the voltage control signal into 0V and 12V PWM signals, the voltage of the power supply voltage terminal Vdd can be 12V. Of course, in other embodiments, other suitable level converters 302 may be used, and this disclosure does not limit them.

[0093] Figure 10 A schematic diagram of the structure of a voltage conversion circuit according to some embodiments of the present disclosure is shown. Figure 7 Based on the corresponding embodiment, considering that load changes can easily lead to instability in the turn-off voltage signal output from the voltage output terminal of the voltage regulation sub-circuit 120, such as... Figure 10 As shown, in some embodiments, the voltage conversion circuit 100 may further include a sampling sub-circuit 130. The input terminal of the sampling sub-circuit 130 is electrically connected to the voltage output terminal of the voltage adjustment sub-circuit 120, i.e., the voltage output terminal of the aforementioned buck-boost topology circuit 301. The output terminal of the sampling sub-circuit 130 is electrically connected to the microprocessor 110. The sampling sub-circuit 130 is configured to sample the turn-off voltage signal output from the voltage output terminal of the voltage adjustment sub-circuit 120 and feed the sampled voltage back to the microprocessor 110, so that the microprocessor 110 adjusts the duty cycle of the voltage control signal according to the sampled voltage to improve the stability of the output turn-off voltage signal. It should be noted that the circuit structure of the sampling sub-circuit 130 can be found in related technologies and will not be detailed here.

[0094] Figure 11 A schematic diagram of the structure of the driver circuit board 10 according to other embodiments of this disclosure is shown. For example... Figure 11 As shown, the drive circuit board 10 may also include a power interface 410. For example, the voltage input terminal VIN of the voltage regulation sub-circuit 120 described above may be electrically connected to the power interface 410. For example, the power interface 410 may input a 12V DC voltage to the voltage input terminal VIN.

[0095] like Figure 11As shown, the driver circuit board 10 may also include a power management IC (PMIC). For example, the power management IC 420 may be electrically connected to the power interface 410 via a buck converter to power some of the power-consuming circuits in the driver circuit board 10 (such as the microprocessor 110 mentioned above).

[0096] It should be noted that, in addition to the circuits described above, the drive circuit board 10 may also include other circuit structures and / or electronic devices, depending on the needs of the actual product.

[0097] In other embodiments, the voltage conversion circuit 100 described above may include a power manager, which includes a signal acquisition terminal and a shutdown voltage output terminal. The signal acquisition terminal of the power manager is electrically connected to a frame start signal line to acquire the frame start signal. For example, the power manager may include a memory and a processor. The memory stores a computer program that can run on the processor. The computer program is executed by the processor in the following steps: determining the refresh rate of the display panel 20 based on the acquired frame start signal, and controlling the shutdown voltage output terminal to output a shutdown voltage signal to the display panel 20 based on the refresh rate. The difference between the voltage value of the shutdown voltage signal and the reference shutdown voltage tends to increase as the refresh rate increases.

[0098] For example, the power manager can pre-set N different frequency levels corresponding to the shutdown voltage values, where N is an integer greater than or equal to 2. After obtaining the refresh rate of the display panel 20, the refresh rate is matched with the preset N frequency levels to determine the target frequency level. Based on the shutdown voltage value corresponding to the target frequency level, the shutdown voltage output terminal is controlled to output the corresponding shutdown voltage signal. It should be noted that the setting of the N different frequency levels can refer to the relevant description in the above embodiment, and will not be repeated here. The higher the frequency level, the greater the difference between the shutdown voltage value corresponding to the reference shutdown voltage.

[0099] This disclosure provides a method for voltage output of a display panel, based on several embodiments. Figure 12 A flowchart of a voltage output method according to some embodiments of this disclosure is shown. For example... Figure 12 As shown, the method may include the following steps S110 and S120.

[0100] Step S110: Obtain the refresh rate of the display panel.

[0101] Step S120: According to the refresh rate of the display panel, output a shutdown voltage signal to the display panel. The shutdown voltage signal is configured to control the switching devices of the sub-pixels in the display panel to be in the shutdown state. The difference between the voltage value of the shutdown voltage signal and the reference shutdown voltage increases with the increase of the refresh rate.

[0102] For example, the voltage output method described above can be executed by the power manager on the driver circuit board. The implementation process and technical effects of steps S110 and S120 can be referred to the relevant descriptions in the above embodiments, and will not be repeated here.

[0103] This disclosure provides a display device in several embodiments, including a display panel and a driving circuit board as described in any of the embodiments above. The display panel includes a display area and a bezel area located on at least one side of the display area. The display area is provided with a plurality of pixel units arranged in an array, each pixel unit including a plurality of sub-pixels. The bezel area is provided with a gate driving circuit. The gate driving circuit includes a plurality of cascaded shift registers, the signal output terminals of which are electrically connected to the control terminals of switching devices of at least one row of sub-pixels. The output terminal of a voltage conversion circuit on the driving circuit board is electrically connected to the off-voltage terminal of the shift registers.

[0104] For example, the display panel can be a liquid crystal display panel. For example, the display device can be any product or component with a display function, such as a monitor, television, mobile phone, tablet computer, laptop computer, digital photo frame, or navigator. Of course, the display devices provided in the embodiments of this disclosure are not limited to the types listed above.

[0105] Furthermore, those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0106] Although exemplary embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make further changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

Claims

1. A driving circuit board for a display panel, characterized in that, include: A voltage conversion circuit is configured to obtain the refresh frequency of the display panel and output a shutdown voltage signal to the display panel according to the refresh frequency. The shutdown voltage signal is configured to control the switching devices of the sub-pixels in the display panel to be in a shutdown state. The difference between the voltage value of the shutdown voltage signal and the reference shutdown voltage increases with the increase of the refresh frequency.

2. The driving circuit board according to claim 1, characterized in that, The voltage conversion circuit includes a microprocessor and a voltage regulation sub-circuit, wherein the voltage regulation sub-circuit is electrically connected to the microprocessor; The microprocessor is configured to acquire a frame start signal, determine the refresh frequency of the display panel based on the frame start signal, and output a voltage control signal to the voltage adjustment sub-circuit based on the refresh frequency. The voltage adjustment sub-circuit is configured to output a shutdown voltage signal to the display panel under the control of the voltage control signal.

3. The driving circuit board according to claim 2, characterized in that, The microprocessor is configured to determine a target frequency level that matches the refresh frequency from N preset frequency levels, and output a voltage control signal corresponding to the target frequency level, where N is an integer greater than or equal to 2, and the voltage control signal corresponding to different frequency levels is different. Among them, the higher the frequency level, the higher the refresh rate. The higher the level of the target frequency level, the greater the difference between the voltage value of the shutdown voltage signal output by the voltage adjustment sub-circuit and the reference shutdown voltage.

4. The driving circuit board according to claim 3, characterized in that, Each frequency level corresponds to a refresh rate, and the refresh rate of the (i+1)th frequency level is greater than the refresh rate of the ith frequency level, where i is an integer from 1 to N-1; or, Each frequency level corresponds to a refresh frequency range. The minimum value of the refresh frequency range corresponding to the (i+1)th frequency level is greater than the maximum value of the refresh frequency range corresponding to the i-th frequency level, where i is an integer from 1 to N-1.

5. The drive circuit board according to any one of claims 2-4, characterized in that, The voltage adjustment sub-circuit includes a buck-boost converter chip, a first resistor, a second resistor, and at least one resistor adjustment branch. The first end of the first resistor and the first end of the second resistor are electrically connected to the feedback terminal of the buck-boost converter chip. The second end of the first resistor is electrically connected to the voltage output terminal of the voltage adjustment sub-circuit. The second end of the second resistor is grounded. The resistance adjustment branch is connected in parallel with the second resistor. The control terminal of the resistance adjustment branch is electrically connected to the microprocessor and is configured to adjust the resistance value of the feedback resistor connected to the feedback terminal of the buck-boost converter chip under the control of the voltage control signal, so as to adjust the turn-off voltage signal output by the voltage output terminal.

6. The driving circuit board according to claim 5, characterized in that, The resistance adjustment branch includes a third resistor and a first switching device connected in series. The control terminal of the first switching device is electrically connected to the microprocessor to receive the voltage control signal, which is configured to control the switching state of the first switching device.

7. The driving circuit board according to claim 3 or 4, characterized in that, The voltage adjustment sub-circuit includes a buck-boost topology circuit. The control terminal of the second switching device in the buck-boost topology circuit is electrically connected to the microprocessor to receive the voltage control signal. The voltage control signal is a pulse width modulation signal, and the duty cycle of the voltage control signal is different for different frequency levels. The buck-boost topology is configured to output the turn-off voltage signal based on the input voltage and the duty cycle of the received voltage control signal.

8. The driving circuit board according to claim 7, characterized in that, The voltage regulation sub-circuit further includes a level converter. The input terminal of the level converter is electrically connected to the microprocessor, and the output terminal is electrically connected to the control terminal of the second switching device. The level converter is configured to perform level conversion on the voltage control signal output by the microprocessor and output the level-converted voltage control signal to the control terminal of the second switching device. The high-level voltage of the level-converted voltage control signal is greater than the high-level voltage of the voltage control signal output by the microprocessor.

9. The driving circuit board according to claim 7, characterized in that, The voltage conversion circuit further includes a sampling sub-circuit. The input terminal of the sampling sub-circuit is electrically connected to the voltage output terminal of the voltage adjustment sub-circuit, and the output terminal is electrically connected to the microprocessor. The sampling sub-circuit is configured to sample the off-voltage signal output by the voltage output terminal and feed the sampled voltage back to the microprocessor, so that the microprocessor adjusts the duty cycle of the voltage control signal according to the sampled voltage.

10. The driving circuit board according to claim 2, characterized in that, The microprocessor is a timing controller.

11. A display device, characterized in that, Includes a display panel and a driving circuit board as described in any one of claims 1-10; The display panel includes a display area and a border area located on at least one side of the display area. The display area is provided with a plurality of pixel units arranged in an array. The pixel unit includes a plurality of sub-pixels. The border area is provided with a gate driving circuit. The gate driving circuit includes a plurality of cascaded shift registers. The signal output terminal of the shift register is electrically connected to the control terminal of the switching device of at least one row of sub-pixels. The output terminal of the voltage conversion circuit on the driver circuit board is electrically connected to the turn-off voltage terminal of the shift register.

12. A voltage output method for a display panel, characterized in that, include: Obtain the refresh rate of the display panel; According to the refresh rate of the display panel, a shutdown voltage signal is output to the display panel, and the shutdown voltage signal is configured to control the switching devices of the sub-pixels in the display panel to be in a shutdown state; The difference between the voltage value of the shutdown voltage signal and the reference shutdown voltage increases with the increase of the refresh frequency.

Images