Dimming data storage structure and storage method, chip and display device

Abstract

The embodiment of the application discloses a dimming data storage structure and a storage method, a chip and a display device, and relates to the technical field of display dimming. In view of the problems that SRAM storage dimming data has area redundancy in a small data amount scene, low serial reading efficiency, and large circuit scale and high design complexity caused by post-data separation logic, the application adopts a storage array composed of D-type flip-flops to store dimming data, performs a decoding operation on the input target address through an address decoding unit, and enables the storage array to output the dimming data of the whole row and multiple channels in parallel; further, a front serial separation unit is arranged at the write-in end of the storage array, and the splitting and classified storage of direct current data, pulse width modulation data and jitter data are completed in the data serial write-in process. The scheme provided by the embodiment of the application does not need pre-reading and additional caching, significantly improves the dimming data reading efficiency, greatly reduces the chip layout area, and reduces the design and layout difficulty of the digital logic circuit.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a dimming data storage structure and storage method, chip and display device. Background Technology

[0002] Display dimming refers to the process of controlling backlight brightness, and dimming data is a set of key parameters describing this process, including duty cycle, frequency, and brightness range. These data directly affect display quality, visual comfort, and energy consumption. In the field of display dimming control, the efficiency of dimming data storage and processing, as well as chip layout area control, are the core technical challenges.

[0003] In existing technologies, dimming data storage solutions suffer from problems such as unreasonable selection of storage media, resulting in area redundancy and low read efficiency.

[0004] Therefore, there is a need for a new dimming data storage structure and method, chip and display device that can overcome at least one of the above problems. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide a dimming data storage structure and storage method, chip and display device, and in particular a dimming data internal storage structure and processing scheme, which aims to improve the reading efficiency of dimming data.

[0006] According to a first aspect of the embodiments of this application, a dimming data storage structure is provided, comprising:

[0007] A storage array for storing dimming data; the storage array includes multiple storage units; each storage unit includes a trigger storage unit;

[0008] The address decoding unit is electrically connected to the storage array; the address decoding unit is configured to perform a decoding operation on the input target address to obtain all the storage cells of the corresponding row, so that the storage array can output the dimming data of the entire row in parallel.

[0009] Optionally, the trigger storage unit is a D-type trigger; each D-type trigger stores 1 bit of binary dimming data; the storage unit storing single-channel multi-bit dimming data includes multiple D-type triggers.

[0010] Optionally, the dimming data includes at least two types selected from DC data, pulse width modulation data, and jitter data, with different types of dimming data stored in independent storage partitions of the storage array.

[0011] Optionally, the dimming data storage structure further includes:

[0012] A pre-separation unit is disposed at the write end of the storage array and is used to separate different types of dimming data before the dimming data is stored in the storage array.

[0013] Optionally, the pre-separation unit includes a serial separation logic circuit; the serial separation logic circuit is adapted to the serial writing method of the dimming data, and splits DC data, pulse width modulation data and jitter data in real time during the serial transmission of data.

[0014] Optionally, the storage array is divided into at least two dynamically definable storage partitions, and the data type stored in each storage partition is dynamically configured by the current display mode;

[0015] The display mode includes at least one selected from DC and dithering, pulse width modulation and dithering, and DC and pulse width modulation.

[0016] Optionally, the storage array includes a ping-pong storage architecture;

[0017] The ping-pong storage architecture includes a first storage buffer unit and a second storage buffer unit; the first storage buffer unit and the second storage buffer unit alternately perform the write operation and read operation of the dimming data.

[0018] Optionally, the storage capacity of the storage array meets the requirement that it be twice the product of the number of scans, the number of channels, and the bit width of the brightness data.

[0019] Optionally, the address decoding unit performs a decoding operation on the input target address to index all storage units of the corresponding row.

[0020] According to a second aspect of this application, a dimming data storage method is provided, comprising:

[0021] Receives serially input mixed dimming data;

[0022] Before the hybrid dimming data is written to the storage array, the hybrid dimming data is split into at least two types of DC data, pulse width modulation data and jitter data by a serial separation logic circuit.

[0023] The split dimming data of different types are serially written into the corresponding storage units of the storage array, wherein the storage unit includes a trigger storage unit;

[0024] The target address is input to the address decoding unit. After one decoding, the storage array outputs a full row of multi-channel dimming data in parallel.

[0025] According to a third aspect of this application, a chip is provided, comprising:

[0026] The dimming data storage structure described above.

[0027] According to a fourth aspect of this application, a display device is provided, comprising:

[0028] The dimming data storage structure described above; and

[0029] The display panel has a backlight that is electrically connected to the dimming data storage structure for receiving and executing the dimming data.

[0030] According to the dimming data storage structure and method, chip and display device of the present application embodiments, the dimming data in the corresponding storage unit is output according to the input target address, eliminating the need for operations such as reading one line in advance, shortening the data reading time and improving the reading efficiency of dimming data.

[0031] Furthermore, for a single line of dimming data containing multiple channels, only one address indexing operation is needed to directly output the entire line of data, resulting in high data reading efficiency.

[0032] Furthermore, there is no need to set up additional temporary storage space for the next row of data and independent storage space for the current display row, which improves data reading efficiency while adapting to the needs of backlight parallel output.

[0033] Furthermore, a dimming data storage array is built using triggers. By leveraging the area advantage of triggers in small data storage scenarios, the physical area required for dimming data storage is reduced, thus saving chip area.

[0034] Furthermore, by placing the mixed separation processing logic of DC data / pulse width modulation data / jitter data before storing the dimming data into the storage array, the storage process of dimming data is optimized and the storage efficiency of dimming data is improved.

[0035] Furthermore, for serially written dimming data, only one set of serial separation logic circuit is needed to complete the splitting of DC data / pulse width modulation data / jitter data before the data is serially written to the storage array, and store the split data into the corresponding storage units respectively, realizing the classified storage of data. There is no need to add additional parallel separation logic circuit, no additional area overhead, effectively improving the chip integration and simplifying the complexity of circuit design. Attached Figure Description

[0036] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0037] Figure 1 A schematic diagram of a dimming data storage structure according to an embodiment of this application is shown;

[0038] Figure 2 A flowchart of a dimming data storage method according to an embodiment of this application is shown;

[0039] Figure 3 A schematic diagram illustrating the workflow of the overall architecture of DFF storage combined with front-end separation according to an embodiment of this application is shown.

[0040] Figure 4 A circuit structure block diagram of a DFF dimming data storage array according to an embodiment of this application is shown;

[0041] Figure 5 A schematic diagram of the DFF array readout timing according to an embodiment of this application is shown;

[0042] Figure 6 A schematic diagram illustrating the workflow of a hybrid data separation logic architecture according to an embodiment of this application is shown.

[0043] Figure 7 A schematic diagram of the structure of a display device according to an embodiment of this application is shown. Detailed Implementation

[0044] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. The present application may be presented in various forms; only some examples are described below.

[0045] The inventors discovered that traditional dimming data storage solutions have two major technical flaws, as follows:

[0046] 1) Inappropriate selection of storage media leads to redundant area and low read efficiency:

[0047] The storage capacity of dimming data needs to meet the requirement of "number of scans × number of channels × brightness data bit width (16 bits) × 2". In application scenarios with a small number of backlight scans, if SRAM (Static Random-Access Memory) is used as the storage medium, on the one hand, the layout area of ​​SRAM itself is relatively large, which makes it poorly adaptable to scenarios with small data storage; on the other hand, SRAM adopts a serial reading method, while backlight displays need to output multi-channel brightness data in parallel (such as dimming data of 16 channels in a row). In this case, SRAM needs to perform 16 read operations one by one to obtain a complete row of data, which cannot directly match the requirements of parallel output of backlight.

[0048] To address the SRAM incompatibility issue, existing technologies require additional "read one row ahead" control logic, along with additional temporary storage space for the next row of data and independent storage space for the current display row. This not only increases the time overhead of data reading but also adds the design of serial reading logic circuits, further leading to chip area redundancy and reduced reading efficiency.

[0049] 2) The mixed data separation logic design is unreasonable, increasing the logic circuit area:

[0050] The dimming data input to the bus is a mixture of DC (Direct Current) and PWM (Pulse Width Modulation) data. Since the display device has multiple display modes, the dimming process requires the coordinated action of DC and PWM data to achieve the target brightness adjustment. Therefore, the mixed data input to the bus needs to be processed separately according to different display modes to meet the channel output requirements.

[0051] In existing technologies, the logic for separating mixed data is set after indexing data from the storage unit. Since the data output by the index is parallel data, multiple sets of separation logic circuits need to be designed for the parallel data to complete the separation of DC data and PWM data, which greatly increases the layout area of ​​the logic circuit and reduces the chip integration density.

[0052] To address the aforementioned problems, the inventors proposed a new dimming data storage structure. Figure 1 A schematic diagram of a dimming data storage structure according to an embodiment of this application is shown. Figure 1 As shown, the dimming data storage structure according to an embodiment of this application includes a storage array 100 and an address decoding unit 200. The storage array 100 includes a plurality of storage cells 110.

[0053] Specifically, the storage array 100 is used to store dimming data. The storage array 100 includes multiple storage cells 110. Optionally, the type, format, etc., of the dimming data can be the same as or modified accordingly from existing technologies. Optionally, the storage cell 110 includes a flip-flop storage cell. Different flip-flop storage cells are used to store different dimming data. The flip-flop storage cell includes, for example, a D-type flip-flop (DFF) or other types of flip-flops. A D-type flip-flop is an edge-sensitive storage cell whose main function is to "latch" the data at the input terminal D to the output terminal Q when the edge of the clock signal arrives, and maintain this state until the next clock edge. Optionally, each D-type flip-flop can store 1 bit of binary dimming data (0 or 1), and multiple flip-flops combined can store multiple bits of data. Optionally, a storage cell 110 includes multiple D-type flip-flops. A storage cell storing single-channel multi-bit dimming data includes multiple D-type flip-flops.

[0054] Address decoding unit 200 is electrically connected to dimming data storage array 100. Address decoding unit 200 is configured to perform a decoding operation on the input target address to obtain all storage cells of the corresponding row, enabling storage array 100 to output dimming data of the entire row in parallel across multiple channels. Optionally, address decoding unit 200 performs a decoding operation on the input target address to index and obtain all storage cells of the corresponding row.

[0055] Optionally, the storage array includes a ping-pong storage architecture. The ping-pong storage architecture includes a first storage buffer unit and a second storage buffer unit. The first and second storage buffer units alternately perform write and read operations on dimming data. This alternating execution of the first and second storage buffer units improves the efficiency of writing and reading dimming data.

[0056] Optionally, the storage capacity of the storage array 100 is set according to the order of magnitude of the number of scans multiplied by the number of channels multiplied by the brightness data bit width (e.g., sixteen bits) and then multiplied by two, in order to meet the storage requirements of dimming.

[0057] In an optional embodiment of this application, the dimming data includes direct current (DC) data and / or pulse width modulation (PWM) data and / or dithering data. The DC data, PWM data, and dithering data are stored in corresponding storage units 110. DC data, for example, refers to data used in DC dimming (DC dimming) (DC data includes at least one of voltage values, current values, etc.). DC dimming controls brightness by adjusting the magnitude of DC voltage or current, i.e., by directly changing the voltage / current value supplied to the light source; the higher the voltage, the greater the brightness. Pulse width modulation data, for example, refers to data used in PWM dimming (PWM data includes duty cycle and frequency information, etc.). Pulse width modulation (dimming) controls the average power output by adjusting the duty cycle of the pulse signal, where duty cycle = high-level time ÷ period time; different brightness levels are simulated by rapid switching (typically at frequencies from several hundred Hz to several kHz); the higher the duty cycle, the greater the brightness. Optionally, a hybrid dimming strategy is used, i.e., different dimming data are used for different brightness ranges. For example, DC dimming can be used when the brightness is high and PWM dimming can be used when the brightness is low; or DC dimming or PWM dimming can be automatically switched according to ambient light, usage scenario, etc.

[0058] Optionally, the dimming data includes direct current (DC) data and / or pulse width modulation (PWM) data. The DC data and PWM data are stored in corresponding storage units 110. PWM data, for example, refers to data used in PWM dimming (duty cycle, frequency, etc.). DC data includes at least one selected from power supply voltage, reference voltage, current limit value, bias voltage, threshold voltage, and feedback voltage. DC data is used to ensure the normal operation, safety protection, and stability of the dimming system and is the foundation for the reliable operation of PWM dimming technology.

[0059] Optionally, backlight dimming-related dithering technology is an important technique used in display systems to improve visual effects and dimming accuracy. Dithering is a digital signal processing technique whose core principle is to optimize the performance of low-bit-depth signals by adding specific noise or random signals to the low bits. Dithering data refers to the data involved in dithering technology. Dithering data can be temporal dithering data, which involves rapidly switching different brightness levels over time, utilizing the persistence of vision in the human eye to create the perception of intermediate brightness. Dithering data can also be spatial dithering data, which involves distributing different brightness pixels in a spatial dimension to simulate intermediate grayscale.

[0060] In an optional embodiment of this application, the (chip / dimming data storage structure) supports three display operating modes: DC+Dither, PWM+Dither, and DC+PWM. The bit widths of the two data types can be flexibly configured in each mode, with the total number of bits after combination not exceeding the maximum precision of the display data; the effective bit width of each data component can be 0, as long as the overall combined bit width is greater than 0. Therefore, the serial hybrid dimming data sent from the bus needs to be parsed and separated according to different display modes, decomposing independent DC, PWM, and Dither data components to meet the dimming output requirements of each channel. Optionally, for the DC+Dither operating mode, DC data and Dither data are stored in different partitions (independent storage partitions) of the dimming data storage structure; for the PWM+Dither operating mode, PWM data and Dither data are stored in different partitions of the dimming data storage structure; for the DC+PWM operating mode, DC data and PWM data are stored in different partitions of the dimming data storage structure. Optionally, the storage array is divided into at least two dynamically definable storage partitions, and the data type stored in each storage partition is dynamically configured by the current display mode; the display mode includes at least one of DC + dithering, pulse width modulation + dithering, and DC + pulse width modulation, and the bit width of different types of data in each mode can be flexibly configured.

[0061] In an optional embodiment of this application, the dimming data storage structure further includes a (pre-)separation unit. The pre-separation unit is located at the write end of the storage array and is used to split different types of dimming data before the dimming data is stored in the storage array, that is, to separate the DC data, pulse width modulation data, and jitter data in the dimming data. The separated DC data, pulse width modulation data, and jitter data are stored in their respective storage units. Optionally, the different types of data separated from the dimming data can be rationally partitioned and stored according to actual needs.

[0062] Optionally, dimming data is written serially. The separation unit includes (single / multiple) serial separation logic circuits, which separate DC data, pulse width modulation data, and jitter data during the serial writing of dimming data. Optionally, the pre-separation unit includes a single set of serial separation logic circuits, which has a simple structure and can save circuit area.

[0063] According to a second aspect of this application, a dimming data storage method is provided. This dimming data storage method is applied, for example, to the dimming data storage structure described above.

[0064] Figure 2 A flowchart illustrating a dimming data storage method according to an embodiment of this application is shown. Figure 2 As shown, the dimming data storage method according to this application includes the following steps:

[0065] In step S101, serially input mixed dimming data is received;

[0066] The system receives serially input hybrid dimming data, which includes at least two of the following: DC data, pulse width modulation data, and dithering data. The received dimming data may refer to a set of parameters and instructions used to control the brightness of the light source, including brightness setpoints, control instructions, and operating modes. Precise adjustment of the backlight brightness is achieved through this dimming data.

[0067] In step S102, before the mixed dimming data is written to the storage array, the mixed dimming data is split into at least two types of DC data, pulse width modulation data and jitter data by a serial separation logic circuit.

[0068] In step S103, the split dimming data of different types are serially written into the corresponding storage units of the storage array, wherein the storage unit includes a trigger storage unit;

[0069] In step S104, the target address is input to the address decoding unit. After one decoding, the storage array outputs the entire row of multi-channel dimming data in parallel.

[0070] Figure 3 A schematic diagram illustrating the workflow of a DFF storage combined with a front-end separation overall architecture according to an embodiment of this application is shown. Figure 3 As shown, the workflow of DFF storage in conjunction with the front-end separation architecture includes the following steps:

[0071] In step S201, serial hybrid dimming data is input;

[0072] The system receives input of serial mixed dimming data, wherein the dimming data includes at least one selected from DC data, pulse width modulation data, and jitter data.

[0073] In step S202, the pre-serial mixed data separation logic is implemented;

[0074] A (single) serial circuit is used to implement a front-end serial mixed data separation logic to separate DC data, pulse width modulation data, and jitter data.

[0075] In step S203, the DFF trigger storage array stores the data.

[0076] The separated DC data, pulse width modulation data, and jitter data are divided into two zones for storage according to the display mode control, and then stored in the DFF trigger storage array.

[0077] In step S204, address decoding directly indexes the address;

[0078] By decoding the address, the stored dimming data can be directly indexed and located.

[0079] In step S205, the entire row of multi-channel parallel dimming data is output.

[0080] The entire row of multi-channel parallel dimming data output enables backlight driving.

[0081] According to the embodiments of this application, the DFF storage combined with the front-end separation overall architecture has better area for small data volumes, and a single index can output the entire row of data without the need for pre-reading and additional caching.

[0082] Figure 4 A circuit block diagram of a DFF dimming data storage array according to an embodiment of this application is shown. Figure 4 As shown, the serial separation logic outputs two component data streams. Component 1 is defined in DFF storage partition one mode, and component 2 is defined in DFF storage partition two mode. The address decoding module addresses to the corresponding position in the DFF trigger array, enabling parallel dimming output of the entire row's multi-channel data. This DFF dimming data storage array has only two independent storage partitions dynamically defined by the current display mode. Inputting the row address and channel address completes the direct indexing of the array units; one address decoding enables the parallel direct output of the entire row's channel data, matching the backlight driver.

[0083] Figure 5 A schematic diagram of the DFF array readout timing according to an embodiment of this application is shown. Figure 5 As shown, the timing control module sends a row address index to the DFF storage array, and the DFF storage array outputs the entire row of 16 channels of data in parallel to realize the backlight drive output.

[0084] Figure 6 A schematic diagram illustrating the workflow of a hybrid data separation logical architecture according to an embodiment of this application is shown. Figure 6 As shown, the workflow of the hybrid data separation logical architecture includes the following steps:

[0085] In step S301, bus serial mixed data input;

[0086] It receives input of serial mixed data from the bus, which includes DC data, pulse width modulation data, and jitter data.

[0087] In step S302, a single set of serial pre-processor separation logic is used;

[0088] Run a single set of serial pre-separation logic.

[0089] In step S303, the DC / PWM / Dither components are split;

[0090] Separate DC data, pulse width modulation (PWM) data, and dither data components from the mixed data.

[0091] In step S304, the data is serially written to the DFF storage array;

[0092] The separated components are classified and serially written to the DFF storage array.

[0093] In step S305, the DFF array is directly read out in parallel.

[0094] Data in the DFF array is read out and output directly in parallel to achieve backlight driving.

[0095] In the above embodiments of this application, by utilizing the inherent characteristics of serial transmission, only one set of serial separation logic is required, without the need for redundant parallel circuits, resulting in low area overhead.

[0096] In one specific embodiment of this application, the dimming data storage structure is based on a DFF (Digital Flip-Flop) storage structure design. Addressing the dimming data storage requirements on the order of "number of scans × number of channels × brightness data bit width (16 bits) × 2", and considering application scenarios with relatively few backlight scans, the traditional SRAM storage solution is abandoned. Instead, a DFF (Digital Flip-Flop) is used to build the dimming data storage array. Leveraging the area advantage of DFF in small data storage scenarios, the technical shortcomings of SRAM area redundancy are resolved.

[0097] Unlike the serial reading method of SRAM, DFF memory arrays support direct indexing of data through address decoding. That is, by inputting the target address, the corresponding DFF memory cell can be directly located and the target data can be output.

[0098] For a specific embodiment containing 16 channels of dimming data in a row, traditional SRAM requires 16 read operations to obtain the complete row of 16 channels of data; while the DFF storage array used in this solution only requires one address index operation to directly output the entire row of 16 channels of dimming data, without the need for sequential reading.

[0099] The technical effects of the dimming data storage structure in this application include, but are not limited to:

[0100] It eliminates the need for serial read logic circuitry required for SRAM, significantly reducing chip layout area;

[0101] It completely eliminates the need for "reading one line ahead" in traditional solutions, shortens data reading time, eliminates the need for additional temporary storage space for the next line of data and independent storage space for the current display line, further saves chip area, improves data reading efficiency, and adapts to the needs of parallel backlight output.

[0102] Furthermore, the mixed data separation logic adopts a front-end design (optimized processing timing). The separation processing logic for the mixed data of DC data, pulse width modulation (PWM) data, and dither data in the dimming data is deployed in advance, before the dimming data is stored in the DFF storage array. This replaces the traditional design of "storing index and then performing data separation", which solves the technical defect of redundant separation logic circuit area at the root.

[0103] The dimming mixed data sent from the bus is transmitted serially, and the process of storing the dimming data into the DFF storage array is also a serial write process. Based on the inherent characteristics of serial data transmission and serial writing, this solution only requires a set of serial separation logic circuits. This allows for the (intelligent) splitting of mixed data of multiple types, such as DC data, PWM data, and Dither data, before the dimming data is serially written into the DFF storage array. Each split component is then written to its corresponding independent storage unit in the DFF storage array, achieving classified data storage. Optionally, when the display mode has only two components, only two storage partitions are needed. The component type stored in each partition is defined by the display mode, further saving storage space.

[0104] Compared to traditional back-end separation designs, if mixed data separation is performed after indexing data from the DFF storage array, and the storage array index output is in parallel data format, multiple independent separation logic circuits must be designed for different display modes and parallel data paths to complete the data splitting, resulting in redundant logic circuits and a significant increase in chip layout area. In contrast, the front-end serial separation architecture of this solution can fully reuse the data serial transmission and serial writing links, eliminating the need to build multiple sets of parallel separation logic circuits, resulting in no additional area overhead, effectively improving chip integration, and significantly reducing the circuit design complexity of digital logic and the difficulty of back-end layout.

[0105] According to a third aspect of this application, a chip is provided. The (memory) chip includes the dimming data storage structure described above.

[0106] According to a fourth aspect of this application, a display device is provided. The display device includes a dimming data storage structure and a display panel as described above. A backlight of the display panel is electrically connected to the dimming data storage structure for receiving and executing dimming data. Optionally, the display panel includes at least one selected from cathode ray tube display panels, digital light processing display panels, liquid crystal display panels, light-emitting diode display panels, organic light-emitting diode display panels, quantum dot display panels, Micro-LED display panels, Mini-LED display panels, field emission display panels, plasma display panels, electrophoretic display panels, or electrowetting display panels.

[0107] Figure 7A schematic diagram of a display device according to an embodiment of this application is shown. Figure 7 As shown, the display device 9 according to an embodiment of this application includes a backlight 901, a processor 902, and a memory 903. The memory 903 stores one or more computer programs. When the processor 902 executes one or more computer programs, it causes the processor 902 to implement the dimming data storage method described above. The backlight 901 dims according to the dimming data.

[0108] Finally, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The embodiments described above, as per the implementation of this application, do not exhaustively describe all details, nor do they limit the application to only the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A dimming data storage structure, comprising: A storage array for storing dimming data; The storage array includes multiple storage units; The storage unit includes a trigger storage unit; An address decoding unit is electrically connected to the memory array; The address decoding unit is configured to perform a decoding operation on the input target address to obtain all the storage units of the corresponding row, enabling the storage array to output the entire row of multi-channel dimming data in parallel. The dimming data includes at least two types selected from DC data, pulse width modulation data, and jitter data, and different types of dimming data are stored in independent storage partitions of the storage array. The dimming data storage structure also includes: A pre-separation unit is disposed at the write end of the storage array and is used to split different types of dimming data before the dimming data is stored in the storage array. The pre-separation unit includes a serial separation logic circuit. The serial separation logic circuit is adapted to the serial writing method of the dimming data and splits DC data, pulse width modulation data and jitter data in real time during the serial transmission of data.

2. The dimming data storage structure according to claim 1, wherein, The trigger storage unit is a D-type trigger; each D-type trigger stores 1 bit of binary dimming data; the storage unit storing single-channel multi-bit dimming data includes multiple D-type triggers.

3. The dimming data storage structure according to claim 1, wherein, The storage array is divided into at least two dynamically definable storage partitions, and the data types stored in each storage partition are dynamically configured by the current display mode. The display mode includes at least one selected from DC and dithering, pulse width modulation and dithering, and DC and pulse width modulation.

4. The dimming data storage structure according to claim 1, wherein, The storage array includes a ping-pong storage architecture; The ping-pong storage architecture includes a first storage buffer unit and a second storage buffer unit; the first storage buffer unit and the second storage buffer unit alternately perform the write operation and read operation of the dimming data.

5. The dimming data storage structure according to claim 1, wherein, The storage capacity of the storage array meets the requirement that it be twice the product of the number of scans, the number of channels, and the bit width of the brightness data.

6. The dimming data storage structure according to claim 1, wherein, The address decoding unit performs a decoding operation on the input target address and indexes all storage units of the corresponding row.

7. A dimming data storage method, applied to the dimming data storage structure as described in any one of claims 1-6, comprising: Receives serially input mixed dimming data; Before the hybrid dimming data is written to the storage array, the hybrid dimming data is split into at least two types of DC data, pulse width modulation data and jitter data by a serial separation logic circuit. The split dimming data of different types are serially written into the corresponding storage units of the storage array, wherein the storage unit includes a trigger storage unit; The target address is input to the address decoding unit. After one decoding, the storage array outputs a full row of multi-channel dimming data in parallel.

8. A chip, comprising: The dimming data storage structure as described in any one of claims 1-6.

9. A display device, comprising: The dimming data storage structure as described in any one of claims 1-6; as well as The display panel has a backlight that is electrically connected to the dimming data storage structure for receiving and executing the dimming data.

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