Methods of operating memory devices, memory systems, and input / output circuits
Patent Information
- Application Number
- CN202510130765.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-05
- Publication Date
- 2026-08-07
Smart Images
Figure CN122531429A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a method of operating a memory device, a memory system, and an input / output circuit. Background Technology
[0002] With the continuous development of science and technology, semiconductor devices are widely used in various electronic devices and products. For example, Dynamic Random Access Memory (DRAM), as a volatile memory, is a commonly used semiconductor memory device in computers. Summary of the Invention
[0003] This disclosure provides a method of operating a memory device, a memory system, and an input / output circuit.
[0004] In a first aspect, embodiments of this disclosure provide a memory device, the memory device including a first die, the first die including an impedance calibration circuit; the impedance calibration circuit including a receiving circuit, a transmitting circuit, and a calibration control circuit; wherein...
[0005] The receiving circuit is coupled to the calibration control circuit and is configured to generate a calibration start signal;
[0006] The calibration control circuit is configured to generate a first enable signal based on the calibration start signal, and generate a second enable signal after generating the first enable signal;
[0007] The transmitting circuit is coupled to the calibration control circuit and is configured to output a third enable signal based on the second enable signal;
[0008] The receiving circuit is also configured to generate a first calibration end signal.
[0009] In one optional embodiment, the receiving circuit includes a signal processing circuit, a first signal generation circuit, and a second signal generation circuit; the transmitting circuit includes a first output terminal and a second output terminal; wherein,
[0010] The output terminals of the first signal generation circuit and the second signal generation circuit are both coupled to the calibration control circuit.
[0011] The first input terminal of the first signal generation circuit is coupled to the output terminal of the signal processing circuit.
[0012] The first input terminal of the second signal generation circuit is coupled to the first output terminal of the transmitting circuit.
[0013] In one alternative implementation, the transmitting circuit is specifically configured as follows:
[0014] A second calibration end signal is generated based on the second enable signal, and the second calibration end signal is output from the first output terminal of the transmitting circuit;
[0015] The third enable signal is generated based on the second enable signal, and the third enable signal is output from the second output terminal of the transmitting circuit.
[0016] In one optional embodiment, the memory device includes a plurality of dies, each of the plurality of dies including one of the impedance calibration circuits; the die that receives the first selection signal through the receiving circuit of the die is the first die; the second input terminal of the first signal generation circuit and the second input terminal of the second signal generation circuit of one of the plurality of dies are both coupled to the second output terminal of the transmitting circuit of another die.
[0017] In one optional embodiment, the plurality of dies further includes a plurality of second dies; the plurality of second dies include a second die coupled to the transmitting circuit of the first die and a second die coupled to the receiving circuit of the first die; the receiving circuit of the second die receives a second selection signal.
[0018] In one alternative implementation, the signal processing circuit of the first die is configured to generate a calibration enable signal based on the calibration command, the first selection signal, and the first calibration flag signal.
[0019] The first signal generation circuit of the first die is configured to generate the calibration start signal of the first die based on the calibration enable signal in response to the first selection signal.
[0020] In one optional implementation, the third enable signal includes a first transition edge and a second transition edge, wherein the first transition edge precedes the second transition edge.
[0021] The first signal generation circuit of the second die is configured to generate the calibration start signal of the second die based on the first transition edge of the third enable signal received by the receiving circuit of the second die in response to the second selection signal.
[0022] The second signal generation circuit of the first die is configured to generate the first calibration end signal of the first die based on the second transition edge of the third enable signal received by the receiving circuit of the first die in response to the first selection signal.
[0023] In one optional implementation, the first signal generation circuit includes a first selection circuit and a first signal generator; the second signal generation circuit includes a second selection circuit and a second signal generator; wherein,
[0024] The first input terminal of the first selection circuit is coupled to the output terminal of the signal processing circuit; the second input terminal of the first selection circuit is coupled to the second output terminal of the transmitting circuit of the other die.
[0025] The input terminal of the first signal generator is coupled to the output terminal of the first selection circuit; the output terminal of the first signal generator is coupled to the calibration control circuit.
[0026] The first input terminal of the second selection circuit is coupled to the first output terminal of the transmitting circuit; the second input terminal of the second selection circuit is coupled to the second output terminal of the transmitting circuit of the other die.
[0027] The input terminal of the second signal generator is coupled to the output terminal of the second selection circuit; the output terminal of the second signal generator is coupled to the calibration control circuit.
[0028] In one optional implementation, the control terminal of the first selection circuit and the control terminal of the second selection circuit of the first die both receive the first selection signal; the first selection signal instructs the first selection circuit to output the signal received at the first input terminal of the first selection circuit; the first selection signal instructs the second selection circuit to output the signal received at the second input terminal of the second selection circuit.
[0029] In one optional implementation, the calibration command includes a first calibration command and a second calibration command; the impedance calibration circuit further includes a third selection circuit, a first command generation circuit, and a second command generation circuit; the output terminal of the first command generation circuit is coupled to a first input terminal of the third selection circuit; the output terminal of the second command generation circuit is coupled to a second input terminal of the third selection circuit; and the output terminal of the third selection circuit is coupled to one input terminal of the signal processing circuit.
[0030] The first command generation circuit is configured to periodically generate the first calibration command;
[0031] The second command generation circuit is configured to: receive and parse an external calibration command, and generate the second calibration command;
[0032] The third selection circuit is configured to: output the first calibration command in the first calibration mode; and output the second calibration command in the second calibration mode.
[0033] In one optional implementation, the receiving circuit includes a trigger; a first input of the trigger receives the calibration start signal; a second input of the trigger receives the first calibration end signal; the trigger is configured to:
[0034] A second calibration flag signal is output based on the calibration start signal and the first calibration end signal.
[0035] In one optional embodiment, the impedance calibration circuit further includes a calibration sub-circuit coupled to the calibration control circuit and coupled to a reference resistor; the calibration sub-circuit is configured to:
[0036] In response to the first enable signal, a first calibration operation is performed based on the reference resistor, and a first calibration result is obtained;
[0037] In response to the second enable signal, a second calibration operation is performed based on the first calibration result, and a second calibration result is obtained.
[0038] In one optional embodiment, the memory device includes an input / output circuit; the input / output circuit includes a pull-up drive circuit for the first die, a pull-down drive circuit, and the impedance calibration circuit; the calibration sub-circuit is further configured to:
[0039] The first calibration result is sent to one of the pull-up drive circuit and the pull-down drive circuit, and the second calibration result is sent to the other of the pull-up drive circuit and the pull-down drive circuit.
[0040] Secondly, this disclosure provides a memory system, comprising:
[0041] At least one memory device according to any of the above embodiments;
[0042] A controller is coupled to at least one of the memory devices and configured to control the memory devices.
[0043] In one alternative implementation, the controller is configured to generate an external calibration command;
[0044] The input / output circuitry in the memory device is configured to perform an impedance calibration operation in response to the external calibration command.
[0045] Thirdly, this disclosure provides a method for operating an input / output circuit, including:
[0046] Generate calibration start signal;
[0047] A first enable signal is generated based on the calibration start signal, and a second enable signal is generated after the first enable signal is generated;
[0048] A third enable signal is output based on the second enable signal;
[0049] Generate the first calibration end signal.
[0050] In one optional implementation, the operation method further includes:
[0051] A second calibration end signal is generated based on the second enable signal.
[0052] In one optional implementation, generating the calibration start signal includes:
[0053] A calibration enable signal is generated based on the calibration command, the first selection signal, and the first calibration flag signal;
[0054] In response to the first selection signal, the calibration start signal of the first die is generated based on the calibration enable signal.
[0055] In one optional implementation, generating the calibration start signal further includes:
[0056] In response to the second selection signal, the calibration start signal of the second die is generated based on the first transition edge of the third enable signal received by the receiving circuit of the second die;
[0057] The generation of the first calibration end signal includes:
[0058] In response to the first selection signal, the first calibration end signal is generated based on the second transition edge of the third enable signal received by the receiving circuit of the first die.
[0059] In one optional implementation, the calibration command includes a first calibration command and a second calibration command; the operation method further includes:
[0060] The first calibration command is generated periodically;
[0061] Receive and parse external calibration commands, and generate the second calibration command;
[0062] In the first calibration mode, the first calibration command is output;
[0063] In the second calibration mode, the second calibration command is output.
[0064] In one optional implementation, the operation method further includes:
[0065] A second calibration flag signal is output based on the calibration start signal and the first calibration end signal.
[0066] In one optional implementation, the operation method further includes:
[0067] In response to the first enable signal, a first calibration operation is performed based on the reference resistor, and a first calibration result is obtained;
[0068] In response to the second enable signal, a second calibration operation is performed based on the first calibration result, and a second calibration result is obtained.
[0069] In one optional implementation, the operation method further includes:
[0070] The first calibration result is sent to one of the pull-up drive circuit and the pull-down drive circuit, and the second calibration result is sent to the other of the pull-up drive circuit and the pull-down drive circuit. Attached Figure Description
[0071] Figure 1 A schematic diagram of an electronic device provided in an embodiment of this disclosure;
[0072] Figure 2 A schematic diagram of DRAM provided for an embodiment of this disclosure;
[0073] Figure 3 A schematic diagram of the pull-up drive circuit and the pull-down drive circuit provided in the embodiments of this disclosure;
[0074] Figure 4 Schematic diagram of the impedance calibration circuit provided in the embodiments of this disclosure Figure 1 ;
[0075] Figure 5 Schematic diagram of the impedance calibration circuit provided in the embodiments of this disclosure Figure 2
[0076] Figure 6 A schematic diagram of a plurality of dies in a memory device provided in an embodiment of this disclosure;
[0077] Figure 7 This is a schematic diagram showing the connection of multiple dies provided in an embodiment of this disclosure;
[0078] Figure 8 A schematic diagram of the receiving circuit and the transmitting circuit in the impedance calibration circuit provided in the embodiments of this disclosure;
[0079] Figure 9 Circuit diagrams of the receiving and transmitting circuits in the impedance calibration circuit provided as a specific example of this disclosure;
[0080] Figure 10A schematic diagram of the receiving and transmitting circuits of the first die and the receiving and transmitting circuits of the second die provided for embodiments of this disclosure;
[0081] Figure 11 A timing diagram for performing impedance calibration operations provided in embodiments of this disclosure;
[0082] Figure 12 This is a flowchart illustrating the operation method of the input / output circuit provided in the embodiments of this disclosure. Detailed Implementation
[0083] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0084] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0085] In the accompanying drawings, the same reference numerals denote the same elements throughout.
[0086] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0087] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0088] Figure 1 This is a schematic diagram of an electronic device provided in an embodiment of this disclosure. The electronic device 1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.
[0089] like Figure 1 As shown, electronic device 1 may include a memory system 10 and a host 20. The memory system 10 may include a controller 110 and a memory device 120. The host 20 may include a processor of electronic device 1, such as a central processing unit (CPU) or a system-on-chip (SoC) (e.g., an application processor (AP)). The controller 110 is coupled to both the host 20 and the memory device 120, and the controller 110 may be configured to communicate with the host 20 and control the memory device 120.
[0090] In some embodiments, controller 110 may be configured to control operations of memory device 120, such as read operations, erase operations, write operations, refresh operations, etc. In some embodiments, controller 110 is also configured to process error correction codes (ECCs) regarding data read from or written to memory device 120. In other embodiments, controller 110 may also be configured to perform any other suitable operation, such as formatting memory device 120.
[0091] In some embodiments, controller 110 can receive data, commands, and addresses from host 20 and can send data, commands, and addresses to memory device 120. Specifically, controller 110 may include command generator 111, address generator 112, device interface 113, and host interface 114. Controller 110 can receive data, commands, and addresses from host 20 through host interface 114, decode commands received from host 20 through command generator 111 to generate access command CMD, and provide access command CMD to memory device 120 through device interface 113. Controller 110 can decode addresses received from host interface 114 through address generator 112 to generate address ADDR to be accessed in memory array 121, and provide the address ADDR to be accessed to memory device 120 through device interface 113. The access command may be a signal instructing memory device 120 to write or read data by accessing one or more memory cells in memory array 121 corresponding to address ADDR. In addition, the controller 110 can also send a refresh command to the memory device 120. The refresh command may be a signal instructing the memory device 120 to read and rewrite data by accessing one or more memory cells of the memory array 121 corresponding to the address ADDR.
[0092] In some specific examples, memory device 120 may be flash memory, such as NAND flash memory, or random access memory (RAM), such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), double-data-rate SDRAM (DDR SDRAM), phase-change random access memory (PRAM), resistive random access memory (ReRAM), magnetic random access memory (MRAM), etc. The following explanation will use DRAM as an example.
[0093] In some embodiments, Figure 2 This is a schematic diagram illustrating a memory device according to an embodiment of the present disclosure. (Referring to...) Figure 1 and Figure 2The memory device includes a memory array 121 and peripheral circuitry 122 coupled to the memory array 121. The peripheral circuitry 122 may include a sense amplifier circuit 1221, a row decoder 1222, a column decoder 1223, an input / output circuit 1224, etc. The memory array 121 includes multiple memory cells arranged in an array. Multiple memory cells in the same row are coupled to word lines (WL), and multiple memory cells in the same column are coupled to bit lines (BL). Each memory cell includes a transistor (T) and a capacitor (C). The word line (WL) is connected to the gate of the transistor (T), and the bit line (BL) is connected to one of the source and drain of the transistor (T). The other of the source and drain of the transistor (T) is connected to one electrode of the capacitor (C), and the other electrode of the capacitor (C) is connected to a fixed voltage. The memory cell is configured to store "1" or "0" by utilizing the amount of charge stored in the capacitor (C). By specifying row and column addresses, individual memory cells within a DRAM chip can be accessed independently, and read, write, or refresh operations can be performed on the stored data. Here, Figure 2 It can also be a schematic diagram of a die in a memory device.
[0094] In some embodiments, refer to Figure 3 The input / output circuit 1224 may include a pull-up drive circuit 131 and a pull-down drive circuit 132. Here, we take the pull-up drive circuit 131 and the pull-down drive circuit 132 coupled to an input / output pad (e.g., DQ pad) 133 in the input / output circuit 1224 as an example. Pull-up drive circuit 131 can be coupled between the power supply terminal and the input / output pad 133, and pull-down drive circuit 132 can be coupled between the ground terminal and the input / output pad 133. Pull-up drive circuit 131 can include multiple pull-up drivers, and pull-down drive circuit 132 can include multiple pull-down drivers. The resistance value of each pull-up driver and the resistance value of each pull-down driver are the same fixed value. By setting the number of pull-up drivers connected in parallel between the power supply terminal and the input / output pad 133 in the pull-up drive circuit and the number of pull-down drivers connected in parallel between the ground terminal and the input / output pad 133 in the pull-down drive circuit, the input impedance or output impedance for signal transmission through the input / output pad 133 can be set to match the impedance of the peer interface and the impedance of the link, thereby reducing signal reflection and improving signal integrity.
[0095] However, due to fluctuations in process and environmental conditions (such as temperature and voltage), the resistance values of pull-up and pull-down drivers are difficult to keep constant for a long time, leading to impedance matching failure. In this case, impedance calibration (ZQ Calibration) is required to calibrate the resistance values of the pull-up and pull-down drivers.
[0096] In some specific examples, the input / output circuit 1224 may include an impedance calibration circuit, which can be coupled to a reference resistor located externally to the memory device via a ZQ pad. The reference resistor has a fixed resistance value that is unaffected by environmental conditions, and this resistance value serves as the target resistance value for the pull-up and pull-down drivers. The impedance calibration circuit may include pull-up drivers with the same structure as those in the pull-up drive circuit and pull-down drivers with the same structure as those in the pull-down drive circuit. The impedance calibration process may include performing pull-up calibration and pull-down calibration based on the reference resistor, respectively, to adjust the resistance values of the pull-up and pull-down drivers in the impedance calibration circuit to the target resistance values, and obtain corresponding calibration results (e.g., calibration codes for setting the resistance values of the pull-up and pull-down drivers). The pull-up calibration results and pull-down calibration results may be sent to the pull-up and pull-down drive circuits, respectively, to adjust the resistance values of multiple pull-up drivers in the pull-up drive circuit and multiple pull-down drivers in the pull-down drive circuit, respectively.
[0097] In some embodiments, a memory device may include multiple dies, and the impedance calibration circuits of these dies are coupled to the same reference resistor. Therefore, the impedance calibration of these multiple dies needs to be performed sequentially, which consumes a significant amount of time, resulting in low impedance calibration efficiency and consequently affecting the response speed of the memory device. Thus, it is necessary to improve the efficiency of impedance calibration in memory devices comprising multiple dies.
[0098] The present disclosure provides the following implementation methods.
[0099] This disclosure provides a memory device including a first die, the first die including an impedance calibration circuit. Figure 4 Schematic diagram of the impedance calibration circuit provided in the embodiments of this disclosure Figure 1 , refer to Figure 4The impedance calibration circuit 200 includes a receiving circuit 201, a transmitting circuit 202, and a calibration control circuit 203. The receiving circuit 201 is coupled to the calibration control circuit 203 and configured to generate a calibration start signal. The calibration control circuit 203 is configured to generate a first enable signal based on the calibration start signal, and then generate a second enable signal after generating the first enable signal. The transmitting circuit 202 is coupled to the calibration control circuit 203 and configured to output a third enable signal based on the second enable signal. The receiving circuit 201 is also configured to generate a first calibration end signal.
[0100] Figure 5 Schematic diagram of the impedance calibration circuit provided in the embodiments of this disclosure Figure 2 Combined with reference Figure 4 and Figure 5 The receiving circuit 201 is configured to generate a calibration start signal CAL_START; the calibration control circuit 203 is configured to generate a first enable signal PDEN based on the calibration start signal CAL_START, and generate a second enable signal PUEN after generating the first enable signal PDEN; the transmitting circuit 202 is configured to output a third enable signal PUEN_D based on the second enable signal PUEN; the receiving circuit 201 is also configured to generate a first calibration end signal CAL_DONE.
[0101] In some embodiments, refer to Figure 5 The impedance calibration circuit also includes a calibration sub-circuit 204, which is coupled to the calibration control circuit 203, and the calibration sub-circuit 204 is connected to the reference resistor R. ZQ Coupled; the calibration sub-circuit 204 is configured to: respond to the first enable signal PDEN, based on the reference resistor R ZQ Perform a first calibration operation and obtain a first calibration result; in response to a second enable signal PUEN, perform a second calibration operation based on the first calibration result and obtain a second calibration result.
[0102] In some specific examples, the calibration sub-circuit 204 includes a ZQ pad 2041, a first pull-down driver 2042, a second pull-down driver 2043, a pull-up driver 2044, a calibration update circuit 2045, a first comparator 2046, and a second comparator 2047; wherein, the ZQ pad 2041 is connected to an external reference resistor R. ZQ Coupling, reference resistor R ZQ The first pull-down driver 2042 and the second pull-down driver 2043 have the same circuit structure and are both coupled to the ground terminal; the pull-up driver 2044 is coupled to the power supply terminal.
[0103] In some specific examples, the process of performing the first calibration operation may include: the calibration update circuit 2045 sending the initial calibration code of the pull-down driver to the first pull-down driver 2042 in response to the first enable signal PDEN, so as to set the resistance value of the first pull-down driver 2042; and the first comparator 2046 comparing the voltage V on the ZQ pad 2041. io1 With the first reference voltage V ref1 The comparison result is then sent to the calibration update circuit 2045. Here, the voltage at the power supply terminal is V. DD For example, the first reference voltage V ref1 It can be equal to V DD / 2, if the resistance value of the first pull-down driver 2042 is the same as the reference resistor R ZQ If the resistance values are equal, then the voltage V on the ZQ pad 2041 is... io1 With the first reference voltage V ref1 If the resistance values of the first pull-down driver 2042 and the reference resistor R are equal, the first calibration operation is complete; ZQ If the resistance values are not equal, then the voltage V on the ZQ pad 2041 will be... io1 With the first reference voltage V ref1 If they are not equal, the calibration update circuit 2045 can update the calibration code of the pull-down driver according to the comparison result and send the updated calibration code to the first pull-down driver 2042 until the resistance value of the first pull-down driver 2042 equals the reference resistor R. ZQ The resistance value, i.e., the voltage V on the ZQ pad 2041. io1 With the first reference voltage V ref1 If the values are equal, the first calibration operation ends. During the first calibration operation, the calibration update circuit 2045 also sends the calibration code of the pull-down driver to the second pull-down driver 2043. Therefore, when the first calibration operation ends, the resistance value of the second pull-down driver 2043 is the same as the resistance value of the first pull-down driver 2042. Here, the calibration code of the pull-down driver obtained at the end of the first calibration operation is the first calibration result.
[0104] In some specific examples, the process of performing the second calibration operation may include: the calibration update circuit 2045 sending the initial calibration code of the pull-up driver to the pull-up driver 2044 in response to the second enable signal PUEN, so as to set the resistance value of the pull-up driver 2044; and the second comparator 2047 comparing the voltage V on node 2048. io2 With the second reference voltage V ref2 The comparison result is then sent to the calibration update circuit 2045. Here, the second reference voltage V... ref2 It can also be equal to V DD / 2, If the resistance of the pull-up driver 2044 is equal to the resistance of the second pull-down driver 2043, then the voltage V on node 2048 is... io2 With the second reference voltage V ref2 If the resistance values of the pull-up driver 2044 and the second pull-down driver 2043 are not equal, then the voltage V on node 2048 will be equal. io2 With the second reference voltage V ref2 If they are not equal, the calibration update circuit 2045 can update the calibration code of the pull-up driver according to the comparison result and send the updated calibration code to the pull-up driver 2044 until the resistance value of the pull-up driver 2044 is equal to the resistance value of the second pull-down driver 2043, that is, the voltage V on node 2048. io2 With the second reference voltage V ref2 If they are equal, the second calibration operation ends. Here, the calibration code of the pull-up driver obtained at the end of the second calibration operation is the second calibration result.
[0105] It should be noted that the specific examples provided in this disclosure use a pull-down calibration enable signal (PDEN) as the first enable signal, a pull-down calibration operation as the first calibration operation, a pull-up calibration enable signal (PUEN) as the second enable signal, and a pull-up calibration operation as the second calibration operation. The example of performing impedance calibration includes performing a pull-down calibration operation followed by a pull-up calibration operation. However, this disclosure is not limited to this. In other embodiments, a pull-up calibration operation can be performed first, followed by a pull-down calibration operation. In this case, the first enable signal is a pull-up calibration enable signal, the first calibration operation is a pull-up calibration operation, the second enable signal is a pull-down calibration enable signal, and the second calibration operation is a pull-down calibration operation. The calibration sub-circuit includes two pull-up drivers and one pull-down driver. The first pull-up driver is coupled to the ZQ pad, the reference resistor is coupled between the ZQ pad and the ground terminal, and both the first and second pull-up drivers are coupled to the power supply terminal. The pull-down driver is coupled to the ground terminal. For simplicity, the following embodiments will use the pull-down calibration enable signal (PDEN) as the first enable signal and the pull-up calibration enable signal (PUEN) as the second enable signal as the example.
[0106] In some embodiments, the memory device includes an input / output circuit, which includes a pull-up drive circuit, a pull-down drive circuit, and an impedance calibration circuit for a first die; the calibration sub-circuit 204 is further configured to send a first calibration result to one of the pull-up drive circuit and the pull-down drive circuit, and to send a second calibration result to one of the pull-up drive circuit and the pull-down drive circuit.
[0107] In some specific examples, the first calibration result can be sent to the pull-down drive circuit to set the resistance values of multiple pull-down drivers in the pull-down drive circuit, and the second calibration result can be sent to the pull-up drive circuit to set the resistance values of multiple pull-up drivers in the pull-up drive circuit. Here, the circuit structure of the pull-down driver in the pull-down drive circuit is the same as the circuit structure of the first pull-down driver 2042 in the calibration sub-circuit 204, and the circuit structure of the pull-up driver in the pull-up drive circuit is the same as the circuit structure of the pull-up driver 2044 in the calibration sub-circuit 204. Thus, the impedance calibration operation for the first die can be completed.
[0108] As can be seen from the impedance calibration process provided in the example above, the reference resistor R is only required when performing the first calibration operation. ZQ Then, when it is necessary to access the common reference resistor R in the memory device ZQ When performing impedance calibration operations on multiple dies, the impedance calibration operation of one die can partially overlap with the impedance calibration operation of another die in time to improve the efficiency of performing impedance operations on multiple dies. This requires connecting the impedance calibration circuits of multiple dies together.
[0109] Figure 6 This is a schematic diagram of a plurality of dies in a memory device provided in an embodiment of the present disclosure. The memory device may include a plurality of dies DIE0 to DIEn, and the specific composition of each die may be as follows: Figure 2 Similarly, each die may include a memory array and a sense amplifier, row decoder, column decoder, and input / output circuitry coupled to the memory array. Here, the arrangement and number of dies in the memory device are merely illustrative and are not intended to limit the specific memory device provided in the embodiments of this disclosure.
[0110] In this embodiment of the disclosure, the input / output circuit of any one of the plurality of dies in the memory device may include an impedance calibration circuit, and the impedance calibration circuit of the plurality of dies is connected to a reference resistor R. ZQ coupling. Specifically, Figure 7 This is a schematic diagram illustrating the connection of multiple dies provided in an embodiment of this disclosure. (Refer to reference...) Figures 5 to 7Any one of the multiple dies DIE0 to DIEn may include an impedance calibration circuit 200. For two dies that are coupled to each other, the receiving circuit RX of one die is coupled to the transmitting circuit TX of the other die. The multiple dies may include a first die and multiple second dies; here, we take DIE0 as the first die and DIE1 to DIEn as the multiple second dies. The multiple second dies include a second die (DIE1) coupled to the transmitting circuit TX of the first die DIE0 and a second die (DIEn) coupled to the receiving circuit RX of the first die DIE0. In addition, any one of the multiple dies also includes a selection signal generation circuit (M), and the selection signal generation circuit of the first die DIE0 is connected to the power supply terminal and configured to: generate a first selection signal STm and send the first selection signal STm to the receiving circuit RX of the first die DIE0; the selection signal generation circuit of the second die is connected to the ground terminal and configured to: generate a second selection signal STs and send the second selection signal STs to the receiving circuit RX of the second die. In other words, among multiple dies, the die that receives the first selection signal STm through its receiving circuit RX is designated as the first die, while the other dies that receive the second selection signal STs through their receiving circuits RX can all be designated as the second dies. Here, the first selection signal STm can be a logic high level, and the second selection signal STs can be a logic low level.
[0111] In this embodiment, the circuit structure of the impedance calibration circuit in the second die can be the same as that in the first die. Hereinafter, the structure and function of the receiving circuit 201 and the transmitting circuit 202 in the impedance calibration circuit 200 will be described using the impedance calibration circuit 200 in one die as an example. Figure 8 This is a schematic diagram of the receiving circuit and the transmitting circuit in the impedance calibration circuit provided in the embodiments of this disclosure. Figure 9 The circuit diagrams of the receiving and transmitting circuits in the impedance calibration circuit provided as a specific example of this disclosure.
[0112] In some embodiments, in conjunction with reference Figure 5 , Figure 7 and Figure 8The receiving circuit 201 includes a signal processing circuit 211, a first signal generation circuit 212, and a second signal generation circuit 213; the transmitting circuit 202 includes a first output terminal and a second output terminal; wherein, the output terminals of the first signal generation circuit 212 and the second signal generation circuit 213 are both coupled to the calibration control circuit 203; the first input terminal of the first signal generation circuit 212 is coupled to the output terminal of the signal processing circuit 211; the first input terminal of the second signal generation circuit 213 is coupled to the first output terminal of the transmitting circuit 202; the second input terminals of the first signal generation circuit 212 and the second input terminals of the second signal generation circuit 213 are both coupled to the second output terminal of the transmitting circuit of another die. Here, the other die can be one of a plurality of dies that is coupled to the receiving circuit 201 of the die through its transmitting circuit.
[0113] In some specific examples, in conjunction with reference Figure 5 , Figure 7 , Figure 8 and Figure 9 The signal processing circuit 211 includes an AND gate; the first signal generation circuit 212 includes a first selection circuit 2121 and a first signal generator 2122; and the second signal generation circuit 213 includes a second selection circuit 2131 and a second signal generator 2132. The first input terminal of the first selection circuit 2121 is coupled to the output terminal of the signal processing circuit 2111, and the second input terminal of the first selection circuit 2121 is coupled to the second output terminal of the transmitting circuit of another die. The input terminal of the first signal generator 2122 is coupled to the output terminal of the first selection circuit 2121, and the output terminal of the first signal generator 2122 is coupled to the calibration control circuit 203. The first input terminal of the second selection circuit 2131 is coupled to the first output terminal of the transmitting circuit 202, and the second input terminal of the second selection circuit 2131 is coupled to the second output terminal of the transmitting circuit of another die. The input terminal of the second signal generator 2132 is coupled to the output terminal of the second selection circuit 2131, and the output terminal of the second signal generator 2132 is coupled to the calibration control circuit 203.
[0114] In a specific example, the first signal generator 2122 is a rising edge triggered signal generator, and the second signal generator 2132 is a falling edge triggered signal generator. The first signal generator 2122 can generate a calibration start signal CAL_START based on the rising edge of the signal input from its input terminal, and the second signal generator 2132 can generate a first calibration end signal CAL_DONE based on the falling edge of the signal input from its input terminal.
[0115] In some specific examples, the transmitting circuit 202 includes a first delay circuit 2021 and a second delay circuit 2022, the first output terminal of the transmitting circuit 202 is the output terminal of the second delay circuit 2022, and the second output terminal of the transmitting circuit 202 is the output terminal of the first delay circuit 2021.
[0116] In some specific examples, the transmitting circuit 202 is specifically configured to: generate a second calibration end signal SELF_DONE based on the second enable signal PUEN, and output the second calibration end signal SELF_DONE from the first output terminal of the transmitting circuit 202; generate a third enable signal PUEN_D based on the second enable signal PUEN, and output the third enable signal PUEN_D from the second output terminal of the transmitting circuit 202. Here, both the third enable signal PUEN_D and the second calibration end signal SELF_DONE are signals obtained by delaying the second enable signal PUEN, so the pulse waveforms of the third enable signal PUEN_D and the second calibration end signal SELF_DONE can both be the same as the pulse waveform of the second enable signal PUEN.
[0117] In this disclosure embodiment, in conjunction with reference to Figure 7 and Figure 9 The control terminals of the first selector 2121 and the second selector 2131 receive the same selection signal ST. For the first die, the control terminals of the first selector 2121 and the second selector 2131 receive a first selection signal STm. For the second die, the control terminals of the first selector 2121 and the second selector 2131 receive a second selection signal STs. Specifically, the first selection signal STm indicates that the first selection circuit 2121 outputs the signal received at its first input terminal; the first selection signal STm indicates that the second selection circuit 2131 outputs the signal received at its second input terminal; the second selection signal STs indicates that the first selection circuit 2121 outputs the signal received at its second input terminal; and the second selection signal STs indicates that the second selection circuit 2131 outputs the signal received at its first input terminal. The following will use the first die (DIE0), the second die (DIE1) coupled to the transmitting circuit of the first die, and the second die (DIEn) coupled to the receiving circuit of the first die as examples to illustrate the signal generation and transmission process in the impedance calibration process.
[0118] Figure 10 The diagram illustrates the receiving and transmitting circuits of the first die and the second die, as provided in embodiments of this disclosure. Figure 11This is a timing diagram for performing impedance calibration operations according to an embodiment of the present disclosure. Here, "m" and "s" are used to distinguish the circuit structures in the first die and the second die, respectively.
[0119] In some embodiments, refer to Figure 10 The signal processing circuit 211m of the first die DIE0 is configured to generate a calibration enable signal based on the calibration command, the first selection signal STm, and the first calibration flag signal CAL_FLAG. The first signal generation circuit 212m of the first die DIE0 is configured to generate a calibration start signal CAL_START of the first die DIE0 based on the calibration enable signal. Specifically, the first selection circuit 2121m of the first die DIE0 can respond to the first selection signal STm by outputting the signal received at the first input terminal of the first selection circuit 2121m, that is, the first selection circuit 2121m can output the calibration enable signal generated by the signal processing circuit 211m and output the calibration enable signal to the first signal generator 2122m. The first signal generator 2122m can generate the calibration start signal CAL_START of the first die DIE0 based on the rising edge of the calibration enable signal.
[0120] In some specific examples, in conjunction with reference Figure 5 and Figure 9 The calibration command may include a first calibration command and a second calibration command. The impedance calibration circuit 200 also includes a third selection circuit 223, a first command generation circuit 221, and a second command generation circuit 222. The output of the first command generation circuit 221 is coupled to the first input of the third selection circuit 223. The output of the second command generation circuit 222 is coupled to the second input of the third selection circuit 223. The output of the third selection circuit 223 is coupled to one input of the signal processing circuit 211. The first command generation circuit 221 is configured to periodically generate the first calibration command. The second command generation circuit 222 is configured to receive and parse external calibration commands and generate the second calibration command. The third selection circuit 223 is configured to output the first calibration command in the first calibration mode and output the second calibration command in the second calibration mode. Here, the first calibration mode can be a background calibration mode, and the first command generation circuit 221 can periodically generate the first calibration command so that the impedance calibration circuit periodically performs impedance calibration operations. The second calibration mode is a calibration mode that performs impedance calibration operations in response to an external calibration command. The external calibration command can be generated by the controller, that is, the memory device can perform impedance calibration operations in response to an external calibration command generated by the controller.
[0121] In some specific examples, in conjunction with reference Figure 10 and Figure 11The first calibration flag signal CAL_FLAG indicates the state of the impedance calibration circuit. Before the impedance calibration operation begins, the first calibration flag signal CAL_FLAG remains at a logic high level. At this time, since the first selection signal STm is at a logic high level, if the signal processing circuit 211m of the first die DIE0 receives a calibration command at a logic high level, it can output a calibration enable signal, which is also at a logic high level. Subsequently, the first calibration flag signal CAL_FLAG changes from a logic high level to a logic low level, indicating that the impedance calibration circuit is in the process of performing an impedance calibration operation. In this case, before the impedance calibration operation is completed, that is, before the first calibration flag signal CAL_FLAG changes to a logic high level, even if the signal processing circuit 211m of the first die DIE0 receives another calibration command, it will not generate a calibration enable signal again, thereby avoiding interference from external calibration commands to the ongoing impedance calibration operation.
[0122] Combined with reference Figure 10 and Figure 11 The calibration control circuit of the first die DIE0 can generate a first enable signal PDEN based on the calibration start signal CAL_START of the first die DIE0, and generate a second enable signal PUEN after generating the first enable signal PDEN, so as to perform the impedance calibration operation of the first die DIE0. The transmitting circuit 202m of the first die DIE0 can generate a third enable signal PUEN_D based on the second enable signal PUEN, and output the third enable signal PUEN_D to the receiving circuit 201s of the second die DIE1.
[0123] In some embodiments, the third enable signal PUEN_D includes a first transition edge and a second transition edge, with the first transition edge preceding the second transition edge. Here, we take an example where the first transition edge is a rising edge and the second transition edge is a falling edge. The first signal generation circuit 212s of the second die DIE1 is configured to: in response to the second selection signal STs, generate a calibration start signal CAL_START for the second die DIE1 based on the first transition edge of the third enable signal PUEN_D received by the receiving circuit 201s of the second die DIE1. Specifically, the first selection circuit 2121s of the second die DIE1 can output the signal received at the second input terminal of the first selection circuit 2121s in response to the second selection signal STs. That is, the first selection circuit 2121s can output the third enable signal PUEN_D received from the first die DIE0 and output the third enable signal PUEN_D to the first signal generator 2122s. The first signal generator 2122s can generate the calibration start signal CAL_START of the second die DIE1 based on the rising edge of the third enable signal PUEN_D. Then, the calibration control circuit of the second die DIE1 can generate the first enable signal PDEN and the second enable signal PUEN in response to the calibration start signal CAL_START to perform the impedance calibration operation of the second die DIE1. Here, referring to the reference... Figure 10 and Figure 11 Since the third enable signal PUEN_D is a delayed signal of the second enable signal PUEN, the calibration start signal CAL_START of the second die can be considered to be generated based on the rising edge of the second enable signal PUEN of the first die DIE0. That is, after the first die DIE0 starts to respond to the second enable signal PUEN to perform the second calibration operation, the second die DIE1 can generate its calibration start signal and start to perform impedance calibration operation.
[0124] In this embodiment, the calibration start signal of the first die is generated based on a calibration command, a first selection signal, and a calibration flag signal. That is, the first die can act as the master die, being the first die to initiate impedance calibration. The calibration start signal of the second die is generated based on a third enable signal output by the previous die. That is, the second die can act as a slave die, and the first calibration operation of the second die can partially overlap with the second calibration operation of the previous die, thereby improving the efficiency of impedance calibration operations performed by multiple dies.
[0125] In some embodiments, refer to Figure 9 The transmitting circuit 202 can generate a second calibration end signal SELF_DONE based on the second enable signal PUEN, and output the second calibration end signal SELF_DONE from the first output terminal of the transmitting circuit 202 to the second input terminal of the second signal generation circuit 213. (Refer to...) Figure 10 For the second die, the second selection circuit 2131s in its second signal generation circuit 213s can respond to the second selection signal STs and output the second calibration end signal SELF_DONE to the second signal generator 2132s. The second signal generator 2132s can generate a first calibration end signal CAL_DONE for the second die based on the falling edge of the second calibration end signal SELF_DONE. This signal is used to indicate the end of the impedance calibration operation for the second die. For the first die, the second selection circuit 2131m of its second signal generation circuit 213m will not output the second calibration end signal SELF_DONE to the second signal generator 2132m in response to the first selection signal STm. Instead, it will output the third enable signal PUEN_D received from the last second die DIEn to the second signal generator 2132m. The second signal generator 2132m will generate a first calibration end signal CAL_DONE for the first die DIE0 based on the falling edge of the third enable signal PUEN_D. This signal is used to indicate the end of the impedance calibration operation for all dies.
[0126] Here, in conjunction with reference Figure 10 and Figure 11 Since the third enable signal PUEN_D is a delayed version of the second enable signal PUEN, the first calibration end signal CAL_DONE of the first die DIE0 can be considered to be generated based on the falling edge of the second enable signal PUEN of the last second die DIEn. Therefore, when the first calibration end signal CAL_DONE of the first die DIE0 is generated, the second calibration operation of the last second die DIEn has already been completed, thereby improving the reliability of impedance calibration operations performed by multiple dies.
[0127] In some embodiments, return to reference Figure 9 The receiving circuit 201 further includes a flip-flop 214. The first input of the flip-flop 214 receives a calibration start signal CAL_START, and the second input receives a first calibration end signal CAL_DONE. The flip-flop 214 is configured to generate a second calibration flag signal CAL_FLAG_OUT based on the calibration start signal CAL_START and the first calibration end signal CAL_DONE. Here, the flip-flop 214 is an SR flip-flop, and its first input can be a set input (S), and its second input can be a reset input (R).
[0128] Combined with reference Figure 10 and Figure 11When the second input of the flip-flop 214m of the first die DIE0 receives the first calibration end signal CAL_DONE, the calibration start signal CAL_START received at the first input of the flip-flop 214m remains at a logic low level. Then, after the second input of the flip-flop 214m receives the first calibration end signal CAL_DONE and changes to a logic high level,
[0130] Inverting output terminal ( The second calibration flag signal CAL_FLAG_OUT output by the first die DIE0 is set to a logic high level, and remains at a logic high level even after the first calibration signal CAL_DONE transitions to a low level again. Here, the inverting output of the flip-flop 214m of the first die DIE0 can be coupled to the first calibration flag signal CAL_FLAG. That is, the second calibration flag signal CAL_FLAG_OUT output by the first die DIE0 can set the first calibration flag signal CAL_FLAG from a logic low level to a logic high level. Therefore, the rising edge of the first calibration flag signal CAL_FLAG can indicate that the impedance calibration circuits of multiple dies have exited the impedance calibration state.
[0131] It should be noted that in the above embodiments, DIE0 is taken as the first die and DIE1 to DIEn as the second dies, but this disclosure is not limited to this. Since the impedance calibration circuit in the first die and the impedance calibration circuit in the second die have the same circuit structure, the selection signal generation circuit of any one of the dies from DIE0 to DIEn can be connected to the power supply terminal, and the selection signal generation circuit of the remaining dies can be connected to the ground terminal. That is, any one die can be used as the master die and the remaining dies as slave dies, achieving similar effects to the above embodiments. Therefore, the flexibility of memory devices including multiple dies in performing impedance calibration operations can be improved.
[0132] In this embodiment, the receiving circuit of the first die and the receiving circuit of the second die can receive a first selection signal and a second selection signal, respectively. The signal transmission path of the receiving circuit of the first die can be different from that of the receiving circuit of the second die. On one hand, the receiving circuit of the second die can generate a calibration start signal of the second die based on the first transition edge of the third enable signal output by the previous die, so that the second calibration operation of the second die can partially overlap with the first calibration operation of the previous die, thereby improving the efficiency of multiple dies performing impedance calibration operations and improving the response speed of the memory device. On the other hand, the receiving circuit of the first die can generate a first calibration end signal of the first die based on the second transition edge of the third enable signal output by the last second die, so that when the first calibration end signal of the first die is generated, the second calibration operation of the last second die has been completed, thereby enabling the first calibration end signal generated by the receiving circuit of the first die to accurately indicate the completion of the impedance calibration operation of multiple dies and improving the reliability of multiple dies performing impedance calibration operations.
[0133] Based on a concept similar to the memory devices described above, this disclosure also provides a memory system comprising: at least one memory device as described in any of the above embodiments; and a controller coupled to and configured to control the memory device.
[0134] In some embodiments, the controller is configured to generate an external calibration command; and the input / output circuitry in the memory device is configured to perform an impedance calibration operation in response to the external calibration command.
[0135] In some specific examples, refer to Figure 5 External calibration commands can be received and parsed by the second command generation circuit 222 to generate a second calibration command, and the memory device can perform impedance calibration operations through the second calibration mode.
[0136] Here, the composition and function of the memory system can be referred to in the foregoing embodiments. Figure 1 The description will not be repeated here.
[0137] Based on a concept similar to the memory device described above, this disclosure also provides a method for operating an input / output circuit. Figure 12 This is a flowchart illustrating the operation method of the input / output circuit provided in the embodiments of this disclosure, with reference to... Figure 12 The operation method of the input / output circuit includes the following steps:
[0138] Step S10: Generate calibration start signal;
[0139] Step S20: Generate a first enable signal based on the calibration start signal, and generate a second enable signal after generating the first enable signal;
[0140] Step S30: Output a third enable signal based on the second enable signal;
[0141] Step S40: Generate the first calibration end signal.
[0142] In some specific examples, the input / output circuit can be the input / output circuit in the memory device provided in any of the above embodiments. The input / output circuit may include pull-up drive circuits, pull-down drive circuits, and impedance calibration circuits of multiple dies.
[0143] In some embodiments, the operation method of the input / output circuit further includes: generating a second calibration end signal based on a second enable signal.
[0144] In some embodiments, the process of performing step S10 may include: generating a calibration enable signal based on a calibration command, a first selection signal, and a first calibration flag signal; and generating a calibration start signal for a first die based on the calibration enable signal in response to the first selection signal.
[0145] In some embodiments, the process of performing step S10 may further include: generating a calibration start signal for the second die based on a first transition edge of a third enable signal received by the receiving circuit of the second die in response to a second selection signal; the process of performing step S40 may include: generating a first calibration end signal based on a second transition edge of a third enable signal received by the receiving circuit of the first die in response to a first selection signal.
[0146] In some embodiments, the calibration command includes a first calibration command and a second calibration command; the operation method of the input / output circuit further includes: periodically generating the first calibration command; receiving and parsing an external calibration command to generate the second calibration command; outputting the first calibration command in a first calibration mode; and outputting the second calibration command in a second calibration mode.
[0147] In some embodiments, the operation method of the input / output circuit further includes: outputting a second calibration flag signal based on the calibration start signal and the first calibration end signal.
[0148] In some embodiments, the operation method of the input / output circuit further includes: in response to a first enable signal, performing a first calibration operation based on a reference resistor and obtaining a first calibration result; and in response to a second enable signal, performing a second calibration operation based on the first calibration result and obtaining a second calibration result.
[0149] In some embodiments, the operation method of the input / output circuit further includes: sending a first calibration result to one of the pull-up drive circuit and the pull-down drive circuit, and sending a second calibration result to the other of the pull-up drive circuit and the pull-down drive circuit.
[0150] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.
[0151] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.
[0152] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A memory device, characterized in that, The memory device includes a first die, the first die including an impedance calibration circuit; the impedance calibration circuit includes a receiving circuit, a transmitting circuit, and a calibration control circuit; wherein... The receiving circuit is coupled to the calibration control circuit and is configured to generate a calibration start signal; The calibration control circuit is configured to generate a first enable signal based on the calibration start signal, and generate a second enable signal after generating the first enable signal; The transmitting circuit is coupled to the calibration control circuit and is configured to output a third enable signal based on the second enable signal; The receiving circuit is also configured to generate a first calibration end signal.
2. The memory device according to claim 1, characterized in that, The receiving circuit includes a signal processing circuit, a first signal generation circuit, and a second signal generation circuit; the transmitting circuit includes a first output terminal and a second output terminal; wherein... The output terminals of the first signal generation circuit and the second signal generation circuit are both coupled to the calibration control circuit. The first input terminal of the first signal generation circuit is coupled to the output terminal of the signal processing circuit. The first input terminal of the second signal generation circuit is coupled to the first output terminal of the transmitting circuit.
3. The memory device according to claim 2, characterized in that, The transmitting circuit is specifically configured as follows: A second calibration end signal is generated based on the second enable signal, and the second calibration end signal is output from the first output terminal of the transmitting circuit; The third enable signal is generated based on the second enable signal, and the third enable signal is output from the second output terminal of the transmitting circuit.
4. The memory device according to claim 2, characterized in that, The memory device includes a plurality of dies, and any one of the plurality of dies includes one of the impedance calibration circuits; The die that receives the first selection signal through the die's receiving circuit is the first die; The second input terminal of the first signal generation circuit and the second input terminal of the second signal generation circuit of one of the plurality of dies are both coupled to the second output terminal of the transmitting circuit of another of the plurality of dies.
5. The memory device according to claim 4, characterized in that, The plurality of dies further includes a plurality of second dies; the plurality of second dies includes a second die coupled to the transmitting circuit of the first die and a second die coupled to the receiving circuit of the first die; the receiving circuit of the second die receives a second selection signal.
6. The memory device according to claim 4, characterized in that, The signal processing circuit of the first die is configured to generate a calibration enable signal based on the calibration command, the first selection signal, and the first calibration flag signal; The first signal generation circuit of the first die is configured to generate the calibration start signal of the first die based on the calibration enable signal in response to the first selection signal.
7. The memory device according to claim 5, characterized in that, The third enable signal includes a first transition edge and a second transition edge, wherein the first transition edge precedes the second transition edge; The first signal generation circuit of the second die is configured to generate the calibration start signal of the second die based on the first transition edge of the third enable signal received by the receiving circuit of the second die in response to the second selection signal. The second signal generation circuit of the first die is configured to generate the first calibration end signal of the first die based on the second transition edge of the third enable signal received by the receiving circuit of the first die in response to the first selection signal.
8. The memory device according to claim 4, characterized in that, The first signal generation circuit includes a first selection circuit and a first signal generator; the second signal generation circuit includes a second selection circuit and a second signal generator; wherein, The first input terminal of the first selection circuit is coupled to the output terminal of the signal processing circuit; the second input terminal of the first selection circuit is coupled to the second output terminal of the transmitting circuit of the other die. The input terminal of the first signal generator is coupled to the output terminal of the first selection circuit; the output terminal of the first signal generator is coupled to the calibration control circuit. The first input terminal of the second selection circuit is coupled to the first output terminal of the transmitting circuit; the second input terminal of the second selection circuit is coupled to the second output terminal of the transmitting circuit of the other die. The input terminal of the second signal generator is coupled to the output terminal of the second selection circuit; the output terminal of the second signal generator is coupled to the calibration control circuit.
9. The memory device according to claim 8, characterized in that, The control terminals of the first selection circuit and the second selection circuit of the first die both receive the first selection signal; the first selection signal instructs the first selection circuit to output the signal received at the first input terminal of the first selection circuit; the first selection signal instructs the second selection circuit to output the signal received at the second input terminal of the second selection circuit.
10. The memory device according to claim 6, characterized in that, The calibration command includes a first calibration command and a second calibration command; the impedance calibration circuit further includes a third selection circuit, a first command generation circuit, and a second command generation circuit; the output terminal of the first command generation circuit is coupled to the first input terminal of the third selection circuit; the output terminal of the second command generation circuit is coupled to the second input terminal of the third selection circuit. The output of the third selection circuit is coupled to one input of the signal processing circuit. The first command generation circuit is configured to periodically generate the first calibration command; The second command generation circuit is configured to: receive and parse an external calibration command, and generate the second calibration command; The third selection circuit is configured to output the first calibration command in the first calibration mode; In the second calibration mode, the second calibration command is output.
11. The memory device according to claim 1, characterized in that, The receiving circuit includes a trigger; a first input terminal of the trigger receives the calibration start signal; a second input terminal of the trigger receives the first calibration end signal; the trigger is configured to: A second calibration flag signal is output based on the calibration start signal and the first calibration end signal.
12. The memory device according to claim 1, characterized in that, The impedance calibration circuit further includes a calibration sub-circuit, which is coupled to the calibration control circuit and to a reference resistor; the calibration sub-circuit is configured to: In response to the first enable signal, a first calibration operation is performed based on the reference resistor, and a first calibration result is obtained; In response to the second enable signal, a second calibration operation is performed based on the first calibration result, and a second calibration result is obtained.
13. The memory device according to claim 12, characterized in that, The memory device includes an input / output circuit; the input / output circuit includes a pull-up drive circuit, a pull-down drive circuit, and the impedance calibration circuit of the first die; the calibration sub-circuit is further configured to: The first calibration result is sent to one of the pull-up drive circuit and the pull-down drive circuit, and the second calibration result is sent to the other of the pull-up drive circuit and the pull-down drive circuit.
14. A memory system, characterized in that, include: At least one memory device as claimed in any one of claims 1 to 13; A controller is coupled to at least one of the memory devices and configured to control the memory devices.
15. The memory system according to claim 14, characterized in that, The controller is configured to generate external calibration commands; The input / output circuitry in the memory device is configured to perform an impedance calibration operation in response to the external calibration command.
16. An operation method for an input / output circuit, characterized in that, include: Generate calibration start signal; A first enable signal is generated based on the calibration start signal, and a second enable signal is generated after the first enable signal is generated; A third enable signal is output based on the second enable signal; Generate the first calibration end signal.
17. The method of operating the input / output circuit according to claim 16, characterized in that, The operation method further includes: A second calibration end signal is generated based on the second enable signal.
18. The method of operating the input / output circuit according to claim 16, characterized in that, The generation of the calibration start signal includes: A calibration enable signal is generated based on the calibration command, the first selection signal, and the first calibration flag signal; In response to the first selection signal, the calibration start signal of the first die is generated based on the calibration enable signal.
19. The method of operating the input / output circuit according to claim 18, characterized in that, The generation of the calibration start signal also includes: In response to the second selection signal, the calibration start signal of the second die is generated based on the first transition edge of the third enable signal received by the receiving circuit of the second die; The generation of the first calibration end signal includes: In response to the first selection signal, the first calibration end signal is generated based on the second transition edge of the third enable signal received by the receiving circuit of the first die.
20. The method of operating the input / output circuit according to claim 18, characterized in that, The calibration command includes a first calibration command and a second calibration command; the operation method further includes: The first calibration command is generated periodically; Receive and parse external calibration commands, and generate the second calibration command; In the first calibration mode, the first calibration command is output; In the second calibration mode, the second calibration command is output.
21. The method of operating the input / output circuit according to claim 16, characterized in that, The operation method further includes: A second calibration flag signal is output based on the calibration start signal and the first calibration end signal.
22. The method of operating the input / output circuit according to claim 16, characterized in that, The operation method further includes: In response to the first enable signal, a first calibration operation is performed based on the reference resistor, and a first calibration result is obtained; In response to the second enable signal, a second calibration operation is performed based on the first calibration result, and a second calibration result is obtained.
23. The method of operating the input / output circuit according to claim 22, characterized in that, The operation method further includes: The first calibration result is sent to one of the pull-up drive circuit and the pull-down drive circuit, and the second calibration result is sent to the other of the pull-up drive circuit and the pull-down drive circuit.