A clock processing circuit and a memory

Abstract

The present disclosure provides a clock processing circuit and a memory, the clock processing circuit comprising a first half-phase interpolator, the first half-phase interpolator comprising: a first interpolation link, a first input end of the first interpolation link receiving a first initial clock, a second input end of the first interpolation link receiving a second initial clock, the first interpolation link being configured to perform interpolation processing on the first initial clock and the second initial clock, and output a first interpolated clock; a second interpolation link, a first input end of the second interpolation link receiving a third initial clock, a second input end of the second interpolation link receiving a fourth initial clock, the second interpolation link being configured to perform interpolation processing on the third initial clock and the fourth initial clock, and output a second interpolated clock; and a first cross sampling module, the first cross sampling module being connected with the first interpolation link and the second interpolation link, and being configured to output a first target clock and a second target clock in response to the first interpolated clock and the second interpolated clock.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a clock processing circuit and a memory. Background Technology

[0002] Taking Dynamic Random Access Memory (DRAM) as an example, a phase-locked loop (PLL), a delay-locked loop (DLL), and a voltage-mode phase interpolator (VMPI) are used to process the differential clock from the host, ultimately outputting a four-phase interpolated clock. However, the DLL has a complex circuit structure, large circuit area, and reliability risks. The VMPI suffers from clock input deviation and structural asymmetry. These factors all contribute to poor linearity of the final four-phase interpolated clock, thus affecting the performance stability of the memory. Summary of the Invention

[0003] This disclosure provides a clock processing circuit and a memory.

[0004] The technical solution of this disclosure embodiment is implemented as follows: In a first aspect, embodiments of this disclosure provide a clock processing circuit, the clock processing circuit including a first half-phase interpolator, the first half-phase interpolator comprising: A first interpolation link receives a first initial clock at its first input and a second initial clock at its second input, configured to interpolate the first and second initial clocks and output a first interpolated clock. A second interpolation link receives a third initial clock at its first input and a fourth initial clock at its second input, configured to interpolate the third and fourth initial clocks and output a second interpolated clock. The first, second, third, and fourth initial clocks are sequentially separated by a preset phase angle, and the target change edge of the first interpolated clock and the target change edge of the second interpolated clock are... The preset phase angle is twice the difference between the target change edges; the first cross-sampling module is connected to both the first interpolation link and the second interpolation link, and is configured to output a first target clock and a second target clock in response to the first interpolation clock and the second interpolation clock; wherein, the rising edge of the first target clock is generated in response to the target change edge of the first interpolation clock, the falling edge of the first target clock is generated in response to the target change edge of the second interpolation clock, the rising edge of the second target clock is generated in response to the target change edge of the second interpolation clock, and the falling edge of the second target clock is generated in response to the target change edge of the first interpolation clock.

[0005] In some embodiments, the clock processing circuit includes a second half-phase interpolator, the second half-phase interpolator comprising: a third interpolation link, wherein a first input terminal receives a second initial clock, and a second input terminal receives a first initial clock, configured to perform interpolation processing on the second initial clock and the first initial clock, and output a third interpolated clock; a fourth interpolation link, wherein a first input terminal receives a fourth initial clock, and a second input terminal receives a third initial clock, configured to perform interpolation processing on the fourth initial clock and the third initial clock, and output a fourth interpolated clock; wherein the target change edge of the third interpolated clock and the target change edge of the fourth interpolated clock differ from each other by a preset phase angle of twice; and a second cross-sampling module, which is connected to... The third interpolation link and the fourth interpolation link are both connected and configured to output a third target clock and a fourth target clock in response to the third interpolation clock and the fourth interpolation clock; wherein, the rising edge of the third target clock is generated in response to the target change edge of the third interpolation clock, the falling edge of the third target clock is generated in response to the target change edge of the fourth interpolation clock, the rising edge of the fourth target clock is generated in response to the target change edge of the fourth interpolation clock, and the falling edge of the fourth target clock is generated in response to the target change edge of the third interpolation clock; the target change edges of the first interpolation clock, the third interpolation clock, the second interpolation clock, and the fourth interpolation clock are sequentially differed by a preset phase angle.

[0006] In some embodiments, the first interpolation link, the second interpolation link, the third interpolation link, and the fourth interpolation link have the same structure, each including: a pulse generation module, configured to receive a first input clock transmitted via a first input terminal and a second input clock transmitted via a second input terminal, perform logical processing on the first input clock and the second input clock, and output a first pulse signal, a second pulse signal, and a reset signal; wherein the rising edge of the first pulse signal is aligned with the rising edge of the first input clock, and the falling edge of the first pulse signal is aligned with the falling edge of the second input clock; the second pulse signal has the same level state as the second input clock, and the reset signal has the opposite level state to the first pulse signal; an integral interpolation module, connected to the pulse generation module, configured to receive and perform integral interpolation processing based on the first pulse signal, the second pulse signal, and the reset signal, and output an interpolated clock; wherein the interpolated clock is one of the first interpolation clock, the second interpolation clock, the third interpolation clock, and the fourth interpolation clock.

[0007] In some embodiments, the pulse generation module includes: a pulse generator configured to perform logic processing on the first input clock and the second input clock, and output a first pulse logic signal, a second pulse logic signal, and a reset logic signal; and a signal shaping module connected to the pulse generator, configured to receive the first pulse logic signal, the second pulse logic signal, and the reset logic signal; perform pulse normalization processing on the first pulse logic signal, the second pulse logic signal, and the reset logic signal, and output the first pulse signal, the second pulse signal, and the reset signal.

[0008] In some embodiments, the clock processing circuit further includes a phase-splitting circuit; the phase-splitting circuit is configured to receive a differential clock pair, perform phase-splitting processing on the differential clock pair, and output a first initial clock, a second initial clock, a third initial clock, and a fourth initial clock; the signal shaping module is specifically configured to sample the first pulse logic signal using the differential clock pair and output the first pulse signal; sample the second pulse logic signal using the differential clock pair and output the second pulse signal; and sample the reset logic signal using the differential clock pair and output the reset signal.

[0009] In some embodiments, the integral interpolation module includes: a first integral module, including a first variable capacitor, configured to receive the first pulse signal, the second pulse signal, and the reset signal, and to discharge the first variable capacitor when the reset signal is in a second state; a second integral module, including a second variable capacitor, configured to receive the first pulse signal, the second pulse signal, and the reset signal, and to discharge the second variable capacitor in response to the first pulse signal and the second pulse signal when the reset signal is in the second state, wherein the discharge rate of the first variable capacitor is greater than the discharge rate of the second variable capacitor; wherein, when the reset signal is in a first state, the first variable capacitor is charged at least via a first power supply voltage. The second variable capacitor is charged at least via a second power supply voltage; the first power supply voltage is greater than the second power supply voltage, so that the charging voltage of the first variable capacitor is higher than the charging voltage of the second variable capacitor; a differential comparator, the input terminal of which is coupled to the first variable capacitor, and the complementary input terminal of which is coupled to the second variable capacitor, the differential comparator is used to amplify the voltage difference between the input terminal and the complementary input terminal, and output an intermediate signal; a self-reset module, connected to the differential comparator, is configured to receive the reset signal and the intermediate signal; when the reset signal is in a second state, the intermediate signal is output as the interpolation clock; when the reset signal is in a first state, the interpolation clock is set to a high level.

[0010] In some embodiments, the first integration module includes a first transistor, a second transistor, a first current generating circuit, a second current generating circuit, and a digital-to-analog converter (DAC). The control terminal of the first transistor receives the inverted signal of the reset signal; the first terminal of the first transistor receives a third power supply voltage; the second terminal of the first transistor is connected to the first terminal of the first current generating circuit; the second terminal of the first current generating circuit is connected to the DAC and a bias current source. The control terminal of the first current generating circuit receives the first pulse signal. The control terminal of the second transistor receives a self-limiting control signal; the first terminal of the second transistor receives the third power supply voltage; the second terminal of the second transistor is connected to the first terminal of the second current generating circuit; the second terminal of the second current generating circuit is connected to the DAC and the bias current source. The control terminal of the second current generating circuit receives the second pulse signal. The second terminals of both the first transistor and the second transistor are connected to the first variable capacitor. The rising edge of the self-limiting control signal is generated in response to the rising edge of the reset signal, and the falling edge of the self-limiting control signal is generated in response to the target change edge of the interpolation clock.

[0011] In some embodiments, the second integration module includes a third transistor, a fourth transistor, a third current generating circuit, and a fourth current generating circuit; the control terminal of the third transistor receives the inverted signal of the reset signal, the first terminal of the third transistor receives a third power supply voltage, the second terminal of the third transistor is connected to the first terminal of the third current generating circuit, the control terminal of the third current generating circuit receives the first pulse signal, and the second terminal of the third current generating circuit is connected to a bias current source; the control terminal of the fourth transistor receives a self-limiting control signal, the first terminal of the fourth transistor receives the third power supply voltage, the second terminal of the fourth transistor is connected to the first terminal of the fourth current generating circuit, the control terminal of the fourth current generating circuit receives the second pulse signal, and the second terminal of the fourth current generating circuit is connected to the bias current source; the second terminals of both the third transistor and the fourth transistor are connected to the second variable capacitor.

[0012] In some embodiments, the integral interpolation module further includes a self-limiting module. The self-limiting module is configured to receive and respond to the reset signal and the inverted signal of the interpolation clock, and output a self-limiting control signal. The self-limiting module includes a fifth transistor, a sixth transistor, a first NOT gate, a first tri-state inverter, and a first NAND gate. The control terminal of the fifth transistor receives the inverted signal of the reset signal, the first terminal of the fifth transistor receives a fourth power supply voltage, the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor, the second terminal of the sixth transistor is connected to a reference ground, and the control terminal of the sixth transistor receives the inverted signal of the interpolation clock. The second terminal of the fifth transistor is also connected to the first input terminal of the first NAND gate via the first NOT gate, the second input terminal of the first NAND gate receives the inverted signal of the reset signal, the output terminal of the first NAND gate is connected to the control terminal of the first tri-state inverter, the output terminal of the first NOT gate is connected to its own input terminal via the first tri-state inverter, and the second terminal of the fifth transistor outputs the self-limiting control signal.

[0013] In some embodiments, the self-reset module includes a second tri-state inverter, a second NOT gate, and a seventh transistor; the input of the second tri-state inverter is connected to the output of the differential comparator, the control terminal of the second tri-state inverter receives the inverted signal of the reset signal, the output of the second tri-state inverter is connected to the input of the second NOT gate, the second NOT gate is used to output the interpolated clock; the input of the second NOT gate is also connected to a reference ground via the seventh transistor, and the control terminal of the seventh transistor receives the reset signal.

[0014] In some embodiments, the first integration module further includes a third capacitor, and the second integration module further includes a fourth capacitor; the first variable capacitor is connected to the input of the differential comparator via the third capacitor; and the second variable capacitor is connected to the complementary input of the differential comparator via the fourth capacitor.

[0015] In some embodiments, the first integration module further includes a first transmission gate, and the second integration module further includes a second transmission gate; the first variable capacitor is connected to a first terminal of the third capacitor, the input terminal of the first transmission gate receives the first power supply voltage, the control terminal of the first transmission gate receives the reset signal, and the input terminal of the differential comparator is connected to a second terminal of the third capacitor and to the output terminal of the first transmission gate; the second variable capacitor is connected to a first terminal of the fourth capacitor, the input terminal of the second transmission gate receives the second power supply voltage, the control terminal of the second transmission gate receives the reset signal, and the complementary input terminal of the differential comparator is connected to a second terminal of the fourth capacitor and to the output terminal of the second transmission gate.

[0016] In some embodiments, the first half-phase interpolator further includes a first duty cycle calibration module, configured to receive and perform duty cycle calibration processing on the first target clock and the second target clock, and output a first sampling clock and a third sampling clock; the second half-phase interpolator further includes a second duty cycle calibration module, configured to receive and perform duty cycle calibration processing on the third target clock and the fourth target clock, and output a second sampling clock and a fourth sampling clock; the duty cycles of the first sampling clock, the third sampling clock, the second sampling clock, and the fourth sampling clock are all 50%, and their phases are sequentially separated by a preset phase angle.

[0017] Secondly, embodiments of this disclosure provide a memory that includes the clock processing circuit described in the first aspect.

[0018] This disclosure provides a clock processing circuit and memory that reconstructs the overall architecture of clock processing from a system perspective. By adjusting the clock signal through an interpolation link, it eliminates the need for a delay phase-locked loop, reducing circuit area occupation and routing deviations, and improving the linearity of the final output interpolated clock. Attached Figure Description

[0019] Figure 1 A schematic diagram of the structure of a storage system; Figure 2 This is a schematic diagram of another storage system provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the structure of the first half-phase interpolator provided in the embodiments of this disclosure; Figure 4 This is a schematic diagram of the signal of the first half-phase interpolator provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the overall architecture of the clock processing circuit provided in the embodiments of this disclosure; Figure 6 This is a detailed structural schematic diagram of the first half-phase interpolator provided in the embodiments of this disclosure; Figure 7 This is a schematic diagram of the internal signals of the first half-phase interpolator provided in an embodiment of this disclosure; Figure 8 This is a schematic diagram of the structure of the integral interpolation module provided in the embodiments of this disclosure; Figure 9 This is a detailed structural schematic diagram of the integral interpolation module provided in the embodiments of this disclosure; Figure 10 This is a schematic diagram of the structure of the first duty cycle adjustment module provided in an embodiment of this disclosure. Detailed Implementation

[0020] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0022] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0023] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0024] Embodiments are described and illustrated in the accompanying drawings by functional blocks, circuits, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based fabrication techniques or other manufacturing techniques. Where functional blocks, circuits, units, and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuit systems) for performing other functions. Furthermore, without departing from the scope of the technical concept of this disclosure, each functional block, circuit, unit and / or module of the embodiments may be physically divided into two or more interactive and separate functional blocks, circuits, units and / or modules of the embodiments, and each functional block, circuit, unit and / or module may be physically combined into more complex functional blocks, circuits, units and / or modules.

[0025] First, the nouns and terms used in the embodiments of this disclosure will be explained: Dynamic Random Access Memory (DRAM); Synchronous Dynamic Random Access Memory (SDRAM); Double Data Rate SDRAM (DDR); Low-power DDR (LPDDR); Fifth generation DDR (DDR5).

[0026] Please see Figure 1 It shows a schematic diagram of the structure of a storage system. For example... Figure 1 As shown, the storage system may include a memory controller 100 and a memory 200, with the memory controller 100 controlling the memory 200 to operate. For example, the memory controller 100 may control the memory 200 according to requests from a processor supporting various applications, such as server applications, personal computer applications, and mobile applications. The memory controller 100 may be set up independently of the processor core or integrated with the processor core on the same chip (i.e., a system-on-a-chip, SoC).

[0027] Specifically, the memory controller 100 instructs the memory 200 to perform actions by sending a command address signal CA and a chip select signal CS to the memory 200. At the same time, the memory controller 100 and the memory 200 exchange data through the data signal DQ. The above are only some examples of signals and not all of them.

[0028] like Figure 1 As shown, the memory includes a phase-locked loop (PLL), a delay-locked loop (DLL) 210, and an 8-phase interpolator 220, which is essentially a voltage-mode phase interpolator.

[0029] The phase-locked loop (PLL) is configured to output differential clock pairs CK_t / c. The delay phase-locked loop 210 is configured to receive and process the differential clock pair CK_t / c by phase splitting, delaying, duty cycle adjustment, and locking, and output eight locking clocks with different phases: CK_0°, CK_45°, CK_90°, CK_135°, CK_180°, CK_225°, and CK_270°. The phases of these eight locking clocks differ by 45° sequentially (within the allowable error range).

[0030] An 8-phase interpolator 220 is configured to receive and interpolate eight locked clocks CK_0°~CK_270°, outputting four output clocks with different phases: CK_0+X°, CK_90+X°, CK_180+X°, and CK_270+X°. The phases of these four output clocks differ by 90° sequentially (within an acceptable error range). Exemplarily, these four output clocks, after subsequent processing, are ultimately used to sample the data signal DQ; in other examples, these four output clocks may also have other functions.

[0031] However, on the one hand, the circuit structure of the 8-phase interpolator 220 is complex and poses a risk to its oscillation reliability; on the other hand, the delay phase-locked loop 210 needs to output an accurate eight-phase locked clock to the 8-phase interpolator 220, but due to layout and routing limitations, timing deviations (skew) between the phase clocks are unavoidable; furthermore, the asymmetry in the physical layout of the 8-phase interpolator 220 will cause the final output interpolated clock to still have phase errors. These problems will affect the linearity of the output of the 8-phase interpolator 220.

[0032] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0033] In one embodiment of this disclosure, please refer to Figure 2 This illustrates a schematic diagram of another storage system provided in an embodiment of this disclosure. Figure 2 As shown, the storage system includes a memory controller 100 and a memory 300. The interaction method between the memory controller 100 and the memory 300 is the same as that between the memory controller 100 and the memory 200 described above, and will not be repeated here.

[0034] like Figure 2 As shown, the memory 300 includes a phase-locked loop (PLL) and a clock processing circuit 310, which includes a phase splitting circuit 31 and a 4-phase interpolator 32.

[0035] The phase-locked loop (PLL) is configured to output differential clock pairs CK_t / c. Phase splitting circuit 31 is configured to receive differential clock pairs CK_c / CK_t, perform phase splitting processing on the differential clock pairs CK_c / CK_t, and output a first initial clock CKI, a second initial clock CKQ, a third initial clock CKIB, and a fourth initial clock CKQB.

[0036] The 4-phase interpolator 32 is configured to receive and interpolate the first initial clock CKI, the second initial clock CKQ, the third initial clock CKIB and the fourth initial clock CKQB, and output the first sampling clock CKTA0°, the second sampling clock CKTA180°, the third sampling clock CKTA90° and the fourth sampling clock CKTA270°.

[0037] Here, the differential clock pair includes a first clock CK_c and a second clock CK_t. The first clock CK_c and the second clock CK_t have the same frequency (within the allowable error range) and opposite levels (i.e., 180° phase difference). The first initial clock CKI, the second initial clock CKQ, the third initial clock CKIB, and the fourth initial clock CKQB have the same frequency (within the allowable error range), and the frequency of the first initial clock CKI is half the frequency of the first clock CK_c (within the allowable error range).

[0038] All subsequent numerical comparisons in this disclosure are within the allowable error range and will not be elaborated further.

[0039] Thus, the clock processing circuit 310 provided in this embodiment of the present disclosure does not require a delay phase-locked loop structure, which significantly reduces the circuit area and eliminates reliability risks such as failure to start oscillation; the 4-phase interpolator 32 only needs to interpolate the 4-phase clock and does not involve the 8-phase clock, which can reduce the skew between the input clocks caused by transmission from different lines and ultimately improve the linearity of the sampling clock.

[0040] In some embodiments, the 4-phase interpolator 32 includes a first half-phase interpolator 321. For example... Figure 3 As shown, the first half-phase interpolator 321 includes: The first interpolation link 3211 has a first input terminal receiving a first initial clock CKI and a second input terminal receiving a second initial clock CKQ. It is configured to perform interpolation processing on the first initial clock CKI and the second initial clock CKQ and output the first interpolation clock CKo_0°. The second interpolation link 3212 has a first input terminal receiving a third initial clock CKIB and a second input terminal receiving a fourth initial clock CKQB. It is configured to perform interpolation processing on the third initial clock CKIB and the fourth initial clock CKQB and output a second interpolation clock CKo_180°. The first cross-sampling module 3213 is connected to both the first interpolation link 3211 and the second interpolation link 3212, and is configured to output the first target clock CKout_0° and the second target clock CKout_180° in response to the first interpolation clock CKo_0° and the second interpolation clock CKo_180°.

[0041] It should be noted that, please refer to Figure 4 This illustrates a signal diagram of the clock processing circuit 310 provided in this embodiment of the disclosure. Figure 4As shown, the first initial clock CKI, the second initial clock CKQ, the third initial clock CKIB, and the fourth initial clock CKQB are sequentially separated by a preset phase angle (90° is shown as an example). The target change edge of the first interpolated clock CKo_0° and the target change edge of the second interpolated clock CKo_180° are separated by twice the preset phase angle.

[0042] For example, the preset phase angle can be the following values: 45°, 90°, 135°... The embodiments disclosed herein will be described with a preset phase angle of 90°. In this case, the first initial clock CKI, the second initial clock CKQ, the third initial clock CKIB, and the fourth initial clock CKQB are sequentially 90° apart, and the first interpolated clock CKo_0° and the second interpolated clock CKo_180° are 180° apart.

[0043] In some embodiments, see Figure 4 The target change edges are all falling edges. However, this does not constitute a relevant restriction.

[0044] In other embodiments, the target change edge can be a rising edge.

[0045] In some other embodiments, the target change edge of different clocks may be different.

[0046] In some embodiments, see Figure 4 The rising edge of the first target clock CKout_0° is generated in response to the target change edge of the first interpolation clock CKo_0°, the falling edge of the first target clock CKout_0° is generated in response to the target change edge of the second interpolation clock CKo_180°, the rising edge of the second target clock CKout_180° is generated in response to the target change edge of the second interpolation clock CKo_180°, and the falling edge of the second target clock CKout_180° is generated in response to the target change edge of the first interpolation clock CKo_0°. This embodiment of the present disclosure is described in detail below using this as an example, but this does not constitute a limitation.

[0047] In other embodiments, it can also be designed such that: the falling edge of the first target clock CKout_0° is generated in response to the target change edge of the first interpolation clock CKo_0°, the rising edge of the first target clock CKout_0° is generated in response to the target change edge of the second interpolation clock CKo_180°, the falling edge of the second target clock CKout_180° is generated in response to the target change edge of the second interpolation clock CKo_180°, and the rising edge of the second target clock CKout_180° is generated in response to the target change edge of the second interpolation clock CKo_180°.

[0048] It should be noted that the first cross-sampling module 3213 can be implemented using a common SR latch structure (also known as a reset / set trigger), which has a set terminal, a reset terminal, an output terminal, and an inverting output terminal. (1) The set terminal receives one of the first interpolation clock CKo_0° and the second interpolation clock CKo_180°; (2) The reset terminal (Reset) receives the other of the first interpolation clock CKo_0° and the second interpolation clock CKo_180°; (3) The output terminal outputs one of the first target clock CKout_0° and the second target clock CKout_180°; (4) The inverting output terminal outputs the other of the first target clock CKout_0° and the second target clock CKout_180°.

[0049] The first cross-sampling module 3213 can be formed by cross-coupling of two NOR gates or two NAND gates, and the choice can be made according to the actual application scenario.

[0050] In some embodiments, see Figure 5 The 4-phase interpolator 32 further includes a second half-phase interpolator 322, which includes: The third interpolation link 3221 has a first input terminal receiving a second initial clock CKQ and a second input terminal receiving a first initial clock CKI. It is configured to perform interpolation processing on the second initial clock CKQ and the first initial clock CKI, and output a third interpolation clock CKo_90°. The fourth interpolation link 3222 has a first input terminal receiving the fourth initial clock CKQB and a second input terminal receiving the third initial clock CKIB. It is configured to perform interpolation processing on the fourth initial clock CKQB and the third initial clock CKIB, and output the fourth interpolated clock CKo_270°. The second cross-sampling module 3223 is connected to both the third interpolation link 3221 and the fourth interpolation link 3222, and is configured to output the third target clock CKout_90° and the fourth target clock CKout_270° in response to the third interpolation clock CKo_90° and the fourth interpolation clock CKo_270°.

[0051] It should be noted that the target change edges of the third interpolation clock CKo_90° and the fourth interpolation clock CKo_270° differ by a preset phase angle of 2 (e.g., 180°); the target rising edges of the first interpolation clock CKo_0°, the third interpolation clock CKo_90°, the second interpolation clock CKo_180°, and the fourth interpolation clock CKo_270° differ by a preset phase angle (e.g., 90°) in sequence.

[0052] It should be noted that the rising edge of the third target clock CKout_90° is generated in response to the target change edge of the third interpolation clock CKo_90°, the falling edge of the third target clock CKout_90° is generated in response to the target change edge of the fourth interpolation clock CKo_270°, the rising edge of the fourth target clock CKout_270° is generated in response to the target change edge of the fourth interpolation clock CKo_270°, and the falling edge of the fourth target clock CKout_270° is generated in response to the target change edge of the third interpolation clock CKo_90°.

[0053] The phases of the first target clock CKout_0°, the third target clock CKout_90°, the second target clock CKout_180°, and the fourth target clock CKout_270° are successively separated by a preset phase angle (for example, 90°).

[0054] It should be noted that the second cross-sampling module 3223 can be implemented using a common SR latch structure, such as forming it by cross-coupling of two NOR gates or two NAND gates, which can be selected according to the actual application scenario.

[0055] It should be understood that the second half-phase interpolator 322 and the first half-phase interpolator 321 have the same structure, differing only in the waveform of the input clock. Therefore, all modifications to the first half-phase interpolator 321 can be applied to the second half-phase interpolator 322.

[0056] Please see Figure 6 This illustrates a schematic diagram of the structure of the first half-phase interpolator 321 provided in this embodiment of the disclosure. Figure 6 As shown, the first half-phase interpolator 321 also includes a first sampling module 327, a first data selector 325, and a second data selector 326, with the following functions: The first sampling module 327 is configured to perform pulse normalization processing on the first initial clock CKI, the second initial clock CKQ, the third initial clock CKIB, and the fourth initial clock CKQB, and then output them one by one. Specifically, differential clocks CK_c / CK_t can be used to sample the first initial clock CKI, the second initial clock CKQ, the third initial clock CKIB, and the fourth initial clock CKQB respectively.

[0057] The input terminal of the first data selector 325 is connected to the output terminal of the first sampling module 327, and the first output terminal and the second output terminal of the first data selector 325 are connected one-to-one with the first input terminal and the second input terminal of the first interpolation link 3211. The first data selector 325 is configured to receive a first initial clock CKI, a second initial clock CKQ, a third initial clock CKIB, and a fourth initial clock CKQB, transmit the first initial clock CKI to the first input terminal of the first interpolation link 3211, and transmit the second initial clock CKQ to the second input terminal of the first interpolation link 3211.

[0058] The input terminal of the second data selector 326 is connected to the output terminal of the first sampling module 327, and the first output terminal / second output terminal of the second data selector 326 is connected one-to-one with the first input terminal / second input terminal of the second interpolation link 3212. The second data selector 326 is configured to receive a first initial clock CKI, a second initial clock CKQ, a third initial clock CKIB, and a fourth initial clock CKQB, transmit the third initial clock CKIB to the first input terminal of the second interpolation link 3212, and transmit the fourth initial clock CKQB to the second input terminal of the second interpolation link 3212.

[0059] In one example, the first sampling module 327 can be implemented using multiple D-type flip-flops. The clock terminal of the D-type flip-flop receives the aforementioned differential clock pair CK_c / CK_t, and the input terminal of the D-type flip-flop receives a first initial clock CKI (or a second initial clock CKQ, or a third initial clock CKIB, or a fourth initial clock CKQB). The output terminal of the D-type flip-flop is connected to the corresponding input terminals of the first data selector 325 and the second data selector 326.

[0060] In another example, the first sampling module 327 may also utilize other devices with waveform regularization, including but not limited to: SR latches, logic devices, transistors and other basic circuit elements.

[0061] Similarly, the second half-phase interpolator 322 also includes a second sampling module, a third data selector, and a fourth data selector.

[0062] The second sampling module is configured to perform pulse normalization processing on the first initial clock CKI, the second initial clock CKQ, the third initial clock CKIB, and the fourth initial clock CKQB. The input of the third data selector is connected to the output of the second sampling module, and the first and second outputs of the third data selector are connected one-to-one with the third interpolation link 3221 (see reference). Figure 5The first input terminal of the third interpolation link 3221 is connected to the second input terminal. The third data selector is configured to receive the first initial clock CKI, the second initial clock CKQ, the third initial clock CKIB, and the fourth initial clock CKQB, transmit the second initial clock CKQ to the first input terminal of the third interpolation link 3221, and transmit the first initial clock CKI to the second input terminal of the third interpolation link 3221.

[0063] The input of the fourth data selector is connected to the output of the second sampling module, and the first and second outputs of the fourth data selector are connected one-to-one with the fourth interpolation link 3222 (see reference). Figure 5 The first input terminal / second input terminal of the fourth data selector is connected. The fourth data selector is configured to receive the first initial clock CKI, the second initial clock CKQ, the third initial clock CKIB and the fourth initial clock CKQB, transmit the fourth initial clock CKQB to the first input terminal of the fourth interpolation link 3222, and transmit the third initial clock CKIB to the second input terminal of the second interpolation link 3212.

[0064] In this embodiment of the disclosure, the first interpolation link 3211, the second interpolation link 3212, the third interpolation link 3221 and the fourth interpolation link 3222 have the same structure, and any one of them will be referred to as an interpolation link below.

[0065] Please refer to Figure 6 The first interpolation link 3211 or the second interpolation link 3212 in the process, any interpolation link includes: The pulse generation module 40 is configured to receive a first input clock CKIn1 transmitted via a first input terminal and a second input clock CKIn2 transmitted via a second input terminal, perform logical processing on the first input clock CKIn1 and the second input clock CKIn2, and output a first pulse signal A, a second pulse signal B and a reset signal Rst. The integral interpolation module 50 is connected to the pulse generation module 40 and is configured to receive and perform integral interpolation processing based on the first pulse signal A, the second pulse signal B and the reset signal Rst, and output the interpolation clock CKo.

[0066] Unless otherwise specified, the interpolation clock CKo can indicate any one of the first interpolation clock CKo_0°, the second interpolation clock CKo_180°, the third interpolation clock CKo_90°, and the fourth interpolation clock CKo_270°. Specifically, the output of the integral interpolation module 50 in the first interpolation link 3211 is the first interpolation clock CKo_0°; the output of the integral interpolation module 50 in the second interpolation link 3212 is the second interpolation clock CKo_180°; the output of the integral interpolation module 50 in the third interpolation link 3221 is the third interpolation clock CKo_90°; and the output of the integral interpolation module 50 in the second interpolation link 3212 is the fourth interpolation clock CKo_270°.

[0067] It should be noted that, please refer to Figure 7 This illustrates a signal timing diagram of an interpolation link provided in an embodiment of this disclosure. For example... Figure 7 As shown, the second input clock CKIn2 lags behind the first input clock CKIn1 by a preset phase angle (e.g., 90°). The rising edge of the first pulse signal A is aligned with the rising edge of the first input clock CKIn1, and the falling edge of the first pulse signal A is aligned with the falling edge of the second input clock CKIn2. The second pulse signal B has the same level as the second input clock CKIn2, and the reset signal Rst has the opposite level to the first pulse signal A.

[0068] for Figure 7 Without considering the distortion of the first input clock CKIn1 and the second input clock CKIn2: (1) The duty cycle of the first pulse signal A is 75%, its rising edge is aligned with the rising edge of the first input clock CKIn1, and its falling edge is aligned with the rising edge of the second input clock CKIn2. (2) The duty cycle of the second pulse signal B is 50%, its rising edge is aligned with the rising edge of the second input clock CKIn2, and its falling edge is aligned with the falling edge of the second input clock CKIn2. (3) The duty cycle of the reset signal Rst is 25%, its falling edge is aligned with the rising edge of the first input clock CKIn1, and its rising edge is aligned with the rising edge of the second input clock CKIn2.

[0069] In one specific embodiment, please refer to Figure 6 The pulse generation module 40 includes: The pulse generator 41 is configured to perform logic processing on the first input clock CKIn1 and the second input clock CKIn2, and output a first pulse logic signal A0, a second pulse logic signal B0 and a reset logic signal Rst0. The signal shaping module 42 is connected to the pulse generator 41 and is configured to receive the first pulse logic signal A0, the second pulse logic signal B0 and the reset logic signal Rst0; perform pulse normalization processing on the first pulse logic signal A0, the second pulse logic signal B0 and the reset logic signal Rst0, and output the first pulse signal A, the second pulse signal B and the reset signal Rst.

[0070] For example, pulse generator 41 may include OR gates, NOT gates and AND gates.

[0071] The OR logic gate is configured to perform an OR operation on the first input clock CKIn1 and the second input clock CKIn2, and output the first pulse logic signal A0. The driver is configured to perform delay matching on the second input clock CKIn2 (matching the delay of the above OR logic gate / the following NOR NOT logic gate) and output the second pulse logic signal B0; The NOR gate is configured to perform an NOR operation on the first input clock CKIn1 and the second input clock CKIn2, and output a reset logic signal Rst0.

[0072] Due to the diversity of circuit devices, the same function can be achieved by combining different circuit devices (e.g., AND gate, OR gate, NOT gate, XNOR gate, XOR gate, data selector, enable transmission gate, etc.). Therefore, the circuit device composition of pulse generator 41 is only an exemplary structure and does not constitute a limitation of this disclosure.

[0073] In some embodiments, the signal shaping module 42 can also be formed using multiple D-type flip-flops, with its clock terminal receiving a differential clock pair CK_c / CK_t, its input terminal receiving a first pulse logic signal A0 (or a second pulse logic signal B0, or a reset logic signal Rst0), and outputting a first pulse signal A (or a second pulse signal B, or a reset signal Rst).

[0074] Specifically, the signal shaping module 42 is configured to sample the first pulse logic signal A0 of CK_c / CK_t using a differential clock and output the first pulse signal A; sample the second pulse logic signal B0 of CK_c / CK_t using a differential clock and output the second pulse signal B; and sample the reset logic signal Rst0 of CK_c / CK_t using a differential clock and output the reset signal Rst.

[0075] In this way, since the differential clock pair CK_c / CK_t has a higher frequency, it is used to resample the logic signal output by the pulse generator 41, so that the rising and falling edges of the generated first pulse signal A, second pulse signal B, and reset signal Rst are relatively neat and in the desired position, which facilitates subsequent interpolation processing.

[0076] In some embodiments, see Figure 8 The integral interpolation module 50 includes: The first integration module 51 includes a first variable capacitor 511, configured to receive a first pulse signal A, a second pulse signal B and a reset signal Rst, and discharge the first variable capacitor 511 in response to the first pulse signal A and the second pulse signal B when the reset signal Rst is in a second state (e.g., low level 0). The second integration module 52 includes a second variable capacitor 521, configured to receive a first pulse signal A, a second pulse signal B, and a reset signal Rst. When the reset signal Rst is in a second state (e.g., low level 0), the second variable capacitor 521 is discharged in response to the first pulse signal A and the second pulse signal B, and the discharge rate of the first variable capacitor 511 is greater than the discharge rate of the second variable capacitor 521. When the reset signal Rst is in a first state (e.g., high level 1), the first variable capacitor 511 is charged at least via a first power supply voltage V1, and the second variable capacitor 521 is charged at least via a second power supply voltage V2. The first power supply voltage V1 is greater than the second power supply voltage V2, so that the charging voltage of the first variable capacitor 511 is higher than the charging voltage of the second variable capacitor 521, that is, the charging rate of the first variable capacitor 511 is also higher than the charging rate of the second variable capacitor 521.

[0077] Differential comparator 53, the input terminal of differential comparator 53 is coupled to the first variable capacitor 511, and the complementary input terminal of differential comparator 53 is coupled to the second variable capacitor 521. Differential comparator 53 is used to amplify the voltage difference between the input terminal and the complementary input terminal and output an intermediate signal. The self-reset module 54 is connected to the differential comparator 53 and is configured to receive a reset signal Rst and an intermediate signal; when the reset signal Rst is in the second state (e.g., low level 0), the intermediate signal is output as an interpolation clock CKo; when the reset signal Rst is in the first state (e.g., high level 1), the interpolation clock CKo is set to a high level.

[0078] Overall, the working principle of the integral interpolation module 50 is as follows: (1) When the reset signal Rst is in the first state (e.g., high level 1), both the first variable capacitor 511 and the second variable capacitor 521 are charged; since the charging voltage of the first variable capacitor 511 is higher, the first variable capacitor 511 is precharged to a higher first charge value, and the second variable capacitor 521 is precharged to a lower second charge value; at the same time, the output of the differential comparator 53 is isolated from the interpolation clock CKo, and under the control of the self-reset module 54, the interpolation clock CKo is set to a high level. (2) After the reset signal Rst changes to the second state (e.g., low level 0), the output of the differential comparator 53 and the interpolation clock Cko change to the on state; for a period of time at the beginning, since the first variable capacitor 511 has a higher charge, it can provide a higher voltage, so the input voltage of the differential comparator 53 is greater than the complementary input voltage, and the output is high level. Therefore, the interpolation clock CKo continues to remain at the high level. (3) After a period of time when the reset signal Rst is in the second state (e.g., low level 0), since the discharge rate of the first variable capacitor 511 is greater than that of the second variable capacitor 521, the voltage provided by the first variable capacitor 511 will gradually become less than that provided by the second variable capacitor 521, causing the intermediate signal to jump to low level 0, thus... Figure 7 When the interpolated clock Cko in the middle changes to a low level, a target change edge is generated.

[0079] In some embodiments, see Figure 9 The first integration module 51 includes a first transistor 512, a second transistor 513, a first current generating circuit 514, a second current generating circuit 515, and a digital-to-analog converter 518 (also known as a Currentsteering DAC). The control terminal of the first transistor 512 receives the inverted reset signal RstN; the first terminal of the first transistor 512 receives the third power supply voltage V3; the second terminal of the first transistor 512 is connected to the first terminal of the first current generating circuit 514; the second terminal of the first current generating circuit 514 is connected to the digital-to-analog converter 518 and the bias current source; the control terminal of the first current generating circuit 514 receives the first pulse signal A. The first terminal of the second transistor 513 receives the third power supply voltage V3, and the second terminal of the second transistor 513 is connected to the first terminal of the second current generating circuit 515. The second terminal of the second current generating circuit 515 is connected to the digital-to-analog converter 518 and the bias current source. The control terminal of the second current generating circuit 515 receives the second pulse signal B. The second terminals of the first transistor 512 and the second transistor 513 are both connected to the first variable capacitor 511, and the other terminal of the first variable capacitor 511 is connected to the reference ground.

[0080] It should be noted that both the first current generating circuit 514 and the second current generating circuit 515 can use a current steering network, and their specific operating parameters can be designed independently.

[0081] When both the first transistor 512 and the second transistor 513 are off, in response to the high-level first pulse signal A, the first current generating circuit 514 is turned on, and the first variable capacitor 511 is discharged through the first current generating circuit 514; in response to the high-level second pulse signal B, the second current generating circuit 515 is turned on, and the first variable capacitor 511 is discharged through the second current generating circuit 515.

[0082] The following explanation uses the first transistor 512 and the second transistor 513 as examples of P-type doping, but this does not constitute a limitation.

[0083] Thus, when both the first transistor 512 and the second transistor 513 are closed, the third power supply voltage V3 will also charge the first variable capacitor 511 based on the aforementioned first power supply voltage V1; and the third power supply voltage V3 will charge the second variable capacitor 521 based on the aforementioned second power supply voltage V2.

[0084] In one example, the second transistor 513 can be omitted, and both the second current generating circuit 515 and the first current generating circuit 514 are connected to the third power supply voltage V3 via the first transistor 512. In this way, when the reset signal Rst is high (RstN=0), the first transistor 512 and the second transistor 513 will close, and the third power supply voltage V3 will start charging the first variable capacitor 511, thus simplifying the circuit structure.

[0085] In another example, see Figure 9 The control terminal of the second transistor 513 receives the self-limiting control signal CKN2. Please refer to [link / reference needed]. Figure 7 The rising edge of the self-limiting control signal CKN2 is generated in response to the rising edge of the reset signal Rst, and the falling edge of the self-limiting control signal CKN2 is generated in response to the target change edge of the interpolation clock CKo. Thus, when the reset signal Rst is high (RstN=0), the first transistor 512 will close to charge the first variable capacitor 511; when the self-limiting control signal CKN2 is low (0), the second transistor 513 will close to charge the first variable capacitor 511, thereby accelerating the charging speed.

[0086] Thus, at the interpolation clock CKo, the target change is generated along ( Figure 7 After the falling edge, it means that the interpolation result has been achieved, and the self-limiting control signal CKN2 can be used to start the charging process of the third power supply voltage V3 to the first variable capacitor 511, ensuring that the first variable capacitor 511 has enough time to precharge.

[0087] In some embodiments, see Figure 9The second integration module 52 includes a third transistor 522, a fourth transistor 523, a third current generating circuit 524, and a fourth current generating circuit 525. The control terminal of the third transistor 522 receives the inverted signal RstN of the reset signal, the first terminal of the third transistor 522 receives the third power supply voltage V3, the second terminal of the third transistor 522 is connected to the first terminal of the third current generating circuit 524, the control terminal of the third current generating circuit 524 receives the first pulse signal A, and the second terminal of the third current generating circuit 524 is connected to the bias current source. The first terminal of the fourth transistor 523 receives the third power supply voltage V3, the second terminal of the fourth transistor 523 is connected to the first terminal of the fourth current generating circuit 525, the control terminal of the fourth current generating circuit 525 receives the second pulse signal B, and the second terminal of the fourth current generating circuit 525 is connected to the bias current source. The second terminals of the third transistor 522 and the fourth transistor 523 are both connected to the second variable capacitor 521, and the other terminal of the second variable capacitor 521 is grounded.

[0088] In the example above, both the third transistor 522 and the fourth transistor 523 can be (but are not limited to) P-type doping.

[0089] It should be noted that the working principle of the second integration module 52 is similar to that of the first integration module 51. When both the third transistor 522 and the fourth transistor 523 are off, in response to the high-level first pulse signal A, the third current generating circuit 524 is turned on, and the second variable capacitor 521 is discharged through the third current generating circuit 524; in response to the high-level second pulse signal B, the fourth current generating circuit 525 is turned on, and the second variable capacitor 521 is discharged through the fourth current generating circuit 525.

[0090] like Figure 9 As shown, since all current generating circuits are connected to the same bias current source, but the current generating circuit in the first integration module 51 is also connected to the digital-to-analog converter 518, the discharge speed of the first variable capacitor 511 is faster than that of the second variable capacitor 521.

[0091] In one example, the fourth transistor 523 may be omitted, and the fourth current generating circuit 525 may be connected to the third power supply voltage V3 via the third transistor 522.

[0092] In another example, see Figure 9 The control terminal of the fourth transistor 523 receives the self-limiting control signal CKN2.

[0093] In some embodiments, the first transistor 512, the second transistor 513, the third transistor 522, and the fourth transistor 523 are all connected to the same power supply voltage, which is the third power supply voltage V3.

[0094] In some other embodiments, the power supply voltages connected to the first transistor 512 and the second transistor 513 may be different, but the power supply voltages connected to the first transistor 512 and the third transistor 522 are the same, and the power supply voltages connected to the second transistor 513 and the fourth transistor 523 are the same.

[0095] In some embodiments, see Figure 9 The integral interpolation module 50 also includes a self-limiting module 55; the self-limiting module 55 is configured to receive and respond to the reset signal Rst and the feedback clock (which generates the interpolation clock CKo after being inverted, and can therefore be regarded as the inverted signal of the interpolation clock CKo), and output a self-limiting control signal CKN2.

[0096] like Figure 9 As shown, the self-limiting module 55 includes a fifth transistor 551, a sixth transistor 552, a first NOT gate 553, a first tri-state inverter 554, and a first NAND gate 555; The control terminal of the fifth transistor 551 receives the inverted signal RstN of the reset signal. The first terminal of the fifth transistor 551 receives the fourth power supply voltage V4. The second terminal of the fifth transistor 551 is connected to the first terminal of the sixth transistor 552. The second terminal of the sixth transistor 552 is connected to the reference ground (providing the ground voltage 0). The control terminal of the sixth transistor 552 (via an even number of inverters) receives the feedback clock. The second terminal of the fifth transistor 551 is also connected to the first input terminal of the first NAND gate 555 via the first NOT gate 553. The second input terminal of the first NAND gate 555 receives the inverted signal RstN of the reset signal. The output terminal of the first NAND gate 555 is connected to the control terminal of the first tri-state inverter 554 (which is active low). The output terminal of the first NOT gate 553 is connected to its own input terminal via the first tri-state inverter 554. The second terminal of the fifth transistor 551 outputs a self-limiting control signal CKN2.

[0097] Please combine Figure 7 The fifth transistor, 551, is P-type doped, and the sixth transistor, 552, is N-type doped. The self-limiting control signal CKN2 changes as follows: (1) When the reset signal Rst changes to the first state (high level 1), the feedback clock is set to low level 0, and then the sixth transistor 552 is turned off and the fifth transistor 551 is turned on, and the self-limiting control signal CKN2 is in the first state (high level 1). (2) When the reset signal Rst just changes to the second state (low level 0) and the interpolation clock CKo is in the first state (high level 1), the sixth transistor 552 and the fifth transistor 551 are both turned off, the first tri-state inverter 554 is turned on, and the first tri-state inverter 554 and the first NOT gate 553 together form a level hold, and the self-limiting control signal CKN2 is held in the first state (high level 1). (3) When the reset signal Rst changes to the second state (low level 0) and the interpolation clock CKo changes to the second state (low level 0), the sixth transistor 552 is turned on and the fifth transistor 551 is turned off, and the self-limiting control signal CKN2 is in the second state (low level 1).

[0098] In some embodiments, see Figure 9 The self-reset module 54 includes a second tri-state inverter 541, a second NOT gate 542, and a seventh transistor 543; The input of the second tri-state inverter 541 is connected to the output of the differential comparator 53. The control terminal of the second tri-state inverter 541 (which is active high) receives the inverted signal RstN of the reset signal. The output of the second tri-state inverter 541 is connected to the input of the second NOT gate 542. The second NOT gate 542 is used to output the interpolated clock CKo. The input of the second NOT gate 542 is also connected to the reference ground via the seventh transistor 543, and the control terminal of the seventh transistor 543 receives the reset signal Rst.

[0099] It should be noted that when the reset signal Rst is high (RstN=0), the second tri-state inverter 541 will isolate the input and output terminals; when the reset signal Rst is low (RstN=1), the second tri-state inverter 541 will invert the input signal and output it.

[0100] Here, the seventh transistor 543 is N-type doped. When the reset signal Rst is high (1), the input of the second NOT gate 542 (i.e., the feedback clock) is set low (0), thereby setting the interpolation clock CKo high (1).

[0101] In some embodiments, see Figure 9 The first integration module 51 also includes a third capacitor 516, and the second integration module 52 also includes a fourth capacitor 526. The first variable capacitor 511 is connected to the input terminal of the differential comparator 53 via the third capacitor 516, and the voltage values ​​on both sides of the first variable capacitor 511 can be regarded as the same, thereby realizing level shifting. The second variable capacitor 521 is connected to the complementary input terminal of the differential comparator 53 via the fourth capacitor 526, and the voltage values ​​on both sides of the first variable capacitor 511 can be regarded as the same, thereby realizing level shifting.

[0102] In some embodiments, the first integration module 51 further includes a first transmission gate 517, and the second integration module 52 further includes a second transmission gate 527; The first variable capacitor 511 is connected to the first end of the third capacitor 516, the input end of the first transmission gate 517 receives the first power supply voltage V1, the control end of the first transmission gate 517 receives the reset signal Rst, and the input end of the differential comparator 53 is connected to the second end of the third capacitor 516 and to the output end of the first transmission gate 517. The second variable capacitor 521 is connected to the first terminal of the fourth capacitor 526. The input terminal of the second transmission gate 527 receives the second power supply voltage V2. The control terminal of the second transmission gate 527 receives the reset signal Rst. The complementary input terminal of the differential comparator 53 is connected to the second terminal of the fourth capacitor 526 and to the output terminal of the second transmission gate 527.

[0103] Thus, when the reset signal Rst is high (RstN=0), the first transmission gate 517 and the second transmission gate 527 are turned on, and the first power supply voltage V1 and the second power supply voltage V2 charge the first variable capacitor 511 and the second variable capacitor 521 in a one-to-one correspondence, causing them to have different charging speeds; conversely, when the reset signal Rst is low (RstN=1), the first transmission gate 517 and the second transmission gate 527 isolate their respective input and output terminals.

[0104] In some embodiments, see Figure 9 The differential comparator 53 includes an eighth transistor 531, a ninth transistor 532, a tenth transistor 533, an eleventh transistor 534, and a twelfth transistor 535.

[0105] The first terminal of the eighth transistor 531 and the first terminal of the tenth transistor 533 both receive a power supply voltage (e.g., the fifth power supply voltage V5). The control terminal and the second terminal of the eighth transistor 531, the first terminal of the ninth transistor 532, and the control terminal of the tenth transistor 533 are connected together. The second terminal of the tenth transistor 533 and the first terminal of the eleventh transistor 534 are connected together. The second terminal of the ninth transistor 532 and the second terminal of the eleventh transistor 534 form a connection point, and this connection point is connected to the reference ground via the twelfth transistor 535. The control terminal of the twelfth transistor 535 receives the bias voltage Vbias.

[0106] The control terminal of the ninth transistor 532 serves as the input terminal of the differential inverter 53, the control terminal of the eleventh transistor 534 serves as the inverting input terminal of the differential inverter 53, and the first terminal of the eleventh transistor 534 serves as the output terminal of the differential inverter 53.

[0107] Here, the eighth transistor 531 and the tenth transistor 533 are both P-type doped, while the second terminal of the ninth transistor 532, the eleventh transistor 534, and the twelfth transistor 535 are all N-type doped.

[0108] The above does not constitute any limitation. The differential comparator 53 can adopt any structure with amplification and comparison functions.

[0109] In some embodiments, see Figure 6 The first half-phase interpolator 321 also includes a first duty cycle calibration module 324, which is configured to receive and perform duty cycle calibration on the first target clock CKout_0° and the second target clock CKout_180°, and output the first sampling clock CKTA0° and the second sampling clock CKTA180°. Similarly, the second half-phase interpolator 322 also includes a second duty cycle calibration module, configured to receive and perform duty cycle calibration processing on the third target clock CKout_90° and the fourth target clock CKout_270°, and output the third sampling clock CKTA90° and the fourth sampling clock CKTA270° (see reference). Figure 2 ).

[0110] It should be noted that the first target clock CKout_0° and the first sampling clock CKTA0° are in phase (e.g., their rising edges are aligned, and the falling edges are shifted to adjust the duty cycle; or, their falling edges are aligned, and the rising edges are shifted to adjust the duty cycle). Similarly, the second sampling clock CKTA180° and the second target clock CKout_180° are in phase, the third sampling clock CKTA90° and the third target clock CKout_90° are in phase, and the fourth sampling clock CKTA270° and the fourth target clock CKout_270° are in phase.

[0111] It should be noted that the first duty cycle calibration module 324 and the second duty cycle calibration module have the same structure, and any device capable of adjusting the duty cycle can be used.

[0112] Please see Figure 10 This illustrates a schematic diagram of the structure of the first duty cycle calibration module 324 provided in an embodiment of this disclosure. Figure 10 As shown, the first duty cycle calibration module 324 includes a first repetition unit, which includes a third NOT gate 601, a fourth NOT gate 602, a fifth NOT gate 603, a sixth NOT gate 604, a thirteenth transistor 605, a fourteenth transistor 606, a fifteenth transistor 607, a sixteenth transistor 608, a ninth NOT gate 609, and a tenth NOT gate 610. The first target clock CKout_0° is transmitted sequentially through the third NOT gate 601 and the fourth NOT gate 602 to the control terminal of the thirteenth transistor 605. The output signal of the third NOT gate 601 is also transmitted to the control terminal of the fifteenth transistor 607. The second target clock CKout_180° is transmitted sequentially through the fifth NOT gate 603 and the sixth NOT gate 604 to the control terminal of the fourteenth transistor 606. The output signal of the fifth NOT gate 603 is also transmitted to the control terminal of the sixteenth transistor 608. The sixth power supply voltage V6, the thirteenth transistor 605, the fourteenth transistor 606, and the reference ground are connected in sequence; the sixth power supply voltage V6, the fifteenth transistor 607, the sixteenth transistor 608, and the reference ground are connected in sequence. The connection point between the thirteenth transistor 605 and the fourteenth transistor 606 is coupled to the connection point between the fifteenth transistor 607 and the sixteenth transistor 608 as an output node; this output node outputs the first sampling clock CKTA0° through the ninth NOT gate 609 and the tenth NOT gate 610 in sequence.

[0113] In one example, the second sampling clock CKTA180° can be generated by inverting the first sampling clock CKTA0°.

[0114] In another example, the first duty cycle calibration module 324 also includes a second repetition unit. The second repetition unit has the same structure as the first repetition unit, but the third NOT gate 601 in the second repetition unit receives the second target clock CKout_180°, the fifth NOT gate 603 in the second repetition unit receives the first target clock CKout_0°, and the second repetition unit outputs the second sampling clock CKTA180°.

[0115] Due to the diversity of circuit devices, the same function can be achieved by combining different circuit devices (such as AND gate, OR gate, NOT gate, XNOR gate, XOR gate, data selector, enable transmission gate, etc.). Therefore, the aforementioned circuit device composition is only an exemplary structure and does not constitute any undisclosed limitation.

[0116] The doping types of transistors described above are merely examples and do not constitute any limitation. For N-type doped transistors, the enable state of the control signal is high ("1") to control the transistor in a closed state, and low ("0") to control the transistor in a closed state. For P-type doped transistors, the enable state of the control signal is low ("0") to control the transistor in a closed state, and high ("1") to control the transistor in a closed state. In logic-matched transistors, the doping type of any transistor can be adjusted.

[0117] In summary, the present disclosure provides a current integral phase interpolator technical solution, the basic operating principle of which is based on the processing of a four-phase initial clock generated by frequency reduction: first, the initial clock of four phases is generated by frequency division through the phase splitting circuit 31, and then the four-phase interpolated clock is finally generated by passing through two half-phase interpolators respectively.

[0118] For details, please see Figure 6 After entering the Half Phase Interpolator, the first pulse signal A, the second pulse signal B, and the reset signal Rst are generated by quadrant selection. The signal shaping module (e.g., bidirectional edge flip-flop DET DFF) is used to synchronously eliminate the influence of layout dependency. Then, after entering the core integral interpolation module, the signal with accurate interpolation on the falling edge is output. Finally, the signal enters the cross-sampling module (SR flip-flop) and the duty cycle correction module (DCC) for duty cycle correction, and finally outputs two inverted signals with a duty cycle of 50%.

[0119] Please see Figure 9 Upon entering the Integrating Interpolator module, the first pulse signal A triggers the digital-to-analog converter to generate an additional discharge current I1, and the second pulse signal B triggers the digital-to-analog transcoder to generate an additional current I2. Combined with the bias current source, a waveform is generated on the variable capacitor. This waveform is detected by the differential comparator when it crosses a threshold, and the output delayed interpolation time CKo is output. Key enhancements to the current integrating phase interpolator include using a replica integrator to offset the effects of static current (the main structures of the first and second integrating modules are mirror images of each other), level shifting to ensure the comparator common-mode level (third capacitor 516 and fourth capacitor 526), ​​and a self-reset mechanism to optimize the reset time.

[0120] Thus, the integration module, mirror structure, differential structure, and comparator significantly improve the interpolation linearity, resulting in substantial improvements in the rising and falling edges of the final sampling clock across various scenarios. Due to the presence of the cross-sampling module and duty cycle adjustment module, the output signal duty cycle approaches 50%. Furthermore, since this phase interpolator structure only requires four-phase input, the delay-locked loop 210 in the channel can be omitted (see reference). Figure 1 This avoids the risk of oscillation failure caused by the complex circuitry of a delay-locked loop (PLL). Furthermore, only two signals need to enter the phase-splitting circuit, avoiding the skew problem caused by the eight-phase output of a delay-locked loop. This significantly improves the nonlinearity risk of the phase interpolation circuit, thereby optimizing the data sampling window and reducing timing errors. Simultaneously, eliminating the need for a dedicated delay-locked loop significantly reduces implementation complexity.

[0121] In yet another embodiment of this disclosure, a memory is provided that may include the aforementioned clock processing circuitry 310.

[0122] In this application, the term 'memory' refers to any physical device or module used for storing data, including but not limited to: memory chips, memory dies, multi-chip packages, ball grid array (BGA) packaged memory, single in-line memory modules, dual in-line memory modules, small outline dual in-line memory modules, micro dual in-line memory modules, registered memory, low-load memory, high-bandwidth memory, solid-state drives, embedded multimedia cards, general-purpose flash memory, memory cards, and on-board packaged or integrated memory cells. In another embodiment of this disclosure, an electronic device is provided, which includes the aforementioned memory. This electronic device may be a user equipment (UE), mobile device, handheld device, computing device, in-vehicle device, wearable device, etc. Examples include: personal computers (PCs), mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), enterprise digital assistants (EDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc., server computers, data centers, workstations, mobile phones, smartphones, and tablets.

[0123] The above description is merely an example embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or circuit embodiments provided in this disclosure can be arbitrarily combined to obtain new method or circuit embodiments without conflict. The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A clock processing circuit, characterized in that, The clock processing circuit includes a first half-phase interpolator, which comprises: The first interpolation link has a first input terminal receiving a first initial clock and a second input terminal receiving a second initial clock. It is configured to perform interpolation processing on the first initial clock and the second initial clock, and output the first interpolated clock. The second interpolation link receives a third initial clock at its first input terminal and a fourth initial clock at its second input terminal. It is configured to perform interpolation processing on the third initial clock and the fourth initial clock to output a second interpolated clock. The first initial clock, the second initial clock, the third initial clock, and the fourth initial clock are sequentially separated by a preset phase angle. The target change edge of the first interpolated clock and the target change edge of the second interpolated clock differ by twice the preset phase angle. The first cross-sampling module is connected to both the first interpolation link and the second interpolation link, and is configured to output a first target clock and a second target clock in response to the first interpolation clock and the second interpolation clock; wherein the rising edge of the first target clock is generated in response to the target change edge of the first interpolation clock, the falling edge of the first target clock is generated in response to the target change edge of the second interpolation clock, the rising edge of the second target clock is generated in response to the target change edge of the second interpolation clock, and the falling edge of the second target clock is generated in response to the target change edge of the first interpolation clock.

2. The clock processing circuit according to claim 1, characterized in that, The clock processing circuit includes a second half-phase interpolator, which comprises: The third interpolation link has a first input terminal receiving a second initial clock and a second input terminal receiving a first initial clock. It is configured to perform interpolation processing on the second initial clock and the first initial clock, and output a third interpolation clock. The fourth interpolation link receives a fourth initial clock at its first input terminal and a third initial clock at its second input terminal. It is configured to perform interpolation processing on the fourth initial clock and the third initial clock, and output a fourth interpolated clock. The target change edge of the third interpolated clock and the target change edge of the fourth interpolated clock differ from each other by a preset phase angle equal to twice the target phase angle. The second cross-sampling module, connected to both the third and fourth interpolation links, is configured to output a third target clock and a fourth target clock in response to the third and fourth interpolation clocks; wherein the rising edge of the third target clock is generated in response to the target change edge of the third interpolation clock, the falling edge of the third target clock is generated in response to the target change edge of the fourth interpolation clock, the rising edge of the fourth target clock is generated in response to the target change edge of the fourth interpolation clock, and the falling edge of the fourth target clock is generated in response to the target change edge of the third interpolation clock. The target change edges of the first interpolation clock, the third interpolation clock, the second interpolation clock, and the fourth interpolation clock are sequentially differed by a preset phase angle.

3. The clock processing circuit according to claim 2, characterized in that, The first interpolation link, the second interpolation link, the third interpolation link, and the fourth interpolation link have the same structure, each including: A pulse generation module is configured to receive a first input clock transmitted via a first input terminal and a second input clock transmitted via a second input terminal, perform logical processing on the first input clock and the second input clock, and output a first pulse signal, a second pulse signal, and a reset signal; wherein the rising edge of the first pulse signal is aligned with the rising edge of the first input clock, and the falling edge of the first pulse signal is aligned with the falling edge of the second input clock; the second pulse signal has the same level state as the second input clock, and the reset signal has the opposite level state to the first pulse signal; An integral interpolation module, connected to the pulse generation module, is configured to receive and perform integral interpolation processing based on the first pulse signal, the second pulse signal, and the reset signal, and output an interpolation clock; wherein the interpolation clock is one of the first interpolation clock, the second interpolation clock, the third interpolation clock, and the fourth interpolation clock.

4. The clock processing circuit according to claim 3, characterized in that, The pulse generation module includes: A pulse generator is configured to perform logical processing on the first input clock and the second input clock, and output a first pulse logic signal, a second pulse logic signal and a reset logic signal; The signal shaping module is connected to the pulse generator and is configured to receive the first pulse logic signal, the second pulse logic signal and the reset logic signal; perform pulse normalization processing on the first pulse logic signal, the second pulse logic signal and the reset logic signal, and output the first pulse signal, the second pulse signal and the reset signal.

5. The clock processing circuit according to claim 4, characterized in that, The clock processing circuit also includes a phase splitting circuit; The phase-splitting circuit is configured to receive differential clock pairs, perform phase-splitting processing on the differential clock pairs, and output the first initial clock, the second initial clock, the third initial clock, and the fourth initial clock. The signal shaping module is specifically configured to use the differential clock to sample the first pulse logic signal and output the first pulse signal; The second pulse logic signal is sampled using the differential clock, and the second pulse signal is output. The reset logic signal is sampled using the differential clock, and the reset signal is output.

6. The clock processing circuit according to claim 3, characterized in that, The integral interpolation module includes: The first integration module includes a first variable capacitor, configured to receive the first pulse signal, the second pulse signal and the reset signal, and to discharge the first variable capacitor when the reset signal is in a second state; The second integration module includes a second variable capacitor and is configured to receive the first pulse signal, the second pulse signal, and the reset signal. When the reset signal is in a second state, the module discharges the second variable capacitor in response to the first pulse signal and the second pulse signal, and the discharge rate of the first variable capacitor is greater than the discharge rate of the second variable capacitor. When the reset signal is in a first state, the first variable capacitor is charged at least via a first power supply voltage, and the second variable capacitor is charged at least via a second power supply voltage. The first power supply voltage is greater than the second power supply voltage, so that the charging voltage of the first variable capacitor is higher than the charging voltage of the second variable capacitor. A differential comparator, wherein the input terminal of the differential comparator is coupled to the first variable capacitor, and the complementary input terminal of the differential comparator is coupled to the second variable capacitor, and the differential comparator is used to amplify the voltage difference between the input terminal and the complementary input terminal and output an intermediate signal; The self-reset module is connected to the differential comparator and configured to receive the reset signal and the intermediate signal; when the reset signal is in the second state, it outputs the intermediate signal as the interpolation clock; when the reset signal is in the first state, it sets the interpolation clock to a high level.

7. The clock processing circuit according to claim 6, characterized in that, The first integration module includes a first transistor, a second transistor, a first current generating circuit, a second current generating circuit, and a digital-to-analog converter; The control terminal of the first transistor receives the inverted signal of the reset signal; the first terminal of the first transistor receives the third power supply voltage; the second terminal of the first transistor is connected to the first terminal of the first current generating circuit; the second terminal of the first current generating circuit is connected to the digital-to-analog converter and the bias current source; the control terminal of the first current generating circuit receives the first pulse signal. The control terminal of the second transistor receives a self-limiting control signal, the first terminal of the second transistor receives a third power supply voltage, the second terminal of the second transistor is connected to the first terminal of the second current generating circuit, and the second terminal of the second current generating circuit is connected to the digital-to-analog converter and the bias current source. The control terminal of the second current generating circuit receives the second pulse signal; The second terminals of both the first transistor and the second transistor are connected to the first variable capacitor; the rising edge of the self-limiting control signal is generated in response to the rising edge of the reset signal, and the falling edge of the self-limiting control signal is generated in response to the target change edge of the interpolation clock.

8. The clock processing circuit according to claim 6, characterized in that, The second integration module includes a third transistor, a fourth transistor, a third current generating circuit, and a fourth current generating circuit; The control terminal of the third transistor receives the inverted signal of the reset signal, the first terminal of the third transistor receives the third power supply voltage, the second terminal of the third transistor is connected to the first terminal of the third current generating circuit, the control terminal of the third current generating circuit receives the first pulse signal, and the second terminal of the third current generating circuit is connected to the bias current source. The control terminal of the fourth transistor receives a self-limiting control signal, the first terminal of the fourth transistor receives a third power supply voltage, the second terminal of the fourth transistor is connected to the first terminal of the fourth current generating circuit, the control terminal of the fourth current generating circuit receives the second pulse signal, and the second terminal of the fourth current generating circuit is connected to the bias current source. The second terminals of both the third transistor and the fourth transistor are connected to the second variable capacitor.

9. The clock processing circuit according to claim 6, characterized in that, The integral interpolation module also includes a self-limiting module. The self-limiting module is configured to receive and respond to the reset signal and the inverted signal of the interpolation clock, and output a self-limiting control signal. The self-limiting module includes a fifth transistor, a sixth transistor, a first NOT gate, a first tri-state inverter, and a first NAND gate; The control terminal of the fifth transistor receives the inverted signal of the reset signal, the first terminal of the fifth transistor receives the fourth power supply voltage, the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor, the second terminal of the sixth transistor is connected to the reference ground, and the control terminal of the sixth transistor receives the inverted signal of the interpolation clock. The second terminal of the fifth transistor is also connected to the first input terminal of the first NAND gate via the first NOT gate. The second input terminal of the first NAND gate receives the inverted signal of the reset signal. The output terminal of the first NAND gate is connected to the control terminal of the first tri-state inverter. The output terminal of the first NOT gate is connected to its own input terminal via the first tri-state inverter. The self-limiting control signal is output from the second terminal of the fifth transistor.

10. The clock processing circuit according to claim 6, characterized in that, The self-reset module includes a second tri-state inverter, a second NOT gate, and a seventh transistor; The input terminal of the second tri-state inverter is connected to the output terminal of the differential comparator. The control terminal of the second tri-state inverter receives the inverted signal of the reset signal. The output terminal of the second tri-state inverter is connected to the input terminal of the second NOT gate. The second NOT gate is used to output the interpolated clock. The input of the second NOT gate is also connected to a reference ground via the seventh transistor, and the control terminal of the seventh transistor receives the reset signal.

11. The clock processing circuit according to claim 6, characterized in that, The first integration module further includes a third capacitor, and the second integration module further includes a fourth capacitor; The first variable capacitor is connected to the input of the differential comparator via the third capacitor; The second variable capacitor is connected to the complementary input of the differential comparator via the fourth capacitor.

12. The clock processing circuit according to claim 11, characterized in that, The first integration module further includes a first transmission gate, and the second integration module further includes a second transmission gate; The first variable capacitor is connected to the first terminal of the third capacitor, the input terminal of the first transmission gate receives the first power supply voltage, the control terminal of the first transmission gate receives the reset signal, and the input terminal of the differential comparator is connected to the second terminal of the third capacitor and to the output terminal of the first transmission gate. The second variable capacitor is connected to the first terminal of the fourth capacitor, the input terminal of the second transmission gate receives the second power supply voltage, the control terminal of the second transmission gate receives the reset signal, and the complementary input terminal of the differential comparator is connected to the second terminal of the fourth capacitor and to the output terminal of the second transmission gate.

13. The clock processing circuit according to claim 2, characterized in that, The first half-phase interpolator further includes a first duty cycle calibration module, which is configured to receive and perform duty cycle calibration processing on the first target clock and the second target clock, and output a first sampling clock and a third sampling clock. The second half-phase interpolator further includes a second duty cycle calibration module, which is configured to receive and perform duty cycle calibration processing on the third target clock and the fourth target clock, and output a second sampling clock and a fourth sampling clock. The duty cycle of the first sampling clock, the third sampling clock, the second sampling clock, and the fourth sampling clock is 50%, and their phases are successively separated by a preset phase angle.

14. A memory, characterized in that, Includes the clock processing circuit as described in any one of claims 1-13.

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