Memory device performing refresh operation and operating method thereof

Abstract

The present application relates to a memory device performing a refresh operation and an operating method thereof. A memory device includes a refresh control circuit configured to generate an internal refresh signal based on a self-refresh interval signal; a lock control circuit configured to generate the self-refresh interval signal according to a self-refresh entry command and a self-refresh exit command, and to generate a lock enable signal according to the self-refresh interval signal and the internal refresh signal; and a clock generation circuit configured to generate an internal clock by delaying and fixing an external clock in response to the lock enable signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0014324, filed on February 5, 2025, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure relate to semiconductor design technology, and more particularly to a memory device that performs a self-refresh operation. Background Technology

[0004] Storage devices, such as dynamic random access memory (DRAM), may include arrays of memory cells for storing data. Each memory cell constituting the array may include a cell transistor acting as a switch and a cell capacitor for storing data. To prevent the data stored in the cell capacitor from being lost, a refresh operation is required to recharge the data in the memory cell. Refresh operations are divided into automatic refresh operations and self-refresh operations. Automatic refresh operations are performed whenever a refresh command is issued from the memory controller to the storage device, while self-refresh operations are performed by the storage device itself, with the memory controller only setting the refresh cycle.

[0005] Since the storage device processes data synchronously with an external clock, an internal clock can be generated by delaying the external clock by a specific period using a delay phase-locked loop (DLL) circuit. Internal operations such as reading or writing can then be performed based on this internal clock. Because the storage device is not controlled by the internal clock during the self-refresh operation, the DLL circuit is disabled when the self-refresh operation begins, and its locking operation is re-executed when the self-refresh operation ends. Therefore, techniques for adjusting the startup timing of the DLL circuit's locking operation are needed. Summary of the Invention

[0006] Embodiments of this disclosure relate to a storage device and a method of operating the same, the storage device being able to adjust the startup timing of a DLL circuit locking operation when exiting a self-refresh mode.

[0007] According to one embodiment of the present disclosure, a storage device includes: a refresh control circuit configured to generate an internal refresh signal based on a self-refresh interval signal; a lock control circuit configured to generate a self-refresh interval signal based on a self-refresh enter command and a self-refresh exit command, and to generate a lock start signal based on the self-refresh interval signal and the internal refresh signal; and a clock generation circuit configured to generate an internal clock by delaying and fixing an external clock in response to the lock start signal.

[0008] According to one embodiment of this disclosure, a storage device includes: a refresh control circuit configured to generate an internal refresh signal based on a self-refresh interval signal; a lock control circuit configured to generate a self-refresh interval signal based on a self-refresh enter command and a self-refresh exit command, generate a first extended interval signal and a second extended interval signal based on the self-refresh interval signal, and generate a lock start signal based on running speed information by selecting one of the first extended interval signal and the second extended interval signal, wherein the first extended interval signal has a variable activation period based on the internal refresh signal, and the second extended interval signal has a preset activation period; and a clock generation circuit configured to generate an internal clock by delaying and fixing an external clock in response to the lock start signal.

[0009] According to one embodiment of this disclosure, a method for operating a storage device includes: generating at least one speed signal having a logic level based on operating speed information; generating a self-refresh interval signal activated by a self-refresh enter command and deactivated by a self-refresh exit command; generating an internal refresh signal during an activation period of the self-refresh interval signal; generating a first extended interval signal and a second extended interval signal, the first extended interval signal having a variable activation period based on the internal refresh signal, and the second extended interval signal having a preset activation period; generating a lock-on start signal by selecting one of the first extended interval signal and the second extended interval signal based on the speed signal; and generating an internal clock by delaying and fixing an external clock in response to the lock-on start signal.

[0010] According to one embodiment of this disclosure, the storage device can suppress peak current generation and prevent lock operation failure by adjusting the start timing of the DLL circuit lock operation so that it does not overlap with the self-refresh operation that occurs just before exiting the self-refresh mode.

[0011] Furthermore, according to embodiments of this disclosure, the storage device can minimize the overlap with the self-refresh operation by adjusting the startup timing of the locking operation according to the operating speed, thereby ensuring both high-speed operation stability and low-speed operation efficiency. Attached Figure Description

[0012] Figure 1 It is a timing diagram used to describe the locking operation of a DLL circuit when exiting self-refresh mode.

[0013] Figure 2 This is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0014] Figure 3 It is shown Figure 2 Detailed configuration diagram of the memory core.

[0015] Figure 4A and Figure 4B It is used to describe according to Figure 2 Timing diagram of the memory refresh signal generated by the first mode signal and the second mode signal.

[0016] Figure 5 It is shown Figure 2 Detailed configuration diagram of the self-refresh control circuit.

[0017] Figure 6 It is shown Figure 5 Detailed circuit diagram of the first signal generator.

[0018] Figure 7 It is shown Figure 5 Detailed circuit diagram of the second signal generator.

[0019] Figure 8A and Figure 8B It is used to describe Figure 5 Timing diagram of the operation of the self-refresh control circuit.

[0020] Figure 9 It is shown Figure 2 Detailed configuration diagram of the start-up control circuit.

[0021] Figure 10 This is a block diagram illustrating a storage device according to another embodiment of the present disclosure.

[0022] Figure 11 It is shown Figure 10 Detailed circuit diagram of the start-up control circuit.

[0023] Figure 12 It is used to describe Figure 11 A table showing the operation of the start-up control circuit.

[0024] Figure 13A and 13B It is used to describe Figure 10 Timing diagram of the operation of the storage device.

[0025] Figure 14 This is a block diagram illustrating a storage system according to an embodiment of the present disclosure. Detailed Implementation

[0026] Various embodiments of this disclosure will be described in detail with reference to the accompanying drawings. However, the embodiments of this disclosure may be implemented in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make this disclosure more detailed and complete, and to fully convey the scope of protection of this disclosure to those skilled in the art. Throughout all the drawings and embodiments of this disclosure, the same reference numerals always refer to the same parts.

[0027] It should be understood that when an element is identified as "coupled" or "connected" to another element, it may mean that the two are directly coupled or that they are electrically connected to each other by another circuit between them. It should also be understood that the terms "comprising," "including," "having," etc., as used in this specification, indicate the presence of stated features, quantities, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, and / or combinations thereof. In this disclosure, unless the context clearly indicates otherwise, the singular form also includes the plural form.

[0028] Figure 1 It is a timing diagram used to describe the locking operation of a DLL circuit when exiting self-refresh mode.

[0029] like Figure 1 As shown, the storage device can receive a self-refresh enter command (SRE) and a self-refresh exit command (SRX) from an external device (e.g., a memory controller) synchronized with an external clock (CK), and generate a self-refresh interval signal (SRED), the activation period of which is defined by these commands. The storage device can generate a predetermined number of internal refresh signals during the activation period of the self-refresh interval signal (SREF), and perform a self-refresh operation in response to these internal refresh signals, sequentially refreshing multiple rows.

[0030] According to specifications (e.g., JEDEC specifications for timing parameters of Double Data Rate (DDR) or Low Power DDR (LPDDR) type DRAM), a memory device can receive a valid command after a predetermined time (hereinafter referred to as "tXS_DLL") elapsed from the input of the self-refresh exit command SRX. The valid command can be used to indicate operation synchronized with an external clock CK. Therefore, the memory device can control a delay phase-locked loop (DLL) circuit such that the locking operation is completed within the predetermined time tXS_DLL. For example, in response to the self-refresh exit command SRX, the memory device can generate a lock-in signal SREF_DLL, and the DLL circuit can initiate a locking operation in response to the lock-in signal SREF_DLL. Figure 1 In this context, the signal marked "DLL_LOCK" indicates a signal that is activated during a locking operation.

[0031] At this point, if the self-refresh operation, based on the internal refresh signal generated just before exiting the self-refresh mode, overlaps with the locking operation of the DLL circuit, peak current consumption may increase, resulting in power supply noise. In particular, the DLL circuit, which includes the internal clock for generating the memory device, is a sensitive circuit with a long delay line; when the supply voltage is unstable, timing errors may occur, potentially leading to memory device failure. Therefore, various methods for controlling the timing of the locking operation to reduce the overlap between the self-refresh and locking operations have been discussed.

[0032] Below, this disclosure will describe a method for adjusting the activation timing of the lock start signal SREF_DLL to minimize the overlap between the self-refresh operation that occurs just before exiting the self-refresh mode and the DLL circuit locking operation.

[0033] Figure 2 This is a block diagram illustrating a storage device 100 according to an embodiment of the present disclosure. Figure 3 It is shown Figure 2 Detailed configuration diagram of the memory core 110. Figure 4A and Figure 4B It is used to describe according to Figure 2 Timing diagram of the memory refresh signal REF_BK<3:0> generated by the first mode signal NOR_MD and the second mode signal FGR_MD.

[0034] like Figure 2 As shown, the storage device 100 may include a memory core 110, a command / address receiving circuit 120, a clock buffer 122, a command decoder 130, an address generation circuit 132, a memory control circuit 134, a mode setting circuit 140, a mode control circuit 150, a refresh control circuit 160, a lock control circuit 170, a clock generation circuit 180, and a data input / output circuit 190.

[0035] The memory core 110 can be an area within the storage device 100 that stores data. For example... Figure 3 As shown, the memory core 110 may include first to fourth memory banks BK0 to BK3. Each of the first to fourth memory banks BK0 to BK3 may include a cell array region, wherein multiple memory cells coupled to multiple rows and columns are arranged in an array; and peripheral circuitry configured to perform activation, precharge, read, write, and refresh operations on the cell array region. The peripheral circuitry may include a row decoder configured to activate or deactivate rows in the cell array region; and a column decoder and input / output circuitry configured to input / output data from the cell array region.

[0036] Each of the first to fourth memory banks BK0 to BK3 can perform an activation operation to activate the row selected by row address RADD when the corresponding memory bank activation signal in the memory bank activation signal ACT_BK<0:3> is activated. Each of the first to fourth memory banks BK0 to BK3 can perform a precharge operation to deactivate the activated row when the corresponding memory bank precharge signal in the memory bank precharge signal PCG_BK<0:3> is activated. Each of the first to fourth memory banks BK0 to BK3 can perform a write operation to write data IDATA to the memory cell coupled to the column selected by column address CADD when the corresponding memory bank write signal in the memory bank write signal WT_BK<0:3> is activated. Each of the first to fourth memory banks BK0 to BK3 can perform a read operation to read data IDATA from the memory cell coupled to the column selected by column address CADD when the corresponding memory bank read signal in the corresponding memory bank read signal RD_BK<0:3> is activated. In addition, each of the first to fourth memory banks BK0 to BK3 can perform a refresh operation to refresh the row selected by the row refresh address RADD_REF when the corresponding memory bank refresh signal in the corresponding memory bank refresh signal REF_BK<3:0> is activated.

[0037] Command / address receiving circuit 120 can receive command / address signal C / A. Depending on the type of storage device 100, commands and addresses can be input through the same input terminal, or commands and addresses can be input through different input terminals, as illustrated in the figure where commands and addresses are input through the same input terminal. The command / address signal C / A can consist of multiple bits.

[0038] Clock buffer 122 can receive an external clock CK from the memory controller. Command / address receiving circuit 120 can receive command / address signals C / A in sync with the clock received by clock buffer 122.

[0039] Command decoder 130 can decode the command / address signal C / A received by command / address receiving circuit 120 to generate activation command ACT, precharge command PCG, write command WT, read command RD, self refresh enter command SRE, self refresh exit command SRX, auto refresh command AREF, and mode setting command MRS.

[0040] The activation command ACT is a signal input during an activation operation, the precharge command PCG is a signal input during a precharge operation, the write command WT is a signal input during a write operation, and the read command RD can be a signal input during a read operation. The self-refresh enter command SRE and the self-refresh exit command SRX are signals used to define the refresh period for performing a self-refresh operation. The self-refresh interval signal SREF, described below, can be a signal having an activation period determined by the self-refresh enter command SRE and the self-refresh exit command SRX. The activation period of the self-refresh interval signal SREF can be defined as the self-refresh operation interval. The automatic refresh command AREF is a signal provided by the memory controller to indicate an automatic refresh operation. For reference, a refresh operation can include: an automatic refresh operation, which is performed each time the memory controller applies a refresh command to the memory device; and a self-refresh operation, which is performed autonomously by the memory device while the memory controller only defines the refresh period. The mode setting command MRS is a signal used to read configuration data corresponding to the internal address signal ICA from the mode setting circuit 140.

[0041] Address generation circuit 132 can classify the internal address signal ICA received from command decoder 130 into bank address BKADD, row address RADD, and column address CADD. Bank address BKADD is used to select one of the first to fourth banks BK0 to BK3 included in bank core 110. Row address RADD is used to select one of the rows in the bank. Column address CADD is used to select the column in the bank used for read and write operations. Each address BKADD, RADD, and CADD can consist of multiple bits.

[0042] The memory bank control circuit 134 can decode the memory bank address BKADD to generate memory bank activation signals ACT_BK<3:0>, memory bank precharge signals PCG_BK<3:0>, memory bank read signals RD_BK<3:0>, and memory bank write signals WT_BK<3:0> corresponding to the first to fourth memory banks BK0 to BK3, respectively. The memory bank control circuit 134 can activate the memory bank activation signal selected by the memory bank address BKADD in the memory bank activation signal ACT_BK<3:0> in response to the activation command ACT. Similarly, the memory control circuit 134 can activate the memory precharge signal of the memory selected by memory address BKADD in the memory precharge signal PCG_BK<3:0> in response to the precharge command PCG, activate the memory write signal of the memory selected by memory address BKADD in the memory write signal WT_BK<3:0> in response to the write command WT, and activate the memory read signal of the memory selected by memory address BKADD in the memory read signal RD_BK<3:0> in response to the read command RD. The memory control circuit 134 can also decode the memory refresh address BKADD_REF to generate memory refresh signals REF_BK<3:0> corresponding to the first to fourth memory banks BK0 to BK3, respectively. In response to the internal refresh signal IREF, the memory control circuit 134 can activate the memory refresh signal of the memory selected by memory refresh address BKADD_REF in the memory refresh signal REF_BK<3:0>.

[0043] The mode setting circuit 140 can store configuration data for internal operations and read the configuration data corresponding to the internal address signal ICA in response to the mode setting command MRS. The mode setting circuit 140 can be implemented using a known mode register set. In one embodiment, the configuration data may include refresh setting information MD for setting the refresh operation mode and test mode information TM for setting lock operation parameters.

[0044] The mode control circuit 150 can output one of a first mode signal NOR_MD and a second mode signal FGR_MD based on the self-refresh interval signal SREF and refresh setting information MD. The mode control circuit 150 can output either the first mode signal NOR_MD or the second mode signal FGR_MD according to the refresh setting information MD. However, during the active period of the self-refresh interval signal SREF (i.e., the self-refresh operation interval), the second mode signal FGR_MD is output regardless of the refresh setting information MD. The second mode signal FGR_MD can be a signal representing fine-grained refresh (FGR) mode, while the first mode signal NOR_MD can be a signal representing a non-FGR mode (hereinafter referred to as normal mode).

[0045] For reference, the FGR mode divides refresh operations into finer granularities, so that a refresh task that would normally be executed as a single refresh command within a refresh cycle (tRFC) is instead divided into two or four refresh commands. In one embodiment, the mode control circuit 150 can output a first mode signal NOR_MD or a second mode signal FGR_MD according to the mode setting, but during the self-refresh operation, the second mode signal FGR_MD is output regardless of the mode setting.

[0046] In response to the self-refresh interval signal SREF and the automatic refresh command AREF, the refresh control circuit 160 can generate an internal refresh signal IREFF. During the activation period of the self-refresh interval signal SREF, the refresh control circuit 160 can periodically activate the internal refresh signal IREFF, thereby performing a self-refresh operation that sequentially refreshes multiple rows during the self-refresh operation. Furthermore, the refresh control circuit 160 can activate the internal refresh signal IREFF each time the automatic refresh command AREF is input. Therefore, each time the automatic refresh command AREF is input, an automatic refresh operation is performed to sequentially refresh multiple rows.

[0047] Furthermore, the refresh control circuit 160 can adjust the number and / or pulse width of the internal refresh signal IREF based on the first mode signal NOR_MD and the second mode signal FGR_MD. Based on the first mode signal NOR_MD, the second mode signal FGR_MD, and the internal refresh signal IREF, the refresh control circuit 160 can generate a memory bank refresh address BKADD_REF and a row refresh address RADD_REF to specify the row in the memory bank to be refreshed. In some embodiments, the refresh control circuit 160 can generate the memory bank refresh address BKADD_REF and the row refresh address RADD_REF separately for automatic refresh operations and self-refresh operations.

[0048] refer to Figure 4A The diagram illustrates the memory bank refresh signal REF_BK<3:0> generated during the first mode when the first mode signal NOR_MD is activated (NORM_MD = H). In the first mode, the refresh control circuit 160 can control the internal refresh signal IREF to generate pulses with a first pulse width W1 during the first unit refresh period tRFC1, and sequentially output memory bank refresh addresses BKADD_REF with values ​​from 0 to 3. At this time, the refresh control circuit 160 can change the row refresh address RADD_REF (e.g., increment by "+1") each time the internal refresh signal IREF is activated. Therefore, during the first unit refresh period tRFC1, the memory bank refresh signal REF_BK<3:0> can be sequentially activated to refresh one row of each of the first to fourth memory banks BK0 to BK3.

[0049] refer to Figure 4B The diagram illustrates the memory bank refresh signal REF_BK<3:0> generated during the second mode when the second mode signal FGR_MD is activated (FGR_MD = "H"). In the second mode, the refresh control circuit 160 can control the internal refresh signal IREF to generate pulses with a second pulse width W2 during the second unit refresh period tRFC2, and can change the value of the memory bank refresh address BKADD_REF from 0 to 1 or from 2 to 3 to output the memory bank refresh address BKADD_REF with the changed value. At this time, the refresh control circuit 160 can change the row refresh address RADD_REF every time the internal refresh signal IREF is activated twice. Therefore, during the second unit refresh period tRFC2, the two signals in the memory bank refresh signal REF_BK<3:0> can be activated sequentially to refresh one row in each of the two memory banks BK0 to BK3.

[0050] like Figure 4A and Figure 4B As shown, in the first mode, all memory banks BK0 to BK3 can be refreshed according to one internal refresh signal IRFE, while in the second mode, all memory banks can be refreshed according to two internal refresh signals IRFE. Therefore, the first unit refresh period tRFC1 can be relatively longer than the second unit refresh period tRFC2, and the first pulse width W1 of the internal refresh signal IRFE in the first mode can be relatively larger than the second pulse width W2 in the second mode. Although Figure 4A and Figure 4B The diagram shows that the memory refresh signals REF_BK<3:0> are activated sequentially to reduce peak current, but according to the embodiment, the memory refresh signals REF_BK<3:0> can also be activated simultaneously.

[0051] The locking control circuit 170 can generate a self-refresh interval signal SREF based on the self-refresh entry command SRE and the self-refresh exit command SRX, and generate a locking start signal SREF_DLL based on the self-refresh interval signal SREF and the internal refresh signal IREF.

[0052] More specifically, the locking control circuit 170 may include a self-refresh control circuit 172 and a start control circuit 174.

[0053] The self-refresh control circuit 172 can generate a self-refresh interval signal SREF based on the self-refresh enter command SRE and the self-refresh exit command SRX. The self-refresh control circuit 172 can generate a first extended interval signal SREFI and a second extended interval signal SREF_EX based on the self-refresh interval signal SREF. The self-refresh control circuit 172 can control the first extended interval signal SREFI to have a variable activation period based on the internal refresh signal IREF, and control the second extended interval signal SREF_EX to have a preset activation period. Detailed configuration and operation of the self-refresh control circuit 172 will be discussed in conjunction with... Figures 5 to 8B Please provide an explanation.

[0054] In response to the test mode information TM provided by the mode setting circuit 140, the startup control circuit 174 can output a lock-start signal SREF_DLL by selecting one of the first extended interval signal SREFI and the second extended interval signal SREF_EX. In some embodiments, in response to the test mode information TM, the startup control circuit 174 can output a lock-start signal SREF_DLL by selecting one of the self-refresh interval signal SREF, the first extended interval signal SREFI, and the second extended interval signal SREF_EX.

[0055] Clock generation circuit 180 can generate an internal clock ICLK based on the clock received by clock buffer 122. Clock generation circuit 180 can be disabled in power-down mode according to a reset signal (not shown) and enabled according to a lock-on start signal SREF_DLL. For example, clock generation circuit 180 can be implemented using a known delay phase-locked loop (DLL) circuit. In response to the lock-on start signal SREF_DLL, the DLL circuit can generate the internal clock ICLK by performing a lock operation to delay and fix the phase of the clock received by clock buffer 122.

[0056] Data input / output circuitry 190 can receive data DQ from or transmit data DQ to the memory controller. Data input / output circuitry 190 can transmit and receive data DQ synchronized with an internal clock ICLK. Data input / output circuitry 190 may include: data input circuitry 192 for receiving data DQ to be written to memory core 110 during a write operation; and data output circuitry 194 for transmitting data DQ read from memory core 110 during a read operation. Data input circuitry 192 can receive data DQ synchronized with the internal clock ICLK according to a write command WT, while data output circuitry 194 can transmit data DQ synchronized with the internal clock ICLK according to a read command RD.

[0057] Figure 5 It is shown Figure 2Detailed configuration diagram of the self-refresh control circuit. Figure 6 It is shown Figure 5 Detailed circuit diagram of the first signal generator 210. Figure 7 It is shown Figure 5 Detailed circuit diagram of the second signal generator 220.

[0058] See Figure 5 The self-refresh control circuit 172 may include first to third signal generators 210 to 230.

[0059] The first signal generator 210 can generate a self-refresh interval signal SREF, which is activated in response to a self-refresh enter command SRE and deactivated in response to a self-refresh exit command SRX. For example, see Figure 6 The first signal generator 210 may include a first inverter INV11, a second inverter INV12, a first NAND gate ND11, and a second NAND gate ND12, and is implemented as an SR latch, which receives a self-refresh enter command SRE as a set signal and a self-refresh exit command SRX as a reset signal.

[0060] The second signal generator 220 can generate a first extended interval signal SREFI, which is activated in response to a self-refresh enter command SRE and deactivated in response to a self-refresh exit command SRX or an internal refresh signal IREF. For example, referring to 7, the second signal generator 220 may include a first inverter INV21, a first NAND gate ND21, a second NAND gate ND22, and a buffer BU21. The first inverter INV21 inverts the self-refresh interval signal SREF. The first NAND gate ND21, whose output terminal is cross-coupled to the input terminal of the second NAND gate ND22, can receive the output signal of the first inverter INV21 at another input terminal. The second NAND gate ND22, whose output terminal is cross-coupled to the input terminal of the first NAND gate ND21, can receive the internal refresh signal IREF at another input terminal. The buffer BU21 buffers the output signal of the first NAND gate ND21 to output the first extended interval signal SREFI. The buffer BU21 can be implemented using a chain of an even number of inverters. With this configuration, the second signal generator 220 can generate a first extended interval signal SREFI, which is activated when the self-refresh interval signal SREF is activated and deactivated when the self-refresh interval signal SREF is deactivated. Here, the first extended interval signal SREFI can have an activation period that varies depending on whether the internal refresh signal is activated when the self-refresh interval signal SREF is deactivated.

[0061] The third signal generator 230 can generate a second extended interval signal SREF_EX, which responds to the activation of the self-refresh entry command SRE and the deactivation of a delayed signal SRXD, which is a self-refresh exit command SRX delayed by a preset delay time tD. For example, the third signal generator 230 may include a delay circuit 232 and an SR latch 234. The delay circuit 232 can generate the delayed signal SRXD by delaying the self-refresh exit command SRX by a preset delay time tD. The SR latch 234 can receive the self-refresh entry command SRE as a set signal and the delayed signal SRXD as a reset signal. The delay circuit 232 can be implemented using an RC delay. The SR latch 234 can have... Figure 6 The first signal generator 210 shown has a basically the same configuration. With this configuration, the third signal generator 230 can generate a second extended interval signal SREF_EX with an activation period that is extended by a fixed delay time tD from the end of the self-refresh operation interval.

[0062] The preset delay time tD of the third signal generator 230 can be set to a time shorter than the pulse width (i.e., the second pulse width W2) of the internal refresh signal IREF in the second mode. For example, when the second pulse width W2 is set to 60 nanoseconds, the preset delay time can be set to 30 to 50 nanoseconds.

[0063] Figure 8A and Figure 8B It is used to describe Figure 5 Timing diagram of the operation of the self-refresh control circuit.

[0064] See Figure 8A and 8B The first signal generator 210 can generate a self-refresh interval signal SREF, which is activated in response to a self-refresh enter command SRE and deactivated in response to a self-refresh exit command SRX. In one embodiment, during the activation period of the self-refresh interval signal SREF (i.e., during the self-refresh operation), the second mode signal FGR_MD can be activated regardless of the refresh setting information MD, and the internal refresh signal IREF can generate a pulse with a second pulse width W2.

[0065] The third signal generator 230 can generate a second extended interval signal SREF_EX, which is activated in response to the self-refresh entry command SRE and deactivated after a preset delay time tD from the activation of the self-refresh exit command SRX. In this case, the preset delay time tD can be set to a time shorter than the pulse width (i.e., the second pulse width W2) of the internal refresh signal IREF in the second mode.

[0066] The second signal generator 220 can generate a first extended interval signal SREFI, which is activated in response to the self-refresh enter command SRE and deactivated in response to the self-refresh exit command SRX or the internal refresh signal IREF.

[0067] like Figure 8A As shown, when the internal refresh signal IREF is deactivated when the self-refresh interval signal SREF is deactivated, the second signal generator 220 can generate a first extended interval signal SREFI, which is deactivated in response to the self-refresh exit command SRX. In this case, the first extended interval signal SREFI can have the same activation period as the self-refresh interval signal SREF, and among the self-refresh interval signal SREF, the first extended interval signal SREFI, and the second extended interval signal SREF_EX, the second extended interval signal SREF_EX can have the longest activation period.

[0068] On the other hand, such as Figure 8B As shown, when the internal refresh signal IREF is activated when the self-refresh interval signal SREF is deactivated, that is, when the internal refresh signal IREF is generated just before exiting the self-refresh mode, the second signal generator 220 can generate a first extended interval signal SREFI that is deactivated on the falling edge of the internal refresh signal IREEF. In this case, the first extended interval signal SREFI can have a longer activation period than the self-refresh interval signal SREF due to the internal refresh signal IREEF. Among the self-refresh interval signal SREF, the first extended interval signal SREFI can have the longest activation period.

[0069] Figure 9 It is shown Figure 2 Detailed configuration diagram of the start-up control circuit 174.

[0070] like Figure 9 As shown, the startup control circuit 174 may include a first multiplexer 310 and a second multiplexer 320.

[0071] In response to the first bit TM in the test mode information TM<1:0> <0> The first multiplexer 310 can output a pre-extended interval signal PRE_SREF by selecting one of the first extended interval signal SREFI and the second extended interval signal SREF_EX. First bit TM <0> This can be referred to as the first test mode signal. For example, the first multiplexer 310 can be used as the first test mode signal TM. <0> The first extended range signal SREFI is selected when the logic level is low, while the first test mode signal TM is selected when the logic level is low. <0> The second extended interval signal SREF_EX is selected when the logic level is high.

[0072] In response to the second bit TM in the test mode information TM<1:0> <1> The second multiplexer 320 can output a lock start signal SREF_DLL by selecting one of the self-refresh interval signal SREF and the pre-expansion interval signal PRE_SREF. Second bit TM <1> This can be referred to as the second test mode signal. For example, the second multiplexer 320 can be used as the second test mode signal TM. <1> The self-refresh interval is selected when the logic level is low, and when the second test mode signal TM is low... <1> It is the pre-expansion interval selection signal PRE_SREF when the logic level is high.

[0073] With the above configuration, in response to the test mode information TM, the start control circuit 174 can select one of the self-refresh interval signal SREF, the first extended interval signal SREFI, and the second extended interval signal SREF_EX, and output the selected signal as the lock start signal SREF_DLL.

[0074] As described above, the storage device 100 according to an embodiment of this disclosure can adjust the activation timing of the lock-in signal SREF_DLL so that the locking operation of the DLL circuit does not overlap with the self-refresh operation that occurs just before exiting the self-refresh mode. For example, in response to the test mode information TM<1:0> being "10", the storage device 100 can generate the lock-in signal SREF_DLL based on the first extended interval signal SREFI, thereby controlling the DLL circuit to perform the locking operation after the self-refresh operation is completed, thereby avoiding overlap between the self-refresh operation and the locking operation. Alternatively, in response to the test mode information TM being "11", the storage device 100 can generate the lock-in signal SREF_DLL based on the second extended interval signal SREF_EX, thereby minimizing the overlap between the self-refresh operation and the locking operation while ensuring operational flexibility. Therefore, the occurrence of peak current can be suppressed and locking operation failures can be prevented.

[0075] Figure 10 This is a block diagram illustrating a storage device 400 according to another embodiment of the present disclosure.

[0076] See Figure 10 The storage device 400 may include a memory core 410, a command / address receiving circuit 420, a clock buffer 422, a command decoder 430, an address generation circuit 432, a memory control circuit 434, a mode setting circuit 440, a mode control circuit 450, a refresh control circuit 460, a lock control circuit 470, a clock generation circuit 480, and a data input / output circuit 490.

[0077] Figure 10The memory core 410, command / address receiving circuit 420, clock buffer 422, command decoder 430, address generation circuit 432, memory bank control circuit 434, mode control circuit 450, refresh control circuit 460, clock generation circuit 480, and data input / output circuit 490 can be integrated with... Figure 2 The components shown have essentially the same configuration and operation.

[0078] The mode setting circuit 440 can store configuration data for setting internal operations and read the configuration data corresponding to the internal address signal ICA in response to the mode setting command MRS. The configuration data may include refresh setting information MD for setting the refresh operation mode, test mode information TM for setting the lock operation parameters, and operating speed information OP_INF for indicating the data transfer rate of the storage device 400.

[0079] In response to the self-refresh enter command SRE and the self-refresh exit command SRX, the locking control circuit 470 can generate a self-refresh interval signal SREF, and based on the self-refresh interval signal SREF, generate a first extended interval signal SREFI and a second extended interval signal SREF_EX. The locking control circuit 470 can control the first extended interval signal SREFI to have a variable activation period based on the internal refresh signal IREF, and can control the second extended interval signal SREF_EX to have a preset activation period. According to the running speed information OP_INF, the locking control circuit 470 can generate a locking start signal SREF_DLL by selecting one of the first extended interval signal SREFI and the second extended interval signal SREF_EX.

[0080] More specifically, the locking control circuit 470 may include a self-refresh control circuit 472 and a start control circuit 474.

[0081] In response to the self-refresh enter command SRE and the self-refresh exit command SRX, the self-refresh control circuit 472 can generate a self-refresh interval signal SREF. Based on the self-refresh interval signal SREF, the self-refresh control circuit 472 can generate a first extended interval signal SREFI and a second extended interval signal SREF_EX. The self-refresh control circuit 472 can perform [interactions / reactions]. Figures 5 to 8B The self-refresh control circuit 172 in the middle has basically the same configuration and operation.

[0082] In response to the test mode information TM and running speed information OP_INF provided by the mode setting circuit 440, the startup control circuit 474 can output a lock-start signal SREF_DLL by selecting one of the first extended interval signal SREFI and the second extended interval signal SREF_EX. In some embodiments, in response to the test mode information TM and running speed information OP_INF, the startup control circuit 474 can output the lock-start signal SREF_DLL by selecting one of the self-refresh interval signal SREF, the first extended interval signal SREFI, and the second extended interval signal SREF_EX.

[0083] Figure 11 It is shown Figure 10 Detailed circuit diagram of the start-up control circuit 474.

[0084] like Figure 11 As shown, the start control circuit 474 may include a selection control circuit 510, a first multiplexer 520, and a second multiplexer 530.

[0085] The selection control circuit 510 can set the first to fourth speed signals S0 to S3 according to the running speed information OP_INF<3:0>, and respond to the first and second bits TM of the test mode information TM<2:0>. <0> and TM <1> The output selection signal SEL is generated by selecting one of the speed signals S0 to S3. The first bit and the second bit TM<1:0> can be referred to as the first test mode signal.

[0086] In response to the selection signal SEL, the first multiplexer 520 can output a pre-extended interval signal PRE_SREF by selecting one of the first extended interval signal SREFI and the second extended interval signal SREF_EX. For example, the first multiplexer 520 can select the first extended interval signal SREFI when the selection signal SEL is logic low, and select the second extended interval signal SREF_EX when the selection signal SEL is logic high.

[0087] In response to the third bit TM in the test mode information TM<2:0> <2> The second multiplexer 530 can output a lock start signal SREF_DLL by selecting one of the self-refresh interval signal SREF and the pre-expansion interval signal PRE_SREF. The third bit TM <2> This can be referred to as the second test mode signal. For example, the second multiplexer 530 can be used as the second test mode signal TM. <2> The self-refresh interval is selected when the logic level is low, and when the second test mode signal TM is low... <2> It is the pre-expansion interval selection signal PRE_SREF when the logic level is high.

[0088] More specifically, the selection control circuit 510 may include a speed setting circuit 512 and a third multiplexer 514.

[0089] The speed setting circuit 512 can set the first to fourth speed signals S0 to S3 according to the operating speed information OP_INF<3:0>. In this case, the first speed signal S0 can be fixed at a logic high level, and the fourth speed signal S3 can be fixed at a logic low level, while the logic levels of the second speed signal S1 and the third speed signal S2 can vary according to the operating speed information OP_INF<3:0>. For example, the second speed signal S1 can be at a logic high level when the data rate of the storage device 400 is set to 3200 Mbps or less, and at a logic low level when the data rate exceeds 3200 Mbps. The third speed signal S2 can be at a logic high level when the data rate of the storage device 400 is set to 6000 Mbps or less, and at a logic low level when the data rate exceeds 6000 Mbps.

[0090] In response to the first test mode signal TM<1:0>, the third multiplexer 514 can output a selection signal SEL by selecting one of the first to fourth speed signals S0 to S3.

[0091] For example, the third multiplexer 514 can output a logic-high first speed signal S0 as a selection signal SEL in response to the first test mode signal TM<1:0> being "00", and can output a logic-low fourth speed signal S3 as a selection signal SEL in response to the first test mode signal TM<1:0> being "11". The third multiplexer 514 can output a second speed signal S1 as a selection signal SEL in response to the first test mode signal TM<1:0> being "01", and can output a third speed signal S2 as a selection signal SEL in response to the first test mode signal TM<1:0> being "10".

[0092] Figure 12 It is used to describe Figure 11 A table showing the operation of the start control circuit 474.

[0093] See Figure 12 When the second test mode signal TM <2> When the logic level is low (CASE 1), the start control circuit 474 can output the self-refresh interval signal SREF as the lock start signal SREF_DLL, regardless of the selection signal SEL (i.e., test mode information TM<2:0>).

[0094] When the test mode information TM<2:0> is input as “100” (CASE 2), the start control circuit 474 can output the first speed signal S0, which is set to logic high, as the selection signal SEL, and can output the second extended range signal SREF_EX as the lock start signal SREF_DLL in response to the selection signal SEL.

[0095] When the test mode information TM<2:0> for “101” is input (CASE 3), the startup control circuit 474 can output the second speed signal S1 as the selection signal SEL, and in response to the selection signal SEL, can output either the first extended range signal SREFI or the second extended range signal SREF_EX as the lock-on signal SREF_DLL. In this case, when the running speed information OP_INF<3:0> indicates a data rate greater than 3200Mbps, the startup control circuit 474 can output the first extended range signal SREFI. When the running speed information OP_INF<3:0> indicates a data rate less than or equal to 3200Mbps, the startup control circuit 474 can output the second extended range signal SREF_EX. That is, in an environment of 3200Mbps or less, the lock-on operation is controlled by the second extended range signal SREF_EX, while in an environment exceeding 3200Mbps, the lock-on operation is controlled by the first extended range signal SREFI.

[0096] When the test mode information TM<2:0> for "110" is input (CASE 4), the startup control circuit 474 can output the third speed signal S2 as the selection signal SEL, and in response to the selection signal SEL, can output either the first extended range signal SREFI or the second extended range signal SREF_EX as the lock-on signal SREF_DLL. In this case, when the running speed information OP_INF<3:0> indicates a data rate greater than 6000Mbps, the startup control circuit 474 can output the first extended range signal SREFI. When the running speed information OP_INF<3:0> indicates a data rate less than or equal to 6000Mbps, the startup control circuit 474 can output the second extended range signal SREF_EX. That is, in an environment of 6000Mbps or less, the lock-on operation is controlled by the second extended range signal SREF_EX, while in an environment exceeding 6000Mbps, the lock-on operation is controlled by the first extended range signal SREFI.

[0097] When the test mode information TM<2:0> is input as “111” (CASE 5), the start control circuit 474 can output the fourth speed signal S3, which is set to logic low, as the selection signal SEL, and can output the first extended range signal SREFI as the lock start signal SREF_DLL in response to the selection signal SEL.

[0098] Figure 13A and Figure 13B It is used to describe Figure 10 Timing diagram of the operation of storage device 400 in the middle.

[0099] like Figure 13A and Figure 13B As shown, the self-refresh interval signal SREF can be activated in response to the self-refresh enter command SRE and deactivated in response to the self-refresh exit command SRX. During the activation period of the self-refresh interval signal SREF (i.e., during the self-refresh operation), the first mode signal NOR_MD can be deactivated and the second mode signal FGR_MD can be activated, so that the FGR mode is applied.

[0100] like Figure 13A As shown, a storage device 400 operating at a speed higher than a reference speed (e.g., exceeding 3200 Mbps or 6000 Mbps) can generate a first extended interval signal SREFI based on an internal refresh signal IREEF that occurs just before exiting the self-refresh mode, and can generate a lock-in start signal SREF_DLL based on the first extended interval signal SREFI. Therefore, the storage device 400 operating at a higher speed can adjust the timing of the lock operation to activate the lock-in start signal SREF_DLL on the falling edge of the internal refresh signal IREEF, thereby avoiding overlap between the self-refresh operation and the lock operation.

[0101] like Figure 13B As shown, the storage device 400 operating at a speed lower than the reference speed can generate a lock-in signal SREF_DLL based on a second extended interval signal SREF_EX with a preset activation period, regardless of the internal refresh signal IREF that occurs just before the end of the self-refresh operation. Thus, the storage device 400 operating at a lower speed can activate the lock-in signal SREF_DLL with a fixed margin from the end of the self-refresh operation, thereby ensuring that the locking operation is completed within a predetermined time tXS_DLL as defined by the specification and minimizing overlap.

[0102] As described above, the storage device 400 according to an embodiment of this disclosure can flexibly adjust the activation timing of the lock start signal SREF_DLL based on the operating speed to minimize the overlap between the self-refresh operation and the locking operation of the DLL circuit. Therefore, both high-speed operation stability and low-speed operation efficiency can be guaranteed.

[0103] Figure 14 This is a block diagram illustrating a storage system 1000 according to an embodiment of the present disclosure.

[0104] See Figure 14 As shown, the storage system 1000 may include a storage device 1100 and a memory controller 1200.

[0105] Storage system 1000 is a device that stores data under the control of a host, such as a mobile phone, smartphone, MP3 player, laptop, desktop computer, game console, television, tablet computer, or in-vehicle infotainment system. The host can be an external device of storage system 1000.

[0106] The memory controller 1200 typically controls the operation of the storage system 1000 and the overall data exchange between the host and the storage device 1100. In response to a request REQ from the host, the memory controller 1200 can generate a command / address signal C / A and provide it to the storage device 1100. The memory controller 1200 can also provide a clock CK along with the command / address signal C / A. The memory controller 1200 can provide the data DQ corresponding to the request REQ from the host to the storage device 1100, and can also provide the data DQ read from the storage device 1100 to the host. The command / address signal C / A provided by the memory controller 1200 to the storage device 1100 may include activation commands, precharge commands, write commands, read commands, self-refresh enter commands, self-refresh exit commands, automatic refresh commands, and mode setting commands, etc.

[0107] Storage device 1100 can store data DQ. Storage device 1100 can operate in response to control of memory controller 1200. Storage device 1100 may include a memory cell array, wherein a plurality of memory cells for storing data DQ are arranged in an array. Storage device 1100 may include DRAM (Dynamic Random Access Memory) with dynamic memory cells that require refresh. In some embodiments, storage device 1100 may be DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, or RDRAM (Rambus DRAM).

[0108] Storage device 1100 can receive address / command signals C / A from memory controller 1200 and access an address-selected region in the memory cell array. That is, storage device 1100 can perform operations indicated by commands on the address-selected region. For example, storage device 1100 can write data DQ to the selected region in response to a write command, or read data DQ from the selected region in response to a read command. Storage device 1100 can periodically activate an internal refresh signal during a self-refresh operation defined by a self-refresh enter command and a self-refresh exit command, thereby performing a self-refresh operation. Alternatively, storage device 1100 can activate the internal refresh signal whenever an automatic refresh command is input, thereby performing an automatic refresh operation accordingly.

[0109] Storage device 1100 can be corresponding Figure 2 The storage device 100 shown or Figure 10 The storage device 400 shown is an example. That is, the storage device 1100 can be configured to apply FGR mode during a self-refresh operation, regardless of the mode setting.

[0110] In one embodiment, the storage device 1100 may include: a refresh control circuit configured to generate an internal refresh signal based on a self-refresh interval signal; a lock control circuit configured to generate a self-refresh interval signal based on a self-refresh enter command and a self-refresh exit command, and to generate a lock start signal based on the self-refresh interval signal and the internal refresh signal; and a clock generation circuit configured to generate an internal clock by delaying and fixing an external clock in response to the lock start signal. Thus, the storage device 1100 according to an embodiment of this disclosure can suppress peak current generation and prevent lock operation failure by adjusting the lock operation start timing so that it does not overlap with the refresh operation triggered by the internal refresh signal generated just before exiting the self-refresh mode.

[0111] In another embodiment, the storage device 1100 may include: a refresh control circuit configured to generate an internal refresh signal based on a self-refresh interval signal; a lock control circuit configured to generate a self-refresh interval signal according to a self-refresh enter command and a self-refresh exit command, generate a first extended interval signal having a variable activation period based on the self-refresh interval signal and a second extended interval signal having a preset activation period, and generate a lock start signal based on running speed information by selecting one of the first extended interval signal and the second extended interval signal; and a clock generation circuit configured to generate an internal clock by delaying and fixing an external clock in response to the lock start signal. Thus, the storage device 1100 according to an embodiment of this disclosure can ensure stability during high-speed operation and efficiency during low-speed operation by adjusting the lock operation start timing according to the running speed so that it does not overlap with the refresh operation triggered by the internal refresh signal generated just before exiting the self-refresh mode.

[0112] Various embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is for illustrative purposes only. Therefore, the embodiments of this disclosure are not limited to those described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made beyond the embodiments disclosed herein. These embodiments can be combined to form additional embodiments.

[0113] It should be noted that although the technical spirit of this disclosure is illustrated in conjunction with embodiments, these descriptions are for illustrative purposes only and should not be construed as limiting. Those skilled in the art will understand that various modifications can be made without departing from the technical spirit of this disclosure and the scope of the appended claims.

[0114] For example, the logic gates and transistors given as examples in the above embodiments can be implemented in different positions and types depending on the polarity of the input signal.

Claims

1. A storage device, comprising: The refresh control circuit generates an internal refresh signal based on the self-refresh interval signal. A locking control circuit, comprising: generating a self-refresh interval signal based on a self-refresh enter command and a self-refresh exit command; and generating a locking start signal based on the self-refresh interval signal and the internal refresh signal; and A clock generation circuit that, in response to the lock-on signal, generates an internal clock by delaying and fixing an external clock.

2. The storage device according to claim 1, further comprising: The mode setting circuit, which: reads configuration data in response to a mode setting command; and The mode control circuit outputs a first mode signal or a second mode signal based on the configuration data, and outputs the second mode signal regardless of the configuration data when the self-refresh interval signal is activated.

3. The storage device according to claim 2, wherein, The refresh control circuit adjusts the number, pulse width, or both of the internal refresh signals according to the first mode signal and the second mode signal.

4. The storage device according to claim 1, wherein the locking control circuit: When the internal refresh signal is activated when the self-refresh interval signal is deactivated, the lock start signal is activated according to the falling edge of the internal refresh signal. When the internal refresh signal is not activated when the self-refresh interval signal is deactivated, the lock start signal is activated according to the deactivation of the self-refresh interval signal.

5. The storage device according to claim 1, in, The locking control circuit includes: A self-refresh control circuit, comprising: generating a self-refresh interval signal based on the self-refresh entry command and the self-refresh exit command; and generating a first extended interval signal and a second extended interval signal based on the self-refresh interval signal; and The start control circuit outputs the lock start signal by selecting one of the first extended range signal and the second extended range signal. The first extended interval signal has a variable activation period based on the internal refresh signal, and the second extended interval signal has a preset activation period.

6. The storage device according to claim 5, wherein, The self-refresh control circuit includes: A first signal generator, which generates the self-refresh interval signal, the self-refresh interval signal being activated by the self-refresh enter command and deactivated by the self-refresh exit command; A second signal generator, which: generates a first extended interval signal, the first extended interval signal being activated when the self-refresh interval signal is activated and deactivated when the self-refresh interval signal is deactivated, the first extended interval signal having an extended activation period, the extended activation period varying depending on whether the internal refresh signal is activated when the self-refresh interval signal is deactivated; and A third signal generator generates a second extended interval signal, which is activated by the self-refresh entry command and deactivated by a delay signal, wherein the delay signal is generated by delaying the self-refresh exit command by a preset delay time.

7. The storage device according to claim 6, wherein, The second signal generator includes: An inverter, which inverts the self-refresh interval signal; A first NAND gate and a second NAND gate, the first NAND gate and the second NAND gate being cross-coupled at their input and output terminals, the first NAND gate receiving the output of the inverter, and the second NAND gate receiving the internal refresh signal; and The buffer buffers the output of the first NAND gate to output the first extended interval signal.

8. The storage device according to claim 6, wherein, The third signal generator includes: A delay circuit, wherein: the self-refresh exit command is delayed by a preset delay time to generate the delay signal; and SR latch, which generates a second extended interval signal that is activated by the self-refresh entry command and deactivated by the delay signal.

9. The storage device according to claim 6, wherein, The preset delay time is shorter than the pulse width of the internal refresh signal.

10. The storage device according to claim 5, wherein, The start-up control circuit includes: A first multiplexer, which: based on a first test mode signal, outputs a pre-expanded interval signal by selecting one of a first extended interval signal and a second extended interval signal; and The second multiplexer, based on the second test mode signal, outputs the lock start signal by selecting one of the self-refresh interval signal and the pre-expansion interval signal.

11. A storage device comprising: The refresh control circuit generates an internal refresh signal based on the self-refresh interval signal. A locking control circuit, comprising: generating a self-refresh interval signal based on a self-refresh enter command and a self-refresh exit command; generating a first extended interval signal and a second extended interval signal based on the self-refresh interval signal; and generating a locking start signal by selecting one of the first extended interval signal and the second extended interval signal based on running speed information. The first extended interval signal has a variable activation period based on the internal refresh signal, while the second extended interval signal has a preset activation period. A clock generation circuit that, in response to the lock-on signal, generates an internal clock by delaying and fixing an external clock.

12. The storage device according to claim 11, wherein, The refresh control circuit generates the internal refresh signal based on the self-refresh interval signal, and adjusts the number, pulse width, or both of the internal refresh signal based on the mode signal indicating the FGR mode, where FGR refers to fine-grained refresh.

13. The storage device according to claim 12, wherein, The mode signal indicates the FGR mode during the activation period of the self-refresh interval signal.

14. The storage device according to claim 12, in, The preset activation period includes the activation period of the self-refresh interval signal and a preset delay time, and The preset delay time is shorter than the pulse width of the internal refresh signal.

15. The storage device according to claim 11, wherein, The locking control circuit includes: A self-refresh control circuit, comprising: generating a self-refresh interval signal based on the self-refresh entry command and the self-refresh exit command; and generating a first extended interval signal and a second extended interval signal based on the self-refresh interval signal; and The start control circuit, based on the running speed information, outputs the lock start signal by selecting one of the first extended interval signal and the second extended interval signal.

16. The storage device according to claim 15, wherein, The start-up control circuit includes: The selection control circuit sets multiple speed signals based on the running speed information, and selects one of the speed signals in response to a first test mode signal to output a selection signal; A first multiplexer, wherein: based on the selection signal, it outputs a pre-expanded interval signal by selecting one of the first extended interval signal and the second extended interval signal; and The second multiplexer, in response to the second test mode signal, outputs the lock start signal by selecting one of the pre-expansion interval signal and the self-refresh interval signal.

17. The storage device according to claim 16, wherein, The selection control circuit includes: A speed setting circuit, comprising: generating the speed signal, the speed signal having a logic level based on the operating speed information; and A third multiplexer, which, in response to the first test mode signal, outputs the selection signal by selecting one of the speed signals.

18. A method of operating a storage device, the method comprising: Generate at least one speed signal, the at least one speed signal having a logic level based on running speed information; A self-refresh interval signal is generated, which is activated by a self-refresh enter command and deactivated by a self-refresh exit command. An internal refresh signal is generated during the activation period of the self-refresh interval signal; A first extended interval signal and a second extended interval signal are generated. The first extended interval signal has a variable activation period based on the internal refresh signal, while the second extended interval signal has a preset activation period. Based on the speed signal, a lock-up start signal is generated by selecting one of the first extended interval signal and the second extended interval signal; as well as In response to the lock-on signal, an internal clock is generated by delaying and fixing the external clock.

19. The operating method according to claim 18, wherein, Generating the internal refresh signal includes: The number, pulse width, or both of the internal refresh signals are adjusted based on the mode signal indicating the FGR mode, where FGR stands for Fine-Grained Refresh.

20. The operating method according to claim 19, in, The preset activation period includes the activation period of the self-refresh interval signal and a preset delay time, and The preset delay time is shorter than the pulse width of the internal refresh signal.

21. The operating method according to claim 18, wherein, Generating the lock start signal includes: When the speed signal has a first logic level, the first extended interval signal is selected, and the first logic level indicates that the speed is higher than the reference speed. When the speed signal has a second logic level, the second extended interval signal is selected, and the second logic level indicates that the speed is lower than the reference speed.

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