Refresh control circuit, memory and electronic device

Abstract

The present disclosure provides a refresh control circuit, a memory and an electronic device, wherein the refresh control circuit is applied to refresh control of a storage array, comprising: a register circuit configured to obtain and store row hammer addresses of the storage array; a refresh controller configured to, in response to a received refresh command, perform a row hammer refresh operation on a victim row corresponding to the row hammer addresses stored in the register circuit when the storage array is in an in-memory computing mode; the refresh controller is further configured to, after the row hammer refresh operation on the victim rows corresponding to all the row hammer addresses stored in the register circuit is completed, generate and output an adjustment enable signal in an active state to indicate to shorten a refresh cycle time of the storage array in the in-memory computing mode; the refresh control circuit provided by the present disclosure is used to optimize the time occupied by the refresh operation of the DRAM and increase the read-write time of the DRAM.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and in particular to a refresh control circuit, a memory, and an electronic device. Background Technology

[0002] According to the JEDEC standard, DRAM (Dynamic Random Access Memory) needs to be refreshed periodically to maintain the integrity of the stored data. For example, by setting the standard refresh cycle time tRFC (Refresh Cycle Time) to 280ns ​​and the standard refresh interval tREFI (Refresh timeInterval) to 3.9us, the refresh operation can be performed periodically.

[0003] In high-temperature environments, the leakage rate of DRAM memory cells increases significantly, reducing data retention capability and necessitating shorter refresh intervals to ensure data reliability. For example, the preset mode register (MR) in the memory is configured with temperature encoding to adapt to refresh requirements at different temperatures; MR is an internal configuration register of the DRAM used to store the encoded value output by the temperature sensor to determine the actual refresh interval tREFIe executed by the system.

[0004] When the temperature code of MR is 11111B, the actual refresh interval tREFIe is shortened to 0.125 times the standard value, i.e., 0.125 × tREFI (approximately 487.5 ns). Under this high-temperature condition, the duration of a single refresh accounts for as much as approximately 57.4% of the actual refresh interval (280 ns / 487.5 ns), and the refresh operation significantly squeezes the normal read and write time window of DRAM. Especially in in-memory computing mode, the surge in refresh overhead will severely compress the available read and write bandwidth during the computing process, directly restricting the effective read and write performance of the memory and the efficiency of in-memory computing operations.

[0005] Optimizing the time ratio of DRAM refresh operations and freeing up more available read and write time, especially improving DRAM read and write performance in in-memory computing mode, is a technical problem that urgently needs to be solved in the field of DRAM performance improvement. Summary of the Invention

[0006] This disclosure provides a refresh control circuit, a memory, and an electronic device to optimize the refresh operation time of DRAM in in-memory computing mode and increase the read and write time of DRAM.

[0007] This disclosure provides a refresh control circuit for refreshing control of a memory array, comprising: a register circuit configured to acquire and store row hammer addresses of the memory array; a refresh controller configured to, when the memory array is in in-memory computing mode, perform row hammer refresh operations on the affected rows corresponding to the row hammer addresses stored in the register circuit in response to a received refresh command; the refresh controller is further configured to, after the row hammer refresh operations on all the affected rows corresponding to the row hammer addresses stored in the register circuit are completed, generate and output an adjustment enable signal in an active state to indicate a shortening of the refresh cycle time of the memory array in in-memory computing mode.

[0008] Optionally, the refresh controller includes: a row hammer address counter, configured to receive an in-memory compute enable signal, and when the in-memory compute enable signal is in a valid state to indicate that the memory array is in the in-memory compute mode, count the row hammer addresses that have completed the row hammer refresh operation to obtain a first count value; when the first count value is equal to the number of row hammer addresses stored in the register circuit or the maximum value of the row hammer addresses that the register circuit can store, the row hammer address counter generates and outputs the adjustment enable signal that is in a valid state.

[0009] Optionally, the register circuit is further configured to receive the in-memory computation enable signal and, in response to the in-memory computation enable signal being in a valid state, to stop acquiring the row hammer address.

[0010] Optionally, the refresh controller is further configured to, when the in-memory compute enable signal is active to indicate that the memory array is in in-memory compute mode, execute the row hammer refresh operation in response to each refresh command until the row hammer refresh operation for all victim rows corresponding to the row hammer addresses stored in the register circuit is completed; or, at intervals of a preset number of refresh commands, execute the row hammer refresh operation in response to the currently received refresh command until the row hammer refresh operation for all victim rows corresponding to the row hammer addresses stored in the register circuit is completed.

[0011] Optionally, the refresh controller is further configured to, when the in-memory computing enable signal is in an invalid state to indicate that the memory array is in memory mode, execute the row hammer refresh operation in response to the currently received refresh command at preset intervals of refresh commands.

[0012] Optionally, the refresh controller includes: a refresh counting circuit configured to count the refresh command to obtain a second count value, and when the second count value is equal to a preset value, generate and output a row hammer refresh enable signal in a valid state; a row hammer refresh control circuit configured to receive the refresh command and the row hammer refresh enable signal, and when the row hammer refresh enable signal is in a valid state, generate and output a row hammer refresh signal in response to the refresh command to indicate that the row hammer refresh operation is performed on the victim row corresponding to the row hammer address; and a register circuit configured to output a row hammer address in response to the row hammer refresh enable signal in a valid state.

[0013] Optionally, the refresh counting circuit is further configured to be disabled in response to the adjustment enable signal being in an active state.

[0014] Optionally, the refresh counting circuit includes: a counting unit configured to count the refresh command to obtain the second count value; and a comparison unit configured to receive the second count value and the preset value, and when the second count value and the preset value match, generate and output the row hammer refresh enable signal in a valid state.

[0015] Optionally, the refresh controller further includes: a configuration module configured to configure and provide the preset value; wherein, in the in-memory computing mode, the preset value is configured to be 1.

[0016] Optionally, the refresh controller further includes: a configuration module configured to configure and provide the preset value; wherein the preset value is configured according to the row hammer refresh ratio.

[0017] Optionally, the configuration module is further configured to obtain the temperature code corresponding to the current temperature of the memory to which the refresh control circuit belongs, and configure the preset value according to the temperature code.

[0018] Optionally, the memory to which the refresh control circuit belongs further includes an in-memory computing controller; the configuration module is further configured to output the temperature code to the in-memory computing controller; the in-memory computing controller is configured to generate and output the refresh command according to the temperature code.

[0019] Optionally, the configuration module configures the preset value according to the temperature code, including: when the temperature code indicates that the current temperature of the memory is rising, the configuration module increases the configured preset value; when the temperature code indicates that the current temperature of the memory is falling, the configuration module decreases the configured preset value.

[0020] In another aspect, this disclosure provides a memory including the refresh control circuit described above.

[0021] Optionally, the refresh command includes a first refresh command, and the refresh control circuit is configured to receive the first refresh command sent externally in storage mode, and control the execution of a refresh operation in response to the first refresh command.

[0022] Optionally, the refresh command further includes a second refresh command, and the memory further includes: an in-memory computing controller configured to provide the second refresh command to the refresh control circuit in in-memory computing mode, and receive an adjustment enable signal in an active state fed back by the refresh control circuit; the refresh control circuit is configured to control the execution of a refresh operation in response to the second refresh command in in-memory computing mode.

[0023] In another aspect, this disclosure provides an electronic device, including a processing device and a storage device electrically connected to the processing device; the storage device includes the memory provided above.

[0024] The technical solution provided in this disclosure has at least the following advantages: When the memory array is in in-memory computing mode, the refresh controller, upon receiving a refresh command, performs targeted row hammer refresh operations only for the row hammer addresses recorded in the register circuit. After all the affected rows corresponding to the recorded row hammer addresses have been refreshed, the refresh controller generates and outputs an adjustment enable signal in an effective state, explicitly indicating that the system can safely shorten the refresh cycle time. This mechanism breaks through the limitation of fixed refresh cycle time in traditional solutions, dynamically releasing the memory access bandwidth occupied by excessive row hammer refresh operations in in-memory computing mode. This effectively solves the technical problem that the refresh cycle time cannot be shortened due to maintaining row hammer refresh protection in in-memory computing mode, resulting in the memory array's memory access bandwidth being occupied by unnecessary row hammer refresh operations. This effectively increases the read / write time window of the memory array in in-memory computing mode, significantly improving the in-memory computing execution efficiency and overall computing performance of DRAM. Attached Figure Description

[0025] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1This is a schematic diagram of the structure of a refresh control circuit provided in some embodiments of this disclosure; Figure 2 A schematic diagram of the structure of a refresh controller including a refresh counting circuit and a horizontal hammer refresh control circuit, provided for some embodiments of this disclosure; Figure 3 This is a schematic diagram of the structure of a refresh counting circuit provided in some embodiments of this disclosure; Figure 4 This is a schematic diagram of the structure of a refresh controller including a row hammer address counter, provided for some embodiments of this disclosure; Figure 5 Provided for embodiments of this disclosure Figure 4 Based on the example refresh controller, here is a schematic diagram of the refresh control circuit. Figure 6 A schematic diagram of the structure of a refresh controller including a second type of row hammer address counter provided for some embodiments of this disclosure; Figure 7 This is a schematic diagram illustrating a specific implementation structure of a refresh control circuit provided in some embodiments of this disclosure; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure.

[0027] Explanation of reference numerals in the attached figures: 110 - Storage array, 101 - Register circuit, 102 - Refresh controller, 120 - Array refresh control circuit, 201 - Row hammer address counter, 301 - Refresh counting circuit, 302 - Row hammer refresh control circuit, 303 - Configuration module, 401 - Counting unit, 402 - Comparison unit, 501 - Processing device, 502 - Storage device. Detailed Implementation

[0028] As is known from the background technology, the actual refresh interval tREFIe of DRAM changes with temperature. Specifically, as the DRAM temperature increases, tREFIe decreases, and the proportion of the DRAM's single refresh cycle time to the actual refresh interval increases, resulting in a corresponding decrease in read / write time; conversely, as the DRAM temperature decreases, tREFIe increases, and the proportion of the DRAM's single refresh cycle time to the actual refresh interval decreases, resulting in a corresponding increase in read / write time.

[0029] For refresh operations in DRAM, some refresh operations are used only to perform normal refresh operations, while others are used to perform both normal refresh operations and row hammer refresh operations. Row hammer refresh operations are used to avoid the row hammer effect (RowHammer, which occurs when the same data line is enabled multiple times in memory, causing adjacent bits of that data line to flip).

[0030] As the mainstream storage device, DRAM performs computational operations directly within the storage array in its Processing-in-Memory (PIM) mode, thereby alleviating data transfer bottlenecks.

[0031] When the memory array in DRAM switches to in-memory computing mode, the NPU (Neural Processing Unit) located inside the DRAM sequentially activates the row addresses in the memory array to read weight data. Its access mode naturally covers most rows in DRAM, which is equivalent to performing a refresh operation on the memory array sequentially. This ensures that the NPU access itself does not induce the hammer effect. In other words, the memory does not need to perform row hammer refresh operation in in-memory computing mode.

[0032] In some embodiments, the NPU may also be a separate chip located outside the DRAM, interacting with the DRAM through a dedicated interface.

[0033] Therefore, in in-memory computing mode, by disabling row hammer refresh operations, the row hammer refresh operation can be released from occupying the refresh operation time window (i.e., refresh cycle time tRFC). The number of refresh operations required for each refresh command is reduced. At the same time, the number of refresh operations required for the memory to complete the overall refresh is reduced, which can adaptively shorten the refresh cycle time tRFC. This increases the available read and write time of the memory array in in-memory computing mode, significantly improving the in-memory computing execution efficiency and overall computing performance of DRAM.

[0034] In response, this disclosure provides a refresh control circuit for refreshing control of a memory array, comprising: a register circuit configured to acquire and store row hammer addresses of the memory array; a refresh controller configured to, when the memory array is in in-memory computing mode, perform row hammer refresh operations on the affected rows corresponding to the row hammer addresses stored in the register circuit in response to a received refresh command; the refresh controller is further configured to, after the row hammer refresh operations on all affected rows corresponding to the row hammer addresses stored in the register circuit are completed, generate and output an adjustment enable signal in an active state to indicate a shortening of the refresh cycle time of the memory array in in-memory computing mode.

[0035] In the description of the embodiments of this disclosure, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. In the description of the embodiments of this disclosure, "multiple" means two or more, unless otherwise explicitly defined. Similarly, "multiple sets" refers to two or more sets (including two sets), and "multiple pieces" refers to two or more pieces (including two pieces).

[0036] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0037] In the description of the embodiments of this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0038] In the description of the embodiments of this disclosure, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the embodiments of this disclosure and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this disclosure. For example, if the device or element in the illustration is inverted, then the element described as "below," "under," "down," or "bottom" of other elements or features will be oriented "above" or "top" of said other elements or features. Therefore, the term "below" may, depending on the context in which the term is used, encompass both above and below orientations, which will be obvious to those skilled in the art. Materials may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0039] In the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0040] In the description of embodiments of this disclosure, the terms "about," "approximately," "roughly," or "about" for a numerical value referring to a specific parameter include the numerical value, and those skilled in the art will understand that the deviation from the numerical value is within acceptable tolerances of the specific parameter. For example, "about" or "about" for a numerical value may include additional numerical values ​​that are in the range of 90.0% to 110.0% of the numerical value, such as in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0041] In the accompanying drawings corresponding to the embodiments of this disclosure, the thickness and / or area of ​​layers, films, panels, regions, etc., are enlarged for better understanding and ease of description. Throughout the specification, the same reference numerals denote the same elements. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor on a portion of the edge of the entire surface.

[0042] In the description of embodiments of this disclosure, when a component "includes" another component, other components are not excluded unless otherwise stated, and may be further included. When a component (such as a layer, film, region, or substrate) is described as being on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be an intermediate component between the two components. Conversely, when a component is described as being on the surface of another component, or a component is "directly" on another component, or another component is formed or disposed on the surface of a component, it indicates that there is no intermediate component between the two components. For simplicity and clarity, various components may be drawn at any scale. In the drawings, some components may be omitted for simplicity.

[0043] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. The aforementioned component may refer to a layer, film, region, portion, structure, or plate, etc.

[0044] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0045] Figure 1 This is a schematic diagram of the structure of a refresh control circuit provided in some embodiments of this disclosure. (See also...) Figure 1 The refresh control circuit provided in this embodiment is applied to the refresh control of the storage array 110. The refresh control of the storage array 110 includes normal refresh operation performed according to the refresh command and row hammer refresh operation performed according to the refresh command.

[0046] It should be noted that, in Figure 1 In the example, the module highlighted by the dashed box is used for the refresh control of a single memory array 110, meaning that the memory array 110, register circuit 101, and array refresh control circuit 120 correspond one-to-one. The memory includes multiple memory arrays 110, meaning that the memory includes multiple register circuits 101 and multiple array refresh control circuits 120.

[0047] In other embodiments, each memory array corresponds to a register circuit, and the correspondence between the memory array and the register circuit can also be set to many-to-one. Similarly, the correspondence between the memory array and the array refresh control circuit can also be set to many-to-one.

[0048] The refresh control circuit provided in this embodiment includes a register circuit 101 and a refresh controller 102.

[0049] Register circuit 101 is configured to acquire and store the row hammer address of storage array 110. In some embodiments, register circuit 101 is further configured to acquire and store the row hammer address of storage array 110 and the corresponding count value.

[0050] In some embodiments, the register circuit 101 also has a sampling and counting function (which can be implemented by the address sampling circuit included in the register circuit 101, not shown in the figure). By sampling the row activation operations in the storage array 110 (sampling according to a preset rule or random sampling), and counting the row address corresponding to the sampled row activation operation and the corresponding activation count, the register circuit 101 identifies the row hammer address that may trigger the row hammer effect. Based on the identification result, the register circuit 101 persistently saves each row hammer address and its corresponding count value as status information for subsequent refresh calls. In addition, this process does not involve active address sampling or dynamic updates, but only relies on existing access behavior to update the count value corresponding to the row address, thereby providing an accurate address basis for the row hammer refresh operation.

[0051] The count value can be set to the number of activations / accesses since the last refresh, or it can be set to the initial value (non-zero) + the number of activations / accesses. The initial value corresponding to each row hammer address can also be different. The initial value is related to the duration stored in the register circuit 101.

[0052] The refresh controller 102 is configured to perform a row hammer refresh operation on the victim row corresponding to the row hammer address stored in the register circuit 101 in response to a received refresh command when the storage array 110 is in in-memory computing mode.

[0053] The victim line corresponding to the hammer address includes at least hammer address + 1 and hammer address - 1. In some embodiments, the victim line corresponding to the hammer address also includes hammer address ± 2, hammer address ± 3, etc.

[0054] The refresh controller 102 is also configured to generate and output an adjustment enable signal in an active state after the row hammer refresh operation of all row hammer addresses corresponding to the victim rows stored in the register circuit 101 is completed, so as to indicate a reduction in the refresh cycle time of the memory array in in-memory computing mode.

[0055] For example, refresh controller 102 outputs a row hammer refresh enable signal and an array refresh signal corresponding to different memory arrays 110 according to the refresh command. Register circuit 101 outputs a row hammer address according to the row hammer refresh enable signal. Array refresh control circuit 120 corresponding to memory array 110 performs row hammer refresh on memory array 110 according to the corresponding row hammer address and array refresh signal. Alternatively, when refresh controller 102 only outputs the array refresh signal corresponding to memory array 110 according to the refresh command, array refresh control circuit 120 performs normal refresh operation on memory array 110, and does not perform row hammer refresh operation on memory array 110.

[0056] During this process, the refresh controller 102 generates and outputs an adjustment enable signal in an effective state based on the state that all the affected rows corresponding to the row hammer addresses stored in the register circuit 101 have completed the row hammer refresh operation. The adjustment enable signal in an effective state serves as an explicit control instruction to instruct the memory array 110 to shorten the original refresh cycle time in in-memory computing mode.

[0057] Additionally, when each row hammer address in register circuit 101 is output to array refresh control circuit 120 to complete the row hammer refresh operation for the corresponding affected row, register circuit 101 can remove that row hammer address until all row hammer addresses in register circuit 100 are cleared. The adjustment enable signal, which is in an active state, is generated with the sole trigger condition that all row hammer addresses in register circuit 101 have been cleared, and its output is only used to adjust the refresh cycle time. Therefore, its function is directly related to the adjustment of the refresh cycle time and does not involve any additional control over the refresh command frequency, address sampling, or row hammer effect detection.

[0058] In summary, when the memory array 110 is in in-memory computing mode, the refresh controller 102, upon receiving a refresh command, performs targeted row hammer refresh operations only for the row hammer addresses recorded in the register circuit 101. Once all the affected rows corresponding to the recorded row hammer addresses have been refreshed, the refresh controller 102 generates and outputs an adjustment enable signal indicating that the system can safely shorten the refresh cycle time. This mechanism overcomes the limitation of a fixed refresh cycle time in traditional solutions, dynamically releasing the memory access bandwidth occupied by excessive row hammer refresh operations in in-memory computing mode. This effectively solves the technical problem that the refresh cycle time cannot be shortened due to maintaining row hammer refresh protection in in-memory computing mode, resulting in the memory array's memory access bandwidth being occupied by unnecessary row hammer refresh operations. Consequently, it can effectively increase the read / write time window of the memory array in in-memory computing mode, significantly improving the in-memory computing execution efficiency and overall computing performance of DRAM.

[0059] In some embodiments, a corresponding and independent refresh controller 102 can be set for each storage array 110. In this case, the refresh controller 102 can support refresh modes such as REFab (full bank refresh command) / REFsb (same bank refresh command) in in-memory computing mode. Under this scheme, after all row hammer addresses corresponding to each storage array 110 have been refreshed, its corresponding refresh cycle time can be shortened without waiting for all storage arrays 110 to have completed the refresh of all row hammer addresses. That is, the refresh cycle time of each storage array 110 can be adjusted independently.

[0060] In other embodiments, a refresh controller 102 can be set for all storage arrays 110. In in-memory computing mode, refresh modes such as REFab / REFsb can be supported. In this scheme, it is necessary to wait for all storage arrays 110 to complete the row hammer refresh operation of all row hammer addresses before shortening the refresh cycle time of all storage arrays 110.

[0061] Figure 2 This is a schematic diagram of the structure of a refresh controller, including a refresh counting circuit and a horizontal hammer refresh control circuit, provided in some embodiments of this disclosure. Figure 3 This is a schematic diagram of the structure of a refresh counting circuit provided in some embodiments of this disclosure.

[0062] refer to Figure 2 In some embodiments, the refresh controller 102 includes a refresh counting circuit 301 and a row hammer refresh control circuit 302.

[0063] The refresh counting circuit 301 is configured to count refresh commands to obtain a second count value, and when the second count value is equal to a preset value, generate and output a row hammer refresh enable signal that is in an active state.

[0064] The row hammer refresh control circuit 302 is configured to receive a refresh command and a row hammer refresh enable signal, and when the row hammer refresh enable signal is in an active state, generate and output a row hammer refresh signal in response to the refresh command to indicate that a row hammer refresh operation is performed on the victim row corresponding to the row hammer address.

[0065] Register circuit 101 is configured to output a row hammer address in response to a row hammer refresh enable signal that is in an active state. In some embodiments, register circuit 101 may output row hammer addresses sequentially according to the magnitude of the count value.

[0066] As can be seen from the foregoing, the refresh controller 102 provided in this embodiment is applied to the normal refresh control and row hammer refresh control of the storage array. The array refresh signal output by the refresh controller 102 is used to control the array refresh control circuit 120 to perform normal refresh operation or row hammer refresh operation on the corresponding storage array 110.

[0067] When the refresh controller 102 provides the array refresh control circuit 120 with a row hammer refresh signal or row hammer refresh information in an effective state, the array refresh control circuit 120 performs a row hammer refresh operation on the corresponding memory array 110; when the refresh controller 102 does not provide the array refresh control circuit 120 with a row hammer refresh signal or provides row hammer refresh information in an invalid state, the array refresh control circuit 120 performs a normal refresh operation on the corresponding memory array 110.

[0068] Therefore, the hammer refresh signal can be regarded as a hammer enable signal used to indicate whether a hammer refresh operation is to be performed.

[0069] In some embodiments, the array refresh signal is generated by the row hammer refresh control circuit 302. In this case, the row hammer refresh control circuit 302 is configured to receive a refresh command and a row hammer refresh enable signal, and generate and output the row hammer refresh signal and the array refresh signal in response to the refresh command when the row hammer refresh enable signal is in an active state, or generate and output the array refresh signal in response to the refresh command when the row hammer refresh enable signal is in an inactive state.

[0070] In other embodiments, the array refresh signal may be generated by other control modules in the refresh controller. For example, the refresh controller includes a first control module that generates a corresponding array refresh signal according to each refresh command.

[0071] In some embodiments, the array refresh signal is generated by the row hammer refresh control circuit 302. However, the row hammer refresh control circuit 302 is configured to receive a refresh command and a row hammer refresh enable signal, and when the row hammer refresh enable signal is in a valid state, generate and output only a valid row hammer refresh signal in response to the refresh command (without generating an array refresh signal or generating an invalid array refresh signal), or when the row hammer refresh enable signal is in a invalid state, generate and output only a valid array refresh signal in response to the refresh command (without generating a row hammer refresh signal or generating an invalid row hammer refresh signal). At this time, the valid row hammer refresh signal is used to indicate that the array refresh control circuit 120 performs a row hammer refresh operation or a row hammer refresh operation + normal refresh operation on the corresponding memory array 110.

[0072] In this example, the refresh controller 102 counts the refresh commands one by one through the refresh counting circuit 301 to obtain a second count value. When the second count value reaches a preset value, the hammer refresh enable signal is triggered to enter the effective state. Then, the hammer refresh control circuit 302 responds to the current refresh command to generate a hammer refresh signal. That is, the refresh controller 102 can control the refresh commands to be executed once based on the current refresh command every second count value interval through the refresh counting circuit 301. The remaining refresh commands are used to perform normal refresh operations or other special refresh operations.

[0073] At this time, register circuit 101 is driven by row hammer refresh enable signal and outputs a row hammer address stored therein; row hammer refresh signal is used to instruct array refresh control circuit 120 to perform row hammer refresh operation on the corresponding memory array 110. Array refresh control circuit 120 responds to array refresh signal and performs row hammer refresh operation on memory array 110 according to row hammer address output by register circuit 101; that is, in in-memory computing mode, when the second count value is equal to the preset value, refresh controller 102 can perform a row hammer refresh operation on the victim row corresponding to the specified row hammer address. This process is triggered sequentially according to the counting condition to ensure that each row hammer address in each register circuit 101 is identified and refreshed one by one in an independent refresh cycle.

[0074] It should be noted that "perform a row hammer refresh operation on the victim row corresponding to the specified row hammer address" does not specifically refer to performing a refresh operation on a single victim row. In practical applications, "perform a row hammer refresh operation on the victim row corresponding to the specified row hammer address" can refer to performing a refresh operation on multiple victim rows (row hammer address ±1, row hammer address ±1, row hammer address ±2, etc.). The number of victim rows refreshed depends on the number of refresh operations (refreshes performed on specific row addresses) that can be executed in a single refresh command.

[0075] After all row hammer addresses of register circuit 101 have been refreshed, refresh controller 102 generates and outputs an adjustment enable signal that is in an active state.

[0076] In some embodiments, the refresh counting circuit 301 is also configured to be disabled in response to an adjustment enable signal that is in an active state.

[0077] As can be seen from the above description of the principle of in-memory computing mode, the access of the memory array in the memory in in-memory computing mode will not induce the hammer effect. The row hammer address in register circuit 101 is stored before the memory array enters the in-memory computing mode. After the row hammer refresh operation in in-memory computing mode refreshes all the row hammer addresses stored in register circuit 101, the memory array will no longer be affected by the row hammer effect and will need to perform the row hammer refresh operation again.

[0078] Therefore, in in-memory computing mode, the refresh counter circuit 301 can be disabled by adjusting the enable signal in an active state. The refresh controller 102 no longer controls the row hammer refresh operation on the memory array 110, so as to release the invalid row hammer refresh operation in in-memory computing mode from the occupation of the refresh operation time window (i.e. refresh cycle time). At this time, the number of refresh operations required for the memory to complete the overall refresh is reduced, and the refresh cycle time tRFC can be shortened adaptively, thereby increasing the available read and write time window of the memory array in in-memory computing mode, significantly improving the in-memory computing execution efficiency and overall computing performance of DRAM.

[0079] refer to Figure 2 and Figure 3 In some embodiments, the refresh counting circuit 301 includes a counting unit 401 and a comparison unit 402. The counting unit 401 is configured to count refresh commands to obtain a second count value. The comparison unit 402 is configured to receive the second count value and a preset value, and when the second count value and the preset value match, generate and output a row hammer refresh enable signal that is in an active state.

[0080] In one example, the counting unit 401 is configured according to a counter, which can be an adder or a carry-lookahead adder, etc. The comparison unit 402 is configured according to a comparator, with one input of the comparator receiving a second count value, the other input of the comparator receiving a preset value, and the output of the comparator being used to output a row hammer refresh enable signal that is in an active state.

[0081] When the preset value is configured to be a small value, in the in-memory computing mode, the memory can quickly perform the row hammer refresh operation to clear all the row hammer addresses stored in the register circuit 101, thereby shortening the refresh cycle time as quickly as possible and increasing the available read and write time of the memory array in the in-memory computing mode.

[0082] In some embodiments, the refresh controller 102 is further configured to perform row hammer refresh operations in response to each refresh command when the in-memory compute enable signal is active to indicate that the memory array is in in-memory compute mode, until the row hammer refresh operations for the victim rows corresponding to all row hammer addresses stored in the register circuit are completed.

[0083] In some embodiments, the refresh controller 102 further includes a configuration module 303. The configuration module 303 is configured to configure and provide a preset value; wherein, in in-memory computing mode, the preset value is configured to be 1.

[0084] The refresh controller 102 explicitly sets the preset value to 1 in the in-memory calculation mode through the configuration module 303, so that when the refresh counting circuit 301 receives a refresh command, the second count value immediately reaches the preset value, thereby immediately generating a valid row hammer refresh enable signal, triggering the row hammer refresh control circuit 302 to generate a row hammer refresh signal, so as to perform a row hammer refresh operation on the victim row corresponding to each row hammer address stored in the register circuit 101.

[0085] Based on this configuration, in in-memory computing mode, the array refresh control circuit 120 can perform row hammer refresh operation based on each refresh command until all the victim rows corresponding to the row hammer addresses stored in the register circuit 101 are refreshed. In this way, the memory can clear all the row hammer addresses stored in the register circuit 101 as quickly as possible in in-memory computing mode.

[0086] In this example, the refresh counting circuit 301 can stop counting refresh commands and instead directly generate a valid hammer refresh enable signal based on each refresh command, thereby triggering the hammer refresh control circuit 302 to generate a hammer refresh signal.

[0087] Based on the background technology, the impact of external factors such as temperature on the ability of capacitors to store data is considered. When the memory temperature is high, and the preset value is configured to 1, the continuous row hammer refresh operation postpones the original normal refresh operation, which may cause data errors in some memory cells.

[0088] In some embodiments, the refresh controller 102 is further configured to perform row hammer refresh operations in response to the currently received refresh command at preset intervals of refresh commands, until the row hammer refresh operations of all victim rows corresponding to all row hammer addresses stored in the register circuit are completed.

[0089] In some embodiments, the refresh controller 102 further includes a configuration module 303. The configuration module 303 is configured to configure and provide preset values ​​(corresponding to a preset number of preset values); wherein the preset values ​​are configured according to the row hammer refresh ratio.

[0090] The configuration module 303 dynamically sets a preset value based on the actual row hammer refresh ratio of the memory, so that the refresh counting circuit 301 triggers the row hammer refresh enable signal only when the cumulative number of refresh commands reaches the dynamically set preset value. That is, under the premise of ensuring that the stored data is not erroneous, all row hammer addresses stored in the register circuit 101 are cleared.

[0091] In some embodiments, the configuration module 303 is further configured to obtain the temperature code corresponding to the current temperature of the memory to which the refresh control circuit belongs, and configure a preset value according to the temperature code.

[0092] The configuration module 303 dynamically sets a preset value based on the actual row hammer refresh rate of the memory. This ensures that the refresh counter circuit 301 only triggers the row hammer refresh enable signal when the cumulative number of refresh commands reaches this dynamically set preset value. In other words, while ensuring the stored data is error-free, it clears all row hammer addresses stored in the register circuit 101 as quickly as possible. Furthermore, the preset value is adaptively adjusted according to the current temperature of the memory, allowing the memory to adjust the speed at which it clears all row hammer addresses stored in the register circuit 101 to adapt to temperature changes. This, in turn, accelerates the refresh operation of all affected rows corresponding to the row hammer addresses while ensuring the reliability of the stored data.

[0093] In some embodiments, the configuration module 303 configures a preset value according to a temperature code, including: when the temperature code indicates that the current temperature of the memory is rising, the configuration module 303 increases the configured preset value; when the temperature code indicates that the current temperature of the memory is falling, the configuration module 303 decreases the configured preset value.

[0094] In some embodiments, the memory to which the refresh control circuit belongs further includes: an in-memory computing controller ( Figure 3 (Not illustrated in the image). Configuration module 303 is also configured to output temperature codes to the in-memory computing controller; the in-memory computing controller is configured to generate and output refresh commands based on the temperature codes.

[0095] The in-memory compute controller is the overall controller of the memory array in in-memory compute mode, such as the NPU. The NPU generates and outputs refresh commands based on temperature codes. Specifically, the NPU adjusts the interval between output refresh commands based on the temperature codes. In one example, the standard refresh interval tREFI between refresh commands is 3.9 µs. When the temperature code is 11111B, the actual refresh interval tREFIe between the NPU's output refresh commands is shortened to 0.125 × tREFI (487.5 ns).

[0096] Figure 4 This is a schematic diagram of the structure of a refresh controller including a first type of row hammer address counter, provided in some embodiments of this disclosure. Figure 5 Provided for embodiments of this disclosure Figure 4 Based on the example refresh controller, here is a schematic diagram of the refresh control circuit. Figure 6 This is a schematic diagram of the structure of a refresh controller including a second type of row hammer address counter, provided in some embodiments of this disclosure. Figure 7 This is a schematic diagram illustrating a specific implementation structure of a refresh control circuit provided in some embodiments of this disclosure.

[0097] refer to Figure 4 In some embodiments, the refresh controller 102 includes a row hammer address counter 201.

[0098] The row hammer address counter 201 is configured to receive an in-memory computation enable signal, and when the in-memory computation enable signal is in an active state to indicate that the memory array 110 is in an in-memory computation mode, count the row hammer addresses that have completed the row hammer refresh operation to obtain a first count value; when the first count value is equal to the number of row hammer addresses stored in the register circuit 101 or the maximum value of the row hammer addresses that the register circuit 101 can store, the row hammer address counter 201 generates and outputs an adjustment enable signal that is in an active state.

[0099] The refresh controller 102 receives the in-memory computation enable signal through its built-in row hammer address counter 201. When the in-memory computation enable signal is valid, it automatically increments the count value after performing a row hammer refresh operation on each affected row corresponding to a row hammer address stored in the register circuit 101, obtaining a first count value. When the first count value reaches the total number of row hammer addresses stored in the register circuit 101 or its maximum capacity, it directly generates an adjustment enable signal. This eliminates the need for external address comparison or manual intervention; the internal counting mechanism alone can accurately determine whether all row hammer refresh operations have been completed, thereby accurately triggering the generation of the adjustment enable signal and reducing the refresh cycle time in in-memory computation mode.

[0100] It should be noted that if the refresh controller 102 is set for each memory array 110 and is independent of each other, an adjustment enable signal in an active state can be directly generated when the first count value reaches the total number of row hammer addresses stored in the register circuit 101. If a shared refresh controller 102 is set for all memory arrays 110, an adjustment enable signal in an active state can be directly generated when the first count value reaches the maximum capacity of the register circuit 101.

[0101] refer to Figure 4 In some embodiments, counting the row hammer addresses that have completed the row hammer refresh operation can be achieved based on the row hammer refresh enable signal that is in an active state. Since the active row hammer refresh enable signal is used to instruct the register circuit 101 to output a row hammer address it stores, and each active row hammer refresh enable signal corresponds to a row hammer address stored in the register circuit 101, the number of row hammer addresses output by the register circuit 101 can be counted by counting the row hammer refresh enable signals.

[0102] refer to Figure 6 In some embodiments, since the hammer refresh enable signal is associated with the hammer refresh signal, counting the hammer addresses that have completed the hammer refresh operation can be achieved based on the hammer refresh signal.

[0103] refer to Figure 5 In some embodiments, register circuit 101 is further configured to receive an in-memory compute enable signal and, in response to an active in-memory compute enable signal, stop acquiring row hammer addresses. As described above regarding the principle of in-memory compute mode, memory access in in-memory compute mode does not induce hammer effects. Therefore, when the in-memory compute enable signal is active, register circuit 101 stops acquiring row hammer addresses to reduce memory power consumption.

[0104] In some embodiments, the refresh controller 102 is further configured to perform a row hammer refresh operation in response to the currently received refresh command at preset intervals when the in-memory computing enable signal is in an invalid state to indicate that the memory array is in memory mode.

[0105] refer to Figure 7 In one application scenario, part of the refresh control circuit can be reused in both storage mode and in-memory computing mode.

[0106] The in-memory compute enable signal is issued by the in-memory compute controller (NPU). The in-memory compute enable signal is used to indicate whether the storage array 110 is in storage mode or in-memory compute mode. When the in-memory compute enable signal is active, the corresponding storage array 110 is in in-memory compute mode; when the in-memory compute enable signal is inactive, the corresponding storage array 110 is in storage mode.

[0107] In normal storage mode, refresh commands are issued by the SOC, and the refresh control circuit is used for normal refresh control and row hammer refresh control of storage array 110.

[0108] In in-memory computing mode, refresh commands are issued by the in-memory computing controller NPU. The refresh control circuit is used for normal refresh control and row hammer refresh control of the storage array 110, and feeds back the adjustment enable signal to the in-memory computing controller NPU according to the number of row hammer refreshes to reduce the refresh cycle time in in-memory computing mode.

[0109] In both normal refresh mode and in-memory calculation mode, the same refresh counting circuit 301 in refresh controller 102 can be used. At this time, the preset value used by refresh counting circuit 301 for judgment is configured according to the row hammer refresh ratio.

[0110] Different refresh counting circuits 301 can be used for normal refresh mode and in-memory calculation mode. The preset value used by the refresh counting circuit 301 for judgment in normal refresh mode is configured according to the row hammer refresh ratio; the preset value used by the refresh counting circuit 301 for judgment in in-memory calculation mode can be set to a fixed value such as 1, 2, 3, etc.

[0111] In summary, for the refresh control circuit provided in this embodiment, when the memory array is in in-memory computing mode, the refresh controller 102, upon receiving a refresh command, performs targeted row hammer refresh operations only for the row hammer addresses recorded in the register circuit. Once all the affected rows corresponding to the recorded row hammer addresses have been refreshed, the refresh controller generates and outputs an adjustment enable signal in an effective state, explicitly indicating that the system can safely shorten the refresh cycle time. This mechanism overcomes the limitation of a fixed refresh cycle time in traditional solutions, dynamically releasing the memory access bandwidth occupied by excessive row hammer refresh operations in in-memory computing mode. This effectively solves the technical problem of being unable to shorten the refresh cycle time due to maintaining row hammer refresh protection in in-memory computing mode, resulting in the memory array's memory access bandwidth being occupied by unnecessary row hammer refresh operations. This effectively increases the read / write time window of the memory array in in-memory computing mode, significantly improving the in-memory computing execution efficiency and overall computing performance of DRAM.

[0112] Accordingly, this disclosure also provides a memory including the refresh control circuit described above. Therefore, the content disclosed in the foregoing embodiments is also applicable to the following embodiments of the memory.

[0113] In some embodiments, the refresh command includes a first refresh command, and the refresh control circuit is configured to receive the first refresh command sent externally in storage mode, and control the execution of a refresh operation in response to the first refresh command.

[0114] In some embodiments, the refresh command further includes a second refresh command, and the memory further includes: an in-memory computing controller, configured to provide the second refresh command to the refresh control circuit in in-memory computing mode, and receive an adjustment enable signal in an active state fed back by the refresh control circuit to indicate adjustment of the refresh cycle time of the memory array in in-memory computing mode; and a refresh control circuit, configured to control the execution of a refresh operation in response to the second refresh command in in-memory computing mode.

[0115] In some embodiments, the memory may be a memory that includes volatile memory cells. For example, the memory may include various dynamic random access memories (DRAMs), such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, or Low Power Double Data Rate (LPDDR) SDRAM.

[0116] In some embodiments, the memory may also be an SRAM memory, a NAND flash memory, a NOR flash memory, an RRAM device, an FRAM device, a PRAM device, a TRAM device, or an MRAM device, etc.

[0117] In some embodiments, the memory may be adapted to a 1C1A (1 CMOS die 1 Array die) memory architecture, a 1C2A (1 CMOS die 2 Array die) memory architecture, a 1CnA (1 CMOS die n Array die) memory architecture, a 2C1A (2 CMOS die 1 Array die) memory architecture, and an nC1A (n CMOS die 1 Array die) memory architecture.

[0118] Accordingly, this disclosure also provides an electronic device that includes the memory provided above. Therefore, the content disclosed in the foregoing embodiments is also applicable to the embodiments of the following electronic devices.

[0119] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure.

[0120] refer to Figure 8 The electronic device includes a processing device 501 and a storage device 502 electrically connected to the processing device 501, the storage device including the memory provided above.

[0121] The processing device 501 described above may refer to one or more processors. For example, the processing device 501 may include one or more central processing units (CPUs), or it may include a CPU and a graphics processing unit (GPU), or it may include an application processor and a coprocessor (e.g., a microcontroller unit or a neural network processor). When the processing device 501 includes multiple processors, these processors may be integrated on the same chip or may be independent chips. A processor may include one or more physical cores, where a physical core is the smallest processing module.

[0122] Schematic, the processing device 501 may be implemented in at least one of the following hardware forms: Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), and Programmable Logic Array (PLA).

[0123] The processing device 501 may integrate one or a combination of several of the following: a central processing unit (CPU), a graphics processing unit (GPU), and a modem.

[0124] Electronic devices may include one or more of the following: smartphones, personal computers (PCs), mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, personal digital assistants (PDAs), portable media players (PMPs), MPEG audio layer 3 (Moving Picture Experts Group Audio Layer III) players, mobile medical devices, cameras, home appliances, medical devices, Internet of Things (IoT) devices, and wearable devices. Wearable devices can be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices may include, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted displays (HMDs).

[0125] In some embodiments, the electronic device can also be used in large servers, such as data centers or AI computers.

[0126] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A refresh control circuit, applied to refresh control of a memory array, characterized in that, include: The register circuit is configured to acquire and store the row hammer address of the memory array; A refresh controller is configured to perform a row hammer refresh operation on the victim row corresponding to the row hammer address stored in the register circuit in response to a received refresh command when the storage array is in in-memory computing mode. The refresh controller is further configured to generate and output an adjustment enable signal in an active state after the row hammer refresh operation of all the affected rows corresponding to the row hammer addresses stored in the register circuit is completed, so as to indicate a reduction in the refresh cycle time of the memory array in in-memory computing mode.

2. The refresh control circuit according to claim 1, characterized in that, The refresh controller includes: The row hammer address counter is configured to receive an in-memory compute enable signal and, when the in-memory compute enable signal is in a valid state to indicate that the memory array is in the in-memory compute mode, count the row hammer addresses that have completed the row hammer refresh operation to obtain a first count value. When the first count value is equal to the number of row hammer addresses stored in the register circuit or the maximum value of the row hammer addresses that the register circuit can store, the row hammer address counter generates and outputs the adjustment enable signal that is in an active state.

3. The refresh control circuit according to claim 2, characterized in that, The register circuit is also configured to receive the in-memory computation enable signal and, in response to the in-memory computation enable signal being in a valid state, to stop acquiring the row hammer address.

4. The refresh control circuit according to claim 2, characterized in that, The refresh controller is further configured to, when the in-memory compute enable signal is in an active state to indicate that the memory array is in in-memory compute mode, execute the row hammer refresh operation in response to each refresh command until the row hammer refresh operation of all the victim rows corresponding to the row hammer addresses stored in the register circuit is completed. Alternatively, at preset intervals, the row hammer refresh operation is performed in response to the currently received refresh command, until the row hammer refresh operation for all victim rows corresponding to the row hammer addresses stored in the register circuit is completed.

5. The refresh control circuit according to claim 2, characterized in that, The refresh controller is further configured to, when the in-memory computing enable signal is in an invalid state to indicate that the memory array is in storage mode, execute the row hammer refresh operation in response to the currently received refresh command at preset intervals of refresh commands.

6. The refresh control circuit according to claim 2, characterized in that, The refresh controller includes: The refresh counting circuit is configured to count the refresh command to obtain a second count value, and when the second count value is equal to a preset value, generate and output a row hammer refresh enable signal that is in an effective state. The row hammer refresh control circuit is configured to receive the refresh command and the row hammer refresh enable signal, and when the row hammer refresh enable signal is in an active state, generate and output a row hammer refresh signal in response to the refresh command to instruct the row hammer refresh operation to be performed on the victim row corresponding to the row hammer address. The register circuit is configured to output a row hammer address in response to the row hammer refresh enable signal being in an active state.

7. The refresh control circuit according to claim 6, characterized in that, The refresh counting circuit is also configured to disable in response to the adjustment enable signal being in an active state.

8. The refresh control circuit according to claim 6, characterized in that, The refresh counting circuit includes: A counting unit is configured to count the refresh commands to obtain the second count value; The comparison unit is configured to receive the second count value and the preset value, and when the second count value and the preset value match, generate and output the row hammer refresh enable signal that is in an active state.

9. The refresh control circuit according to claim 8, characterized in that, The refresh controller further includes a configuration module configured to configure and provide the preset value; wherein, in the in-memory computing mode, the preset value is configured to be 1.

10. The refresh control circuit according to claim 8, characterized in that, The refresh controller further includes a configuration module configured to configure and provide the preset value; wherein the preset value is configured according to the row hammer refresh ratio.

11. The refresh control circuit according to claim 10, characterized in that, The configuration module is further configured to obtain the temperature code corresponding to the current temperature of the memory to which the refresh control circuit belongs, and configure the preset value according to the temperature code.

12. The refresh control circuit according to claim 11, characterized in that, The memory to which the refresh control circuit belongs also includes: an in-memory computing controller; The configuration module is also configured to output the temperature code to the in-memory computing controller; The in-memory computing controller is configured to generate and output the refresh command based on the temperature code.

13. The refresh control circuit according to claim 11, characterized in that, The configuration module configures the preset value according to the temperature code, including: The temperature code represents the current temperature rise of the memory, and the configuration module increases the configured preset value; The temperature code indicates that the current temperature of the memory has decreased, and the configuration module reduces the configured preset value.

14. A memory, characterized in that, The memory includes a refresh control circuit as described in any one of claims 1 to 13.

15. The memory according to claim 14, characterized in that, The refresh command includes a first refresh command. The refresh control circuit is configured to receive the first refresh command sent externally in storage mode and control the execution of a refresh operation in response to the first refresh command.

16. The memory according to claim 14, characterized in that, The refresh command also includes a second refresh command, and the memory further includes: an in-memory computing controller configured to, in in-memory computing mode, provide the second refresh command to the refresh control circuit and receive an adjustment enable signal in an active state fed back by the refresh control circuit; the refresh control circuit is configured to, in in-memory computing mode, control the execution of a refresh operation in response to the second refresh command.

17. An electronic device, characterized in that, include: A processing device, and a storage device electrically connected to the processing device; The storage device includes the memory as described in any one of claims 14 to 16.

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